diff --git a/compiler/vmgen.nim b/compiler/vmgen.nim
index 898b5b5def..dd8b8365ca 100644
--- a/compiler/vmgen.nim
+++ b/compiler/vmgen.nim
@@ -1842,6 +1842,8 @@ proc genArrAccessOpcode(c: PCtx; n: PNode; dest: var TDest; opc: TOpcode;
   if dest < 0: dest = c.getTemp(n.typ)
   if opc in {opcLdArrAddr, opcLdStrIdxAddr} and gfNodeAddr in flags:
     c.gABC(n, opc, dest, a, b)
+    if c.prc.regInfo[a].kind >= slotTempUnknown:
+      c.prc.regInfo[a].kind = slotTempPerm
   elif needsRegLoad():
     var cc = c.getTemp(n.typ)
     c.gABC(n, opc, cc, a, b)
@@ -1858,6 +1860,8 @@ proc genObjAccessAux(c: PCtx; n: PNode; a, b: int, dest: var TDest; flags: TGenF
   if dest < 0: dest = c.getTemp(n.typ)
   if {gfNodeAddr} * flags != {}:
     c.gABC(n, opcLdObjAddr, dest, a, b)
+    if a < c.prc.regInfo.len and c.prc.regInfo[a].kind >= slotTempUnknown:
+      c.prc.regInfo[a].kind = slotTempPerm
   elif needsRegLoad():
     var cc = c.getTemp(n.typ)
     c.gABC(n, opcLdObj, cc, a, b)
diff --git a/tests/vm/t25849.nim b/tests/vm/t25849.nim
new file mode 100644
index 0000000000..a503dd0479
--- /dev/null
+++ b/tests/vm/t25849.nim
@@ -0,0 +1,16 @@
+discard """
+  targets: "c cpp js"
+"""
+
+import std/os
+from std/sequtils import toSeq
+
+iterator items(a: array[3, string]): lent string {.inline.} =
+  for i in 0..2:
+    yield a[i]
+
+static:
+  const key = "NIM_TESTS_TOSENV_KEY"
+  for val in items(["a", "b", "c"]):
+    putEnv(key, val)
+    doAssert (key, val) in toSeq(envPairs())