diff --git a/core/rexcode/isa/arm64/decoder.odin b/core/rexcode/isa/arm64/decoder.odin index bb4b935d8..7eeed8420 100644 --- a/core/rexcode/isa/arm64/decoder.odin +++ b/core/rexcode/isa/arm64/decoder.odin @@ -530,7 +530,10 @@ extract_operand_inline :: #force_inline proc "contextless" ( case .SVE_SHIFT_TSZ_IMM: return Operand{immediate = i64((word >> 16) & 0x7F), kind = .IMMEDIATE, size = 1} case .SVE_PATTERN: - return Operand{immediate = i64((word >> 5) & 0x1F), kind = .IMMEDIATE, size = 1} + return Operand{immediate = i64((word >> 5) & 0x1F), kind = .IMMEDIATE, size = SVE_PATTERN_IMM} + case .IMM_MUL4: + // The field holds the multiplier minus one. + return Operand{immediate = i64(((word >> 16) & 0xF) + 1), kind = .IMMEDIATE, size = SVE_MUL_IMM} // ---- SVE memory operands ---- case .SVE_OFFSET_BASE_SS, .SVE_OFFSET_BASE_SS1, .SVE_OFFSET_BASE_SS2, .SVE_OFFSET_BASE_SS3, diff --git a/core/rexcode/isa/arm64/mnemonic_builders.odin b/core/rexcode/isa/arm64/mnemonic_builders.odin index 4e7e5da6e..8373ea484 100644 --- a/core/rexcode/isa/arm64/mnemonic_builders.odin +++ b/core/rexcode/isa/arm64/mnemonic_builders.odin @@ -434,20 +434,20 @@ emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Inst inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } inst_ldr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } inst_ldr_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } -inst_ldr_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_ldr_ps_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } inst_ldr_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } emit_ldr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_r_l(dst, label)) } emit_ldr_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_z_m(rz, mem)) } -emit_ldr_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_p_m(rz, mem)) } +emit_ldr_ps_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_ldr_ps_m(rz, mem)) } emit_ldr_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_ldr_i_m(imm, mem)) } inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } inst_str_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_mem(mem), {}, {}}} } -inst_str_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +inst_str_ps_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } inst_str_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } emit_str_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_z_m(rz, mem)) } -emit_str_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_p_m(rz, mem)) } +emit_str_ps_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_str_ps_m(rz, mem)) } emit_str_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_str_i_m(imm, mem)) } inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) } emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) } @@ -3565,10 +3565,10 @@ inst_ptrues_pb_i :: #force_inline proc "contextless" (rz: u8, imm: emit_ptrues_pb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_ptrues_pb_i(rz, imm)) } inst_pfalse_pb :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } emit_pfalse_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_pfalse_pb(rz)) } -inst_pfirst_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pfirst_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_pb_p_pb(rz, rz2, rz3)) } -inst_pnext_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } -emit_pnext_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_p_pb(rz, rz2, rz3)) } +inst_pfirst_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pfirst_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pfirst_pb_pb_pb(rz, rz2, rz3)) } +inst_pnext_pb_pb_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_pnext_pb_pb_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_pnext_pb_pb_pb(rz, rz2, rz3)) } inst_brka_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKA, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } emit_brka_pb_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_brka_pb_p_pb(rz, rz2, rz3)) } inst_brkb_pb_p_pb :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .BRKB, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } @@ -4049,56 +4049,98 @@ inst_uqdecd_r_i_i :: #force_inline proc "contextless" (dst: Register inst_uqdecd_zd_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UQDECD, operand_count = 3, length = 4, ops = {op_z_d(rz), op_imm(imm, 4), op_imm(imm2, 4), {}}} } emit_uqdecd_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_uqdecd_r_i_i(dst, imm, imm2)) } emit_uqdecd_zd_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_uqdecd_zd_i_i(rz, imm, imm2)) } -inst_cntp_r_p_p :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } -emit_cntp_r_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_p(dst, rz1, rz2)) } -inst_incp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_incp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_incp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_incp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_incp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_p(dst, rz1)) } -emit_incp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zh_p(rz, rz2)) } -emit_incp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zs_p(rz, rz2)) } -emit_incp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zd_p(rz, rz2)) } -inst_decp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_decp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_decp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_decp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_decp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_p(dst, rz1)) } -emit_decp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zh_p(rz, rz2)) } -emit_decp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zs_p(rz, rz2)) } -emit_decp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zd_p(rz, rz2)) } -inst_sqincp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqincp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqincp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqincp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_sqincp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_p(dst, rz1)) } -emit_sqincp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zh_p(rz, rz2)) } -emit_sqincp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zs_p(rz, rz2)) } -emit_sqincp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zd_p(rz, rz2)) } -inst_sqdecp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_sqdecp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqdecp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_sqdecp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_sqdecp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_p(dst, rz1)) } -emit_sqdecp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zh_p(rz, rz2)) } -emit_sqdecp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zs_p(rz, rz2)) } -emit_sqdecp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zd_p(rz, rz2)) } -inst_uqincp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqincp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqincp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqincp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_uqincp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_p(dst, rz1)) } -emit_uqincp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zh_p(rz, rz2)) } -emit_uqincp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zs_p(rz, rz2)) } -emit_uqincp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zd_p(rz, rz2)) } -inst_uqdecp_r_p :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } -inst_uqdecp_zh_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqdecp_zs_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -inst_uqdecp_zd_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } -emit_uqdecp_r_p :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_p(dst, rz1)) } -emit_uqdecp_zh_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zh_p(rz, rz2)) } -emit_uqdecp_zs_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zs_p(rz, rz2)) } -emit_uqdecp_zd_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zd_p(rz, rz2)) } +inst_cntp_r_p_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } +inst_cntp_r_p_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } +inst_cntp_r_p_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } +inst_cntp_r_p_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .CNTP, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}}} } +emit_cntp_r_p_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_pb(dst, rz1, rz2)) } +emit_cntp_r_p_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_ph(dst, rz1, rz2)) } +emit_cntp_r_p_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_ps(dst, rz1, rz2)) } +emit_cntp_r_p_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8, rz2: u8) { append(instructions, inst_cntp_r_p_pd(dst, rz1, rz2)) } +inst_incp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_incp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_incp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_incp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_incp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_incp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_incp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .INCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_incp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_pb(dst, rz1)) } +emit_incp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_ph(dst, rz1)) } +emit_incp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_ps(dst, rz1)) } +emit_incp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_incp_r_pd(dst, rz1)) } +emit_incp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zh_ph(rz, rz2)) } +emit_incp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zs_ps(rz, rz2)) } +emit_incp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_incp_zd_pd(rz, rz2)) } +inst_decp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_decp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_decp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_decp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_decp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_decp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_decp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .DECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_decp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_pb(dst, rz1)) } +emit_decp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_ph(dst, rz1)) } +emit_decp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_ps(dst, rz1)) } +emit_decp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_decp_r_pd(dst, rz1)) } +emit_decp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zh_ph(rz, rz2)) } +emit_decp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zs_ps(rz, rz2)) } +emit_decp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_decp_zd_pd(rz, rz2)) } +inst_sqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_sqincp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_pb(dst, rz1)) } +emit_sqincp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_ph(dst, rz1)) } +emit_sqincp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_ps(dst, rz1)) } +emit_sqincp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqincp_r_pd(dst, rz1)) } +emit_sqincp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zh_ph(rz, rz2)) } +emit_sqincp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zs_ps(rz, rz2)) } +emit_sqincp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqincp_zd_pd(rz, rz2)) } +inst_sqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_sqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_sqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_sqdecp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_pb(dst, rz1)) } +emit_sqdecp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_ph(dst, rz1)) } +emit_sqdecp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_ps(dst, rz1)) } +emit_sqdecp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_sqdecp_r_pd(dst, rz1)) } +emit_sqdecp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zh_ph(rz, rz2)) } +emit_sqdecp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zs_ps(rz, rz2)) } +emit_sqdecp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sqdecp_zd_pd(rz, rz2)) } +inst_uqincp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqincp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqincp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqincp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqincp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqincp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqincp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQINCP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_uqincp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_pb(dst, rz1)) } +emit_uqincp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_ph(dst, rz1)) } +emit_uqincp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_ps(dst, rz1)) } +emit_uqincp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqincp_r_pd(dst, rz1)) } +emit_uqincp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zh_ph(rz, rz2)) } +emit_uqincp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zs_ps(rz, rz2)) } +emit_uqincp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqincp_zd_pd(rz, rz2)) } +inst_uqdecp_r_pb :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqdecp_r_ph :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqdecp_r_ps :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqdecp_r_pd :: #force_inline proc "contextless" (dst: Register, rz1: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(Register(REG_P | (u16(rz1) & 0xF))), {}, {}}} } +inst_uqdecp_zh_ph :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqdecp_zs_ps :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +inst_uqdecp_zd_pd :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .UQDECP, operand_count = 2, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_uqdecp_r_pb :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_pb(dst, rz1)) } +emit_uqdecp_r_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_ph(dst, rz1)) } +emit_uqdecp_r_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_ps(dst, rz1)) } +emit_uqdecp_r_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, rz1: u8) { append(instructions, inst_uqdecp_r_pd(dst, rz1)) } +emit_uqdecp_zh_ph :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zh_ph(rz, rz2)) } +emit_uqdecp_zs_ps :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zs_ps(rz, rz2)) } +emit_uqdecp_zd_pd :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_uqdecp_zd_pd(rz, rz2)) } inst_ld1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } emit_ld1q_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_ld1q_i_p_m(imm, rz1, mem)) } inst_st1q_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1Q, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } @@ -5662,10 +5704,10 @@ inst_ptrues :: inst_ptrues_pb_i emit_ptrues :: emit_ptrues_pb_i inst_pfalse :: inst_pfalse_pb emit_pfalse :: emit_pfalse_pb -inst_pfirst :: inst_pfirst_pb_p_pb -emit_pfirst :: emit_pfirst_pb_p_pb -inst_pnext :: inst_pnext_pb_p_pb -emit_pnext :: emit_pnext_pb_p_pb +inst_pfirst :: inst_pfirst_pb_pb_pb +emit_pfirst :: emit_pfirst_pb_pb_pb +inst_pnext :: inst_pnext_pb_pb_pb +emit_pnext :: emit_pnext_pb_pb_pb inst_brka :: inst_brka_pb_p_pb emit_brka :: emit_brka_pb_p_pb inst_brkb :: inst_brkb_pb_p_pb @@ -5872,20 +5914,20 @@ inst_uqdecw :: proc{ inst_uqdecw_r_i_i, inst_uqdecw_zs_i_ emit_uqdecw :: proc{ emit_uqdecw_r_i_i, emit_uqdecw_zs_i_i } inst_uqdecd :: proc{ inst_uqdecd_r_i_i, inst_uqdecd_zd_i_i } emit_uqdecd :: proc{ emit_uqdecd_r_i_i, emit_uqdecd_zd_i_i } -inst_cntp :: inst_cntp_r_p_p -emit_cntp :: emit_cntp_r_p_p -inst_incp :: proc{ inst_incp_r_p, inst_incp_zh_p } -emit_incp :: proc{ emit_incp_r_p, emit_incp_zh_p } -inst_decp :: proc{ inst_decp_r_p, inst_decp_zh_p } -emit_decp :: proc{ emit_decp_r_p, emit_decp_zh_p } -inst_sqincp :: proc{ inst_sqincp_r_p, inst_sqincp_zh_p } -emit_sqincp :: proc{ emit_sqincp_r_p, emit_sqincp_zh_p } -inst_sqdecp :: proc{ inst_sqdecp_r_p, inst_sqdecp_zh_p } -emit_sqdecp :: proc{ emit_sqdecp_r_p, emit_sqdecp_zh_p } -inst_uqincp :: proc{ inst_uqincp_r_p, inst_uqincp_zh_p } -emit_uqincp :: proc{ emit_uqincp_r_p, emit_uqincp_zh_p } -inst_uqdecp :: proc{ inst_uqdecp_r_p, inst_uqdecp_zh_p } -emit_uqdecp :: proc{ emit_uqdecp_r_p, emit_uqdecp_zh_p } +inst_cntp :: inst_cntp_r_p_pb +emit_cntp :: emit_cntp_r_p_pb +inst_incp :: proc{ inst_incp_r_pb, inst_incp_zh_ph } +emit_incp :: proc{ emit_incp_r_pb, emit_incp_zh_ph } +inst_decp :: proc{ inst_decp_r_pb, inst_decp_zh_ph } +emit_decp :: proc{ emit_decp_r_pb, emit_decp_zh_ph } +inst_sqincp :: proc{ inst_sqincp_r_pb, inst_sqincp_zh_ph } +emit_sqincp :: proc{ emit_sqincp_r_pb, emit_sqincp_zh_ph } +inst_sqdecp :: proc{ inst_sqdecp_r_pb, inst_sqdecp_zh_ph } +emit_sqdecp :: proc{ emit_sqdecp_r_pb, emit_sqdecp_zh_ph } +inst_uqincp :: proc{ inst_uqincp_r_pb, inst_uqincp_zh_ph } +emit_uqincp :: proc{ emit_uqincp_r_pb, emit_uqincp_zh_ph } +inst_uqdecp :: proc{ inst_uqdecp_r_pb, inst_uqdecp_zh_ph } +emit_uqdecp :: proc{ emit_uqdecp_r_pb, emit_uqdecp_zh_ph } inst_ld1q :: inst_ld1q_i_p_m emit_ld1q :: emit_ld1q_i_p_m inst_st1q :: inst_st1q_i_p_m diff --git a/core/rexcode/isa/arm64/operands.odin b/core/rexcode/isa/arm64/operands.odin index 933ad36ba..dc38c0db3 100644 --- a/core/rexcode/isa/arm64/operands.odin +++ b/core/rexcode/isa/arm64/operands.odin @@ -176,6 +176,21 @@ op_cond :: #force_inline proc "contextless" (c: Cond) -> Operand { // one -- EXT's byte index, for instance, is written `#3`. LANE_INDEX :: u8(0xFF) +// SVE writes its element-count pattern by name (`vl8`, `mul3`, `all`) and its +// multiplier as `mul #N`, so both need telling apart from a plain immediate. +SVE_PATTERN_IMM :: u8(0xFE) +SVE_MUL_IMM :: u8(0xFD) + +// The 32 SVE element-count patterns; the gaps are reserved and print as a +// bare number. +@(rodata) +SVE_PATTERN_NAMES := [32]string{ + "pow2", "vl1", "vl2", "vl3", "vl4", "vl5", "vl6", "vl7", + "vl8", "vl16", "vl32", "vl64", "vl128", "vl256", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "mul4", "mul3", "all", +} + @(require_results) op_lane_index :: #force_inline proc "contextless" (index: i64) -> Operand { return Operand{immediate = index, kind = .IMMEDIATE, size = LANE_INDEX} diff --git a/core/rexcode/isa/arm64/printer.odin b/core/rexcode/isa/arm64/printer.odin index 9479e461c..cf8f3f21d 100644 --- a/core/rexcode/isa/arm64/printer.odin +++ b/core/rexcode/isa/arm64/printer.odin @@ -395,6 +395,18 @@ write_sysreg :: proc(sb: ^strings.Builder, sr: System_Register, uppercase: bool) } } +@(private="file") +write_lowercase :: proc(sb: ^strings.Builder, s: string, uppercase: bool) { + for i in 0 ..< len(s) { + c := s[i] + if uppercase && c >= 'a' && c <= 'z' { + strings.write_byte(sb, c - 'a' + 'A') + } else { + strings.write_byte(sb, c) + } + } +} + @(private="file") write_vector_shape :: proc(sb: ^strings.Builder, r: Register, size: u8, uppercase: bool) { shape := "" @@ -529,6 +541,19 @@ write_operand :: proc( write_vector_shape(sb, op.reg, op.size, opts.uppercase) case .IMMEDIATE: + // An SVE element-count pattern has a name, and its multiplier is + // written `mul #N` rather than as a bare immediate. + if op.size == SVE_PATTERN_IMM { + name := SVE_PATTERN_NAMES[op.immediate & 0x1F] + if name != "" { + write_lowercase(sb, name, opts.uppercase) + return + } + } else if op.size == SVE_MUL_IMM { + strings.write_string(sb, opts.uppercase ? "MUL #" : "mul #") + write_signed_decimal(sb, op.immediate) + return + } strings.write_byte(sb, '#') write_signed_decimal(sb, op.immediate) diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 0880cc546..4e2e00cb2 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -97,68 +97,68 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .AESMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E000, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, { .AESIMC, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VD,.NONE,.NONE}, 0x4520E400, 0xFFFFFFE0, .SVE2, {explicit_count=2} }, { .REV, {.P_REG_B,.P_REG_B,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {explicit_count=2} }, - { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, - { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, { .PTRUE, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {explicit_count=2} }, { .PTRUES, {.P_REG_B,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .REV, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {explicit_count=2} }, @@ -174,10 +174,10 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .INSR, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A43800, 0xFFFFFC00, .SVE, {explicit_count=2} }, { .INSR, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E43800, 0xFFFFFC00, .SVE, {is_64=true, explicit_count=2} }, { .RDSVL, {.X_REG,.IMM_6,.NONE,.NONE}, {.RD,.ENC_IMM6_LO,.NONE,.NONE}, 0x04BF5800, 0xFFFFF800, .SME, {is_64=true, explicit_count=2} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, { .FCMLE, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65512010, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLE, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65912010, 0xFFFFE010, .SVE, {explicit_count=3} }, { .FCMLE, {.P_REG_D,.P_REG_ZERO,.Z_REG_D,.NONE}, {.PD,.PG,.VN,.NONE}, 0x65D12010, 0xFFFFE010, .SVE, {is_64=true, explicit_count=3} }, @@ -614,8 +614,8 @@ DECODE_ENTRIES := [2673]lib.Decode_Entry{ { .BIC, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25004010, 0xFFE0C210, .SVE, {explicit_count=4} }, { .BICS, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true, explicit_count=4} }, { .ORN, {.P_REG_B,.P_REG_ZERO,.P_REG_B,.P_REG_B}, {.PD,.PG4,.PN,.PM}, 0x25804010, 0xFFE0C210, .SVE, {explicit_count=4} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .XAR, {.Z_REG_ANY,.Z_REG_ANY,.Z_REG_ANY,.VEC_SHIFT}, {.VD_TSZ,.VD_TSZ,.VN_TSZ,.SVE_XAR_SHIFT}, 0x04203400, 0xFF20FC00, .SVE2, {explicit_count=4} }, { .FCMEQ, {.P_REG_H,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x65406000, 0xFFE0E010, .SVE, {explicit_count=4} }, { .FCMEQ, {.P_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x65806000, 0xFFE0E010, .SVE, {explicit_count=4} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index aedfd2e53..5d5f20924 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -385,7 +385,7 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .LDR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {explicit_count=2} }, { .LDR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .LDR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .LDR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0x85800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .LDR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1000000, 0xFFE08000, .SME, {explicit_count=2} }, // .STR { .STR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xB9000000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -402,7 +402,7 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .STR, {.D_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Q_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {explicit_count=2} }, { .STR, {.Z_REG_ANY,.MEM_SVE_SI,.NONE,.NONE}, {.VD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5804000, 0xFFE0E000, .SVE, {explicit_count=2} }, - { .STR, {.P_REG,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, + { .STR, {.P_REG_S,.MEM_SVE_SI,.NONE,.NONE}, {.PD,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE5800000, 0xFFE0E010, .SVE, {explicit_count=2} }, { .STR, {.IMM_5,.MEM_SVE_SI,.NONE,.NONE}, {.SVE_IMM5,.SVE_OFFSET_BASE_SI,.NONE,.NONE}, 0xE1200000, 0xFFE08000, .SME, {explicit_count=2} }, // .LDRB { .LDRB, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x39400000, 0xFFC00000, .BASE, {explicit_count=2} }, @@ -2687,9 +2687,9 @@ ENCODE_FORMS := [2671]lib.Encoding{ // .PFALSE { .PFALSE, {.P_REG_B,.NONE,.NONE,.NONE}, {.PD,.NONE,.NONE,.NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {explicit_count=1} }, // .PFIRST - { .PFIRST, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PFIRST, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .PNEXT - { .PNEXT, {.P_REG_B,.P_REG,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, + { .PNEXT, {.P_REG_B,.P_REG_B,.P_REG_B,.NONE}, {.PD,.PN,.PD,.NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {explicit_count=3} }, // .BRKA { .BRKA, {.P_REG_B,.P_REG_MERGE,.P_REG_B,.NONE}, {.PD,.PG4,.PN,.NONE}, 0x25104010, 0xFFFFC210, .SVE, {explicit_count=3} }, // .BRKB @@ -3058,74 +3058,74 @@ ENCODE_FORMS := [2671]lib.Encoding{ { .UQDECD, {.W_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0FC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, { .UQDECD, {.Z_REG_D,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.VD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {explicit_count=3} }, // .CNTP - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, - { .CNTP, {.X_REG,.P_REG_GOV,.P_REG,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_B,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_H,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_S,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, + { .CNTP, {.X_REG,.P_REG_GOV,.P_REG_D,.NONE}, {.RD,.PG,.PN,.NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true, explicit_count=3} }, // .INCP - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .INCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .INCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .INCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .INCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .DECP - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .DECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .DECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .DECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .DECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .SQINCP - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQINCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25288800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25688800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25688000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .SQDECP - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .SQDECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .SQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .UQINCP - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQINCP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25298800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25698800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25698000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQINCP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .UQDECP - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.X_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.W_REG,.P_REG,.NONE,.NONE}, {.RD,.PM,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_H,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_S,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, - { .UQDECP, {.Z_REG_D,.P_REG,.NONE,.NONE}, {.VD,.PM,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.X_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true, explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_B,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_H,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_S,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.W_REG,.P_REG_D,.NONE,.NONE}, {.RD,.PN,.NONE,.NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_H,.P_REG_H,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_S,.P_REG_S,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, + { .UQDECP, {.Z_REG_D,.P_REG_D,.NONE,.NONE}, {.VD,.PN,.NONE,.NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {explicit_count=2} }, // .LD1Q { .LD1Q, {.SME_SLICE_Q,.P_REG_ZERO,.MEM_SVE_SS,.NONE}, {.SME_SLICE_Q,.PG,.SVE_OFFSET_BASE_SS4,.NONE}, 0xE1C00000, 0xFFE00010, .SME, {explicit_count=3} }, // .ST1Q diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 1f4df147d..5c62a1518 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -554,7 +554,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.LDR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD400000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3DC00000, 0xFFC00000, .FP, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85804000, 0xFFE0E000, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, - {{.LDR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, + {{.LDR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0x85800000, 0xFFE0E010, .SVE, {}}, Clobber{written={0}, read={1}, reads_mem=true}}, {{.LDR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1000000, 0xFFE08000, .SME, {}}, Clobber{read={1}, reads_mem=true}}, }, .STR = { @@ -572,7 +572,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.STR, {.D_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0xFD000000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.Q_REG, .MEM_OFFSET, .NONE, .NONE}, {.RT, .OFFSET_BASE_U12, .NONE, .NONE}, 0x3D800000, 0xFFC00000, .FP, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.Z_REG_ANY, .MEM_SVE_SI, .NONE, .NONE}, {.VD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5804000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, - {{.STR, {.P_REG, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, + {{.STR, {.P_REG_S, .MEM_SVE_SI, .NONE, .NONE}, {.PD, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE5800000, 0xFFE0E010, .SVE, {}}, Clobber{read={0, 1}, writes_mem=true}}, {{.STR, {.IMM_5, .MEM_SVE_SI, .NONE, .NONE}, {.SVE_IMM5, .SVE_OFFSET_BASE_SI, .NONE, .NONE}, 0xE1200000, 0xFFE08000, .SME, {}}, Clobber{read={1}, writes_mem=true}}, }, .LDRB = { @@ -3348,10 +3348,10 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.PFALSE, {.P_REG_B, .NONE, .NONE, .NONE}, {.PD, .NONE, .NONE, .NONE}, 0x2518E400, 0xFFFFFFF0, .SVE, {}}, Clobber{written={0}}}, }, .PFIRST = { - {{.PFIRST, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PFIRST, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2558C000, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .PNEXT = { - {{.PNEXT, {.P_REG_B, .P_REG, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, + {{.PNEXT, {.P_REG_B, .P_REG_B, .P_REG_B, .NONE}, {.PD, .PN, .PD, .NONE}, 0x2519C400, 0xFFFFFE10, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, }, .BRKA = { {{.BRKA, {.P_REG_B, .P_REG_MERGE, .P_REG_B, .NONE}, {.PD, .PG4, .PN, .NONE}, 0x25104010, 0xFFFFC210, .SVE, {}}, Clobber{written={0}, read={1, 2}}}, @@ -3824,80 +3824,80 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.UQDECD, {.Z_REG_D, .SVE_PATTERN, .IMM_MUL4, .NONE}, {.VD, .SVE_PATTERN, .IMM_MUL4, .NONE}, 0x04E0CC00, 0xFFF0FC00, .SVE, {}}, Clobber{written={0}, read={0}, fpsr_wr={.QC}}}, }, .CNTP = { - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, - {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_B, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25208020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_H, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25608020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_S, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25A08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, + {{.CNTP, {.X_REG, .P_REG_GOV, .P_REG_D, .NONE}, {.RD, .PG, .PN, .NONE}, 0x25E08020, 0xFFFFE220, .SVE, {is_64=true}}, Clobber{written={0}, read={1, 2}}}, }, .INCP = { - {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.INCP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256C8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EC8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256C8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.INCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EC8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, }, .DECP = { - {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, - {{.DECP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256D8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AD8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25ED8800, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256D8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AD8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, + {{.DECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25ED8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}}}, }, .SQINCP = { - {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25288800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25688800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25688000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQINCP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25288C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25688C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E88C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25288800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25688800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E88800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25688000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25A88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25E88000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .SQDECP = { - {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.SQDECP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256A8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EA8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256A8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EA8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256A8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.SQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EA8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .UQINCP = { - {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25298800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25698800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25698000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQINCP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25298C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25698C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E98C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25298800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25698800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25A98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25E98800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25698000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25A98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQINCP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25E98000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .UQDECP = { - {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.X_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.W_REG, .P_REG, .NONE, .NONE}, {.RD, .PM, .NONE, .NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_H, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_S, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, - {{.UQDECP, {.Z_REG_D, .P_REG, .NONE, .NONE}, {.VD, .PM, .NONE, .NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256B8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.X_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EB8C00, 0xFFFFFE00, .SVE, {is_64=true}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_B, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x252B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_H, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x256B8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_S, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25AB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.W_REG, .P_REG_D, .NONE, .NONE}, {.RD, .PN, .NONE, .NONE}, 0x25EB8800, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_H, .P_REG_H, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x256B8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_S, .P_REG_S, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25AB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, + {{.UQDECP, {.Z_REG_D, .P_REG_D, .NONE, .NONE}, {.VD, .PN, .NONE, .NONE}, 0x25EB8000, 0xFFFFFE00, .SVE, {}}, Clobber{written={0}, read={0, 1}, fpsr_wr={.QC}}}, }, .LD1Q = { {{.LD1Q, {.SME_SLICE_Q, .P_REG_ZERO, .MEM_SVE_SS, .NONE}, {.SME_SLICE_Q, .PG, .SVE_OFFSET_BASE_SS4, .NONE}, 0xE1C00000, 0xFFE00010, .SME, {}}, Clobber{written={0}, read={1, 2}, reads_mem=true}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index a507a901b..caae9aa82 100644 Binary files a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin and b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin differ diff --git a/core/rexcode/isa/arm64/tables/arm64.entries.bin b/core/rexcode/isa/arm64/tables/arm64.entries.bin index b490723b1..2993fafae 100644 Binary files a/core/rexcode/isa/arm64/tables/arm64.entries.bin and b/core/rexcode/isa/arm64/tables/arm64.entries.bin differ