From 29594d1ed444ead3ddd4b45408cbff292795cdcb Mon Sep 17 00:00:00 2001
From: gingerBill <gingerBill@users.noreply.github.com>
Date: Mon, 15 Jun 2026 22:58:06 +0100
Subject: [PATCH] Add to the Encoding_Flags `op_count` and `needs_modrm`

---
 core/rexcode/x86/decoder.odin                 |   21 +-
 core/rexcode/x86/encoding_types.odin          |    6 +-
 core/rexcode/x86/tablegen/gen.odin            |   25 +-
 .../x86/tablegen/generated/decode_tables.odin | 4426 ++++++++---------
 4 files changed, 2246 insertions(+), 2232 deletions(-)

diff --git a/core/rexcode/x86/decoder.odin b/core/rexcode/x86/decoder.odin
index da8ce469e..d66ef36d4 100644
--- a/core/rexcode/x86/decoder.odin
+++ b/core/rexcode/x86/decoder.odin
@@ -573,21 +573,14 @@ decode_opcode_vex :: #force_inline proc(state: ^Decoder_State) -> (entry: ^Decod
 decode_operands :: proc(state: ^Decoder_State, entry: ^Decode_Entry) -> (inst: Instruction, err: Error_Code) {
 	inst.mnemonic = entry.mnemonic
 
-	// Check if we need ModR/M
-	needs_modrm := false
-	for enc in entry.enc {
-		if enc == .MR || enc == .REG || enc == .VVVV {
-			needs_modrm = true
-			break
-		}
-	}
-
 	modrm: u8 = 0
 	modrm_info: ModRM_Info
 	sib: u8 = 0
 	sib_info: SIB_Info
 	has_sib := false
 
+	needs_modrm := entry.flags.needs_modrm
+
 	if needs_modrm {
 		if state.position >= len(state.data) {
 			return {}, .BUFFER_TOO_SHORT
@@ -616,18 +609,16 @@ decode_operands :: proc(state: ^Decoder_State, entry: ^Decode_Entry) -> (inst: I
 	}
 
 	// Decode each operand
-	for op_type, i in entry.ops {
-		if op_type == .NONE {
-			break
-		}
+	op_count := entry.flags.op_count
+	for i in 0..<op_count {
 		op_enc := entry.enc[i]
 
 		// i386: default_64 entries have R64/RM64 operand types but
 		// really mean R32/RM32 in 32-bit mode (same encoded bytes).
-		effective := mode_rewrite_op_type(op_type, state.mode, entry.flags.default_64)
+		effective := mode_rewrite_op_type(entry.ops[i], state.mode, entry.flags.default_64)
 		inst.ops[i] = decode_single_operand(state, effective, op_enc, modrm_info, sib_info, has_sib) or_return
-		inst.operand_count += 1
 	}
+	inst.operand_count += op_count
 
 	return
 }
diff --git a/core/rexcode/x86/encoding_types.odin b/core/rexcode/x86/encoding_types.odin
index 01c70ec1b..fe6ad9ac4 100644
--- a/core/rexcode/x86/encoding_types.odin
+++ b/core/rexcode/x86/encoding_types.odin
@@ -258,8 +258,12 @@ Encoding_Flags :: bit_field u32 {
 	rep_ok:         bool     | 1, // REP prefix valid
 	modrm_reg_ext:  bool     | 1, // ModR/M reg field is opcode extension (use ext field)
 	mode_32_only:   bool     | 1, // only valid in Mode._32 (e.g. short-form INC/DEC at 0x40-0x4F)
-	explicit_count: u8       | 3, // 0..<4 non-implicit operands
+
+	explicit_count: u8       | 2, // 0..<4 non-implicit operands
 	has_implicit:   bool     | 1, // any implicit operand
+
+	op_count:       u8       | 2, // total operands including implicit (0..<4)
+	needs_modrm:    bool     | 1, // any enc is .MR/.REG/.VVVV
 }
 
 // -----------------------------------------------------------------------------
diff --git a/core/rexcode/x86/tablegen/gen.odin b/core/rexcode/x86/tablegen/gen.odin
index 65bf106af..303d9f206 100644
--- a/core/rexcode/x86/tablegen/gen.odin
+++ b/core/rexcode/x86/tablegen/gen.odin
@@ -228,7 +228,7 @@ gen_entries :: proc(sb: ^strings.Builder, name, typ: string, entries: []Collecte
 		strings.write_string(sb, "}, {")
 		for en, i in e.enc { print_enum_buffered(sb, en, 4, i+1 < len(e.enc)) }
 		strings.write_string(sb, "}, ")
-		write_flags(sb, nil, e.flags)
+		write_flags(sb, e, e.flags)
 		strings.write_string(sb, "},\n")
 	}
 	strings.write_string(sb, "}\n\n")
@@ -366,7 +366,7 @@ print_enum_buffered :: proc(sb: ^strings.Builder, x: $T, max_name: int, comma: b
 
 // Complete Encoding_Flags emitter -- every field, so ENCODE_FORMS round-trips
 // the SoT exactly (mode_32_only is read by the encoder).
-write_flags :: proc(sb: ^strings.Builder, enc: Maybe(Encoding), flags: lib.Encoding_Flags) {
+write_flags :: proc(sb: ^strings.Builder, enc: union{lib.Encoding, Collected_Entry}, flags: lib.Encoding_Flags) {
 	parts: [dynamic]string
 	defer delete(parts)
 	if flags.esc != .NONE          { append(&parts, fmt.tprintf("esc=.%v", flags.esc)) }
@@ -382,7 +382,8 @@ write_flags :: proc(sb: ^strings.Builder, enc: Maybe(Encoding), flags: lib.Encod
 	if flags.modrm_reg_ext         { append(&parts, "modrm_reg_ext=true") }
 	if flags.mode_32_only          { append(&parts, "mode_32_only=true") }
 
-	if e, ok := enc.?; ok {
+	switch e in enc {
+	case lib.Encoding:
 		encoding_operand_count: u8 = 0
 		has_implict := false
 		for op_type in e.ops {
@@ -399,6 +400,24 @@ write_flags :: proc(sb: ^strings.Builder, enc: Maybe(Encoding), flags: lib.Encod
 		if has_implict {
 			append(&parts, "has_implict=true")
 		}
+
+	case Collected_Entry:
+		op_count: u8 = 0
+		needs_modrm := false
+		for t, i in e.ops {
+			if t == .NONE { break }
+			op_count += 1
+			enc := e.enc[i]
+			if enc == .MR || enc == .REG || enc == .VVVV {
+				needs_modrm = true
+			}
+		}
+		if op_count > 0 {
+			append(&parts, fmt.tprintf("op_count=%d", op_count))
+		}
+		if needs_modrm {
+			append(&parts, "needs_modrm=true")
+		}
 	}
 
 	strings.write_string(sb, "{")
diff --git a/core/rexcode/x86/tablegen/generated/decode_tables.odin b/core/rexcode/x86/tablegen/generated/decode_tables.odin
index f805b5a7d..4288ed522 100644
--- a/core/rexcode/x86/tablegen/generated/decode_tables.odin
+++ b/core/rexcode/x86/tablegen/generated/decode_tables.odin
@@ -145,237 +145,237 @@ SIB_TABLE := [256]lib.SIB_Info{
 
 @(rodata)
 LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{
-	{.NONE,  0, 0x00, 0xFF, .ADD,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x01, 0xFF, .ADD,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x01, 0xFF, .ADD,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x01, 0xFF, .ADD,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
-	{.NONE,  0, 0x02, 0xFF, .ADD,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x03, 0xFF, .ADD,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x03, 0xFF, .ADD,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x03, 0xFF, .ADD,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x04, 0xFF, .ADD,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x05, 0xFF, .ADD,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x05, 0xFF, .ADD,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x05, 0xFF, .ADD,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x08, 0xFF, .OR,              {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x09, 0xFF, .OR,              {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x09, 0xFF, .OR,              {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
-	{.NONE,  0, 0x09, 0xFF, .OR,              {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x0A, 0xFF, .OR,              {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x0B, 0xFF, .OR,              {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x0B, 0xFF, .OR,              {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x0B, 0xFF, .OR,              {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x0C, 0xFF, .OR,              {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x0D, 0xFF, .OR,              {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x0D, 0xFF, .OR,              {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x0D, 0xFF, .OR,              {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x10, 0xFF, .ADC,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x11, 0xFF, .ADC,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
-	{.NONE,  0, 0x11, 0xFF, .ADC,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x11, 0xFF, .ADC,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x12, 0xFF, .ADC,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x13, 0xFF, .ADC,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x13, 0xFF, .ADC,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x13, 0xFF, .ADC,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x14, 0xFF, .ADC,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x15, 0xFF, .ADC,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x15, 0xFF, .ADC,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x15, 0xFF, .ADC,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x18, 0xFF, .SBB,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x19, 0xFF, .SBB,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x19, 0xFF, .SBB,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x19, 0xFF, .SBB,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
-	{.NONE,  0, 0x1A, 0xFF, .SBB,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x1B, 0xFF, .SBB,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x1B, 0xFF, .SBB,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x1B, 0xFF, .SBB,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x1C, 0xFF, .SBB,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x1D, 0xFF, .SBB,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x1D, 0xFF, .SBB,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x1D, 0xFF, .SBB,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x20, 0xFF, .AND,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x21, 0xFF, .AND,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x21, 0xFF, .AND,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
-	{.NONE,  0, 0x21, 0xFF, .AND,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x22, 0xFF, .AND,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x23, 0xFF, .AND,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x23, 0xFF, .AND,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x23, 0xFF, .AND,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x24, 0xFF, .AND,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x25, 0xFF, .AND,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x25, 0xFF, .AND,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x25, 0xFF, .AND,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x28, 0xFF, .SUB,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x29, 0xFF, .SUB,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
-	{.NONE,  0, 0x29, 0xFF, .SUB,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x29, 0xFF, .SUB,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x2A, 0xFF, .SUB,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x2B, 0xFF, .SUB,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x2B, 0xFF, .SUB,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x2B, 0xFF, .SUB,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x2C, 0xFF, .SUB,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x2D, 0xFF, .SUB,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x2D, 0xFF, .SUB,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x2D, 0xFF, .SUB,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x30, 0xFF, .XOR,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x31, 0xFF, .XOR,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x31, 0xFF, .XOR,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
-	{.NONE,  0, 0x31, 0xFF, .XOR,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x32, 0xFF, .XOR,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x33, 0xFF, .XOR,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x33, 0xFF, .XOR,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x33, 0xFF, .XOR,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x34, 0xFF, .XOR,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x35, 0xFF, .XOR,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x35, 0xFF, .XOR,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x35, 0xFF, .XOR,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x38, 0xFF, .CMP,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {}},
-	{.NONE,  0, 0x39, 0xFF, .CMP,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x39, 0xFF, .CMP,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {}},
-	{.NONE,  0, 0x39, 0xFF, .CMP,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {}},
-	{.NONE,  0, 0x3A, 0xFF, .CMP,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x3B, 0xFF, .CMP,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x3B, 0xFF, .CMP,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x3B, 0xFF, .CMP,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x3C, 0xFF, .CMP,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x3D, 0xFF, .CMP,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x3D, 0xFF, .CMP,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x3D, 0xFF, .CMP,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x40, 0xFF, .INC,             {.R32,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true}},
-	{.NONE,  0, 0x40, 0xFF, .INC,             {.R16,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true}},
-	{.NONE,  0, 0x48, 0xFF, .DEC,             {.R32,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true}},
-	{.NONE,  0, 0x48, 0xFF, .DEC,             {.R16,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true}},
-	{.NONE,  0, 0x50, 0xFF, .PUSH,            {.R16,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x50, 0xFF, .PUSH,            {.R64,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true}},
-	{.NONE,  0, 0x58, 0xFF, .POP,             {.R64,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true}},
-	{.NONE,  0, 0x58, 0xFF, .POP,             {.R16,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x62, 0xFF, .BOUND,           {.R32,       .M32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x62, 0xFF, .BOUND,           {.R16,       .M16_16,    .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x63, 0xFF, .MOVSXD,          {.R64,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x63, 0xFF, .ARPL,            {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {}},
-	{.NONE,  0, 0x68, 0xFF, .PUSH,            {.IMM16,     .NONE,      .NONE,      .NONE}, {.IW,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x68, 0xFF, .PUSH,            {.IMM32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x69, 0xFF, .IMUL,            {.R16,       .RM16,      .IMM16,     .NONE}, {.REG,  .MR,   .IW,   .NONE}, {}},
-	{.NONE,  0, 0x69, 0xFF, .IMUL,            {.R64,       .RM64,      .IMM32,     .NONE}, {.REG,  .MR,   .ID,   .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x69, 0xFF, .IMUL,            {.R32,       .RM32,      .IMM32,     .NONE}, {.REG,  .MR,   .ID,   .NONE}, {}},
-	{.NONE,  0, 0x6A, 0xFF, .PUSH,            {.IMM8SX,    .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x6B, 0xFF, .IMUL,            {.R16,       .RM16,      .IMM8SX,    .NONE}, {.REG,  .MR,   .IB,   .NONE}, {}},
-	{.NONE,  0, 0x6B, 0xFF, .IMUL,            {.R64,       .RM64,      .IMM8SX,    .NONE}, {.REG,  .MR,   .IB,   .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x6B, 0xFF, .IMUL,            {.R32,       .RM32,      .IMM8SX,    .NONE}, {.REG,  .MR,   .IB,   .NONE}, {}},
-	{.NONE,  0, 0x70, 0xFF, .JO,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x71, 0xFF, .JNO,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x72, 0xFF, .JC,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x72, 0xFF, .JB,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x72, 0xFF, .JNAE,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x73, 0xFF, .JAE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x73, 0xFF, .JNB,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x73, 0xFF, .JNC,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x74, 0xFF, .JZ,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x74, 0xFF, .JE,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x75, 0xFF, .JNE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x75, 0xFF, .JNZ,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x76, 0xFF, .JBE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x76, 0xFF, .JNA,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x77, 0xFF, .JNBE,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x77, 0xFF, .JA,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x78, 0xFF, .JS,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x79, 0xFF, .JNS,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7A, 0xFF, .JPE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7A, 0xFF, .JP,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7B, 0xFF, .JPO,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7B, 0xFF, .JNP,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7C, 0xFF, .JL,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7C, 0xFF, .JNGE,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7D, 0xFF, .JNL,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7D, 0xFF, .JGE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7E, 0xFF, .JNG,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7E, 0xFF, .JLE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7F, 0xFF, .JNLE,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x7F, 0xFF, .JG,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x80, 0x00, .ADD,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x80, 0x01, .OR,              {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x80, 0x02, .ADC,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x80, 0x03, .SBB,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x80, 0x04, .AND,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x80, 0x05, .SUB,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x80, 0x06, .XOR,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x80, 0x07, .CMP,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x00, .ADD,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x00, .ADD,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x00, .ADD,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x01, .OR,              {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x01, .OR,              {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x01, .OR,              {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x02, .ADC,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x02, .ADC,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x02, .ADC,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x03, .SBB,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x03, .SBB,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x03, .SBB,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x04, .AND,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x04, .AND,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x04, .AND,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x05, .SUB,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x05, .SUB,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x05, .SUB,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x06, .XOR,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x06, .XOR,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x06, .XOR,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x07, .CMP,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x07, .CMP,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x81, 0x07, .CMP,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x00, .ADD,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x00, .ADD,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x00, .ADD,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x01, .OR,              {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x01, .OR,              {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x01, .OR,              {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x02, .ADC,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x02, .ADC,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x02, .ADC,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x03, .SBB,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x03, .SBB,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x03, .SBB,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x04, .AND,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x04, .AND,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x04, .AND,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x05, .SUB,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x05, .SUB,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x05, .SUB,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x06, .XOR,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x06, .XOR,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x06, .XOR,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x07, .CMP,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x07, .CMP,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x83, 0x07, .CMP,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0x84, 0xFF, .TEST,            {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {}},
-	{.NONE,  0, 0x85, 0xFF, .TEST,            {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x85, 0xFF, .TEST,            {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {}},
-	{.NONE,  0, 0x85, 0xFF, .TEST,            {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {}},
-	{.NONE,  0, 0x86, 0xFF, .XCHG,            {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x87, 0xFF, .XCHG,            {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x87, 0xFF, .XCHG,            {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true}},
-	{.NONE,  0, 0x87, 0xFF, .XCHG,            {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true}},
-	{.NONE,  0, 0x88, 0xFF, .MOV,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {}},
-	{.NONE,  0, 0x89, 0xFF, .MOV,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x89, 0xFF, .MOV,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {}},
-	{.NONE,  0, 0x89, 0xFF, .MOV,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {}},
-	{.NONE,  0, 0x8A, 0xFF, .MOV,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x8B, 0xFF, .MOV,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x8B, 0xFF, .MOV,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x8B, 0xFF, .MOV,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x8C, 0xFF, .MOV,             {.RM64,      .SREG,      .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x8C, 0xFF, .MOV,             {.RM16,      .SREG,      .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {}},
-	{.NONE,  0, 0x8D, 0xFF, .LEA,             {.R64,       .M,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x8D, 0xFF, .LEA,             {.R16,       .M,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x8D, 0xFF, .LEA,             {.R32,       .M,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x8E, 0xFF, .MOV,             {.SREG,      .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0x8E, 0xFF, .MOV,             {.SREG,      .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0x8F, 0x00, .POP,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0x8F, 0x00, .POP,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0x90, 0xFF, .XCHG,            {.EAX_IMPL,  .R32,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x90, 0xFF, .XCHG,            {.AX_IMPL,   .R16,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0x90, 0xFF, .XCHG,            {.RAX_IMPL,  .R64,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {force_rex_w=true}},
+	{.NONE,  0, 0x00, 0xFF, .ADD,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x01, 0xFF, .ADD,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x01, 0xFF, .ADD,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x01, 0xFF, .ADD,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x02, 0xFF, .ADD,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x03, 0xFF, .ADD,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x03, 0xFF, .ADD,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x03, 0xFF, .ADD,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x04, 0xFF, .ADD,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x05, 0xFF, .ADD,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0x05, 0xFF, .ADD,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x05, 0xFF, .ADD,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x08, 0xFF, .OR,              {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x09, 0xFF, .OR,              {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x09, 0xFF, .OR,              {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x09, 0xFF, .OR,              {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x0A, 0xFF, .OR,              {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x0B, 0xFF, .OR,              {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x0B, 0xFF, .OR,              {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x0B, 0xFF, .OR,              {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x0C, 0xFF, .OR,              {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x0D, 0xFF, .OR,              {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0x0D, 0xFF, .OR,              {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x0D, 0xFF, .OR,              {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x10, 0xFF, .ADC,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x11, 0xFF, .ADC,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x11, 0xFF, .ADC,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x11, 0xFF, .ADC,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x12, 0xFF, .ADC,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x13, 0xFF, .ADC,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x13, 0xFF, .ADC,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x13, 0xFF, .ADC,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x14, 0xFF, .ADC,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x15, 0xFF, .ADC,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x15, 0xFF, .ADC,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0x15, 0xFF, .ADC,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x18, 0xFF, .SBB,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x19, 0xFF, .SBB,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x19, 0xFF, .SBB,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x19, 0xFF, .SBB,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x1A, 0xFF, .SBB,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x1B, 0xFF, .SBB,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x1B, 0xFF, .SBB,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x1B, 0xFF, .SBB,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x1C, 0xFF, .SBB,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x1D, 0xFF, .SBB,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0x1D, 0xFF, .SBB,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x1D, 0xFF, .SBB,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x20, 0xFF, .AND,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x21, 0xFF, .AND,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x21, 0xFF, .AND,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x21, 0xFF, .AND,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x22, 0xFF, .AND,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x23, 0xFF, .AND,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x23, 0xFF, .AND,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x23, 0xFF, .AND,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x24, 0xFF, .AND,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x25, 0xFF, .AND,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x25, 0xFF, .AND,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x25, 0xFF, .AND,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0x28, 0xFF, .SUB,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x29, 0xFF, .SUB,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x29, 0xFF, .SUB,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x29, 0xFF, .SUB,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x2A, 0xFF, .SUB,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x2B, 0xFF, .SUB,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x2B, 0xFF, .SUB,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x2B, 0xFF, .SUB,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x2C, 0xFF, .SUB,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x2D, 0xFF, .SUB,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x2D, 0xFF, .SUB,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0x2D, 0xFF, .SUB,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x30, 0xFF, .XOR,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x31, 0xFF, .XOR,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x31, 0xFF, .XOR,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x31, 0xFF, .XOR,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x32, 0xFF, .XOR,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x33, 0xFF, .XOR,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x33, 0xFF, .XOR,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x33, 0xFF, .XOR,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x34, 0xFF, .XOR,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x35, 0xFF, .XOR,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x35, 0xFF, .XOR,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0x35, 0xFF, .XOR,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x38, 0xFF, .CMP,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x39, 0xFF, .CMP,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x39, 0xFF, .CMP,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x39, 0xFF, .CMP,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x3A, 0xFF, .CMP,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x3B, 0xFF, .CMP,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x3B, 0xFF, .CMP,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x3B, 0xFF, .CMP,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x3C, 0xFF, .CMP,             {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x3D, 0xFF, .CMP,             {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x3D, 0xFF, .CMP,             {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0x3D, 0xFF, .CMP,             {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x40, 0xFF, .INC,             {.R32,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}},
+	{.NONE,  0, 0x40, 0xFF, .INC,             {.R16,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}},
+	{.NONE,  0, 0x48, 0xFF, .DEC,             {.R32,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}},
+	{.NONE,  0, 0x48, 0xFF, .DEC,             {.R16,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}},
+	{.NONE,  0, 0x50, 0xFF, .PUSH,            {.R16,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x50, 0xFF, .PUSH,            {.R64,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}},
+	{.NONE,  0, 0x58, 0xFF, .POP,             {.R64,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}},
+	{.NONE,  0, 0x58, 0xFF, .POP,             {.R16,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x62, 0xFF, .BOUND,           {.R32,       .M32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x62, 0xFF, .BOUND,           {.R16,       .M16_16,    .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x63, 0xFF, .MOVSXD,          {.R64,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x63, 0xFF, .ARPL,            {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x68, 0xFF, .PUSH,            {.IMM16,     .NONE,      .NONE,      .NONE}, {.IW,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x68, 0xFF, .PUSH,            {.IMM32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x69, 0xFF, .IMUL,            {.R16,       .RM16,      .IMM16,     .NONE}, {.REG,  .MR,   .IW,   .NONE}, {op_count=3, needs_modrm=true}},
+	{.NONE,  0, 0x69, 0xFF, .IMUL,            {.R64,       .RM64,      .IMM32,     .NONE}, {.REG,  .MR,   .ID,   .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}},
+	{.NONE,  0, 0x69, 0xFF, .IMUL,            {.R32,       .RM32,      .IMM32,     .NONE}, {.REG,  .MR,   .ID,   .NONE}, {op_count=3, needs_modrm=true}},
+	{.NONE,  0, 0x6A, 0xFF, .PUSH,            {.IMM8SX,    .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x6B, 0xFF, .IMUL,            {.R16,       .RM16,      .IMM8SX,    .NONE}, {.REG,  .MR,   .IB,   .NONE}, {op_count=3, needs_modrm=true}},
+	{.NONE,  0, 0x6B, 0xFF, .IMUL,            {.R64,       .RM64,      .IMM8SX,    .NONE}, {.REG,  .MR,   .IB,   .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}},
+	{.NONE,  0, 0x6B, 0xFF, .IMUL,            {.R32,       .RM32,      .IMM8SX,    .NONE}, {.REG,  .MR,   .IB,   .NONE}, {op_count=3, needs_modrm=true}},
+	{.NONE,  0, 0x70, 0xFF, .JO,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x71, 0xFF, .JNO,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x72, 0xFF, .JC,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x72, 0xFF, .JB,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x72, 0xFF, .JNAE,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x73, 0xFF, .JAE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x73, 0xFF, .JNB,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x73, 0xFF, .JNC,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x74, 0xFF, .JZ,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x74, 0xFF, .JE,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x75, 0xFF, .JNE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x75, 0xFF, .JNZ,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x76, 0xFF, .JBE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x76, 0xFF, .JNA,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x77, 0xFF, .JNBE,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x77, 0xFF, .JA,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x78, 0xFF, .JS,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x79, 0xFF, .JNS,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7A, 0xFF, .JPE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7A, 0xFF, .JP,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7B, 0xFF, .JPO,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7B, 0xFF, .JNP,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7C, 0xFF, .JL,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7C, 0xFF, .JNGE,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7D, 0xFF, .JNL,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7D, 0xFF, .JGE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7E, 0xFF, .JNG,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7E, 0xFF, .JLE,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7F, 0xFF, .JNLE,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x7F, 0xFF, .JG,              {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0x80, 0x00, .ADD,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x80, 0x01, .OR,              {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x80, 0x02, .ADC,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x80, 0x03, .SBB,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x80, 0x04, .AND,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x80, 0x05, .SUB,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x80, 0x06, .XOR,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x80, 0x07, .CMP,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x00, .ADD,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x00, .ADD,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x00, .ADD,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x01, .OR,              {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x01, .OR,              {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x01, .OR,              {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x02, .ADC,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x02, .ADC,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x02, .ADC,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x03, .SBB,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x03, .SBB,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x03, .SBB,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x04, .AND,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x04, .AND,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x04, .AND,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x05, .SUB,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x05, .SUB,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x05, .SUB,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x06, .XOR,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x06, .XOR,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x06, .XOR,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x07, .CMP,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x07, .CMP,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x81, 0x07, .CMP,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x00, .ADD,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x00, .ADD,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x00, .ADD,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x01, .OR,              {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x01, .OR,              {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x01, .OR,              {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x02, .ADC,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x02, .ADC,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x02, .ADC,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x03, .SBB,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x03, .SBB,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x03, .SBB,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x04, .AND,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x04, .AND,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x04, .AND,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x05, .SUB,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x05, .SUB,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x05, .SUB,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x06, .XOR,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x06, .XOR,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x06, .XOR,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x07, .CMP,             {.RM32,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x07, .CMP,             {.RM64,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x83, 0x07, .CMP,             {.RM16,      .IMM8SX,    .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x84, 0xFF, .TEST,            {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x85, 0xFF, .TEST,            {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x85, 0xFF, .TEST,            {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x85, 0xFF, .TEST,            {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x86, 0xFF, .XCHG,            {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x87, 0xFF, .XCHG,            {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x87, 0xFF, .XCHG,            {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x87, 0xFF, .XCHG,            {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x88, 0xFF, .MOV,             {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x89, 0xFF, .MOV,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x89, 0xFF, .MOV,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x89, 0xFF, .MOV,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8A, 0xFF, .MOV,             {.R8,        .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8B, 0xFF, .MOV,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8B, 0xFF, .MOV,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8B, 0xFF, .MOV,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8C, 0xFF, .MOV,             {.RM64,      .SREG,      .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8C, 0xFF, .MOV,             {.RM16,      .SREG,      .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8D, 0xFF, .LEA,             {.R64,       .M,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8D, 0xFF, .LEA,             {.R16,       .M,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8D, 0xFF, .LEA,             {.R32,       .M,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8E, 0xFF, .MOV,             {.SREG,      .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8E, 0xFF, .MOV,             {.SREG,      .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0x8F, 0x00, .POP,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0x8F, 0x00, .POP,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0x90, 0xFF, .XCHG,            {.EAX_IMPL,  .R32,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x90, 0xFF, .XCHG,            {.AX_IMPL,   .R16,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0x90, 0xFF, .XCHG,            {.RAX_IMPL,  .R64,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {force_rex_w=true, op_count=2}},
 	{.NONE,  0, 0x90, 0xFF, .NOP,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0x98, 0xFF, .CDQE,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}},
 	{.NONE,  0, 0x98, 0xFF, .CWDE,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
@@ -393,22 +393,22 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{
 	{.NONE,  0, 0x9D, 0xFF, .POPFD,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0x9E, 0xFF, .SAHF,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0x9F, 0xFF, .LAHF,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA0, 0xFF, .MOVABS,          {.AL_IMPL,   .MOFFS8,    .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA0, 0xFF, .MOV,             {.AL_IMPL,   .MOFFS8,    .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA1, 0xFF, .MOVABS,          {.EAX_IMPL,  .MOFFS32,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA1, 0xFF, .MOVABS,          {.AX_IMPL,   .MOFFS16,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA1, 0xFF, .MOVABS,          {.RAX_IMPL,  .MOFFS64,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0xA1, 0xFF, .MOV,             {.EAX_IMPL,  .MOFFS32,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA1, 0xFF, .MOV,             {.AX_IMPL,   .MOFFS16,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA1, 0xFF, .MOV,             {.RAX_IMPL,  .MOFFS64,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0xA2, 0xFF, .MOVABS,          {.MOFFS8,    .AL_IMPL,   .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA2, 0xFF, .MOV,             {.MOFFS8,    .AL_IMPL,   .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA3, 0xFF, .MOVABS,          {.MOFFS16,   .AX_IMPL,   .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA3, 0xFF, .MOVABS,          {.MOFFS64,   .RAX_IMPL,  .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0xA3, 0xFF, .MOVABS,          {.MOFFS32,   .EAX_IMPL,  .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA3, 0xFF, .MOV,             {.MOFFS16,   .AX_IMPL,   .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA3, 0xFF, .MOV,             {.MOFFS32,   .EAX_IMPL,  .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA3, 0xFF, .MOV,             {.MOFFS64,   .RAX_IMPL,  .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {force_rex_w=true}},
+	{.NONE,  0, 0xA0, 0xFF, .MOVABS,          {.AL_IMPL,   .MOFFS8,    .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA0, 0xFF, .MOV,             {.AL_IMPL,   .MOFFS8,    .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA1, 0xFF, .MOVABS,          {.EAX_IMPL,  .MOFFS32,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA1, 0xFF, .MOVABS,          {.AX_IMPL,   .MOFFS16,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA1, 0xFF, .MOVABS,          {.RAX_IMPL,  .MOFFS64,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0xA1, 0xFF, .MOV,             {.EAX_IMPL,  .MOFFS32,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA1, 0xFF, .MOV,             {.AX_IMPL,   .MOFFS16,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA1, 0xFF, .MOV,             {.RAX_IMPL,  .MOFFS64,   .NONE,      .NONE}, {.IMPL, .IQ,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0xA2, 0xFF, .MOVABS,          {.MOFFS8,    .AL_IMPL,   .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA2, 0xFF, .MOV,             {.MOFFS8,    .AL_IMPL,   .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA3, 0xFF, .MOVABS,          {.MOFFS16,   .AX_IMPL,   .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA3, 0xFF, .MOVABS,          {.MOFFS64,   .RAX_IMPL,  .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0xA3, 0xFF, .MOVABS,          {.MOFFS32,   .EAX_IMPL,  .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA3, 0xFF, .MOV,             {.MOFFS16,   .AX_IMPL,   .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA3, 0xFF, .MOV,             {.MOFFS32,   .EAX_IMPL,  .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA3, 0xFF, .MOV,             {.MOFFS64,   .RAX_IMPL,  .NONE,      .NONE}, {.IQ,   .IMPL, .NONE, .NONE}, {force_rex_w=true, op_count=2}},
 	{.NONE,  0, 0xA4, 0xFF, .MOVS,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
 	{.NONE,  0, 0xA4, 0xFF, .MOVSB,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
 	{.NONE,  0, 0xA5, 0xFF, .MOVSQ,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}},
@@ -419,10 +419,10 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{
 	{.NONE,  0, 0xA7, 0xFF, .CMPSD,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
 	{.NONE,  0, 0xA7, 0xFF, .CMPSQ,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}},
 	{.NONE,  0, 0xA7, 0xFF, .CMPSW,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
-	{.NONE,  0, 0xA8, 0xFF, .TEST,            {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA9, 0xFF, .TEST,            {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA9, 0xFF, .TEST,            {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xA9, 0xFF, .TEST,            {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true}},
+	{.NONE,  0, 0xA8, 0xFF, .TEST,            {.AL_IMPL,   .IMM8,      .NONE,      .NONE}, {.IMPL, .IB,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA9, 0xFF, .TEST,            {.EAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA9, 0xFF, .TEST,            {.AX_IMPL,   .IMM16,     .NONE,      .NONE}, {.IMPL, .IW,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xA9, 0xFF, .TEST,            {.RAX_IMPL,  .IMM32,     .NONE,      .NONE}, {.IMPL, .ID,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
 	{.NONE,  0, 0xAA, 0xFF, .STOS,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
 	{.NONE,  0, 0xAA, 0xFF, .STOSB,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
 	{.NONE,  0, 0xAB, 0xFF, .STOSQ,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}},
@@ -438,137 +438,137 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{
 	{.NONE,  0, 0xAF, 0xFF, .SCASQ,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}},
 	{.NONE,  0, 0xAF, 0xFF, .SCASW,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
 	{.NONE,  0, 0xAF, 0xFF, .SCASD,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}},
-	{.NONE,  0, 0xB0, 0xFF, .MOV,             {.R8,        .IMM8,      .NONE,      .NONE}, {.OP_R, .IB,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xB8, 0xFF, .MOVABS,          {.R64,       .IMM64,     .NONE,      .NONE}, {.OP_R, .IQ,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0xB8, 0xFF, .MOV,             {.R32,       .IMM32,     .NONE,      .NONE}, {.OP_R, .ID,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xB8, 0xFF, .MOV,             {.R16,       .IMM16,     .NONE,      .NONE}, {.OP_R, .IW,   .NONE, .NONE}, {}},
-	{.NONE,  0, 0xB8, 0xFF, .MOV,             {.R64,       .IMM64,     .NONE,      .NONE}, {.OP_R, .IQ,   .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0xC0, 0x00, .ROL,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC0, 0x01, .ROR,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC0, 0x02, .RCL,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC0, 0x03, .RCR,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC0, 0x04, .SHL,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC0, 0x05, .SHR,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC0, 0x07, .SAR,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x00, .ROL,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x00, .ROL,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x00, .ROL,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x01, .ROR,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x01, .ROR,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x01, .ROR,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x02, .RCL,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x02, .RCL,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x02, .RCL,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x03, .RCR,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x03, .RCR,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x03, .RCR,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x04, .SHL,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x04, .SHL,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x04, .SHL,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x05, .SHR,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x05, .SHR,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x05, .SHR,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x07, .SAR,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x07, .SAR,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC1, 0x07, .SAR,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xC2, 0xFF, .RET,             {.IMM16,     .NONE,      .NONE,      .NONE}, {.IW,   .NONE, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xB0, 0xFF, .MOV,             {.R8,        .IMM8,      .NONE,      .NONE}, {.OP_R, .IB,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xB8, 0xFF, .MOVABS,          {.R64,       .IMM64,     .NONE,      .NONE}, {.OP_R, .IQ,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0xB8, 0xFF, .MOV,             {.R32,       .IMM32,     .NONE,      .NONE}, {.OP_R, .ID,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xB8, 0xFF, .MOV,             {.R16,       .IMM16,     .NONE,      .NONE}, {.OP_R, .IW,   .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xB8, 0xFF, .MOV,             {.R64,       .IMM64,     .NONE,      .NONE}, {.OP_R, .IQ,   .NONE, .NONE}, {force_rex_w=true, op_count=2}},
+	{.NONE,  0, 0xC0, 0x00, .ROL,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC0, 0x01, .ROR,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC0, 0x02, .RCL,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC0, 0x03, .RCR,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC0, 0x04, .SHL,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC0, 0x05, .SHR,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC0, 0x07, .SAR,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x00, .ROL,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x00, .ROL,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x00, .ROL,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x01, .ROR,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x01, .ROR,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x01, .ROR,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x02, .RCL,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x02, .RCL,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x02, .RCL,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x03, .RCR,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x03, .RCR,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x03, .RCR,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x04, .SHL,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x04, .SHL,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x04, .SHL,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x05, .SHR,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x05, .SHR,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x05, .SHR,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x07, .SAR,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x07, .SAR,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC1, 0x07, .SAR,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC2, 0xFF, .RET,             {.IMM16,     .NONE,      .NONE,      .NONE}, {.IW,   .NONE, .NONE, .NONE}, {op_count=1}},
 	{.NONE,  0, 0xC3, 0xFF, .RET,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xC6, 0x00, .MOV,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC7, 0x00, .MOV,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xC7, 0x00, .MOV,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC7, 0x00, .MOV,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xC8, 0xFF, .ENTER,           {.IMM16,     .IMM8,      .NONE,      .NONE}, {.IW,   .IB,   .NONE, .NONE}, {}},
+	{.NONE,  0, 0xC6, 0x00, .MOV,             {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC7, 0x00, .MOV,             {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC7, 0x00, .MOV,             {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC7, 0x00, .MOV,             {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xC8, 0xFF, .ENTER,           {.IMM16,     .IMM8,      .NONE,      .NONE}, {.IW,   .IB,   .NONE, .NONE}, {op_count=2}},
 	{.NONE,  0, 0xC9, 0xFF, .LEAVE,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xCC, 0xFF, .INT3,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xCD, 0xFF, .INT,             {.IMM8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xCD, 0xFF, .INT,             {.IMM8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
 	{.NONE,  0, 0xCE, 0xFF, .INTO,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xCF, 0xFF, .IRETQ,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}},
 	{.NONE,  0, 0xCF, 0xFF, .IRETD,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xCF, 0xFF, .IRET,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD0, 0x00, .ROL,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD0, 0x01, .ROR,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD0, 0x02, .RCL,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD0, 0x03, .RCR,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD0, 0x04, .SHL,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD0, 0x05, .SHR,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD0, 0x07, .SAR,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x00, .ROL,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x00, .ROL,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x00, .ROL,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x01, .ROR,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x01, .ROR,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x01, .ROR,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x02, .RCL,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x02, .RCL,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x02, .RCL,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x03, .RCR,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x03, .RCR,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x03, .RCR,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x04, .SHL,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x04, .SHL,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x04, .SHL,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x05, .SHR,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x05, .SHR,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x05, .SHR,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x07, .SAR,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x07, .SAR,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD1, 0x07, .SAR,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD2, 0x00, .ROL,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD2, 0x01, .ROR,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD2, 0x02, .RCL,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD2, 0x03, .RCR,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD2, 0x04, .SHL,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD2, 0x05, .SHR,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD2, 0x07, .SAR,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x00, .ROL,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x00, .ROL,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x00, .ROL,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x01, .ROR,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x01, .ROR,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x01, .ROR,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x02, .RCL,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x02, .RCL,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x02, .RCL,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x03, .RCR,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x03, .RCR,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x03, .RCR,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x04, .SHL,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x04, .SHL,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x04, .SHL,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x05, .SHR,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x05, .SHR,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x05, .SHR,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x07, .SAR,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x07, .SAR,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD3, 0x07, .SAR,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
+	{.NONE,  0, 0xD0, 0x00, .ROL,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD0, 0x01, .ROR,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD0, 0x02, .RCL,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD0, 0x03, .RCR,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD0, 0x04, .SHL,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD0, 0x05, .SHR,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD0, 0x07, .SAR,             {.RM8,       .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x00, .ROL,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x00, .ROL,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x00, .ROL,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x01, .ROR,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x01, .ROR,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x01, .ROR,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x02, .RCL,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x02, .RCL,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x02, .RCL,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x03, .RCR,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x03, .RCR,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x03, .RCR,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x04, .SHL,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x04, .SHL,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x04, .SHL,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x05, .SHR,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x05, .SHR,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x05, .SHR,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x07, .SAR,             {.RM64,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x07, .SAR,             {.RM16,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD1, 0x07, .SAR,             {.RM32,      .ONE_IMPL,  .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD2, 0x00, .ROL,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD2, 0x01, .ROR,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD2, 0x02, .RCL,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD2, 0x03, .RCR,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD2, 0x04, .SHL,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD2, 0x05, .SHR,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD2, 0x07, .SAR,             {.RM8,       .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x00, .ROL,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x00, .ROL,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x00, .ROL,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x01, .ROR,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x01, .ROR,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x01, .ROR,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x02, .RCL,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x02, .RCL,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x02, .RCL,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x03, .RCR,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x03, .RCR,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x03, .RCR,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x04, .SHL,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x04, .SHL,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x04, .SHL,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x05, .SHR,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x05, .SHR,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x05, .SHR,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x07, .SAR,             {.RM32,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x07, .SAR,             {.RM16,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xD3, 0x07, .SAR,             {.RM64,      .CL_IMPL,   .NONE,      .NONE}, {.MR,   .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
 	{.NONE,  0, 0xD7, 0xFF, .XLATB,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD7, 0xFF, .XLAT,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD8, 0x01, .FMUL,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD8, 0x02, .FCOM,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD8, 0x03, .FCOMP,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD8, 0x04, .FSUB,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD8, 0x05, .FSUBR,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD8, 0x06, .FDIV,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD8, 0x07, .FDIVR,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD8, 0xFF, .FSUB,            {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xD8, 0x01, .FMUL,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD8, 0x02, .FCOM,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD8, 0x03, .FCOMP,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD8, 0x04, .FSUB,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD8, 0x05, .FSUBR,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD8, 0x06, .FDIV,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD8, 0x07, .FDIVR,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD8, 0xFF, .FSUB,            {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
 	{.NONE,  0, 0xD8, 0xFF, .FCOMP,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD8, 0xFF, .FCOM,            {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD8, 0xFF, .FDIVR,           {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD8, 0xFF, .FDIV,            {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD8, 0xFF, .FMUL,            {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD8, 0xFF, .FCOMP,           {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD8, 0xFF, .FSUBR,           {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD8, 0xFF, .FADD,            {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xD8, 0xFF, .FCOM,            {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xD8, 0xFF, .FDIVR,           {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xD8, 0xFF, .FDIV,            {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xD8, 0xFF, .FMUL,            {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xD8, 0xFF, .FCOMP,           {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xD8, 0xFF, .FSUBR,           {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xD8, 0xFF, .FADD,            {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
 	{.NONE,  0, 0xD8, 0xFF, .FCOM,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD8, 0xFF, .FADD,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD9, 0x02, .FST,             {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD9, 0x03, .FSTP,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD9, 0x04, .FLDENV,          {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD9, 0x05, .FLDCW,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD9, 0x06, .FNSTENV,         {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD9, 0x06, .FSTENV,          {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD9, 0x07, .FNSTCW,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xD9, 0x07, .FSTCW,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
+	{.NONE,  0, 0xD8, 0xFF, .FADD,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD9, 0x02, .FST,             {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD9, 0x03, .FSTP,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD9, 0x04, .FLDENV,          {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD9, 0x05, .FLDCW,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD9, 0x06, .FNSTENV,         {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD9, 0x06, .FSTENV,          {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD9, 0x07, .FNSTCW,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xD9, 0x07, .FSTCW,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
 	{.NONE,  0, 0xD9, 0xFF, .FYL2X,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FLDL2E,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FYL2XP1,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
@@ -576,7 +576,7 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{
 	{.NONE,  0, 0xD9, 0xFF, .FXTRACT,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FCOS,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FLD1,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD9, 0xFF, .FLD,             {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xD9, 0xFF, .FLD,             {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}},
 	{.NONE,  0, 0xD9, 0xFF, .FINCSTP,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FNOP,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FSINCOS,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
@@ -586,7 +586,7 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{
 	{.NONE,  0, 0xD9, 0xFF, .F2XM1,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FCHS,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FPREM,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD9, 0xFF, .FLD,             {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xD9, 0xFF, .FLD,             {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
 	{.NONE,  0, 0xD9, 0xFF, .FSCALE,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FABS,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FSIN,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
@@ -597,191 +597,191 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{
 	{.NONE,  0, 0xD9, 0xFF, .FPTAN,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FSQRT,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FLDL2T,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xD9, 0xFF, .FXCH,            {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xD9, 0xFF, .FXCH,            {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
 	{.NONE,  0, 0xD9, 0xFF, .FRNDINT,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FLDLG2,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xD9, 0xFF, .FDECSTP,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDA, 0x01, .FIMUL,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDA, 0x02, .FICOM,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDA, 0x03, .FICOMP,          {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDA, 0x04, .FISUB,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDA, 0x05, .FISUBR,          {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDA, 0x06, .FIDIV,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDA, 0x07, .FIDIVR,          {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDA, 0xFF, .FCMOVB,          {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xDA, 0x01, .FIMUL,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDA, 0x02, .FICOM,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDA, 0x03, .FICOMP,          {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDA, 0x04, .FISUB,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDA, 0x05, .FISUBR,          {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDA, 0x06, .FIDIV,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDA, 0x07, .FIDIVR,          {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDA, 0xFF, .FCMOVB,          {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
 	{.NONE,  0, 0xDA, 0xFF, .FUCOMPP,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDA, 0xFF, .FIADD,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDA, 0xFF, .FCMOVBE,         {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDA, 0xFF, .FCMOVU,          {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDA, 0xFF, .FCMOVE,          {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDB, 0x01, .FISTTP,          {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDB, 0x02, .FIST,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDB, 0x03, .FISTP,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDB, 0x05, .FLD,             {.M80,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDB, 0x07, .FSTP,            {.M80,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDB, 0xFF, .FCMOVNU,         {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDB, 0xFF, .FCMOVNB,         {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xDA, 0xFF, .FIADD,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDA, 0xFF, .FCMOVBE,         {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDA, 0xFF, .FCMOVU,          {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDA, 0xFF, .FCMOVE,          {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDB, 0x01, .FISTTP,          {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDB, 0x02, .FIST,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDB, 0x03, .FISTP,           {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDB, 0x05, .FLD,             {.M80,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDB, 0x07, .FSTP,            {.M80,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDB, 0xFF, .FCMOVNU,         {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDB, 0xFF, .FCMOVNB,         {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
 	{.NONE,  0, 0xDB, 0xFF, .FNCLEX,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xDB, 0xFF, .FNINIT,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDB, 0xFF, .FILD,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xDB, 0xFF, .FILD,            {.M32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}},
 	{.NONE,  0, 0xDB, 0xFF, .FINIT,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xDB, 0xFF, .FCLEX,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDB, 0xFF, .FCOMI,           {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDB, 0xFF, .FUCOMI,          {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDB, 0xFF, .FCMOVNBE,        {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDB, 0xFF, .FCMOVNE,         {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDC, 0x01, .FMUL,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDC, 0x02, .FCOM,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDC, 0x03, .FCOMP,           {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDC, 0x04, .FSUB,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDC, 0x05, .FSUBR,           {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDC, 0x06, .FDIV,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDC, 0x07, .FDIVR,           {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDC, 0xFF, .FDIV,            {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDC, 0xFF, .FSUBR,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDC, 0xFF, .FDIVR,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDC, 0xFF, .FSUB,            {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDC, 0xFF, .FMUL,            {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDC, 0xFF, .FADD,            {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDC, 0xFF, .FADD,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDD, 0x01, .FISTTP,          {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDD, 0x02, .FST,             {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDD, 0x03, .FSTP,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDD, 0x04, .FRSTOR,          {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDD, 0x06, .FSAVE,           {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDD, 0x06, .FNSAVE,          {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDD, 0x07, .FSTSW,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDD, 0x07, .FNSTSW,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDD, 0xFF, .FST,             {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDD, 0xFF, .FFREE,           {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDD, 0xFF, .FSTP,            {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDD, 0xFF, .FLD,             {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDD, 0xFF, .FUCOMP,          {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xDB, 0xFF, .FCOMI,           {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDB, 0xFF, .FUCOMI,          {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDB, 0xFF, .FCMOVNBE,        {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDB, 0xFF, .FCMOVNE,         {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDC, 0x01, .FMUL,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDC, 0x02, .FCOM,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDC, 0x03, .FCOMP,           {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDC, 0x04, .FSUB,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDC, 0x05, .FSUBR,           {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDC, 0x06, .FDIV,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDC, 0x07, .FDIVR,           {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDC, 0xFF, .FDIV,            {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDC, 0xFF, .FSUBR,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDC, 0xFF, .FDIVR,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDC, 0xFF, .FSUB,            {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDC, 0xFF, .FMUL,            {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDC, 0xFF, .FADD,            {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDC, 0xFF, .FADD,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDD, 0x01, .FISTTP,          {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDD, 0x02, .FST,             {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDD, 0x03, .FSTP,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDD, 0x04, .FRSTOR,          {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDD, 0x06, .FSAVE,           {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDD, 0x06, .FNSAVE,          {.M,         .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDD, 0x07, .FSTSW,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDD, 0x07, .FNSTSW,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDD, 0xFF, .FST,             {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xDD, 0xFF, .FFREE,           {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xDD, 0xFF, .FSTP,            {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xDD, 0xFF, .FLD,             {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDD, 0xFF, .FUCOMP,          {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
 	{.NONE,  0, 0xDD, 0xFF, .FUCOMP,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDD, 0xFF, .FUCOM,           {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xDD, 0xFF, .FUCOM,           {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
 	{.NONE,  0, 0xDD, 0xFF, .FUCOM,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDE, 0x01, .FIMUL,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDE, 0x02, .FICOM,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDE, 0x03, .FICOMP,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDE, 0x04, .FISUB,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDE, 0x05, .FISUBR,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDE, 0x06, .FIDIV,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDE, 0x07, .FIDIVR,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
+	{.NONE,  0, 0xDE, 0x01, .FIMUL,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDE, 0x02, .FICOM,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDE, 0x03, .FICOMP,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDE, 0x04, .FISUB,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDE, 0x05, .FISUBR,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDE, 0x06, .FIDIV,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDE, 0x07, .FIDIVR,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
 	{.NONE,  0, 0xDE, 0xFF, .FSUBRP,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDE, 0xFF, .FSUBP,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xDE, 0xFF, .FSUBP,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
 	{.NONE,  0, 0xDE, 0xFF, .FADDP,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xDE, 0xFF, .FDIVRP,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDE, 0xFF, .FADDP,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDE, 0xFF, .FIADD,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xDE, 0xFF, .FADDP,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDE, 0xFF, .FIADD,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}},
 	{.NONE,  0, 0xDE, 0xFF, .FCOMPP,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDE, 0xFF, .FSUBRP,          {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDE, 0xFF, .FMULP,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDE, 0xFF, .FDIVRP,          {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xDE, 0xFF, .FSUBRP,          {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDE, 0xFF, .FMULP,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDE, 0xFF, .FDIVRP,          {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
 	{.NONE,  0, 0xDE, 0xFF, .FSUBP,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xDE, 0xFF, .FMULP,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xDE, 0xFF, .FDIVP,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDE, 0xFF, .FDIVP,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDF, 0x01, .FISTTP,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDF, 0x02, .FIST,            {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDF, 0x03, .FISTP,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDF, 0x04, .FBLD,            {.M80,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDF, 0x05, .FILD,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDF, 0x06, .FBSTP,           {.M80,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDF, 0x07, .FISTP,           {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xDF, 0xFF, .FFREEP,          {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDF, 0xFF, .FUCOMIP,         {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDF, 0xFF, .FSTSW,           {.AX_IMPL,   .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDF, 0xFF, .FCOMIP,          {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDF, 0xFF, .FILD,            {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xDF, 0xFF, .FNSTSW,          {.AX_IMPL,   .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xE0, 0xFF, .LOOPNE,          {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xE1, 0xFF, .LOOPE,           {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xE2, 0xFF, .LOOP,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xE3, 0xFF, .JCXZ,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xE3, 0xFF, .JECXZ,           {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xE3, 0xFF, .JRCXZ,           {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {force_rex_w=true}},
-	{.NONE,  0, 0xE8, 0xFF, .CALL,            {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xE9, 0xFF, .JMP,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xEB, 0xFF, .JMP,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {}},
+	{.NONE,  0, 0xDE, 0xFF, .FDIVP,           {.STI,       .ST0_IMPL,  .NONE,      .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDF, 0x01, .FISTTP,          {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDF, 0x02, .FIST,            {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDF, 0x03, .FISTP,           {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDF, 0x04, .FBLD,            {.M80,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDF, 0x05, .FILD,            {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDF, 0x06, .FBSTP,           {.M80,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDF, 0x07, .FISTP,           {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDF, 0xFF, .FFREEP,          {.STI,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xDF, 0xFF, .FUCOMIP,         {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDF, 0xFF, .FSTSW,           {.AX_IMPL,   .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xDF, 0xFF, .FCOMIP,          {.ST0_IMPL,  .STI,       .NONE,      .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}},
+	{.NONE,  0, 0xDF, 0xFF, .FILD,            {.M16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xDF, 0xFF, .FNSTSW,          {.AX_IMPL,   .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xE0, 0xFF, .LOOPNE,          {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xE1, 0xFF, .LOOPE,           {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xE2, 0xFF, .LOOP,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xE3, 0xFF, .JCXZ,            {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xE3, 0xFF, .JECXZ,           {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xE3, 0xFF, .JRCXZ,           {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {force_rex_w=true, op_count=1}},
+	{.NONE,  0, 0xE8, 0xFF, .CALL,            {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xE9, 0xFF, .JMP,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {op_count=1}},
+	{.NONE,  0, 0xEB, 0xFF, .JMP,             {.REL8,      .NONE,      .NONE,      .NONE}, {.IB,   .NONE, .NONE, .NONE}, {op_count=1}},
 	{.NONE,  0, 0xF0, 0xFF, .LOCK,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xF4, 0xFF, .HLT,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xF5, 0xFF, .CMC,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xF6, 0x00, .TEST,            {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF6, 0x02, .NOT,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF6, 0x03, .NEG,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF6, 0x04, .MUL,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF6, 0x05, .IMUL,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF6, 0x06, .DIV,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF6, 0x07, .IDIV,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x00, .TEST,            {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x00, .TEST,            {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x00, .TEST,            {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x02, .NOT,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x02, .NOT,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x02, .NOT,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x03, .NEG,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x03, .NEG,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x03, .NEG,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x04, .MUL,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x04, .MUL,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x04, .MUL,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x05, .IMUL,            {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x05, .IMUL,            {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x05, .IMUL,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x06, .DIV,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x06, .DIV,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x06, .DIV,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x07, .IDIV,            {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x07, .IDIV,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xF7, 0x07, .IDIV,            {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
+	{.NONE,  0, 0xF6, 0x00, .TEST,            {.RM8,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xF6, 0x02, .NOT,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF6, 0x03, .NEG,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF6, 0x04, .MUL,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF6, 0x05, .IMUL,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF6, 0x06, .DIV,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF6, 0x07, .IDIV,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x00, .TEST,            {.RM16,      .IMM16,     .NONE,      .NONE}, {.MR,   .IW,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x00, .TEST,            {.RM32,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x00, .TEST,            {.RM64,      .IMM32,     .NONE,      .NONE}, {.MR,   .ID,   .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x02, .NOT,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x02, .NOT,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x02, .NOT,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x03, .NEG,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x03, .NEG,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x03, .NEG,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x04, .MUL,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x04, .MUL,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x04, .MUL,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x05, .IMUL,            {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x05, .IMUL,            {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x05, .IMUL,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x06, .DIV,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x06, .DIV,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x06, .DIV,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x07, .IDIV,            {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x07, .IDIV,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xF7, 0x07, .IDIV,            {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
 	{.NONE,  0, 0xF8, 0xFF, .CLC,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xF9, 0xFF, .STC,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xFA, 0xFF, .CLI,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xFB, 0xFF, .STI,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xFC, 0xFF, .CLD,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
 	{.NONE,  0, 0xFD, 0xFF, .STD,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}},
-	{.NONE,  0, 0xFE, 0x00, .INC,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFE, 0x01, .DEC,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x00, .INC,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x00, .INC,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x00, .INC,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x01, .DEC,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x01, .DEC,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x01, .DEC,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x02, .CALL,            {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x03, .CALL,            {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x03, .CALL,            {.M16_16,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x03, .CALL,            {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x04, .JMP,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x05, .JMP,             {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x05, .JMP,             {.M16_16,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x05, .JMP,             {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x06, .PUSH,            {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}},
-	{.NONE,  0, 0xFF, 0x06, .PUSH,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true}},
+	{.NONE,  0, 0xFE, 0x00, .INC,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFE, 0x01, .DEC,             {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x00, .INC,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x00, .INC,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x00, .INC,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x01, .DEC,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x01, .DEC,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x01, .DEC,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x02, .CALL,            {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x03, .CALL,            {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x03, .CALL,            {.M16_16,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x03, .CALL,            {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x04, .JMP,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x05, .JMP,             {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x05, .JMP,             {.M16_16,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x05, .JMP,             {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x06, .PUSH,            {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{.NONE,  0, 0xFF, 0x06, .PUSH,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}},
 	{.NONE,  2, 0x90, 0xFF, .PAUSE,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {prefix=2}},
-	{._0F,   0, 0x00, 0x00, .SLDT,            {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0x00, 0x00, .SLDT,            {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x00, 0x00, .SLDT,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x00, 0x01, .STR,             {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x00, 0x01, .STR,             {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0x00, 0x01, .STR,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x00, 0x02, .LLDT,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x00, 0x03, .LTR,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x00, 0x04, .VERR,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x00, 0x05, .VERW,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x00, .SGDT,            {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x00, .SGDT,            {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x01, .SIDT,            {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x01, .SIDT,            {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x02, .LGDT,            {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x02, .LGDT,            {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x03, .LIDT,            {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x03, .LIDT,            {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x04, .SMSW,            {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x04, .SMSW,            {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x04, .SMSW,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x06, .LMSW,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x01, 0x07, .INVLPG,          {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
+	{._0F,   0, 0x00, 0x00, .SLDT,            {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x00, 0x00, .SLDT,            {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x00, 0x00, .SLDT,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x00, 0x01, .STR,             {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x00, 0x01, .STR,             {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x00, 0x01, .STR,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x00, 0x02, .LLDT,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x00, 0x03, .LTR,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x00, 0x04, .VERR,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x00, 0x05, .VERW,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x00, .SGDT,            {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x00, .SGDT,            {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x01, .SIDT,            {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x01, .SIDT,            {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x02, .LGDT,            {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x02, .LGDT,            {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x03, .LIDT,            {.M16_64,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x03, .LIDT,            {.M16_32,    .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x04, .SMSW,            {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x04, .SMSW,            {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x04, .SMSW,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x06, .LMSW,            {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x01, 0x07, .INVLPG,          {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
 	{._0F,   0, 0x01, 0xFF, .ENCLU,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x01, 0xFF, .RDPKRU,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x01, 0xFF, .VMFUNC,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
@@ -795,1719 +795,1719 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{
 	{._0F,   0, 0x01, 0xFF, .RDTSCP,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x01, 0xFF, .XGETBV,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x01, 0xFF, .XSETBV,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x02, 0xFF, .LAR,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x02, 0xFF, .LAR,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x02, 0xFF, .LAR,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x03, 0xFF, .LSL,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x03, 0xFF, .LSL,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x03, 0xFF, .LSL,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
+	{._0F,   0, 0x02, 0xFF, .LAR,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x02, 0xFF, .LAR,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x02, 0xFF, .LAR,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x03, 0xFF, .LSL,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x03, 0xFF, .LSL,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x03, 0xFF, .LSL,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
 	{._0F,   0, 0x05, 0xFF, .SYSCALL,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x06, 0xFF, .CLTS,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x07, 0xFF, .SYSRET,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x08, 0xFF, .INVD,            {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x09, 0xFF, .WBINVD,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x0B, 0xFF, .UD2,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x0D, 0x01, .PREFETCHW,       {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x10, 0xFF, .MOVUPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x11, 0xFF, .MOVUPS,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x12, 0xFF, .MOVHLPS,         {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x12, 0xFF, .MOVLPS,          {.XMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x13, 0xFF, .MOVLPS,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x14, 0xFF, .UNPCKLPS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x15, 0xFF, .UNPCKHPS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x16, 0xFF, .MOVHPS,          {.XMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x16, 0xFF, .MOVLHPS,         {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x17, 0xFF, .MOVHPS,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x18, 0x00, .PREFETCHNTA,     {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x18, 0x01, .PREFETCHT0,      {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x18, 0x02, .PREFETCHT1,      {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x18, 0x03, .PREFETCHT2,      {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x1C, 0x00, .CLDEMOTE,        {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x1F, 0x00, .NOP,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x1F, 0x00, .NOP,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0x1F, 0x00, .NOP,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0x20, 0xFF, .MOV,             {.R64,       .CR,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x21, 0xFF, .MOV,             {.R64,       .DR,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x22, 0xFF, .MOV,             {.CR,        .R64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x23, 0xFF, .MOV,             {.DR,        .R64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x28, 0xFF, .MOVAPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x29, 0xFF, .MOVAPS,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x2B, 0xFF, .MOVNTPS,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x2E, 0xFF, .UCOMISS,         {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x2F, 0xFF, .COMISS,          {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
+	{._0F,   0, 0x0D, 0x01, .PREFETCHW,       {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x10, 0xFF, .MOVUPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x11, 0xFF, .MOVUPS,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x12, 0xFF, .MOVHLPS,         {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x12, 0xFF, .MOVLPS,          {.XMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x13, 0xFF, .MOVLPS,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x14, 0xFF, .UNPCKLPS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x15, 0xFF, .UNPCKHPS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x16, 0xFF, .MOVHPS,          {.XMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x16, 0xFF, .MOVLHPS,         {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x17, 0xFF, .MOVHPS,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x18, 0x00, .PREFETCHNTA,     {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x18, 0x01, .PREFETCHT0,      {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x18, 0x02, .PREFETCHT1,      {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x18, 0x03, .PREFETCHT2,      {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x1C, 0x00, .CLDEMOTE,        {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x1F, 0x00, .NOP,             {.RM16,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x1F, 0x00, .NOP,             {.RM64,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x1F, 0x00, .NOP,             {.RM32,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x20, 0xFF, .MOV,             {.R64,       .CR,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x21, 0xFF, .MOV,             {.R64,       .DR,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x22, 0xFF, .MOV,             {.CR,        .R64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x23, 0xFF, .MOV,             {.DR,        .R64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x28, 0xFF, .MOVAPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x29, 0xFF, .MOVAPS,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x2B, 0xFF, .MOVNTPS,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x2E, 0xFF, .UCOMISS,         {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x2F, 0xFF, .COMISS,          {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
 	{._0F,   0, 0x30, 0xFF, .WRMSR,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x31, 0xFF, .RDTSC,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x32, 0xFF, .RDMSR,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x33, 0xFF, .RDPMC,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x34, 0xFF, .SYSENTER,        {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0x35, 0xFF, .SYSEXIT,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x40, 0xFF, .CMOVO,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x40, 0xFF, .CMOVO,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x40, 0xFF, .CMOVO,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x41, 0xFF, .CMOVNO,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x41, 0xFF, .CMOVNO,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x41, 0xFF, .CMOVNO,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x42, 0xFF, .CMOVNAE,         {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x42, 0xFF, .CMOVNAE,         {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x42, 0xFF, .CMOVC,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x42, 0xFF, .CMOVC,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x42, 0xFF, .CMOVC,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x42, 0xFF, .CMOVB,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x42, 0xFF, .CMOVB,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x42, 0xFF, .CMOVB,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x42, 0xFF, .CMOVNAE,         {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x43, 0xFF, .CMOVNC,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x43, 0xFF, .CMOVNC,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x43, 0xFF, .CMOVNC,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x43, 0xFF, .CMOVNB,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x43, 0xFF, .CMOVNB,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x43, 0xFF, .CMOVNB,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x43, 0xFF, .CMOVAE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x43, 0xFF, .CMOVAE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x43, 0xFF, .CMOVAE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x44, 0xFF, .CMOVZ,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x44, 0xFF, .CMOVZ,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x44, 0xFF, .CMOVZ,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x44, 0xFF, .CMOVE,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x44, 0xFF, .CMOVE,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x44, 0xFF, .CMOVE,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x45, 0xFF, .CMOVNZ,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x45, 0xFF, .CMOVNZ,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x45, 0xFF, .CMOVNZ,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x45, 0xFF, .CMOVNE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x45, 0xFF, .CMOVNE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x45, 0xFF, .CMOVNE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x46, 0xFF, .CMOVNA,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x46, 0xFF, .CMOVNA,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x46, 0xFF, .CMOVBE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x46, 0xFF, .CMOVBE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x46, 0xFF, .CMOVBE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x46, 0xFF, .CMOVNA,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x47, 0xFF, .CMOVNBE,         {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x47, 0xFF, .CMOVNBE,         {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x47, 0xFF, .CMOVNBE,         {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x47, 0xFF, .CMOVA,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x47, 0xFF, .CMOVA,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x47, 0xFF, .CMOVA,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x48, 0xFF, .CMOVS,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x48, 0xFF, .CMOVS,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x48, 0xFF, .CMOVS,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x49, 0xFF, .CMOVNS,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x49, 0xFF, .CMOVNS,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x49, 0xFF, .CMOVNS,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4A, 0xFF, .CMOVPE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4A, 0xFF, .CMOVPE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4A, 0xFF, .CMOVP,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4A, 0xFF, .CMOVP,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4A, 0xFF, .CMOVP,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4A, 0xFF, .CMOVPE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4B, 0xFF, .CMOVPO,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4B, 0xFF, .CMOVPO,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4B, 0xFF, .CMOVPO,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4B, 0xFF, .CMOVNP,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4B, 0xFF, .CMOVNP,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4B, 0xFF, .CMOVNP,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4C, 0xFF, .CMOVNGE,         {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4C, 0xFF, .CMOVNGE,         {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4C, 0xFF, .CMOVNGE,         {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4C, 0xFF, .CMOVL,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4C, 0xFF, .CMOVL,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4C, 0xFF, .CMOVL,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4D, 0xFF, .CMOVNL,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4D, 0xFF, .CMOVNL,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4D, 0xFF, .CMOVNL,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4D, 0xFF, .CMOVGE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4D, 0xFF, .CMOVGE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4D, 0xFF, .CMOVGE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4E, 0xFF, .CMOVNG,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4E, 0xFF, .CMOVNG,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4E, 0xFF, .CMOVNG,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4E, 0xFF, .CMOVLE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4E, 0xFF, .CMOVLE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4E, 0xFF, .CMOVLE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4F, 0xFF, .CMOVNLE,         {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4F, 0xFF, .CMOVNLE,         {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4F, 0xFF, .CMOVNLE,         {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4F, 0xFF, .CMOVG,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x4F, 0xFF, .CMOVG,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x4F, 0xFF, .CMOVG,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x50, 0xFF, .MOVMSKPS,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x50, 0xFF, .MOVMSKPS,        {.R64,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0x51, 0xFF, .SQRTPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x52, 0xFF, .RSQRTPS,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x53, 0xFF, .RCPPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x54, 0xFF, .ANDPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x55, 0xFF, .ANDNPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x56, 0xFF, .ORPS,            {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x57, 0xFF, .XORPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x58, 0xFF, .ADDPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x59, 0xFF, .MULPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x5A, 0xFF, .CVTPS2PD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x5B, 0xFF, .CVTDQ2PS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x5C, 0xFF, .SUBPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x5D, 0xFF, .MINPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x5E, 0xFF, .DIVPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x5F, 0xFF, .MAXPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x6E, 0xFF, .MOVD,            {.MM,        .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x6F, 0xFF, .MOVQ,            {.MM,        .MM_M64,    .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x70, 0xFF, .PSHUFW,          {.MM,        .MM_M64,    .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F}},
-	{._0F,   0, 0x78, 0xFF, .VMREAD,          {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x79, 0xFF, .VMWRITE,         {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x7E, 0xFF, .MOVD,            {.RM32,      .MM,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x7F, 0xFF, .MOVQ,            {.MM_M64,    .MM,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x80, 0xFF, .JO,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x81, 0xFF, .JNO,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x82, 0xFF, .JNAE,            {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x82, 0xFF, .JB,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x82, 0xFF, .JC,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x83, 0xFF, .JNC,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x83, 0xFF, .JNB,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x83, 0xFF, .JAE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x84, 0xFF, .JZ,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x84, 0xFF, .JE,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x85, 0xFF, .JNE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x85, 0xFF, .JNZ,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x86, 0xFF, .JNA,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x86, 0xFF, .JBE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x87, 0xFF, .JNBE,            {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x87, 0xFF, .JA,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x88, 0xFF, .JS,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x89, 0xFF, .JNS,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8A, 0xFF, .JP,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8A, 0xFF, .JPE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8B, 0xFF, .JPO,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8B, 0xFF, .JNP,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8C, 0xFF, .JNGE,            {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8C, 0xFF, .JL,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8D, 0xFF, .JNL,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8D, 0xFF, .JGE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8E, 0xFF, .JLE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8E, 0xFF, .JNG,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8F, 0xFF, .JNLE,            {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x8F, 0xFF, .JG,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x90, 0xFF, .SETO,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x91, 0xFF, .SETNO,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x92, 0xFF, .SETNAE,          {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x92, 0xFF, .SETB,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x92, 0xFF, .SETC,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x93, 0xFF, .SETNC,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x93, 0xFF, .SETNB,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x93, 0xFF, .SETAE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x94, 0xFF, .SETZ,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x94, 0xFF, .SETE,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x95, 0xFF, .SETNZ,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x95, 0xFF, .SETNE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x96, 0xFF, .SETNA,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x96, 0xFF, .SETBE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x97, 0xFF, .SETNBE,          {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x97, 0xFF, .SETA,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x98, 0xFF, .SETS,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x99, 0xFF, .SETNS,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9A, 0xFF, .SETP,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9A, 0xFF, .SETPE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9B, 0xFF, .SETPO,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9B, 0xFF, .SETNP,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9C, 0xFF, .SETNGE,          {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9C, 0xFF, .SETL,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9D, 0xFF, .SETNL,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9D, 0xFF, .SETGE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9E, 0xFF, .SETNG,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9E, 0xFF, .SETLE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9F, 0xFF, .SETNLE,          {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0x9F, 0xFF, .SETG,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xA0, 0xFF, .PUSH,            {.SREG,      .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xA1, 0xFF, .POP,             {.SREG,      .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}},
+	{._0F,   0, 0x40, 0xFF, .CMOVO,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x40, 0xFF, .CMOVO,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x40, 0xFF, .CMOVO,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x41, 0xFF, .CMOVNO,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x41, 0xFF, .CMOVNO,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x41, 0xFF, .CMOVNO,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x42, 0xFF, .CMOVNAE,         {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x42, 0xFF, .CMOVNAE,         {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x42, 0xFF, .CMOVC,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x42, 0xFF, .CMOVC,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x42, 0xFF, .CMOVC,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x42, 0xFF, .CMOVB,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x42, 0xFF, .CMOVB,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x42, 0xFF, .CMOVB,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x42, 0xFF, .CMOVNAE,         {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x43, 0xFF, .CMOVNC,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x43, 0xFF, .CMOVNC,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x43, 0xFF, .CMOVNC,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x43, 0xFF, .CMOVNB,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x43, 0xFF, .CMOVNB,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x43, 0xFF, .CMOVNB,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x43, 0xFF, .CMOVAE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x43, 0xFF, .CMOVAE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x43, 0xFF, .CMOVAE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x44, 0xFF, .CMOVZ,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x44, 0xFF, .CMOVZ,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x44, 0xFF, .CMOVZ,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x44, 0xFF, .CMOVE,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x44, 0xFF, .CMOVE,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x44, 0xFF, .CMOVE,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x45, 0xFF, .CMOVNZ,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x45, 0xFF, .CMOVNZ,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x45, 0xFF, .CMOVNZ,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x45, 0xFF, .CMOVNE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x45, 0xFF, .CMOVNE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x45, 0xFF, .CMOVNE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x46, 0xFF, .CMOVNA,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x46, 0xFF, .CMOVNA,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x46, 0xFF, .CMOVBE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x46, 0xFF, .CMOVBE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x46, 0xFF, .CMOVBE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x46, 0xFF, .CMOVNA,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x47, 0xFF, .CMOVNBE,         {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x47, 0xFF, .CMOVNBE,         {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x47, 0xFF, .CMOVNBE,         {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x47, 0xFF, .CMOVA,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x47, 0xFF, .CMOVA,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x47, 0xFF, .CMOVA,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x48, 0xFF, .CMOVS,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x48, 0xFF, .CMOVS,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x48, 0xFF, .CMOVS,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x49, 0xFF, .CMOVNS,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x49, 0xFF, .CMOVNS,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x49, 0xFF, .CMOVNS,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4A, 0xFF, .CMOVPE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4A, 0xFF, .CMOVPE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4A, 0xFF, .CMOVP,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4A, 0xFF, .CMOVP,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4A, 0xFF, .CMOVP,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4A, 0xFF, .CMOVPE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4B, 0xFF, .CMOVPO,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4B, 0xFF, .CMOVPO,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4B, 0xFF, .CMOVPO,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4B, 0xFF, .CMOVNP,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4B, 0xFF, .CMOVNP,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4B, 0xFF, .CMOVNP,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4C, 0xFF, .CMOVNGE,         {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4C, 0xFF, .CMOVNGE,         {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4C, 0xFF, .CMOVNGE,         {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4C, 0xFF, .CMOVL,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4C, 0xFF, .CMOVL,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4C, 0xFF, .CMOVL,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4D, 0xFF, .CMOVNL,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4D, 0xFF, .CMOVNL,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4D, 0xFF, .CMOVNL,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4D, 0xFF, .CMOVGE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4D, 0xFF, .CMOVGE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4D, 0xFF, .CMOVGE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4E, 0xFF, .CMOVNG,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4E, 0xFF, .CMOVNG,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4E, 0xFF, .CMOVNG,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4E, 0xFF, .CMOVLE,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4E, 0xFF, .CMOVLE,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4E, 0xFF, .CMOVLE,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4F, 0xFF, .CMOVNLE,         {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4F, 0xFF, .CMOVNLE,         {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4F, 0xFF, .CMOVNLE,         {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4F, 0xFF, .CMOVG,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4F, 0xFF, .CMOVG,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x4F, 0xFF, .CMOVG,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x50, 0xFF, .MOVMSKPS,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x50, 0xFF, .MOVMSKPS,        {.R64,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x51, 0xFF, .SQRTPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x52, 0xFF, .RSQRTPS,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x53, 0xFF, .RCPPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x54, 0xFF, .ANDPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x55, 0xFF, .ANDNPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x56, 0xFF, .ORPS,            {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x57, 0xFF, .XORPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x58, 0xFF, .ADDPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x59, 0xFF, .MULPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x5A, 0xFF, .CVTPS2PD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x5B, 0xFF, .CVTDQ2PS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x5C, 0xFF, .SUBPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x5D, 0xFF, .MINPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x5E, 0xFF, .DIVPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x5F, 0xFF, .MAXPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x6E, 0xFF, .MOVD,            {.MM,        .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x6F, 0xFF, .MOVQ,            {.MM,        .MM_M64,    .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x70, 0xFF, .PSHUFW,          {.MM,        .MM_M64,    .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x78, 0xFF, .VMREAD,          {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x79, 0xFF, .VMWRITE,         {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x7E, 0xFF, .MOVD,            {.RM32,      .MM,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x7F, 0xFF, .MOVQ,            {.MM_M64,    .MM,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x80, 0xFF, .JO,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x81, 0xFF, .JNO,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x82, 0xFF, .JNAE,            {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x82, 0xFF, .JB,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x82, 0xFF, .JC,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x83, 0xFF, .JNC,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x83, 0xFF, .JNB,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x83, 0xFF, .JAE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x84, 0xFF, .JZ,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x84, 0xFF, .JE,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x85, 0xFF, .JNE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x85, 0xFF, .JNZ,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x86, 0xFF, .JNA,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x86, 0xFF, .JBE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x87, 0xFF, .JNBE,            {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x87, 0xFF, .JA,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x88, 0xFF, .JS,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x89, 0xFF, .JNS,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8A, 0xFF, .JP,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8A, 0xFF, .JPE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8B, 0xFF, .JPO,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8B, 0xFF, .JNP,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8C, 0xFF, .JNGE,            {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8C, 0xFF, .JL,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8D, 0xFF, .JNL,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8D, 0xFF, .JGE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8E, 0xFF, .JLE,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8E, 0xFF, .JNG,             {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8F, 0xFF, .JNLE,            {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x8F, 0xFF, .JG,              {.REL32,     .NONE,      .NONE,      .NONE}, {.ID,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0x90, 0xFF, .SETO,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x91, 0xFF, .SETNO,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x92, 0xFF, .SETNAE,          {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x92, 0xFF, .SETB,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x92, 0xFF, .SETC,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x93, 0xFF, .SETNC,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x93, 0xFF, .SETNB,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x93, 0xFF, .SETAE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x94, 0xFF, .SETZ,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x94, 0xFF, .SETE,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x95, 0xFF, .SETNZ,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x95, 0xFF, .SETNE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x96, 0xFF, .SETNA,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x96, 0xFF, .SETBE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x97, 0xFF, .SETNBE,          {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x97, 0xFF, .SETA,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x98, 0xFF, .SETS,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x99, 0xFF, .SETNS,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9A, 0xFF, .SETP,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9A, 0xFF, .SETPE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9B, 0xFF, .SETPO,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9B, 0xFF, .SETNP,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9C, 0xFF, .SETNGE,          {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9C, 0xFF, .SETL,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9D, 0xFF, .SETNL,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9D, 0xFF, .SETGE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9E, 0xFF, .SETNG,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9E, 0xFF, .SETLE,           {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9F, 0xFF, .SETNLE,          {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0x9F, 0xFF, .SETG,            {.RM8,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xA0, 0xFF, .PUSH,            {.SREG,      .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0xA1, 0xFF, .POP,             {.SREG,      .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
 	{._0F,   0, 0xA2, 0xFF, .CPUID,           {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xA3, 0xFF, .BT,              {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xA3, 0xFF, .BT,              {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xA3, 0xFF, .BT,              {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xA4, 0xFF, .SHLD,            {.RM64,      .R64,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xA4, 0xFF, .SHLD,            {.RM16,      .R16,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F}},
-	{._0F,   0, 0xA4, 0xFF, .SHLD,            {.RM32,      .R32,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F}},
-	{._0F,   0, 0xA5, 0xFF, .SHLD,            {.RM64,      .R64,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xA5, 0xFF, .SHLD,            {.RM32,      .R32,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xA5, 0xFF, .SHLD,            {.RM16,      .R16,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xA8, 0xFF, .PUSH,            {.SREG,      .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xA9, 0xFF, .POP,             {.SREG,      .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}},
+	{._0F,   0, 0xA3, 0xFF, .BT,              {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xA3, 0xFF, .BT,              {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xA3, 0xFF, .BT,              {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xA4, 0xFF, .SHLD,            {.RM64,      .R64,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xA4, 0xFF, .SHLD,            {.RM16,      .R16,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xA4, 0xFF, .SHLD,            {.RM32,      .R32,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xA5, 0xFF, .SHLD,            {.RM64,      .R64,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xA5, 0xFF, .SHLD,            {.RM32,      .R32,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xA5, 0xFF, .SHLD,            {.RM16,      .R16,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xA8, 0xFF, .PUSH,            {.SREG,      .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0xA9, 0xFF, .POP,             {.SREG,      .NONE,      .NONE,      .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
 	{._0F,   0, 0xAA, 0xFF, .RSM,             {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xAB, 0xFF, .BTS,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xAB, 0xFF, .BTS,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xAB, 0xFF, .BTS,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}},
-	{._0F,   0, 0xAC, 0xFF, .SHRD,            {.RM16,      .R16,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F}},
-	{._0F,   0, 0xAC, 0xFF, .SHRD,            {.RM32,      .R32,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F}},
-	{._0F,   0, 0xAC, 0xFF, .SHRD,            {.RM64,      .R64,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xAD, 0xFF, .SHRD,            {.RM32,      .R32,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xAD, 0xFF, .SHRD,            {.RM16,      .R16,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xAD, 0xFF, .SHRD,            {.RM64,      .R64,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xAE, 0x00, .FXSAVE,          {.M512,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xAE, 0x00, .FXSAVE64,        {.M512,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xAE, 0x01, .FXRSTOR64,       {.M512,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xAE, 0x01, .FXRSTOR,         {.M512,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xAE, 0x04, .XSAVE64,         {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xAE, 0x04, .XSAVE,           {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xAE, 0x05, .XRSTOR64,        {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xAE, 0x05, .XRSTOR,          {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xAE, 0x06, .XSAVEOPT64,      {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xAE, 0x06, .XSAVEOPT,        {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xAE, 0x07, .CLFLUSH,         {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
+	{._0F,   0, 0xAB, 0xFF, .BTS,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xAB, 0xFF, .BTS,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xAB, 0xFF, .BTS,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xAC, 0xFF, .SHRD,            {.RM16,      .R16,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xAC, 0xFF, .SHRD,            {.RM32,      .R32,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xAC, 0xFF, .SHRD,            {.RM64,      .R64,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xAD, 0xFF, .SHRD,            {.RM32,      .R32,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xAD, 0xFF, .SHRD,            {.RM16,      .R16,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xAD, 0xFF, .SHRD,            {.RM64,      .R64,       .CL_IMPL,   .NONE}, {.MR,   .REG,  .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xAE, 0x00, .FXSAVE,          {.M512,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xAE, 0x00, .FXSAVE64,        {.M512,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xAE, 0x01, .FXRSTOR64,       {.M512,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xAE, 0x01, .FXRSTOR,         {.M512,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xAE, 0x04, .XSAVE64,         {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xAE, 0x04, .XSAVE,           {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xAE, 0x05, .XRSTOR64,        {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xAE, 0x05, .XRSTOR,          {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xAE, 0x06, .XSAVEOPT64,      {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xAE, 0x06, .XSAVEOPT,        {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xAE, 0x07, .CLFLUSH,         {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
 	{._0F,   0, 0xAE, 0xFF, .MFENCE,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0xAE, 0xFF, .SFENCE,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
 	{._0F,   0, 0xAE, 0xFF, .LFENCE,          {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xAF, 0xFF, .IMUL,            {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xAF, 0xFF, .IMUL,            {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xAF, 0xFF, .IMUL,            {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xB0, 0xFF, .CMPXCHG,         {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xB1, 0xFF, .CMPXCHG,         {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xB1, 0xFF, .CMPXCHG,         {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xB1, 0xFF, .CMPXCHG,         {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}},
-	{._0F,   0, 0xB3, 0xFF, .BTR,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}},
-	{._0F,   0, 0xB3, 0xFF, .BTR,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xB3, 0xFF, .BTR,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xB6, 0xFF, .MOVZX,           {.R32,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xB6, 0xFF, .MOVZX,           {.R16,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xB6, 0xFF, .MOVZX,           {.R64,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xB7, 0xFF, .MOVZX,           {.R32,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xB7, 0xFF, .MOVZX,           {.R64,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xB9, 0xFF, .UD1,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xBA, 0x04, .BT,              {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xBA, 0x04, .BT,              {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xBA, 0x04, .BT,              {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xBA, 0x05, .BTS,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xBA, 0x05, .BTS,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xBA, 0x05, .BTS,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xBA, 0x06, .BTR,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xBA, 0x06, .BTR,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xBA, 0x06, .BTR,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xBA, 0x07, .BTC,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xBA, 0x07, .BTC,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xBA, 0x07, .BTC,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xBB, 0xFF, .BTC,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}},
-	{._0F,   0, 0xBB, 0xFF, .BTC,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xBB, 0xFF, .BTC,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xBC, 0xFF, .BSF,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xBC, 0xFF, .BSF,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xBC, 0xFF, .BSF,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xBD, 0xFF, .BSR,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xBD, 0xFF, .BSR,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xBD, 0xFF, .BSR,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xBE, 0xFF, .MOVSX,           {.R32,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xBE, 0xFF, .MOVSX,           {.R16,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xBE, 0xFF, .MOVSX,           {.R64,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xBF, 0xFF, .MOVSX,           {.R64,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xBF, 0xFF, .MOVSX,           {.R32,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xC0, 0xFF, .XADD,            {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xC1, 0xFF, .XADD,            {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}},
-	{._0F,   0, 0xC1, 0xFF, .XADD,            {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xC1, 0xFF, .XADD,            {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true}},
-	{._0F,   0, 0xC2, 0xFF, .CMPPS,           {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F}},
-	{._0F,   0, 0xC6, 0xFF, .SHUFPS,          {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F}},
-	{._0F,   0, 0xC7, 0x01, .CMPXCHG8B,       {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x01, .CMPXCHG16B,      {.M128,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x03, .XRSTORS64,       {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x03, .XRSTORS,         {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x04, .XSAVEC64,        {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x04, .XSAVEC,          {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x05, .XSAVES,          {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x05, .XSAVES64,        {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x06, .RDRAND,          {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x06, .VMPTRLD,         {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x06, .RDRAND,          {.R16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x06, .RDRAND,          {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x07, .RDSEED,          {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x07, .VMPTRST,         {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x07, .RDSEED,          {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xC7, 0x07, .RDSEED,          {.R16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}},
-	{._0F,   0, 0xC8, 0xFF, .BSWAP,           {.R32,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F}},
-	{._0F,   0, 0xC8, 0xFF, .BSWAP,           {.R64,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true}},
-	{._0F,   0, 0xFF, 0xFF, .UD0,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F}},
-	{._0F,   1, 0x10, 0xFF, .MOVUPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x11, 0xFF, .MOVUPD,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x12, 0xFF, .MOVLPD,          {.XMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x13, 0xFF, .MOVLPD,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x14, 0xFF, .UNPCKLPD,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x15, 0xFF, .UNPCKHPD,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x16, 0xFF, .MOVHPD,          {.XMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x17, 0xFF, .MOVHPD,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x28, 0xFF, .MOVAPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x29, 0xFF, .MOVAPD,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x2B, 0xFF, .MOVNTPD,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x2E, 0xFF, .UCOMISD,         {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x2F, 0xFF, .COMISD,          {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x50, 0xFF, .MOVMSKPD,        {.R64,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}},
-	{._0F,   1, 0x50, 0xFF, .MOVMSKPD,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x51, 0xFF, .SQRTPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x54, 0xFF, .ANDPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x55, 0xFF, .ANDNPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x56, 0xFF, .ORPD,            {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x57, 0xFF, .XORPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x58, 0xFF, .ADDPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x59, 0xFF, .MULPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x5A, 0xFF, .CVTPD2PS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x5B, 0xFF, .CVTPS2DQ,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x5C, 0xFF, .SUBPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x5D, 0xFF, .MINPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x5E, 0xFF, .DIVPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x5F, 0xFF, .MAXPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x60, 0xFF, .PUNPCKLBW,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x61, 0xFF, .PUNPCKLWD,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x62, 0xFF, .PUNPCKLDQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x63, 0xFF, .PACKSSWB,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x64, 0xFF, .PCMPGTB,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x65, 0xFF, .PCMPGTW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x66, 0xFF, .PCMPGTD,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x67, 0xFF, .PACKUSWB,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x68, 0xFF, .PUNPCKHBW,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x69, 0xFF, .PUNPCKHWD,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x6A, 0xFF, .PUNPCKHDQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x6B, 0xFF, .PACKSSDW,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x6C, 0xFF, .PUNPCKLQDQ,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x6D, 0xFF, .PUNPCKHQDQ,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x6E, 0xFF, .MOVD,            {.XMM,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x6E, 0xFF, .MOVQ,            {.XMM,       .R64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}},
-	{._0F,   1, 0x6F, 0xFF, .MOVDQA,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x70, 0xFF, .PSHUFD,          {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x71, 0x02, .PSRLW,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
-	{._0F,   1, 0x71, 0x04, .PSRAW,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
-	{._0F,   1, 0x71, 0x06, .PSLLW,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x02, .PSRLD,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x04, .PSRAD,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x06, .PSLLD,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
-	{._0F,   1, 0x73, 0x02, .PSRLQ,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
-	{._0F,   1, 0x73, 0x06, .PSLLQ,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
-	{._0F,   1, 0x74, 0xFF, .PCMPEQB,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x75, 0xFF, .PCMPEQW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x76, 0xFF, .PCMPEQD,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x7C, 0xFF, .HADDPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x7D, 0xFF, .HSUBPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x7E, 0xFF, .MOVD,            {.RM32,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0x7E, 0xFF, .MOVQ,            {.R64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}},
-	{._0F,   1, 0x7F, 0xFF, .MOVDQA,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xAE, 0x06, .CLWB,            {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
-	{._0F,   1, 0xAE, 0x07, .CLFLUSHOPT,      {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
-	{._0F,   1, 0xC2, 0xFF, .CMPPD,           {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xC4, 0xFF, .PINSRW,          {.XMM,       .R32,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xC4, 0xFF, .PINSRW,          {.XMM,       .M16,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xC5, 0xFF, .PEXTRW,          {.R32,       .XMM,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xC5, 0xFF, .PEXTRW,          {.R64,       .XMM,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, force_rex_w=true}},
-	{._0F,   1, 0xC6, 0xFF, .SHUFPD,          {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xC7, 0x06, .VMCLEAR,         {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}},
-	{._0F,   1, 0xD0, 0xFF, .ADDSUBPD,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xD1, 0xFF, .PSRLW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xD2, 0xFF, .PSRLD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xD3, 0xFF, .PSRLQ,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xD4, 0xFF, .PADDQ,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xD5, 0xFF, .PMULLW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xD6, 0xFF, .MOVQ,            {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xD7, 0xFF, .PMOVMSKB,        {.R64,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}},
-	{._0F,   1, 0xD7, 0xFF, .PMOVMSKB,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xD8, 0xFF, .PSUBUSB,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xD9, 0xFF, .PSUBUSW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xDA, 0xFF, .PMINUB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xDB, 0xFF, .PAND,            {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xDC, 0xFF, .PADDUSB,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xDD, 0xFF, .PADDUSW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xDE, 0xFF, .PMAXUB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xDF, 0xFF, .PANDN,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xE0, 0xFF, .PAVGB,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xE1, 0xFF, .PSRAW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xE2, 0xFF, .PSRAD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xE3, 0xFF, .PAVGW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xE4, 0xFF, .PMULHUW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xE5, 0xFF, .PMULHW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xE6, 0xFF, .CVTTPD2DQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xE7, 0xFF, .MOVNTDQ,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xE8, 0xFF, .PSUBSB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xE9, 0xFF, .PSUBSW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xEA, 0xFF, .PMINSW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xEB, 0xFF, .POR,             {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xEC, 0xFF, .PADDSB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xED, 0xFF, .PADDSW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xEE, 0xFF, .PMAXSW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xEF, 0xFF, .PXOR,            {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xF1, 0xFF, .PSLLW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xF2, 0xFF, .PSLLD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xF3, 0xFF, .PSLLQ,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xF4, 0xFF, .PMULUDQ,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xF5, 0xFF, .PMADDWD,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xF6, 0xFF, .PSADBW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xF7, 0xFF, .MASKMOVDQU,      {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xF8, 0xFF, .PSUBB,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xF9, 0xFF, .PSUBW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xFA, 0xFF, .PSUBD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xFB, 0xFF, .PSUBQ,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xFC, 0xFF, .PADDB,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xFD, 0xFF, .PADDW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   1, 0xFE, 0xFF, .PADDD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1}},
-	{._0F,   2, 0x01, 0x05, .RSTORSSP,        {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}},
+	{._0F,   0, 0xAF, 0xFF, .IMUL,            {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xAF, 0xFF, .IMUL,            {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xAF, 0xFF, .IMUL,            {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB0, 0xFF, .CMPXCHG,         {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB1, 0xFF, .CMPXCHG,         {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB1, 0xFF, .CMPXCHG,         {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB1, 0xFF, .CMPXCHG,         {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB3, 0xFF, .BTR,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB3, 0xFF, .BTR,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB3, 0xFF, .BTR,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB6, 0xFF, .MOVZX,           {.R32,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB6, 0xFF, .MOVZX,           {.R16,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB6, 0xFF, .MOVZX,           {.R64,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB7, 0xFF, .MOVZX,           {.R32,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB7, 0xFF, .MOVZX,           {.R64,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xB9, 0xFF, .UD1,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x04, .BT,              {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x04, .BT,              {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x04, .BT,              {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x05, .BTS,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x05, .BTS,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x05, .BTS,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x06, .BTR,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x06, .BTR,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x06, .BTR,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x07, .BTC,             {.RM64,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x07, .BTC,             {.RM16,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBA, 0x07, .BTC,             {.RM32,      .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBB, 0xFF, .BTC,             {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBB, 0xFF, .BTC,             {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBB, 0xFF, .BTC,             {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBC, 0xFF, .BSF,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBC, 0xFF, .BSF,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBC, 0xFF, .BSF,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBD, 0xFF, .BSR,             {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBD, 0xFF, .BSR,             {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBD, 0xFF, .BSR,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBE, 0xFF, .MOVSX,           {.R32,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBE, 0xFF, .MOVSX,           {.R16,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBE, 0xFF, .MOVSX,           {.R64,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBF, 0xFF, .MOVSX,           {.R64,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xBF, 0xFF, .MOVSX,           {.R32,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xC0, 0xFF, .XADD,            {.RM8,       .R8,        .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xC1, 0xFF, .XADD,            {.RM64,      .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xC1, 0xFF, .XADD,            {.RM32,      .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xC1, 0xFF, .XADD,            {.RM16,      .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xC2, 0xFF, .CMPPS,           {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xC6, 0xFF, .SHUFPS,          {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x01, .CMPXCHG8B,       {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x01, .CMPXCHG16B,      {.M128,      .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x03, .XRSTORS64,       {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x03, .XRSTORS,         {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x04, .XSAVEC64,        {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x04, .XSAVEC,          {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x05, .XSAVES,          {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x05, .XSAVES64,        {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x06, .RDRAND,          {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x06, .VMPTRLD,         {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x06, .RDRAND,          {.R16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x06, .RDRAND,          {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x07, .RDSEED,          {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x07, .VMPTRST,         {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x07, .RDSEED,          {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC7, 0x07, .RDSEED,          {.R16,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   0, 0xC8, 0xFF, .BSWAP,           {.R32,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}},
+	{._0F,   0, 0xC8, 0xFF, .BSWAP,           {.R64,       .NONE,      .NONE,      .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=1}},
+	{._0F,   0, 0xFF, 0xFF, .UD0,             {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x10, 0xFF, .MOVUPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x11, 0xFF, .MOVUPD,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x12, 0xFF, .MOVLPD,          {.XMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x13, 0xFF, .MOVLPD,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x14, 0xFF, .UNPCKLPD,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x15, 0xFF, .UNPCKHPD,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x16, 0xFF, .MOVHPD,          {.XMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x17, 0xFF, .MOVHPD,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x28, 0xFF, .MOVAPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x29, 0xFF, .MOVAPD,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x2B, 0xFF, .MOVNTPD,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x2E, 0xFF, .UCOMISD,         {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x2F, 0xFF, .COMISD,          {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x50, 0xFF, .MOVMSKPD,        {.R64,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x50, 0xFF, .MOVMSKPD,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x51, 0xFF, .SQRTPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x54, 0xFF, .ANDPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x55, 0xFF, .ANDNPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x56, 0xFF, .ORPD,            {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x57, 0xFF, .XORPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x58, 0xFF, .ADDPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x59, 0xFF, .MULPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x5A, 0xFF, .CVTPD2PS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x5B, 0xFF, .CVTPS2DQ,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x5C, 0xFF, .SUBPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x5D, 0xFF, .MINPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x5E, 0xFF, .DIVPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x5F, 0xFF, .MAXPD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x60, 0xFF, .PUNPCKLBW,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x61, 0xFF, .PUNPCKLWD,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x62, 0xFF, .PUNPCKLDQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x63, 0xFF, .PACKSSWB,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x64, 0xFF, .PCMPGTB,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x65, 0xFF, .PCMPGTW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x66, 0xFF, .PCMPGTD,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x67, 0xFF, .PACKUSWB,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x68, 0xFF, .PUNPCKHBW,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x69, 0xFF, .PUNPCKHWD,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6A, 0xFF, .PUNPCKHDQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6B, 0xFF, .PACKSSDW,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6C, 0xFF, .PUNPCKLQDQ,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6D, 0xFF, .PUNPCKHQDQ,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6E, 0xFF, .MOVD,            {.XMM,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6E, 0xFF, .MOVQ,            {.XMM,       .R64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6F, 0xFF, .MOVDQA,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x70, 0xFF, .PSHUFD,          {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x71, 0x02, .PSRLW,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x71, 0x04, .PSRAW,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x71, 0x06, .PSLLW,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x02, .PSRLD,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x04, .PSRAD,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x06, .PSLLD,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x73, 0x02, .PSRLQ,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x73, 0x06, .PSLLQ,           {.XMM,       .IMM8,      .NONE,      .NONE}, {.MR,   .IB,   .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x74, 0xFF, .PCMPEQB,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x75, 0xFF, .PCMPEQW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x76, 0xFF, .PCMPEQD,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7C, 0xFF, .HADDPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7D, 0xFF, .HSUBPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7E, 0xFF, .MOVD,            {.RM32,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7E, 0xFF, .MOVQ,            {.R64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7F, 0xFF, .MOVDQA,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xAE, 0x06, .CLWB,            {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   1, 0xAE, 0x07, .CLFLUSHOPT,      {.M8,        .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   1, 0xC2, 0xFF, .CMPPD,           {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xC4, 0xFF, .PINSRW,          {.XMM,       .R32,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xC4, 0xFF, .PINSRW,          {.XMM,       .M16,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xC5, 0xFF, .PEXTRW,          {.R32,       .XMM,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xC5, 0xFF, .PEXTRW,          {.R64,       .XMM,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xC6, 0xFF, .SHUFPD,          {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xC7, 0x06, .VMCLEAR,         {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   1, 0xD0, 0xFF, .ADDSUBPD,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD1, 0xFF, .PSRLW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD2, 0xFF, .PSRLD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD3, 0xFF, .PSRLQ,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD4, 0xFF, .PADDQ,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD5, 0xFF, .PMULLW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD6, 0xFF, .MOVQ,            {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD7, 0xFF, .PMOVMSKB,        {.R64,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD7, 0xFF, .PMOVMSKB,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD8, 0xFF, .PSUBUSB,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD9, 0xFF, .PSUBUSW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xDA, 0xFF, .PMINUB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xDB, 0xFF, .PAND,            {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xDC, 0xFF, .PADDUSB,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xDD, 0xFF, .PADDUSW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xDE, 0xFF, .PMAXUB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xDF, 0xFF, .PANDN,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE0, 0xFF, .PAVGB,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE1, 0xFF, .PSRAW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE2, 0xFF, .PSRAD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE3, 0xFF, .PAVGW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE4, 0xFF, .PMULHUW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE5, 0xFF, .PMULHW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE6, 0xFF, .CVTTPD2DQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE7, 0xFF, .MOVNTDQ,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE8, 0xFF, .PSUBSB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE9, 0xFF, .PSUBSW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xEA, 0xFF, .PMINSW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xEB, 0xFF, .POR,             {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xEC, 0xFF, .PADDSB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xED, 0xFF, .PADDSW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xEE, 0xFF, .PMAXSW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xEF, 0xFF, .PXOR,            {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xF1, 0xFF, .PSLLW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xF2, 0xFF, .PSLLD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xF3, 0xFF, .PSLLQ,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xF4, 0xFF, .PMULUDQ,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xF5, 0xFF, .PMADDWD,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xF6, 0xFF, .PSADBW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xF7, 0xFF, .MASKMOVDQU,      {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xF8, 0xFF, .PSUBB,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xF9, 0xFF, .PSUBW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xFA, 0xFF, .PSUBD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xFB, 0xFF, .PSUBQ,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xFC, 0xFF, .PADDB,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xFD, 0xFF, .PADDW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xFE, 0xFF, .PADDD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x01, 0x05, .RSTORSSP,        {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
 	{._0F,   2, 0x01, 0xFF, .SETSSBSY,        {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}},
 	{._0F,   2, 0x01, 0xFF, .SAVEPREVSSP,     {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x10, 0xFF, .MOVSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x11, 0xFF, .MOVSS,           {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x12, 0xFF, .MOVSLDUP,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x16, 0xFF, .MOVSHDUP,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x1E, 0x01, .RDSSPQ,          {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   2, 0x1E, 0x01, .RDSSPD,          {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}},
+	{._0F,   2, 0x10, 0xFF, .MOVSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x11, 0xFF, .MOVSS,           {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x12, 0xFF, .MOVSLDUP,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x16, 0xFF, .MOVSHDUP,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x1E, 0x01, .RDSSPQ,          {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   2, 0x1E, 0x01, .RDSSPD,          {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
 	{._0F,   2, 0x1E, 0xFF, .ENDBR64,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}},
 	{._0F,   2, 0x1E, 0xFF, .ENDBR32,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x2A, 0xFF, .CVTSI2SS,        {.XMM,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x2A, 0xFF, .CVTSI2SS,        {.XMM,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
-	{._0F,   2, 0x2C, 0xFF, .CVTTSS2SI,       {.R32,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x2C, 0xFF, .CVTTSS2SI,       {.R64,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
-	{._0F,   2, 0x2D, 0xFF, .CVTSS2SI,        {.R64,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
-	{._0F,   2, 0x2D, 0xFF, .CVTSS2SI,        {.R32,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x51, 0xFF, .SQRTSS,          {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x52, 0xFF, .RSQRTSS,         {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x53, 0xFF, .RCPSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x58, 0xFF, .ADDSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x59, 0xFF, .MULSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x5A, 0xFF, .CVTSS2SD,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x5B, 0xFF, .CVTTPS2DQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x5C, 0xFF, .SUBSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x5D, 0xFF, .MINSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x5E, 0xFF, .DIVSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x5F, 0xFF, .MAXSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x6F, 0xFF, .MOVDQU,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x70, 0xFF, .PSHUFHW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x7E, 0xFF, .MOVQ,            {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0x7F, 0xFF, .MOVDQU,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0xAE, 0x05, .INCSSPD,         {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}},
-	{._0F,   2, 0xAE, 0x05, .INCSSPQ,         {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true}},
-	{._0F,   2, 0xAE, 0x06, .CLRSSBSY,        {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}},
-	{._0F,   2, 0xB8, 0xFF, .POPCNT,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
-	{._0F,   2, 0xB8, 0xFF, .POPCNT,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0xB8, 0xFF, .POPCNT,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0xBC, 0xFF, .TZCNT,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
-	{._0F,   2, 0xBC, 0xFF, .TZCNT,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0xBC, 0xFF, .TZCNT,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0xBD, 0xFF, .LZCNT,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}},
-	{._0F,   2, 0xBD, 0xFF, .LZCNT,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0xBD, 0xFF, .LZCNT,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0xC2, 0xFF, .CMPSS,           {.XMM,       .XMM_M32,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   2, 0xC7, 0x06, .VMXON,           {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}},
-	{._0F,   2, 0xE6, 0xFF, .CVTDQ2PD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2}},
-	{._0F,   3, 0x10, 0xFF, .MOVSD_SSE,       {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x11, 0xFF, .MOVSD_SSE,       {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x12, 0xFF, .MOVDDUP,         {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x2A, 0xFF, .CVTSI2SD,        {.XMM,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true}},
-	{._0F,   3, 0x2A, 0xFF, .CVTSI2SD,        {.XMM,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x2C, 0xFF, .CVTTSD2SI,       {.R64,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true}},
-	{._0F,   3, 0x2C, 0xFF, .CVTTSD2SI,       {.R32,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x2D, 0xFF, .CVTSD2SI,        {.R32,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x2D, 0xFF, .CVTSD2SI,        {.R64,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true}},
-	{._0F,   3, 0x51, 0xFF, .SQRTSD,          {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x58, 0xFF, .ADDSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x59, 0xFF, .MULSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x5A, 0xFF, .CVTSD2SS,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x5C, 0xFF, .SUBSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x5D, 0xFF, .MINSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x5E, 0xFF, .DIVSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x5F, 0xFF, .MAXSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x70, 0xFF, .PSHUFLW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x7C, 0xFF, .HADDPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0x7D, 0xFF, .HSUBPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0xC2, 0xFF, .CMPSD_SSE,       {.XMM,       .XMM_M64,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0xD0, 0xFF, .ADDSUBPS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0xE6, 0xFF, .CVTPD2DQ,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F,   3, 0xF0, 0xFF, .LDDQU,           {.XMM,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3}},
-	{._0F38, 0, 0xC8, 0xFF, .SHA1NEXTE,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38}},
-	{._0F38, 0, 0xC9, 0xFF, .SHA1MSG1,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38}},
-	{._0F38, 0, 0xCA, 0xFF, .SHA1MSG2,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38}},
-	{._0F38, 0, 0xCB, 0xFF, .SHA256RNDS2,     {.XMM,       .XMM_M128,  .XMM0_IMPL, .NONE}, {.REG,  .MR,   .IMPL, .NONE}, {esc=._0F38}},
-	{._0F38, 0, 0xCC, 0xFF, .SHA256MSG1,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38}},
-	{._0F38, 0, 0xCD, 0xFF, .SHA256MSG2,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38}},
-	{._0F38, 0, 0xF0, 0xFF, .MOVBE,           {.R32,       .M32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38}},
-	{._0F38, 0, 0xF0, 0xFF, .MOVBE,           {.R16,       .M16,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38}},
-	{._0F38, 0, 0xF0, 0xFF, .MOVBE,           {.R64,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, force_rex_w=true}},
-	{._0F38, 0, 0xF1, 0xFF, .MOVBE,           {.M32,       .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38}},
-	{._0F38, 0, 0xF1, 0xFF, .MOVBE,           {.M16,       .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38}},
-	{._0F38, 0, 0xF1, 0xFF, .MOVBE,           {.M64,       .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, force_rex_w=true}},
-	{._0F38, 0, 0xF6, 0xFF, .WRSSQ,           {.M64,       .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, force_rex_w=true}},
-	{._0F38, 0, 0xF6, 0xFF, .WRSSD,           {.M32,       .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38}},
-	{._0F38, 1, 0x00, 0xFF, .PSHUFB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x01, 0xFF, .PHADDW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x02, 0xFF, .PHADDD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x03, 0xFF, .PHADDSW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x04, 0xFF, .PMADDUBSW,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x05, 0xFF, .PHSUBW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x06, 0xFF, .PHSUBD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x07, 0xFF, .PHSUBSW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x08, 0xFF, .PSIGNB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x09, 0xFF, .PSIGNW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x0A, 0xFF, .PSIGND,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x0B, 0xFF, .PMULHRSW,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x10, 0xFF, .PBLENDVB,        {.XMM,       .XMM_M128,  .XMM0_IMPL, .NONE}, {.REG,  .MR,   .IMPL, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x14, 0xFF, .BLENDVPS,        {.XMM,       .XMM_M128,  .XMM0_IMPL, .NONE}, {.REG,  .MR,   .IMPL, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x15, 0xFF, .BLENDVPD,        {.XMM,       .XMM_M128,  .XMM0_IMPL, .NONE}, {.REG,  .MR,   .IMPL, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x17, 0xFF, .PTEST,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x1C, 0xFF, .PABSB,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x1D, 0xFF, .PABSW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x1E, 0xFF, .PABSD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x20, 0xFF, .PMOVSXBW,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x21, 0xFF, .PMOVSXBD,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x22, 0xFF, .PMOVSXBQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x23, 0xFF, .PMOVSXWD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x24, 0xFF, .PMOVSXWQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x25, 0xFF, .PMOVSXDQ,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x28, 0xFF, .PMULDQ,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x29, 0xFF, .PCMPEQQ,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x2A, 0xFF, .MOVNTDQA,        {.XMM,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x2B, 0xFF, .PACKUSDW,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x30, 0xFF, .PMOVZXBW,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x31, 0xFF, .PMOVZXBD,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x32, 0xFF, .PMOVZXBQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x33, 0xFF, .PMOVZXWD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x34, 0xFF, .PMOVZXWQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x35, 0xFF, .PMOVZXDQ,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x37, 0xFF, .PCMPGTQ,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x38, 0xFF, .PMINSB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x39, 0xFF, .PMINSD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x3A, 0xFF, .PMINUW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x3B, 0xFF, .PMINUD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x3C, 0xFF, .PMAXSB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x3D, 0xFF, .PMAXSD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x3E, 0xFF, .PMAXUW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x3F, 0xFF, .PMAXUD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x40, 0xFF, .PMULLD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x41, 0xFF, .PHMINPOSUW,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x80, 0xFF, .INVEPT,          {.R64,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x81, 0xFF, .INVVPID,         {.R64,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x82, 0xFF, .INVPCID,         {.R64,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0x82, 0xFF, .INVPCID,         {.R32,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0xDB, 0xFF, .AESIMC,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0xDC, 0xFF, .AESENC,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0xDD, 0xFF, .AESENCLAST,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0xDE, 0xFF, .AESDEC,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0xDF, 0xFF, .AESDECLAST,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0xF5, 0xFF, .WRUSSD,          {.M32,       .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 1, 0xF5, 0xFF, .WRUSSQ,          {.M64,       .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true}},
-	{._0F38, 1, 0xF6, 0xFF, .ADCX,            {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true}},
-	{._0F38, 1, 0xF6, 0xFF, .ADCX,            {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1}},
-	{._0F38, 2, 0xF6, 0xFF, .ADOX,            {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true}},
-	{._0F38, 2, 0xF6, 0xFF, .ADOX,            {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2}},
-	{._0F38, 3, 0xF0, 0xFF, .CRC32,           {.R64,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true}},
-	{._0F38, 3, 0xF0, 0xFF, .CRC32,           {.R32,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=3}},
-	{._0F38, 3, 0xF1, 0xFF, .CRC32,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true}},
-	{._0F38, 3, 0xF1, 0xFF, .CRC32,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=3}},
-	{._0F38, 3, 0xF1, 0xFF, .CRC32,           {.R32,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=3}},
-	{._0F3A, 0, 0xCC, 0xFF, .SHA1RNDS4,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A}},
-	{._0F3A, 1, 0x08, 0xFF, .ROUNDPS,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x09, 0xFF, .ROUNDPD,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x0A, 0xFF, .ROUNDSS,         {.XMM,       .XMM_M32,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x0B, 0xFF, .ROUNDSD,         {.XMM,       .XMM_M64,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x0C, 0xFF, .BLENDPS,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x0D, 0xFF, .BLENDPD,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x0E, 0xFF, .PBLENDW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x0F, 0xFF, .PALIGNR,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x14, 0xFF, .PEXTRB,          {.RM8,       .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x16, 0xFF, .PEXTRD,          {.RM32,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x16, 0xFF, .PEXTRQ,          {.RM64,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, force_rex_w=true}},
-	{._0F3A, 1, 0x17, 0xFF, .EXTRACTPS,       {.RM32,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x20, 0xFF, .PINSRB,          {.XMM,       .RM8,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x21, 0xFF, .INSERTPS,        {.XMM,       .XMM_M32,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x22, 0xFF, .PINSRD,          {.XMM,       .RM32,      .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x22, 0xFF, .PINSRQ,          {.XMM,       .RM64,      .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, force_rex_w=true}},
-	{._0F3A, 1, 0x40, 0xFF, .DPPS,            {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x41, 0xFF, .DPPD,            {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x42, 0xFF, .MPSADBW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x44, 0xFF, .PCLMULQDQ,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x60, 0xFF, .PCMPESTRM,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x61, 0xFF, .PCMPESTRI,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x62, 0xFF, .PCMPISTRM,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0x63, 0xFF, .PCMPISTRI,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
-	{._0F3A, 1, 0xDF, 0xFF, .AESKEYGENASSIST, {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1}},
+	{._0F,   2, 0x2A, 0xFF, .CVTSI2SS,        {.XMM,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x2A, 0xFF, .CVTSI2SS,        {.XMM,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x2C, 0xFF, .CVTTSS2SI,       {.R32,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x2C, 0xFF, .CVTTSS2SI,       {.R64,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x2D, 0xFF, .CVTSS2SI,        {.R64,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x2D, 0xFF, .CVTSS2SI,        {.R32,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x51, 0xFF, .SQRTSS,          {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x52, 0xFF, .RSQRTSS,         {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x53, 0xFF, .RCPSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x58, 0xFF, .ADDSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x59, 0xFF, .MULSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x5A, 0xFF, .CVTSS2SD,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x5B, 0xFF, .CVTTPS2DQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x5C, 0xFF, .SUBSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x5D, 0xFF, .MINSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x5E, 0xFF, .DIVSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x5F, 0xFF, .MAXSS,           {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x6F, 0xFF, .MOVDQU,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x70, 0xFF, .PSHUFHW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=2, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x7E, 0xFF, .MOVQ,            {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x7F, 0xFF, .MOVDQU,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xAE, 0x05, .INCSSPD,         {.R32,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   2, 0xAE, 0x05, .INCSSPQ,         {.R64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   2, 0xAE, 0x06, .CLRSSBSY,        {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   2, 0xB8, 0xFF, .POPCNT,          {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xB8, 0xFF, .POPCNT,          {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xB8, 0xFF, .POPCNT,          {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xBC, 0xFF, .TZCNT,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xBC, 0xFF, .TZCNT,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xBC, 0xFF, .TZCNT,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xBD, 0xFF, .LZCNT,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xBD, 0xFF, .LZCNT,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xBD, 0xFF, .LZCNT,           {.R16,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xC2, 0xFF, .CMPSS,           {.XMM,       .XMM_M32,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=2, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0xC7, 0x06, .VMXON,           {.M64,       .NONE,      .NONE,      .NONE}, {.MR,   .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}},
+	{._0F,   2, 0xE6, 0xFF, .CVTDQ2PD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x10, 0xFF, .MOVSD_SSE,       {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x11, 0xFF, .MOVSD_SSE,       {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x12, 0xFF, .MOVDDUP,         {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x2A, 0xFF, .CVTSI2SD,        {.XMM,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x2A, 0xFF, .CVTSI2SD,        {.XMM,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x2C, 0xFF, .CVTTSD2SI,       {.R64,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x2C, 0xFF, .CVTTSD2SI,       {.R32,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x2D, 0xFF, .CVTSD2SI,        {.R32,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x2D, 0xFF, .CVTSD2SI,        {.R64,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x51, 0xFF, .SQRTSD,          {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x58, 0xFF, .ADDSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x59, 0xFF, .MULSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x5A, 0xFF, .CVTSD2SS,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x5C, 0xFF, .SUBSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x5D, 0xFF, .MINSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x5E, 0xFF, .DIVSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x5F, 0xFF, .MAXSD,           {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x70, 0xFF, .PSHUFLW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x7C, 0xFF, .HADDPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x7D, 0xFF, .HSUBPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0xC2, 0xFF, .CMPSD_SSE,       {.XMM,       .XMM_M64,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0xD0, 0xFF, .ADDSUBPS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0xE6, 0xFF, .CVTPD2DQ,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0xF0, 0xFF, .LDDQU,           {.XMM,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xC8, 0xFF, .SHA1NEXTE,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xC9, 0xFF, .SHA1MSG1,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xCA, 0xFF, .SHA1MSG2,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xCB, 0xFF, .SHA256RNDS2,     {.XMM,       .XMM_M128,  .XMM0_IMPL, .NONE}, {.REG,  .MR,   .IMPL, .NONE}, {esc=._0F38, op_count=3, needs_modrm=true}},
+	{._0F38, 0, 0xCC, 0xFF, .SHA256MSG1,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xCD, 0xFF, .SHA256MSG2,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF0, 0xFF, .MOVBE,           {.R32,       .M32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF0, 0xFF, .MOVBE,           {.R16,       .M16,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF0, 0xFF, .MOVBE,           {.R64,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF1, 0xFF, .MOVBE,           {.M32,       .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF1, 0xFF, .MOVBE,           {.M16,       .R16,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF1, 0xFF, .MOVBE,           {.M64,       .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF6, 0xFF, .WRSSQ,           {.M64,       .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF6, 0xFF, .WRSSD,           {.M32,       .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x00, 0xFF, .PSHUFB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x01, 0xFF, .PHADDW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x02, 0xFF, .PHADDD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x03, 0xFF, .PHADDSW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x04, 0xFF, .PMADDUBSW,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x05, 0xFF, .PHSUBW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x06, 0xFF, .PHSUBD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x07, 0xFF, .PHSUBSW,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x08, 0xFF, .PSIGNB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x09, 0xFF, .PSIGNW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x0A, 0xFF, .PSIGND,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x0B, 0xFF, .PMULHRSW,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x10, 0xFF, .PBLENDVB,        {.XMM,       .XMM_M128,  .XMM0_IMPL, .NONE}, {.REG,  .MR,   .IMPL, .NONE}, {esc=._0F38, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x14, 0xFF, .BLENDVPS,        {.XMM,       .XMM_M128,  .XMM0_IMPL, .NONE}, {.REG,  .MR,   .IMPL, .NONE}, {esc=._0F38, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x15, 0xFF, .BLENDVPD,        {.XMM,       .XMM_M128,  .XMM0_IMPL, .NONE}, {.REG,  .MR,   .IMPL, .NONE}, {esc=._0F38, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x17, 0xFF, .PTEST,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x1C, 0xFF, .PABSB,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x1D, 0xFF, .PABSW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x1E, 0xFF, .PABSD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x20, 0xFF, .PMOVSXBW,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x21, 0xFF, .PMOVSXBD,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x22, 0xFF, .PMOVSXBQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x23, 0xFF, .PMOVSXWD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x24, 0xFF, .PMOVSXWQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x25, 0xFF, .PMOVSXDQ,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x28, 0xFF, .PMULDQ,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x29, 0xFF, .PCMPEQQ,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x2A, 0xFF, .MOVNTDQA,        {.XMM,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x2B, 0xFF, .PACKUSDW,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x30, 0xFF, .PMOVZXBW,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x31, 0xFF, .PMOVZXBD,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x32, 0xFF, .PMOVZXBQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x33, 0xFF, .PMOVZXWD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x34, 0xFF, .PMOVZXWQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x35, 0xFF, .PMOVZXDQ,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x37, 0xFF, .PCMPGTQ,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x38, 0xFF, .PMINSB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x39, 0xFF, .PMINSD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x3A, 0xFF, .PMINUW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x3B, 0xFF, .PMINUD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x3C, 0xFF, .PMAXSB,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x3D, 0xFF, .PMAXSD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x3E, 0xFF, .PMAXUW,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x3F, 0xFF, .PMAXUD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x40, 0xFF, .PMULLD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x41, 0xFF, .PHMINPOSUW,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x80, 0xFF, .INVEPT,          {.R64,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x81, 0xFF, .INVVPID,         {.R64,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x82, 0xFF, .INVPCID,         {.R64,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x82, 0xFF, .INVPCID,         {.R32,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xDB, 0xFF, .AESIMC,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xDC, 0xFF, .AESENC,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xDD, 0xFF, .AESENCLAST,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xDE, 0xFF, .AESDEC,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xDF, 0xFF, .AESDECLAST,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xF5, 0xFF, .WRUSSD,          {.M32,       .R32,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xF5, 0xFF, .WRUSSQ,          {.M64,       .R64,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xF6, 0xFF, .ADCX,            {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xF6, 0xFF, .ADCX,            {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0xF6, 0xFF, .ADOX,            {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0xF6, 0xFF, .ADOX,            {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, op_count=2, needs_modrm=true}},
+	{._0F38, 3, 0xF0, 0xFF, .CRC32,           {.R64,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F38, 3, 0xF0, 0xFF, .CRC32,           {.R32,       .RM8,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F38, 3, 0xF1, 0xFF, .CRC32,           {.R64,       .RM64,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}},
+	{._0F38, 3, 0xF1, 0xFF, .CRC32,           {.R32,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F38, 3, 0xF1, 0xFF, .CRC32,           {.R32,       .RM16,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}},
+	{._0F3A, 0, 0xCC, 0xFF, .SHA1RNDS4,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x08, 0xFF, .ROUNDPS,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x09, 0xFF, .ROUNDPD,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x0A, 0xFF, .ROUNDSS,         {.XMM,       .XMM_M32,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x0B, 0xFF, .ROUNDSD,         {.XMM,       .XMM_M64,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x0C, 0xFF, .BLENDPS,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x0D, 0xFF, .BLENDPD,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x0E, 0xFF, .PBLENDW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x0F, 0xFF, .PALIGNR,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x14, 0xFF, .PEXTRB,          {.RM8,       .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x16, 0xFF, .PEXTRD,          {.RM32,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x16, 0xFF, .PEXTRQ,          {.RM64,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, force_rex_w=true, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x17, 0xFF, .EXTRACTPS,       {.RM32,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x20, 0xFF, .PINSRB,          {.XMM,       .RM8,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x21, 0xFF, .INSERTPS,        {.XMM,       .XMM_M32,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x22, 0xFF, .PINSRD,          {.XMM,       .RM32,      .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x22, 0xFF, .PINSRQ,          {.XMM,       .RM64,      .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, force_rex_w=true, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x40, 0xFF, .DPPS,            {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x41, 0xFF, .DPPD,            {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x42, 0xFF, .MPSADBW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x44, 0xFF, .PCLMULQDQ,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x60, 0xFF, .PCMPESTRM,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x61, 0xFF, .PCMPESTRI,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x62, 0xFF, .PCMPISTRM,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x63, 0xFF, .PCMPISTRI,       {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0xDF, 0xFF, .AESKEYGENASSIST, {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}},
 }
 
 @(rodata)
 VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{
-	{._0F,   0, 0x10, 0xFF, .WIG,  .L1,   .VMOVUPS,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x10, 0xFF, .WIG,  .L0,   .VMOVUPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x11, 0xFF, .WIG,  .L0,   .VMOVUPS,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x11, 0xFF, .WIG,  .L1,   .VMOVUPS,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x12, 0xFF, .WIG,  .L0,   .VMOVHLPS,         {.XMM,       .XMM,       .XMM,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x12, 0xFF, .WIG,  .L0,   .VMOVLPS,          {.XMM,       .XMM,       .M64,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x13, 0xFF, .WIG,  .L0,   .VMOVLPS,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x14, 0xFF, .WIG,  .L0,   .VUNPCKLPS,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x14, 0xFF, .WIG,  .L1,   .VUNPCKLPS,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x15, 0xFF, .WIG,  .L1,   .VUNPCKHPS,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x15, 0xFF, .WIG,  .L0,   .VUNPCKHPS,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x16, 0xFF, .WIG,  .L0,   .VMOVHPS,          {.XMM,       .XMM,       .M64,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x16, 0xFF, .WIG,  .L0,   .VMOVLHPS,         {.XMM,       .XMM,       .XMM,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x17, 0xFF, .WIG,  .L0,   .VMOVHPS,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x28, 0xFF, .WIG,  .L0,   .VMOVAPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x28, 0xFF, .WIG,  .L1,   .VMOVAPS,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x29, 0xFF, .WIG,  .L0,   .VMOVAPS,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x29, 0xFF, .WIG,  .L1,   .VMOVAPS,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x2B, 0xFF, .WIG,  .L1,   .VMOVNTPS,         {.M256,      .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x2B, 0xFF, .WIG,  .L0,   .VMOVNTPS,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x2E, 0xFF, .WIG,  .LIG,  .VUCOMISS,         {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX}},
-	{._0F,   0, 0x2F, 0xFF, .WIG,  .LIG,  .VCOMISS,          {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX}},
-	{._0F,   0, 0x41, 0xFF, .W0,   .L1,   .KANDW,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   0, 0x41, 0xFF, .W1,   .L1,   .KANDQ,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   0, 0x42, 0xFF, .W1,   .L1,   .KANDNQ,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   0, 0x42, 0xFF, .W0,   .L1,   .KANDNW,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   0, 0x44, 0xFF, .W1,   .L0,   .KNOTQ,            {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   0, 0x44, 0xFF, .W0,   .L0,   .KNOTW,            {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   0, 0x45, 0xFF, .W0,   .L1,   .KORW,             {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   0, 0x45, 0xFF, .W1,   .L1,   .KORQ,             {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   0, 0x46, 0xFF, .W1,   .L1,   .KXNORQ,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   0, 0x46, 0xFF, .W0,   .L1,   .KXNORW,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   0, 0x47, 0xFF, .W1,   .L1,   .KXORQ,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   0, 0x47, 0xFF, .W0,   .L1,   .KXORW,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   0, 0x4A, 0xFF, .W0,   .L1,   .KADDW,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   0, 0x4A, 0xFF, .W1,   .L1,   .KADDQ,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   0, 0x4B, 0xFF, .W1,   .L1,   .KUNPCKDQ,         {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   0, 0x4B, 0xFF, .W0,   .L1,   .KUNPCKWD,         {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   0, 0x50, 0xFF, .WIG,  .L1,   .VMOVMSKPS,        {.R32,       .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x50, 0xFF, .WIG,  .L0,   .VMOVMSKPS,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x51, 0xFF, .WIG,  .L1,   .VSQRTPS,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x51, 0xFF, .WIG,  .L0,   .VSQRTPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x52, 0xFF, .WIG,  .L1,   .VRSQRTPS,         {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x52, 0xFF, .WIG,  .L0,   .VRSQRTPS,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x53, 0xFF, .WIG,  .L0,   .VRCPPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x53, 0xFF, .WIG,  .L1,   .VRCPPS,           {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x54, 0xFF, .WIG,  .L0,   .VANDPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x54, 0xFF, .WIG,  .L1,   .VANDPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x55, 0xFF, .WIG,  .L0,   .VANDNPS,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x55, 0xFF, .WIG,  .L1,   .VANDNPS,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x56, 0xFF, .WIG,  .L0,   .VORPS,            {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x56, 0xFF, .WIG,  .L1,   .VORPS,            {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x57, 0xFF, .WIG,  .L0,   .VXORPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x57, 0xFF, .WIG,  .L1,   .VXORPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x58, 0xFF, .WIG,  .L0,   .VADDPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x58, 0xFF, .WIG,  .L1,   .VADDPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x59, 0xFF, .WIG,  .L0,   .VMULPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x59, 0xFF, .WIG,  .L1,   .VMULPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x5A, 0xFF, .WIG,  .L1,   .VCVTPS2PD,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x5A, 0xFF, .WIG,  .L0,   .VCVTPS2PD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x5B, 0xFF, .WIG,  .L1,   .VCVTDQ2PS,        {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x5B, 0xFF, .WIG,  .L0,   .VCVTDQ2PS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x5C, 0xFF, .WIG,  .L0,   .VSUBPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x5C, 0xFF, .WIG,  .L1,   .VSUBPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x5D, 0xFF, .WIG,  .L1,   .VMINPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x5D, 0xFF, .WIG,  .L0,   .VMINPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x5E, 0xFF, .WIG,  .L0,   .VDIVPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x5E, 0xFF, .WIG,  .L1,   .VDIVPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0x5F, 0xFF, .WIG,  .L0,   .VMAXPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x5F, 0xFF, .WIG,  .L1,   .VMAXPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
+	{._0F,   0, 0x10, 0xFF, .WIG,  .L1,   .VMOVUPS,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x10, 0xFF, .WIG,  .L0,   .VMOVUPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x11, 0xFF, .WIG,  .L0,   .VMOVUPS,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x11, 0xFF, .WIG,  .L1,   .VMOVUPS,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x12, 0xFF, .WIG,  .L0,   .VMOVHLPS,         {.XMM,       .XMM,       .XMM,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x12, 0xFF, .WIG,  .L0,   .VMOVLPS,          {.XMM,       .XMM,       .M64,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x13, 0xFF, .WIG,  .L0,   .VMOVLPS,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x14, 0xFF, .WIG,  .L0,   .VUNPCKLPS,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x14, 0xFF, .WIG,  .L1,   .VUNPCKLPS,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x15, 0xFF, .WIG,  .L1,   .VUNPCKHPS,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x15, 0xFF, .WIG,  .L0,   .VUNPCKHPS,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x16, 0xFF, .WIG,  .L0,   .VMOVHPS,          {.XMM,       .XMM,       .M64,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x16, 0xFF, .WIG,  .L0,   .VMOVLHPS,         {.XMM,       .XMM,       .XMM,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x17, 0xFF, .WIG,  .L0,   .VMOVHPS,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x28, 0xFF, .WIG,  .L0,   .VMOVAPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x28, 0xFF, .WIG,  .L1,   .VMOVAPS,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x29, 0xFF, .WIG,  .L0,   .VMOVAPS,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x29, 0xFF, .WIG,  .L1,   .VMOVAPS,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x2B, 0xFF, .WIG,  .L1,   .VMOVNTPS,         {.M256,      .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x2B, 0xFF, .WIG,  .L0,   .VMOVNTPS,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x2E, 0xFF, .WIG,  .LIG,  .VUCOMISS,         {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x2F, 0xFF, .WIG,  .LIG,  .VCOMISS,          {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x41, 0xFF, .W0,   .L1,   .KANDW,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x41, 0xFF, .W1,   .L1,   .KANDQ,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x42, 0xFF, .W1,   .L1,   .KANDNQ,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x42, 0xFF, .W0,   .L1,   .KANDNW,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x44, 0xFF, .W1,   .L0,   .KNOTQ,            {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x44, 0xFF, .W0,   .L0,   .KNOTW,            {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x45, 0xFF, .W0,   .L1,   .KORW,             {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x45, 0xFF, .W1,   .L1,   .KORQ,             {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x46, 0xFF, .W1,   .L1,   .KXNORQ,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x46, 0xFF, .W0,   .L1,   .KXNORW,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x47, 0xFF, .W1,   .L1,   .KXORQ,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x47, 0xFF, .W0,   .L1,   .KXORW,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x4A, 0xFF, .W0,   .L1,   .KADDW,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x4A, 0xFF, .W1,   .L1,   .KADDQ,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x4B, 0xFF, .W1,   .L1,   .KUNPCKDQ,         {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x4B, 0xFF, .W0,   .L1,   .KUNPCKWD,         {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x50, 0xFF, .WIG,  .L1,   .VMOVMSKPS,        {.R32,       .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x50, 0xFF, .WIG,  .L0,   .VMOVMSKPS,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x51, 0xFF, .WIG,  .L1,   .VSQRTPS,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x51, 0xFF, .WIG,  .L0,   .VSQRTPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x52, 0xFF, .WIG,  .L1,   .VRSQRTPS,         {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x52, 0xFF, .WIG,  .L0,   .VRSQRTPS,         {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x53, 0xFF, .WIG,  .L0,   .VRCPPS,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x53, 0xFF, .WIG,  .L1,   .VRCPPS,           {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x54, 0xFF, .WIG,  .L0,   .VANDPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x54, 0xFF, .WIG,  .L1,   .VANDPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x55, 0xFF, .WIG,  .L0,   .VANDNPS,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x55, 0xFF, .WIG,  .L1,   .VANDNPS,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x56, 0xFF, .WIG,  .L0,   .VORPS,            {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x56, 0xFF, .WIG,  .L1,   .VORPS,            {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x57, 0xFF, .WIG,  .L0,   .VXORPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x57, 0xFF, .WIG,  .L1,   .VXORPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x58, 0xFF, .WIG,  .L0,   .VADDPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x58, 0xFF, .WIG,  .L1,   .VADDPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x59, 0xFF, .WIG,  .L0,   .VMULPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x59, 0xFF, .WIG,  .L1,   .VMULPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x5A, 0xFF, .WIG,  .L1,   .VCVTPS2PD,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x5A, 0xFF, .WIG,  .L0,   .VCVTPS2PD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x5B, 0xFF, .WIG,  .L1,   .VCVTDQ2PS,        {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x5B, 0xFF, .WIG,  .L0,   .VCVTDQ2PS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x5C, 0xFF, .WIG,  .L0,   .VSUBPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x5C, 0xFF, .WIG,  .L1,   .VSUBPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x5D, 0xFF, .WIG,  .L1,   .VMINPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x5D, 0xFF, .WIG,  .L0,   .VMINPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x5E, 0xFF, .WIG,  .L0,   .VDIVPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x5E, 0xFF, .WIG,  .L1,   .VDIVPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x5F, 0xFF, .WIG,  .L0,   .VMAXPS,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   0, 0x5F, 0xFF, .WIG,  .L1,   .VMAXPS,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
 	{._0F,   0, 0x77, 0xFF, .WIG,  .L1,   .VZEROALL,         {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
 	{._0F,   0, 0x77, 0xFF, .WIG,  .L0,   .VZEROUPPER,       {.NONE,      .NONE,      .NONE,      .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0x90, 0xFF, .W1,   .L0,   .KMOVQ,            {.K,         .K_M64,     .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   0, 0x90, 0xFF, .W0,   .L0,   .KMOVW,            {.K,         .K_M16,     .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   0, 0x91, 0xFF, .W1,   .L0,   .KMOVQ,            {.M64,       .K,         .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   0, 0x91, 0xFF, .W0,   .L0,   .KMOVW,            {.M16,       .K,         .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   0, 0x92, 0xFF, .W0,   .L0,   .KMOVW,            {.K,         .R32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   0, 0x93, 0xFF, .W0,   .L0,   .KMOVW,            {.R32,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   0, 0x98, 0xFF, .W0,   .L0,   .KORTESTW,         {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   0, 0x98, 0xFF, .W1,   .L0,   .KORTESTQ,         {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   0, 0x99, 0xFF, .W1,   .L0,   .KTESTQ,           {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   0, 0x99, 0xFF, .W0,   .L0,   .KTESTW,           {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   0, 0xC2, 0xFF, .WIG,  .L0,   .VCMPPS,           {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   0, 0xC2, 0xFF, .WIG,  .L1,   .VCMPPS,           {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0xC6, 0xFF, .WIG,  .L1,   .VSHUFPS,          {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   0, 0xC6, 0xFF, .WIG,  .L0,   .VSHUFPS,          {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x10, 0xFF, .WIG,  .L0,   .VMOVUPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x10, 0xFF, .WIG,  .L1,   .VMOVUPD,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x11, 0xFF, .WIG,  .L1,   .VMOVUPD,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x11, 0xFF, .WIG,  .L0,   .VMOVUPD,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x12, 0xFF, .WIG,  .L0,   .VMOVLPD,          {.XMM,       .XMM,       .M64,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x13, 0xFF, .WIG,  .L0,   .VMOVLPD,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x14, 0xFF, .WIG,  .L0,   .VUNPCKLPD,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x14, 0xFF, .WIG,  .L1,   .VUNPCKLPD,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x15, 0xFF, .WIG,  .L1,   .VUNPCKHPD,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x15, 0xFF, .WIG,  .L0,   .VUNPCKHPD,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x16, 0xFF, .WIG,  .L0,   .VMOVHPD,          {.XMM,       .XMM,       .M64,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x17, 0xFF, .WIG,  .L0,   .VMOVHPD,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x28, 0xFF, .WIG,  .L0,   .VMOVAPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x28, 0xFF, .WIG,  .L1,   .VMOVAPD,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x29, 0xFF, .WIG,  .L1,   .VMOVAPD,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x29, 0xFF, .WIG,  .L0,   .VMOVAPD,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x2B, 0xFF, .WIG,  .L0,   .VMOVNTPD,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x2B, 0xFF, .WIG,  .L1,   .VMOVNTPD,         {.M256,      .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x2E, 0xFF, .WIG,  .LIG,  .VUCOMISD,         {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX}},
-	{._0F,   1, 0x2F, 0xFF, .WIG,  .LIG,  .VCOMISD,          {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX}},
-	{._0F,   1, 0x41, 0xFF, .W1,   .L1,   .KANDD,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   1, 0x41, 0xFF, .W0,   .L1,   .KANDB,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   1, 0x42, 0xFF, .W0,   .L1,   .KANDNB,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   1, 0x42, 0xFF, .W1,   .L1,   .KANDND,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   1, 0x44, 0xFF, .W1,   .L0,   .KNOTD,            {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   1, 0x44, 0xFF, .W0,   .L0,   .KNOTB,            {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   1, 0x45, 0xFF, .W0,   .L1,   .KORB,             {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   1, 0x45, 0xFF, .W1,   .L1,   .KORD,             {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   1, 0x46, 0xFF, .W1,   .L1,   .KXNORD,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   1, 0x46, 0xFF, .W0,   .L1,   .KXNORB,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   1, 0x47, 0xFF, .W1,   .L1,   .KXORD,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   1, 0x47, 0xFF, .W0,   .L1,   .KXORB,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   1, 0x4A, 0xFF, .W0,   .L1,   .KADDB,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   1, 0x4A, 0xFF, .W1,   .L1,   .KADDD,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   1, 0x4B, 0xFF, .W0,   .L1,   .KUNPCKBW,         {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   1, 0x50, 0xFF, .WIG,  .L0,   .VMOVMSKPD,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x50, 0xFF, .WIG,  .L1,   .VMOVMSKPD,        {.R32,       .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x51, 0xFF, .WIG,  .L1,   .VSQRTPD,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x51, 0xFF, .WIG,  .L0,   .VSQRTPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x54, 0xFF, .WIG,  .L1,   .VANDPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x54, 0xFF, .WIG,  .L0,   .VANDPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x55, 0xFF, .WIG,  .L0,   .VANDNPD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x55, 0xFF, .WIG,  .L1,   .VANDNPD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x56, 0xFF, .WIG,  .L1,   .VORPD,            {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x56, 0xFF, .WIG,  .L0,   .VORPD,            {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x57, 0xFF, .WIG,  .L0,   .VXORPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x57, 0xFF, .WIG,  .L1,   .VXORPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x58, 0xFF, .WIG,  .L0,   .VADDPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x58, 0xFF, .WIG,  .L1,   .VADDPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x59, 0xFF, .WIG,  .L1,   .VMULPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x59, 0xFF, .WIG,  .L0,   .VMULPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x5A, 0xFF, .WIG,  .L0,   .VCVTPD2PS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x5A, 0xFF, .WIG,  .L1,   .VCVTPD2PS,        {.XMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x5B, 0xFF, .WIG,  .L0,   .VCVTPS2DQ,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x5B, 0xFF, .WIG,  .L1,   .VCVTPS2DQ,        {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x5C, 0xFF, .WIG,  .L1,   .VSUBPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x5C, 0xFF, .WIG,  .L0,   .VSUBPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x5D, 0xFF, .WIG,  .L0,   .VMINPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x5D, 0xFF, .WIG,  .L1,   .VMINPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x5E, 0xFF, .WIG,  .L1,   .VDIVPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x5E, 0xFF, .WIG,  .L0,   .VDIVPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x5F, 0xFF, .WIG,  .L0,   .VMAXPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x5F, 0xFF, .WIG,  .L1,   .VMAXPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x60, 0xFF, .WIG,  .L1,   .VPUNPCKLBW,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x60, 0xFF, .WIG,  .L0,   .VPUNPCKLBW,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x61, 0xFF, .WIG,  .L0,   .VPUNPCKLWD,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x61, 0xFF, .WIG,  .L1,   .VPUNPCKLWD,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x62, 0xFF, .WIG,  .L1,   .VPUNPCKLDQ,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x62, 0xFF, .WIG,  .L0,   .VPUNPCKLDQ,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x63, 0xFF, .WIG,  .L0,   .VPACKSSWB,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x63, 0xFF, .WIG,  .L1,   .VPACKSSWB,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x64, 0xFF, .WIG,  .L1,   .VPCMPGTB,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x64, 0xFF, .WIG,  .L0,   .VPCMPGTB,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x65, 0xFF, .WIG,  .L1,   .VPCMPGTW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x65, 0xFF, .WIG,  .L0,   .VPCMPGTW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x66, 0xFF, .WIG,  .L1,   .VPCMPGTD,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x66, 0xFF, .WIG,  .L0,   .VPCMPGTD,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x67, 0xFF, .WIG,  .L0,   .VPACKUSWB,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x67, 0xFF, .WIG,  .L1,   .VPACKUSWB,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x68, 0xFF, .WIG,  .L1,   .VPUNPCKHBW,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x68, 0xFF, .WIG,  .L0,   .VPUNPCKHBW,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x69, 0xFF, .WIG,  .L1,   .VPUNPCKHWD,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x69, 0xFF, .WIG,  .L0,   .VPUNPCKHWD,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x6A, 0xFF, .WIG,  .L0,   .VPUNPCKHDQ,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x6A, 0xFF, .WIG,  .L1,   .VPUNPCKHDQ,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x6B, 0xFF, .WIG,  .L0,   .VPACKSSDW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x6B, 0xFF, .WIG,  .L1,   .VPACKSSDW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x6C, 0xFF, .WIG,  .L0,   .VPUNPCKLQDQ,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x6C, 0xFF, .WIG,  .L1,   .VPUNPCKLQDQ,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x6D, 0xFF, .WIG,  .L0,   .VPUNPCKHQDQ,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x6D, 0xFF, .WIG,  .L1,   .VPUNPCKHQDQ,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x6E, 0xFF, .WIG,  .L0,   .VMOVD,            {.XMM,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x6E, 0xFF, .W1,   .L0,   .VMOVQ,            {.XMM,       .R64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   1, 0x6F, 0xFF, .WIG,  .L1,   .VMOVDQA,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x6F, 0xFF, .WIG,  .L0,   .VMOVDQA,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x70, 0xFF, .WIG,  .L0,   .VPSHUFD,          {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x70, 0xFF, .WIG,  .L1,   .VPSHUFD,          {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x71, 0x02, .WIG,  .L1,   .VPSRLW,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
-	{._0F,   1, 0x71, 0x02, .WIG,  .L0,   .VPSRLW,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F,   1, 0x71, 0x04, .WIG,  .L1,   .VPSRAW,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
-	{._0F,   1, 0x71, 0x04, .WIG,  .L0,   .VPSRAW,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F,   1, 0x71, 0x06, .WIG,  .L1,   .VPSLLW,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
-	{._0F,   1, 0x71, 0x06, .WIG,  .L0,   .VPSLLW,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x02, .WIG,  .L0,   .VPSRLD,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x02, .WIG,  .L1,   .VPSRLD,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x04, .WIG,  .L0,   .VPSRAD,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x04, .WIG,  .L1,   .VPSRAD,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x06, .WIG,  .L1,   .VPSLLD,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x06, .WIG,  .L0,   .VPSLLD,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F,   1, 0x73, 0x02, .WIG,  .L0,   .VPSRLQ,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F,   1, 0x73, 0x02, .WIG,  .L1,   .VPSRLQ,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
-	{._0F,   1, 0x73, 0x06, .WIG,  .L1,   .VPSLLQ,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}},
-	{._0F,   1, 0x73, 0x06, .WIG,  .L0,   .VPSLLQ,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F,   1, 0x74, 0xFF, .WIG,  .L0,   .VPCMPEQB,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x74, 0xFF, .WIG,  .L1,   .VPCMPEQB,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x75, 0xFF, .WIG,  .L0,   .VPCMPEQW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x75, 0xFF, .WIG,  .L1,   .VPCMPEQW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x76, 0xFF, .WIG,  .L0,   .VPCMPEQD,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x76, 0xFF, .WIG,  .L1,   .VPCMPEQD,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x7E, 0xFF, .WIG,  .L0,   .VMOVD,            {.RM32,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x7E, 0xFF, .W1,   .L0,   .VMOVQ,            {.R64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   1, 0x7F, 0xFF, .WIG,  .L1,   .VMOVDQA,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0x7F, 0xFF, .WIG,  .L0,   .VMOVDQA,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0x90, 0xFF, .W1,   .L0,   .KMOVD,            {.K,         .K_M32,     .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   1, 0x90, 0xFF, .W0,   .L0,   .KMOVB,            {.K,         .K_M8,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   1, 0x91, 0xFF, .W0,   .L0,   .KMOVB,            {.M8,        .K,         .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   1, 0x91, 0xFF, .W1,   .L0,   .KMOVD,            {.M32,       .K,         .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   1, 0x92, 0xFF, .W0,   .L0,   .KMOVB,            {.K,         .R32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   1, 0x93, 0xFF, .W0,   .L0,   .KMOVB,            {.R32,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   1, 0x98, 0xFF, .W0,   .L0,   .KORTESTB,         {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   1, 0x98, 0xFF, .W1,   .L0,   .KORTESTD,         {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   1, 0x99, 0xFF, .W1,   .L0,   .KTESTD,           {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   1, 0x99, 0xFF, .W0,   .L0,   .KTESTB,           {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   1, 0xC2, 0xFF, .WIG,  .L1,   .VCMPPD,           {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xC2, 0xFF, .WIG,  .L0,   .VCMPPD,           {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xC4, 0xFF, .WIG,  .L0,   .VPINSRW,          {.XMM,       .XMM,       .RM16,      .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xC5, 0xFF, .WIG,  .L0,   .VPEXTRW,          {.R32,       .XMM,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xC6, 0xFF, .WIG,  .L0,   .VSHUFPD,          {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xC6, 0xFF, .WIG,  .L1,   .VSHUFPD,          {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xD1, 0xFF, .WIG,  .L1,   .VPSRLW,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xD1, 0xFF, .WIG,  .L0,   .VPSRLW,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xD2, 0xFF, .WIG,  .L0,   .VPSRLD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xD2, 0xFF, .WIG,  .L1,   .VPSRLD,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xD3, 0xFF, .WIG,  .L1,   .VPSRLQ,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xD3, 0xFF, .WIG,  .L0,   .VPSRLQ,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xD4, 0xFF, .WIG,  .L0,   .VPADDQ,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xD4, 0xFF, .WIG,  .L1,   .VPADDQ,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xD5, 0xFF, .WIG,  .L0,   .VPMULLW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xD5, 0xFF, .WIG,  .L1,   .VPMULLW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xD6, 0xFF, .WIG,  .L0,   .VMOVQ,            {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xD7, 0xFF, .WIG,  .L0,   .VPMOVMSKB,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xD7, 0xFF, .WIG,  .L1,   .VPMOVMSKB,        {.R32,       .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xDB, 0xFF, .WIG,  .L1,   .VPAND,            {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xDB, 0xFF, .WIG,  .L0,   .VPAND,            {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xDF, 0xFF, .WIG,  .L1,   .VPANDN,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xDF, 0xFF, .WIG,  .L0,   .VPANDN,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xE1, 0xFF, .WIG,  .L1,   .VPSRAW,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xE1, 0xFF, .WIG,  .L0,   .VPSRAW,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xE2, 0xFF, .WIG,  .L1,   .VPSRAD,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xE2, 0xFF, .WIG,  .L0,   .VPSRAD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xE4, 0xFF, .WIG,  .L0,   .VPMULHUW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xE4, 0xFF, .WIG,  .L1,   .VPMULHUW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xE5, 0xFF, .WIG,  .L1,   .VPMULHW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xE5, 0xFF, .WIG,  .L0,   .VPMULHW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xE6, 0xFF, .WIG,  .L1,   .VCVTTPD2DQ,       {.XMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xE6, 0xFF, .WIG,  .L0,   .VCVTTPD2DQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xE7, 0xFF, .WIG,  .L1,   .VMOVNTDQ,         {.M256,      .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xE7, 0xFF, .WIG,  .L0,   .VMOVNTDQ,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xEB, 0xFF, .WIG,  .L1,   .VPOR,             {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xEB, 0xFF, .WIG,  .L0,   .VPOR,             {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xEF, 0xFF, .WIG,  .L0,   .VPXOR,            {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xEF, 0xFF, .WIG,  .L1,   .VPXOR,            {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xF1, 0xFF, .WIG,  .L0,   .VPSLLW,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xF1, 0xFF, .WIG,  .L1,   .VPSLLW,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xF2, 0xFF, .WIG,  .L0,   .VPSLLD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xF2, 0xFF, .WIG,  .L1,   .VPSLLD,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xF3, 0xFF, .WIG,  .L1,   .VPSLLQ,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xF3, 0xFF, .WIG,  .L0,   .VPSLLQ,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xF4, 0xFF, .WIG,  .L0,   .VPMULUDQ,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xF4, 0xFF, .WIG,  .L1,   .VPMULUDQ,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xF5, 0xFF, .WIG,  .L1,   .VPMADDWD,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xF5, 0xFF, .WIG,  .L0,   .VPMADDWD,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xF7, 0xFF, .WIG,  .L0,   .VMASKMOVDQU,      {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xF8, 0xFF, .WIG,  .L1,   .VPSUBB,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xF8, 0xFF, .WIG,  .L0,   .VPSUBB,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xF9, 0xFF, .WIG,  .L1,   .VPSUBW,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xF9, 0xFF, .WIG,  .L0,   .VPSUBW,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xFA, 0xFF, .WIG,  .L0,   .VPSUBD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xFA, 0xFF, .WIG,  .L1,   .VPSUBD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xFB, 0xFF, .WIG,  .L1,   .VPSUBQ,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xFB, 0xFF, .WIG,  .L0,   .VPSUBQ,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xFC, 0xFF, .WIG,  .L0,   .VPADDB,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xFC, 0xFF, .WIG,  .L1,   .VPADDB,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xFD, 0xFF, .WIG,  .L0,   .VPADDW,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xFD, 0xFF, .WIG,  .L1,   .VPADDW,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   1, 0xFE, 0xFF, .WIG,  .L0,   .VPADDD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   1, 0xFE, 0xFF, .WIG,  .L1,   .VPADDD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   2, 0x10, 0xFF, .WIG,  .LIG,  .VMOVSS,           {.XMM,       .M32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x10, 0xFF, .WIG,  .LIG,  .VMOVSS,           {.XMM,       .XMM,       .XMM,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x11, 0xFF, .WIG,  .LIG,  .VMOVSS,           {.M32,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x2A, 0xFF, .W1,   .LIG,  .VCVTSI2SS,        {.XMM,       .XMM,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}},
-	{._0F,   2, 0x2A, 0xFF, .WIG,  .LIG,  .VCVTSI2SS,        {.XMM,       .XMM,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x2C, 0xFF, .WIG,  .LIG,  .VCVTTSS2SI,       {.R32,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x2C, 0xFF, .W1,   .LIG,  .VCVTTSS2SI,       {.R64,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}},
-	{._0F,   2, 0x2D, 0xFF, .WIG,  .LIG,  .VCVTSS2SI,        {.R32,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x2D, 0xFF, .W1,   .LIG,  .VCVTSS2SI,        {.R64,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}},
-	{._0F,   2, 0x51, 0xFF, .WIG,  .LIG,  .VSQRTSS,          {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x52, 0xFF, .WIG,  .LIG,  .VRSQRTSS,         {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x53, 0xFF, .WIG,  .LIG,  .VRCPSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x58, 0xFF, .WIG,  .LIG,  .VADDSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x59, 0xFF, .WIG,  .LIG,  .VMULSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x5A, 0xFF, .WIG,  .LIG,  .VCVTSS2SD,        {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x5B, 0xFF, .WIG,  .L1,   .VCVTTPS2DQ,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   2, 0x5B, 0xFF, .WIG,  .L0,   .VCVTTPS2DQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   2, 0x5C, 0xFF, .WIG,  .LIG,  .VSUBSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x5D, 0xFF, .WIG,  .LIG,  .VMINSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x5E, 0xFF, .WIG,  .LIG,  .VDIVSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x5F, 0xFF, .WIG,  .LIG,  .VMAXSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0x6F, 0xFF, .WIG,  .L1,   .VMOVDQU,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   2, 0x6F, 0xFF, .WIG,  .L0,   .VMOVDQU,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   2, 0x70, 0xFF, .WIG,  .L1,   .VPSHUFHW,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   2, 0x70, 0xFF, .WIG,  .L0,   .VPSHUFHW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   2, 0x7E, 0xFF, .WIG,  .L0,   .VMOVQ,            {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   2, 0x7F, 0xFF, .WIG,  .L1,   .VMOVDQU,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   2, 0x7F, 0xFF, .WIG,  .L0,   .VMOVDQU,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   2, 0xC2, 0xFF, .WIG,  .LIG,  .VCMPSS,           {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=2, vex_type=.VEX}},
-	{._0F,   2, 0xE6, 0xFF, .WIG,  .L1,   .VCVTDQ2PD,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   2, 0xE6, 0xFF, .WIG,  .L0,   .VCVTDQ2PD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   3, 0x10, 0xFF, .WIG,  .LIG,  .VMOVSD,           {.XMM,       .XMM,       .XMM,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x10, 0xFF, .WIG,  .LIG,  .VMOVSD,           {.XMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x11, 0xFF, .WIG,  .LIG,  .VMOVSD,           {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x2A, 0xFF, .WIG,  .LIG,  .VCVTSI2SD,        {.XMM,       .XMM,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x2A, 0xFF, .W1,   .LIG,  .VCVTSI2SD,        {.XMM,       .XMM,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}},
-	{._0F,   3, 0x2C, 0xFF, .W1,   .LIG,  .VCVTTSD2SI,       {.R64,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}},
-	{._0F,   3, 0x2C, 0xFF, .WIG,  .LIG,  .VCVTTSD2SI,       {.R32,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x2D, 0xFF, .WIG,  .LIG,  .VCVTSD2SI,        {.R32,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x2D, 0xFF, .W1,   .LIG,  .VCVTSD2SI,        {.R64,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}},
-	{._0F,   3, 0x51, 0xFF, .WIG,  .LIG,  .VSQRTSD,          {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x58, 0xFF, .WIG,  .LIG,  .VADDSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x59, 0xFF, .WIG,  .LIG,  .VMULSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x5A, 0xFF, .WIG,  .LIG,  .VCVTSD2SS,        {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x5C, 0xFF, .WIG,  .LIG,  .VSUBSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x5D, 0xFF, .WIG,  .LIG,  .VMINSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x5E, 0xFF, .WIG,  .LIG,  .VDIVSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x5F, 0xFF, .WIG,  .LIG,  .VMAXSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0x70, 0xFF, .WIG,  .L1,   .VPSHUFLW,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   3, 0x70, 0xFF, .WIG,  .L0,   .VPSHUFLW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0}},
-	{._0F,   3, 0x92, 0xFF, .W1,   .L0,   .KMOVQ,            {.K,         .R64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   3, 0x92, 0xFF, .W0,   .L0,   .KMOVD,            {.K,         .R32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   3, 0x93, 0xFF, .W0,   .L0,   .KMOVD,            {.R32,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   3, 0x93, 0xFF, .W1,   .L0,   .KMOVQ,            {.R64,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   3, 0xC2, 0xFF, .WIG,  .LIG,  .VCMPSD,           {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=3, vex_type=.VEX}},
-	{._0F,   3, 0xE6, 0xFF, .WIG,  .L1,   .VCVTPD2DQ,        {.XMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1}},
-	{._0F,   3, 0xE6, 0xFF, .WIG,  .L0,   .VCVTPD2DQ,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 0, 0xF2, 0xFF, .W1,   .L0,   .ANDN,             {.R64,       .R64,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 0, 0xF2, 0xFF, .W0,   .L0,   .ANDN,             {.R32,       .R32,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 0, 0xF3, 0x01, .W1,   .L0,   .BLSR,             {.R64,       .RM64,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F38, 0, 0xF3, 0x01, .W0,   .L0,   .BLSR,             {.R32,       .RM32,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F38, 0, 0xF3, 0x02, .W0,   .L0,   .BLSMSK,           {.R32,       .RM32,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F38, 0, 0xF3, 0x02, .W1,   .L0,   .BLSMSK,           {.R64,       .RM64,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F38, 0, 0xF3, 0x03, .W1,   .L0,   .BLSI,             {.R64,       .RM64,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F38, 0, 0xF3, 0x03, .W0,   .L0,   .BLSI,             {.R32,       .RM32,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F38, 0, 0xF5, 0xFF, .W0,   .L0,   .BZHI,             {.R32,       .RM32,      .R32,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 0, 0xF5, 0xFF, .W1,   .L0,   .BZHI,             {.R64,       .RM64,      .R64,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 0, 0xF7, 0xFF, .W1,   .L0,   .BEXTR,            {.R64,       .RM64,      .R64,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 0, 0xF7, 0xFF, .W0,   .L0,   .BEXTR,            {.R32,       .RM32,      .R32,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x00, 0xFF, .WIG,  .L0,   .VPSHUFB,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x00, 0xFF, .WIG,  .L1,   .VPSHUFB,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x01, 0xFF, .WIG,  .L0,   .VPHADDW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x01, 0xFF, .WIG,  .L1,   .VPHADDW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x02, 0xFF, .WIG,  .L1,   .VPHADDD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x02, 0xFF, .WIG,  .L0,   .VPHADDD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x03, 0xFF, .WIG,  .L0,   .VPHADDSW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x03, 0xFF, .WIG,  .L1,   .VPHADDSW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x04, 0xFF, .WIG,  .L0,   .VPMADDUBSW,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x04, 0xFF, .WIG,  .L1,   .VPMADDUBSW,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x05, 0xFF, .WIG,  .L0,   .VPHSUBW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x05, 0xFF, .WIG,  .L1,   .VPHSUBW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x06, 0xFF, .WIG,  .L1,   .VPHSUBD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x06, 0xFF, .WIG,  .L0,   .VPHSUBD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x07, 0xFF, .WIG,  .L1,   .VPHSUBSW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x07, 0xFF, .WIG,  .L0,   .VPHSUBSW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x08, 0xFF, .WIG,  .L1,   .VPSIGNB,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x08, 0xFF, .WIG,  .L0,   .VPSIGNB,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x09, 0xFF, .WIG,  .L0,   .VPSIGNW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x09, 0xFF, .WIG,  .L1,   .VPSIGNW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x0A, 0xFF, .WIG,  .L0,   .VPSIGND,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x0A, 0xFF, .WIG,  .L1,   .VPSIGND,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x0B, 0xFF, .WIG,  .L1,   .VPMULHRSW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x0B, 0xFF, .WIG,  .L0,   .VPMULHRSW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x0E, 0xFF, .WIG,  .L1,   .VTESTPS,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x0E, 0xFF, .WIG,  .L0,   .VTESTPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x0F, 0xFF, .WIG,  .L0,   .VTESTPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x0F, 0xFF, .WIG,  .L1,   .VTESTPD,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x13, 0xFF, .WIG,  .L0,   .VCVTPH2PS,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x13, 0xFF, .WIG,  .L1,   .VCVTPH2PS,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x16, 0xFF, .W0,   .L1,   .VPERMPS,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x17, 0xFF, .WIG,  .L0,   .VPTEST,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x17, 0xFF, .WIG,  .L1,   .VPTEST,           {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x18, 0xFF, .WIG,  .L1,   .VBROADCASTSS,     {.YMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x18, 0xFF, .WIG,  .L0,   .VBROADCASTSS,     {.XMM,       .M32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x18, 0xFF, .WIG,  .L1,   .VBROADCASTSS,     {.YMM,       .M32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x18, 0xFF, .WIG,  .L0,   .VBROADCASTSS,     {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x19, 0xFF, .WIG,  .L1,   .VBROADCASTSD,     {.YMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x19, 0xFF, .WIG,  .L1,   .VBROADCASTSD,     {.YMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x1A, 0xFF, .WIG,  .L1,   .VBROADCASTF128,   {.YMM,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x1C, 0xFF, .WIG,  .L1,   .VPABSB,           {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x1C, 0xFF, .WIG,  .L0,   .VPABSB,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x1D, 0xFF, .WIG,  .L0,   .VPABSW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x1D, 0xFF, .WIG,  .L1,   .VPABSW,           {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x1E, 0xFF, .WIG,  .L0,   .VPABSD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x1E, 0xFF, .WIG,  .L1,   .VPABSD,           {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x20, 0xFF, .WIG,  .L1,   .VPMOVSXBW,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x20, 0xFF, .WIG,  .L0,   .VPMOVSXBW,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x21, 0xFF, .WIG,  .L0,   .VPMOVSXBD,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x21, 0xFF, .WIG,  .L1,   .VPMOVSXBD,        {.YMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x22, 0xFF, .WIG,  .L1,   .VPMOVSXBQ,        {.YMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x22, 0xFF, .WIG,  .L0,   .VPMOVSXBQ,        {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x23, 0xFF, .WIG,  .L0,   .VPMOVSXWD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x23, 0xFF, .WIG,  .L1,   .VPMOVSXWD,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x24, 0xFF, .WIG,  .L0,   .VPMOVSXWQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x24, 0xFF, .WIG,  .L1,   .VPMOVSXWQ,        {.YMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x25, 0xFF, .WIG,  .L1,   .VPMOVSXDQ,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x25, 0xFF, .WIG,  .L0,   .VPMOVSXDQ,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x28, 0xFF, .WIG,  .L1,   .VPMULDQ,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x28, 0xFF, .WIG,  .L0,   .VPMULDQ,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x29, 0xFF, .WIG,  .L1,   .VPCMPEQQ,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x29, 0xFF, .WIG,  .L0,   .VPCMPEQQ,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x2A, 0xFF, .WIG,  .L0,   .VMOVNTDQA,        {.XMM,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x2A, 0xFF, .WIG,  .L1,   .VMOVNTDQA,        {.YMM,       .M256,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x2B, 0xFF, .WIG,  .L1,   .VPACKUSDW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x2B, 0xFF, .WIG,  .L0,   .VPACKUSDW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x2C, 0xFF, .WIG,  .L0,   .VMASKMOVPS,       {.XMM,       .XMM,       .M128,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x2C, 0xFF, .WIG,  .L1,   .VMASKMOVPS,       {.YMM,       .YMM,       .M256,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x2D, 0xFF, .WIG,  .L1,   .VMASKMOVPD,       {.YMM,       .YMM,       .M256,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x2D, 0xFF, .WIG,  .L0,   .VMASKMOVPD,       {.XMM,       .XMM,       .M128,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x2E, 0xFF, .WIG,  .L0,   .VMASKMOVPS,       {.M128,      .XMM,       .XMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x2E, 0xFF, .WIG,  .L1,   .VMASKMOVPS,       {.M256,      .YMM,       .YMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x2F, 0xFF, .WIG,  .L1,   .VMASKMOVPD,       {.M256,      .YMM,       .YMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x2F, 0xFF, .WIG,  .L0,   .VMASKMOVPD,       {.M128,      .XMM,       .XMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x30, 0xFF, .WIG,  .L1,   .VPMOVZXBW,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x30, 0xFF, .WIG,  .L0,   .VPMOVZXBW,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x31, 0xFF, .WIG,  .L1,   .VPMOVZXBD,        {.YMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x31, 0xFF, .WIG,  .L0,   .VPMOVZXBD,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x32, 0xFF, .WIG,  .L1,   .VPMOVZXBQ,        {.YMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x32, 0xFF, .WIG,  .L0,   .VPMOVZXBQ,        {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x33, 0xFF, .WIG,  .L0,   .VPMOVZXWD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x33, 0xFF, .WIG,  .L1,   .VPMOVZXWD,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x34, 0xFF, .WIG,  .L0,   .VPMOVZXWQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x34, 0xFF, .WIG,  .L1,   .VPMOVZXWQ,        {.YMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x35, 0xFF, .WIG,  .L1,   .VPMOVZXDQ,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x35, 0xFF, .WIG,  .L0,   .VPMOVZXDQ,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x36, 0xFF, .W0,   .L1,   .VPERMD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x37, 0xFF, .WIG,  .L0,   .VPCMPGTQ,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x37, 0xFF, .WIG,  .L1,   .VPCMPGTQ,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x38, 0xFF, .WIG,  .L0,   .VPMINSB,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x38, 0xFF, .WIG,  .L1,   .VPMINSB,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x39, 0xFF, .WIG,  .L0,   .VPMINSD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x39, 0xFF, .WIG,  .L1,   .VPMINSD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x3A, 0xFF, .WIG,  .L0,   .VPMINUW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x3A, 0xFF, .WIG,  .L1,   .VPMINUW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x3B, 0xFF, .WIG,  .L0,   .VPMINUD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x3B, 0xFF, .WIG,  .L1,   .VPMINUD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x3C, 0xFF, .WIG,  .L1,   .VPMAXSB,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x3C, 0xFF, .WIG,  .L0,   .VPMAXSB,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x3D, 0xFF, .WIG,  .L0,   .VPMAXSD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x3D, 0xFF, .WIG,  .L1,   .VPMAXSD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x3E, 0xFF, .WIG,  .L1,   .VPMAXUW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x3E, 0xFF, .WIG,  .L0,   .VPMAXUW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x3F, 0xFF, .WIG,  .L0,   .VPMAXUD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x3F, 0xFF, .WIG,  .L1,   .VPMAXUD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x40, 0xFF, .WIG,  .L1,   .VPMULLD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x40, 0xFF, .WIG,  .L0,   .VPMULLD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x41, 0xFF, .WIG,  .L0,   .VPHMINPOSUW,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0x45, 0xFF, .W1,   .L0,   .VPSRLVQ,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x45, 0xFF, .W0,   .L1,   .VPSRLVD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x45, 0xFF, .W1,   .L1,   .VPSRLVQ,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x45, 0xFF, .W0,   .L0,   .VPSRLVD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x46, 0xFF, .W0,   .L0,   .VPSRAVD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x46, 0xFF, .W0,   .L1,   .VPSRAVD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x47, 0xFF, .W1,   .L1,   .VPSLLVQ,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x47, 0xFF, .W1,   .L0,   .VPSLLVQ,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x47, 0xFF, .W0,   .L0,   .VPSLLVD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x47, 0xFF, .W0,   .L1,   .VPSLLVD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x5A, 0xFF, .WIG,  .L1,   .VBROADCASTI128,   {.YMM,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F38, 1, 0x8C, 0xFF, .W1,   .L1,   .VPMASKMOVQ,       {.YMM,       .YMM,       .M256,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x8C, 0xFF, .W0,   .L0,   .VPMASKMOVD,       {.XMM,       .XMM,       .M128,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x8C, 0xFF, .W0,   .L1,   .VPMASKMOVD,       {.YMM,       .YMM,       .M256,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x8C, 0xFF, .W1,   .L0,   .VPMASKMOVQ,       {.XMM,       .XMM,       .M128,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x8E, 0xFF, .W0,   .L0,   .VPMASKMOVD,       {.M128,      .XMM,       .XMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x8E, 0xFF, .W1,   .L1,   .VPMASKMOVQ,       {.M256,      .YMM,       .YMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x8E, 0xFF, .W1,   .L0,   .VPMASKMOVQ,       {.M128,      .XMM,       .XMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x8E, 0xFF, .W0,   .L1,   .VPMASKMOVD,       {.M256,      .YMM,       .YMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x90, 0xFF, .W0,   .L1,   .VPGATHERDD,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x90, 0xFF, .W0,   .L0,   .VPGATHERDD,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x90, 0xFF, .W1,   .L1,   .VPGATHERDQ,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x90, 0xFF, .W1,   .L0,   .VPGATHERDQ,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x91, 0xFF, .W1,   .L1,   .VPGATHERQQ,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x91, 0xFF, .W0,   .L1,   .VPGATHERQD,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x91, 0xFF, .W1,   .L0,   .VPGATHERQQ,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x91, 0xFF, .W0,   .L0,   .VPGATHERQD,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x92, 0xFF, .W1,   .L0,   .VGATHERDPD,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x92, 0xFF, .W0,   .L0,   .VGATHERDPS,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x92, 0xFF, .W0,   .L1,   .VGATHERDPS,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x92, 0xFF, .W1,   .L1,   .VGATHERDPD,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x93, 0xFF, .W1,   .L0,   .VGATHERQPD,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x93, 0xFF, .W0,   .L0,   .VGATHERQPS,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x93, 0xFF, .W1,   .L1,   .VGATHERQPD,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x93, 0xFF, .W0,   .L1,   .VGATHERQPS,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x96, 0xFF, .W1,   .L0,   .VFMADDSUB132PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x96, 0xFF, .W0,   .L1,   .VFMADDSUB132PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x96, 0xFF, .W1,   .L1,   .VFMADDSUB132PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x96, 0xFF, .W0,   .L0,   .VFMADDSUB132PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x97, 0xFF, .W1,   .L0,   .VFMSUBADD132PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x97, 0xFF, .W1,   .L1,   .VFMSUBADD132PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x97, 0xFF, .W0,   .L1,   .VFMSUBADD132PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x97, 0xFF, .W0,   .L0,   .VFMSUBADD132PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x98, 0xFF, .W1,   .L0,   .VFMADD132PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x98, 0xFF, .W1,   .L1,   .VFMADD132PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x98, 0xFF, .W0,   .L0,   .VFMADD132PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x98, 0xFF, .W0,   .L1,   .VFMADD132PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x99, 0xFF, .W1,   .LIG,  .VFMADD132SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0x99, 0xFF, .W0,   .LIG,  .VFMADD132SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0x9A, 0xFF, .W1,   .L0,   .VFMSUB132PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x9A, 0xFF, .W0,   .L1,   .VFMSUB132PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x9A, 0xFF, .W1,   .L1,   .VFMSUB132PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x9A, 0xFF, .W0,   .L0,   .VFMSUB132PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x9B, 0xFF, .W0,   .LIG,  .VFMSUB132SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0x9B, 0xFF, .W1,   .LIG,  .VFMSUB132SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0x9C, 0xFF, .W0,   .L0,   .VFNMADD132PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x9C, 0xFF, .W1,   .L1,   .VFNMADD132PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x9C, 0xFF, .W0,   .L1,   .VFNMADD132PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x9C, 0xFF, .W1,   .L0,   .VFNMADD132PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x9D, 0xFF, .W1,   .LIG,  .VFNMADD132SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0x9D, 0xFF, .W0,   .LIG,  .VFNMADD132SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0x9E, 0xFF, .W0,   .L1,   .VFNMSUB132PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x9E, 0xFF, .W0,   .L0,   .VFNMSUB132PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x9E, 0xFF, .W1,   .L0,   .VFNMSUB132PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x9E, 0xFF, .W1,   .L1,   .VFNMSUB132PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x9F, 0xFF, .W0,   .LIG,  .VFNMSUB132SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0x9F, 0xFF, .W1,   .LIG,  .VFNMSUB132SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0xA6, 0xFF, .W1,   .L1,   .VFMADDSUB213PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xA6, 0xFF, .W0,   .L0,   .VFMADDSUB213PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xA6, 0xFF, .W1,   .L0,   .VFMADDSUB213PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xA6, 0xFF, .W0,   .L1,   .VFMADDSUB213PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xA7, 0xFF, .W1,   .L0,   .VFMSUBADD213PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xA7, 0xFF, .W1,   .L1,   .VFMSUBADD213PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xA7, 0xFF, .W0,   .L0,   .VFMSUBADD213PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xA7, 0xFF, .W0,   .L1,   .VFMSUBADD213PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xA8, 0xFF, .W1,   .L0,   .VFMADD213PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xA8, 0xFF, .W1,   .L1,   .VFMADD213PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xA8, 0xFF, .W0,   .L1,   .VFMADD213PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xA8, 0xFF, .W0,   .L0,   .VFMADD213PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xA9, 0xFF, .W0,   .LIG,  .VFMADD213SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0xA9, 0xFF, .W1,   .LIG,  .VFMADD213SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0xAA, 0xFF, .W1,   .L0,   .VFMSUB213PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xAA, 0xFF, .W0,   .L0,   .VFMSUB213PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xAA, 0xFF, .W0,   .L1,   .VFMSUB213PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xAA, 0xFF, .W1,   .L1,   .VFMSUB213PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xAB, 0xFF, .W1,   .LIG,  .VFMSUB213SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0xAB, 0xFF, .W0,   .LIG,  .VFMSUB213SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0xAC, 0xFF, .W0,   .L1,   .VFNMADD213PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xAC, 0xFF, .W1,   .L1,   .VFNMADD213PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xAC, 0xFF, .W0,   .L0,   .VFNMADD213PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xAC, 0xFF, .W1,   .L0,   .VFNMADD213PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xAD, 0xFF, .W1,   .LIG,  .VFNMADD213SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0xAD, 0xFF, .W0,   .LIG,  .VFNMADD213SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0xAE, 0xFF, .W0,   .L1,   .VFNMSUB213PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xAE, 0xFF, .W1,   .L0,   .VFNMSUB213PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xAE, 0xFF, .W1,   .L1,   .VFNMSUB213PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xAE, 0xFF, .W0,   .L0,   .VFNMSUB213PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xAF, 0xFF, .W0,   .LIG,  .VFNMSUB213SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0xAF, 0xFF, .W1,   .LIG,  .VFNMSUB213SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0xB6, 0xFF, .W0,   .L1,   .VFMADDSUB231PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xB6, 0xFF, .W0,   .L0,   .VFMADDSUB231PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xB6, 0xFF, .W1,   .L0,   .VFMADDSUB231PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xB6, 0xFF, .W1,   .L1,   .VFMADDSUB231PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xB7, 0xFF, .W1,   .L0,   .VFMSUBADD231PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xB7, 0xFF, .W0,   .L1,   .VFMSUBADD231PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xB7, 0xFF, .W0,   .L0,   .VFMSUBADD231PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xB7, 0xFF, .W1,   .L1,   .VFMSUBADD231PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xB8, 0xFF, .W1,   .L1,   .VFMADD231PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xB8, 0xFF, .W0,   .L1,   .VFMADD231PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xB8, 0xFF, .W0,   .L0,   .VFMADD231PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xB8, 0xFF, .W1,   .L0,   .VFMADD231PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xB9, 0xFF, .W1,   .LIG,  .VFMADD231SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0xB9, 0xFF, .W0,   .LIG,  .VFMADD231SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0xBA, 0xFF, .W1,   .L1,   .VFMSUB231PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xBA, 0xFF, .W1,   .L0,   .VFMSUB231PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xBA, 0xFF, .W0,   .L1,   .VFMSUB231PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xBA, 0xFF, .W0,   .L0,   .VFMSUB231PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xBB, 0xFF, .W1,   .LIG,  .VFMSUB231SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0xBB, 0xFF, .W0,   .LIG,  .VFMSUB231SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0xBC, 0xFF, .W1,   .L0,   .VFNMADD231PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xBC, 0xFF, .W1,   .L1,   .VFNMADD231PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xBC, 0xFF, .W0,   .L0,   .VFNMADD231PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xBC, 0xFF, .W0,   .L1,   .VFNMADD231PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xBD, 0xFF, .W1,   .LIG,  .VFNMADD231SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0xBD, 0xFF, .W0,   .LIG,  .VFNMADD231SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0xBE, 0xFF, .W1,   .L1,   .VFNMSUB231PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xBE, 0xFF, .W1,   .L0,   .VFNMSUB231PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xBE, 0xFF, .W0,   .L1,   .VFNMSUB231PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xBE, 0xFF, .W0,   .L0,   .VFNMSUB231PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xBF, 0xFF, .W1,   .LIG,  .VFNMSUB231SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}},
-	{._0F38, 1, 0xBF, 0xFF, .W0,   .LIG,  .VFNMSUB231SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}},
-	{._0F38, 1, 0xDB, 0xFF, .WIG,  .L0,   .VAESIMC,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0xDC, 0xFF, .WIG,  .L0,   .VAESENC,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0xDD, 0xFF, .WIG,  .L0,   .VAESENCLAST,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0xDE, 0xFF, .WIG,  .L0,   .VAESDEC,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0xDF, 0xFF, .WIG,  .L0,   .VAESDECLAST,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F38, 1, 0xF7, 0xFF, .W1,   .L0,   .SHLX,             {.R64,       .RM64,      .R64,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xF7, 0xFF, .W0,   .L0,   .SHLX,             {.R32,       .RM32,      .R32,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0xF5, 0xFF, .W1,   .L0,   .PEXT,             {.R64,       .R64,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 2, 0xF5, 0xFF, .W0,   .L0,   .PEXT,             {.R32,       .R32,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0xF7, 0xFF, .W0,   .L0,   .SARX,             {.R32,       .RM32,      .R32,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0xF7, 0xFF, .W1,   .L0,   .SARX,             {.R64,       .RM64,      .R64,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 3, 0xF5, 0xFF, .W0,   .L0,   .PDEP,             {.R32,       .R32,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 3, 0xF5, 0xFF, .W1,   .L0,   .PDEP,             {.R64,       .R64,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 3, 0xF6, 0xFF, .W1,   .L0,   .MULX,             {.R64,       .R64,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 3, 0xF6, 0xFF, .W0,   .L0,   .MULX,             {.R32,       .R32,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 3, 0xF7, 0xFF, .W0,   .L0,   .SHRX,             {.R32,       .RM32,      .R32,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 3, 0xF7, 0xFF, .W1,   .L0,   .SHRX,             {.R64,       .RM64,      .R64,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x00, 0xFF, .W1,   .L1,   .VPERMQ,           {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x01, 0xFF, .W1,   .L1,   .VPERMPD,          {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x02, 0xFF, .W0,   .L1,   .VPBLENDD,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x02, 0xFF, .W0,   .L0,   .VPBLENDD,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x06, 0xFF, .WIG,  .L1,   .VPERM2F128,       {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x08, 0xFF, .WIG,  .L1,   .VROUNDPS,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x08, 0xFF, .WIG,  .L0,   .VROUNDPS,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x09, 0xFF, .WIG,  .L0,   .VROUNDPD,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x09, 0xFF, .WIG,  .L1,   .VROUNDPD,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x0A, 0xFF, .WIG,  .LIG,  .VROUNDSS,         {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX}},
-	{._0F3A, 1, 0x0B, 0xFF, .WIG,  .LIG,  .VROUNDSD,         {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX}},
-	{._0F3A, 1, 0x0C, 0xFF, .WIG,  .L0,   .VBLENDPS,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x0C, 0xFF, .WIG,  .L1,   .VBLENDPS,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x0D, 0xFF, .WIG,  .L1,   .VBLENDPD,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x0D, 0xFF, .WIG,  .L0,   .VBLENDPD,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x0E, 0xFF, .WIG,  .L1,   .VPBLENDW,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x0E, 0xFF, .WIG,  .L0,   .VPBLENDW,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x0F, 0xFF, .WIG,  .L1,   .VPALIGNR,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x0F, 0xFF, .WIG,  .L0,   .VPALIGNR,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x14, 0xFF, .WIG,  .L0,   .VPEXTRB,          {.RM8,       .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x15, 0xFF, .WIG,  .L0,   .VPEXTRW,          {.RM16,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x16, 0xFF, .WIG,  .L0,   .VPEXTRD,          {.RM32,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x16, 0xFF, .W1,   .L0,   .VPEXTRQ,          {.RM64,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x17, 0xFF, .WIG,  .L0,   .VEXTRACTPS,       {.RM32,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x18, 0xFF, .WIG,  .L1,   .VINSERTF128,      {.YMM,       .YMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x19, 0xFF, .WIG,  .L1,   .VEXTRACTF128,     {.XMM_M128,  .YMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x1D, 0xFF, .WIG,  .L1,   .VCVTPS2PH,        {.XMM_M128,  .YMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x1D, 0xFF, .WIG,  .L0,   .VCVTPS2PH,        {.XMM_M64,   .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x20, 0xFF, .WIG,  .L0,   .VPINSRB,          {.XMM,       .XMM,       .RM8,       .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x21, 0xFF, .WIG,  .L0,   .VINSERTPS,        {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x22, 0xFF, .WIG,  .L0,   .VPINSRD,          {.XMM,       .XMM,       .RM32,      .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x22, 0xFF, .W1,   .L0,   .VPINSRQ,          {.XMM,       .XMM,       .RM64,      .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x30, 0xFF, .W0,   .L0,   .KSHIFTRB,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x30, 0xFF, .W1,   .L0,   .KSHIFTRW,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x31, 0xFF, .W0,   .L0,   .KSHIFTRD,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x31, 0xFF, .W1,   .L0,   .KSHIFTRQ,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x32, 0xFF, .W1,   .L0,   .KSHIFTLW,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x32, 0xFF, .W0,   .L0,   .KSHIFTLB,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x33, 0xFF, .W0,   .L0,   .KSHIFTLD,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x33, 0xFF, .W1,   .L0,   .KSHIFTLQ,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x38, 0xFF, .WIG,  .L1,   .VINSERTI128,      {.YMM,       .YMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x39, 0xFF, .WIG,  .L1,   .VEXTRACTI128,     {.XMM_M128,  .YMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x40, 0xFF, .WIG,  .L1,   .VDPPS,            {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x40, 0xFF, .WIG,  .L0,   .VDPPS,            {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x41, 0xFF, .WIG,  .L0,   .VDPPD,            {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x42, 0xFF, .WIG,  .L0,   .VMPSADBW,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x42, 0xFF, .WIG,  .L1,   .VMPSADBW,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x44, 0xFF, .WIG,  .L0,   .VPCLMULQDQ,       {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 1, 0x44, 0xFF, .WIG,  .L1,   .VPCLMULQDQ,       {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x46, 0xFF, .WIG,  .L1,   .VPERM2I128,       {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}},
-	{._0F3A, 1, 0x4A, 0xFF, .W0,   .L0,   .VBLENDVPS,        {.XMM,       .XMM,       .XMM_M128,  .XMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x4A, 0xFF, .W0,   .L1,   .VBLENDVPS,        {.YMM,       .YMM,       .YMM_M256,  .YMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x4B, 0xFF, .W0,   .L1,   .VBLENDVPD,        {.YMM,       .YMM,       .YMM_M256,  .YMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x4B, 0xFF, .W0,   .L0,   .VBLENDVPD,        {.XMM,       .XMM,       .XMM_M128,  .XMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x4C, 0xFF, .W0,   .L1,   .VPBLENDVB,        {.YMM,       .YMM,       .YMM_M256,  .YMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x4C, 0xFF, .W0,   .L0,   .VPBLENDVB,        {.XMM,       .XMM,       .XMM_M128,  .XMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0xDF, 0xFF, .WIG,  .L0,   .VAESKEYGENASSIST, {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}},
-	{._0F3A, 3, 0xF0, 0xFF, .W0,   .L0,   .RORX,             {.R32,       .RM32,      .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 3, 0xF0, 0xFF, .W1,   .L0,   .RORX,             {.R64,       .RM64,      .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}},
+	{._0F,   0, 0x90, 0xFF, .W1,   .L0,   .KMOVQ,            {.K,         .K_M64,     .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x90, 0xFF, .W0,   .L0,   .KMOVW,            {.K,         .K_M16,     .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x91, 0xFF, .W1,   .L0,   .KMOVQ,            {.M64,       .K,         .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x91, 0xFF, .W0,   .L0,   .KMOVW,            {.M16,       .K,         .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x92, 0xFF, .W0,   .L0,   .KMOVW,            {.K,         .R32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x93, 0xFF, .W0,   .L0,   .KMOVW,            {.R32,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x98, 0xFF, .W0,   .L0,   .KORTESTW,         {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x98, 0xFF, .W1,   .L0,   .KORTESTQ,         {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x99, 0xFF, .W1,   .L0,   .KTESTQ,           {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0x99, 0xFF, .W0,   .L0,   .KTESTW,           {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   0, 0xC2, 0xFF, .WIG,  .L0,   .VCMPPS,           {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F,   0, 0xC2, 0xFF, .WIG,  .L1,   .VCMPPS,           {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F,   0, 0xC6, 0xFF, .WIG,  .L1,   .VSHUFPS,          {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F,   0, 0xC6, 0xFF, .WIG,  .L0,   .VSHUFPS,          {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F,   1, 0x10, 0xFF, .WIG,  .L0,   .VMOVUPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x10, 0xFF, .WIG,  .L1,   .VMOVUPD,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x11, 0xFF, .WIG,  .L1,   .VMOVUPD,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x11, 0xFF, .WIG,  .L0,   .VMOVUPD,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x12, 0xFF, .WIG,  .L0,   .VMOVLPD,          {.XMM,       .XMM,       .M64,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x13, 0xFF, .WIG,  .L0,   .VMOVLPD,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x14, 0xFF, .WIG,  .L0,   .VUNPCKLPD,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x14, 0xFF, .WIG,  .L1,   .VUNPCKLPD,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x15, 0xFF, .WIG,  .L1,   .VUNPCKHPD,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x15, 0xFF, .WIG,  .L0,   .VUNPCKHPD,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x16, 0xFF, .WIG,  .L0,   .VMOVHPD,          {.XMM,       .XMM,       .M64,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x17, 0xFF, .WIG,  .L0,   .VMOVHPD,          {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x28, 0xFF, .WIG,  .L0,   .VMOVAPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x28, 0xFF, .WIG,  .L1,   .VMOVAPD,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x29, 0xFF, .WIG,  .L1,   .VMOVAPD,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x29, 0xFF, .WIG,  .L0,   .VMOVAPD,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x2B, 0xFF, .WIG,  .L0,   .VMOVNTPD,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x2B, 0xFF, .WIG,  .L1,   .VMOVNTPD,         {.M256,      .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x2E, 0xFF, .WIG,  .LIG,  .VUCOMISD,         {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x2F, 0xFF, .WIG,  .LIG,  .VCOMISD,          {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x41, 0xFF, .W1,   .L1,   .KANDD,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x41, 0xFF, .W0,   .L1,   .KANDB,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x42, 0xFF, .W0,   .L1,   .KANDNB,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x42, 0xFF, .W1,   .L1,   .KANDND,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x44, 0xFF, .W1,   .L0,   .KNOTD,            {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x44, 0xFF, .W0,   .L0,   .KNOTB,            {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x45, 0xFF, .W0,   .L1,   .KORB,             {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x45, 0xFF, .W1,   .L1,   .KORD,             {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x46, 0xFF, .W1,   .L1,   .KXNORD,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x46, 0xFF, .W0,   .L1,   .KXNORB,           {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x47, 0xFF, .W1,   .L1,   .KXORD,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x47, 0xFF, .W0,   .L1,   .KXORB,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x4A, 0xFF, .W0,   .L1,   .KADDB,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x4A, 0xFF, .W1,   .L1,   .KADDD,            {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x4B, 0xFF, .W0,   .L1,   .KUNPCKBW,         {.K,         .K,         .K,         .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x50, 0xFF, .WIG,  .L0,   .VMOVMSKPD,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x50, 0xFF, .WIG,  .L1,   .VMOVMSKPD,        {.R32,       .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x51, 0xFF, .WIG,  .L1,   .VSQRTPD,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x51, 0xFF, .WIG,  .L0,   .VSQRTPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x54, 0xFF, .WIG,  .L1,   .VANDPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x54, 0xFF, .WIG,  .L0,   .VANDPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x55, 0xFF, .WIG,  .L0,   .VANDNPD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x55, 0xFF, .WIG,  .L1,   .VANDNPD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x56, 0xFF, .WIG,  .L1,   .VORPD,            {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x56, 0xFF, .WIG,  .L0,   .VORPD,            {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x57, 0xFF, .WIG,  .L0,   .VXORPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x57, 0xFF, .WIG,  .L1,   .VXORPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x58, 0xFF, .WIG,  .L0,   .VADDPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x58, 0xFF, .WIG,  .L1,   .VADDPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x59, 0xFF, .WIG,  .L1,   .VMULPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x59, 0xFF, .WIG,  .L0,   .VMULPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x5A, 0xFF, .WIG,  .L0,   .VCVTPD2PS,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x5A, 0xFF, .WIG,  .L1,   .VCVTPD2PS,        {.XMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x5B, 0xFF, .WIG,  .L0,   .VCVTPS2DQ,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x5B, 0xFF, .WIG,  .L1,   .VCVTPS2DQ,        {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x5C, 0xFF, .WIG,  .L1,   .VSUBPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x5C, 0xFF, .WIG,  .L0,   .VSUBPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x5D, 0xFF, .WIG,  .L0,   .VMINPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x5D, 0xFF, .WIG,  .L1,   .VMINPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x5E, 0xFF, .WIG,  .L1,   .VDIVPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x5E, 0xFF, .WIG,  .L0,   .VDIVPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x5F, 0xFF, .WIG,  .L0,   .VMAXPD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x5F, 0xFF, .WIG,  .L1,   .VMAXPD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x60, 0xFF, .WIG,  .L1,   .VPUNPCKLBW,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x60, 0xFF, .WIG,  .L0,   .VPUNPCKLBW,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x61, 0xFF, .WIG,  .L0,   .VPUNPCKLWD,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x61, 0xFF, .WIG,  .L1,   .VPUNPCKLWD,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x62, 0xFF, .WIG,  .L1,   .VPUNPCKLDQ,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x62, 0xFF, .WIG,  .L0,   .VPUNPCKLDQ,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x63, 0xFF, .WIG,  .L0,   .VPACKSSWB,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x63, 0xFF, .WIG,  .L1,   .VPACKSSWB,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x64, 0xFF, .WIG,  .L1,   .VPCMPGTB,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x64, 0xFF, .WIG,  .L0,   .VPCMPGTB,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x65, 0xFF, .WIG,  .L1,   .VPCMPGTW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x65, 0xFF, .WIG,  .L0,   .VPCMPGTW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x66, 0xFF, .WIG,  .L1,   .VPCMPGTD,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x66, 0xFF, .WIG,  .L0,   .VPCMPGTD,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x67, 0xFF, .WIG,  .L0,   .VPACKUSWB,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x67, 0xFF, .WIG,  .L1,   .VPACKUSWB,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x68, 0xFF, .WIG,  .L1,   .VPUNPCKHBW,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x68, 0xFF, .WIG,  .L0,   .VPUNPCKHBW,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x69, 0xFF, .WIG,  .L1,   .VPUNPCKHWD,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x69, 0xFF, .WIG,  .L0,   .VPUNPCKHWD,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x6A, 0xFF, .WIG,  .L0,   .VPUNPCKHDQ,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x6A, 0xFF, .WIG,  .L1,   .VPUNPCKHDQ,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x6B, 0xFF, .WIG,  .L0,   .VPACKSSDW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x6B, 0xFF, .WIG,  .L1,   .VPACKSSDW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x6C, 0xFF, .WIG,  .L0,   .VPUNPCKLQDQ,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x6C, 0xFF, .WIG,  .L1,   .VPUNPCKLQDQ,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x6D, 0xFF, .WIG,  .L0,   .VPUNPCKHQDQ,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x6D, 0xFF, .WIG,  .L1,   .VPUNPCKHQDQ,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x6E, 0xFF, .WIG,  .L0,   .VMOVD,            {.XMM,       .RM32,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6E, 0xFF, .W1,   .L0,   .VMOVQ,            {.XMM,       .R64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6F, 0xFF, .WIG,  .L1,   .VMOVDQA,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6F, 0xFF, .WIG,  .L0,   .VMOVDQA,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x70, 0xFF, .WIG,  .L0,   .VPSHUFD,          {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x70, 0xFF, .WIG,  .L1,   .VPSHUFD,          {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x71, 0x02, .WIG,  .L1,   .VPSRLW,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x71, 0x02, .WIG,  .L0,   .VPSRLW,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x71, 0x04, .WIG,  .L1,   .VPSRAW,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x71, 0x04, .WIG,  .L0,   .VPSRAW,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x71, 0x06, .WIG,  .L1,   .VPSLLW,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x71, 0x06, .WIG,  .L0,   .VPSLLW,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x02, .WIG,  .L0,   .VPSRLD,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x02, .WIG,  .L1,   .VPSRLD,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x04, .WIG,  .L0,   .VPSRAD,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x04, .WIG,  .L1,   .VPSRAD,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x06, .WIG,  .L1,   .VPSLLD,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x06, .WIG,  .L0,   .VPSLLD,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x73, 0x02, .WIG,  .L0,   .VPSRLQ,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x73, 0x02, .WIG,  .L1,   .VPSRLQ,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x73, 0x06, .WIG,  .L1,   .VPSLLQ,           {.YMM,       .YMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x73, 0x06, .WIG,  .L0,   .VPSLLQ,           {.XMM,       .XMM,       .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x74, 0xFF, .WIG,  .L0,   .VPCMPEQB,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x74, 0xFF, .WIG,  .L1,   .VPCMPEQB,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x75, 0xFF, .WIG,  .L0,   .VPCMPEQW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x75, 0xFF, .WIG,  .L1,   .VPCMPEQW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x76, 0xFF, .WIG,  .L0,   .VPCMPEQD,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x76, 0xFF, .WIG,  .L1,   .VPCMPEQD,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x7E, 0xFF, .WIG,  .L0,   .VMOVD,            {.RM32,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7E, 0xFF, .W1,   .L0,   .VMOVQ,            {.R64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7F, 0xFF, .WIG,  .L1,   .VMOVDQA,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7F, 0xFF, .WIG,  .L0,   .VMOVDQA,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x90, 0xFF, .W1,   .L0,   .KMOVD,            {.K,         .K_M32,     .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x90, 0xFF, .W0,   .L0,   .KMOVB,            {.K,         .K_M8,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x91, 0xFF, .W0,   .L0,   .KMOVB,            {.M8,        .K,         .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x91, 0xFF, .W1,   .L0,   .KMOVD,            {.M32,       .K,         .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x92, 0xFF, .W0,   .L0,   .KMOVB,            {.K,         .R32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x93, 0xFF, .W0,   .L0,   .KMOVB,            {.R32,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x98, 0xFF, .W0,   .L0,   .KORTESTB,         {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x98, 0xFF, .W1,   .L0,   .KORTESTD,         {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x99, 0xFF, .W1,   .L0,   .KTESTD,           {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x99, 0xFF, .W0,   .L0,   .KTESTB,           {.K,         .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xC2, 0xFF, .WIG,  .L1,   .VCMPPD,           {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F,   1, 0xC2, 0xFF, .WIG,  .L0,   .VCMPPD,           {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F,   1, 0xC4, 0xFF, .WIG,  .L0,   .VPINSRW,          {.XMM,       .XMM,       .RM16,      .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F,   1, 0xC5, 0xFF, .WIG,  .L0,   .VPEXTRW,          {.R32,       .XMM,       .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xC6, 0xFF, .WIG,  .L0,   .VSHUFPD,          {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F,   1, 0xC6, 0xFF, .WIG,  .L1,   .VSHUFPD,          {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F,   1, 0xD1, 0xFF, .WIG,  .L1,   .VPSRLW,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xD1, 0xFF, .WIG,  .L0,   .VPSRLW,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xD2, 0xFF, .WIG,  .L0,   .VPSRLD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xD2, 0xFF, .WIG,  .L1,   .VPSRLD,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xD3, 0xFF, .WIG,  .L1,   .VPSRLQ,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xD3, 0xFF, .WIG,  .L0,   .VPSRLQ,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xD4, 0xFF, .WIG,  .L0,   .VPADDQ,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xD4, 0xFF, .WIG,  .L1,   .VPADDQ,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xD5, 0xFF, .WIG,  .L0,   .VPMULLW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xD5, 0xFF, .WIG,  .L1,   .VPMULLW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xD6, 0xFF, .WIG,  .L0,   .VMOVQ,            {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD7, 0xFF, .WIG,  .L0,   .VPMOVMSKB,        {.R32,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xD7, 0xFF, .WIG,  .L1,   .VPMOVMSKB,        {.R32,       .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xDB, 0xFF, .WIG,  .L1,   .VPAND,            {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xDB, 0xFF, .WIG,  .L0,   .VPAND,            {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xDF, 0xFF, .WIG,  .L1,   .VPANDN,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xDF, 0xFF, .WIG,  .L0,   .VPANDN,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xE1, 0xFF, .WIG,  .L1,   .VPSRAW,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xE1, 0xFF, .WIG,  .L0,   .VPSRAW,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xE2, 0xFF, .WIG,  .L1,   .VPSRAD,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xE2, 0xFF, .WIG,  .L0,   .VPSRAD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xE4, 0xFF, .WIG,  .L0,   .VPMULHUW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xE4, 0xFF, .WIG,  .L1,   .VPMULHUW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xE5, 0xFF, .WIG,  .L1,   .VPMULHW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xE5, 0xFF, .WIG,  .L0,   .VPMULHW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xE6, 0xFF, .WIG,  .L1,   .VCVTTPD2DQ,       {.XMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE6, 0xFF, .WIG,  .L0,   .VCVTTPD2DQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE7, 0xFF, .WIG,  .L1,   .VMOVNTDQ,         {.M256,      .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xE7, 0xFF, .WIG,  .L0,   .VMOVNTDQ,         {.M128,      .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xEB, 0xFF, .WIG,  .L1,   .VPOR,             {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xEB, 0xFF, .WIG,  .L0,   .VPOR,             {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xEF, 0xFF, .WIG,  .L0,   .VPXOR,            {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xEF, 0xFF, .WIG,  .L1,   .VPXOR,            {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF1, 0xFF, .WIG,  .L0,   .VPSLLW,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF1, 0xFF, .WIG,  .L1,   .VPSLLW,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF2, 0xFF, .WIG,  .L0,   .VPSLLD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF2, 0xFF, .WIG,  .L1,   .VPSLLD,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF3, 0xFF, .WIG,  .L1,   .VPSLLQ,           {.YMM,       .YMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF3, 0xFF, .WIG,  .L0,   .VPSLLQ,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.VVVV, .REG,  .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF4, 0xFF, .WIG,  .L0,   .VPMULUDQ,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF4, 0xFF, .WIG,  .L1,   .VPMULUDQ,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF5, 0xFF, .WIG,  .L1,   .VPMADDWD,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF5, 0xFF, .WIG,  .L0,   .VPMADDWD,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF7, 0xFF, .WIG,  .L0,   .VMASKMOVDQU,      {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0xF8, 0xFF, .WIG,  .L1,   .VPSUBB,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF8, 0xFF, .WIG,  .L0,   .VPSUBB,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF9, 0xFF, .WIG,  .L1,   .VPSUBW,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xF9, 0xFF, .WIG,  .L0,   .VPSUBW,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xFA, 0xFF, .WIG,  .L0,   .VPSUBD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xFA, 0xFF, .WIG,  .L1,   .VPSUBD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xFB, 0xFF, .WIG,  .L1,   .VPSUBQ,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xFB, 0xFF, .WIG,  .L0,   .VPSUBQ,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xFC, 0xFF, .WIG,  .L0,   .VPADDB,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xFC, 0xFF, .WIG,  .L1,   .VPADDB,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xFD, 0xFF, .WIG,  .L0,   .VPADDW,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xFD, 0xFF, .WIG,  .L1,   .VPADDW,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xFE, 0xFF, .WIG,  .L0,   .VPADDD,           {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0xFE, 0xFF, .WIG,  .L1,   .VPADDD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x10, 0xFF, .WIG,  .LIG,  .VMOVSS,           {.XMM,       .M32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x10, 0xFF, .WIG,  .LIG,  .VMOVSS,           {.XMM,       .XMM,       .XMM,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x11, 0xFF, .WIG,  .LIG,  .VMOVSS,           {.M32,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x2A, 0xFF, .W1,   .LIG,  .VCVTSI2SS,        {.XMM,       .XMM,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x2A, 0xFF, .WIG,  .LIG,  .VCVTSI2SS,        {.XMM,       .XMM,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x2C, 0xFF, .WIG,  .LIG,  .VCVTTSS2SI,       {.R32,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x2C, 0xFF, .W1,   .LIG,  .VCVTTSS2SI,       {.R64,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x2D, 0xFF, .WIG,  .LIG,  .VCVTSS2SI,        {.R32,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x2D, 0xFF, .W1,   .LIG,  .VCVTSS2SI,        {.R64,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x51, 0xFF, .WIG,  .LIG,  .VSQRTSS,          {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x52, 0xFF, .WIG,  .LIG,  .VRSQRTSS,         {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x53, 0xFF, .WIG,  .LIG,  .VRCPSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x58, 0xFF, .WIG,  .LIG,  .VADDSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x59, 0xFF, .WIG,  .LIG,  .VMULSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x5A, 0xFF, .WIG,  .LIG,  .VCVTSS2SD,        {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x5B, 0xFF, .WIG,  .L1,   .VCVTTPS2DQ,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x5B, 0xFF, .WIG,  .L0,   .VCVTTPS2DQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x5C, 0xFF, .WIG,  .LIG,  .VSUBSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x5D, 0xFF, .WIG,  .LIG,  .VMINSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x5E, 0xFF, .WIG,  .LIG,  .VDIVSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x5F, 0xFF, .WIG,  .LIG,  .VMAXSS,           {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x6F, 0xFF, .WIG,  .L1,   .VMOVDQU,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x6F, 0xFF, .WIG,  .L0,   .VMOVDQU,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x70, 0xFF, .WIG,  .L1,   .VPSHUFHW,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x70, 0xFF, .WIG,  .L0,   .VPSHUFHW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   2, 0x7E, 0xFF, .WIG,  .L0,   .VMOVQ,            {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x7F, 0xFF, .WIG,  .L1,   .VMOVDQU,          {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x7F, 0xFF, .WIG,  .L0,   .VMOVDQU,          {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xC2, 0xFF, .WIG,  .LIG,  .VCMPSS,           {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=4, needs_modrm=true}},
+	{._0F,   2, 0xE6, 0xFF, .WIG,  .L1,   .VCVTDQ2PD,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0xE6, 0xFF, .WIG,  .L0,   .VCVTDQ2PD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x10, 0xFF, .WIG,  .LIG,  .VMOVSD,           {.XMM,       .XMM,       .XMM,       .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x10, 0xFF, .WIG,  .LIG,  .VMOVSD,           {.XMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x11, 0xFF, .WIG,  .LIG,  .VMOVSD,           {.M64,       .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x2A, 0xFF, .WIG,  .LIG,  .VCVTSI2SD,        {.XMM,       .XMM,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x2A, 0xFF, .W1,   .LIG,  .VCVTSI2SD,        {.XMM,       .XMM,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x2C, 0xFF, .W1,   .LIG,  .VCVTTSD2SI,       {.R64,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x2C, 0xFF, .WIG,  .LIG,  .VCVTTSD2SI,       {.R32,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x2D, 0xFF, .WIG,  .LIG,  .VCVTSD2SI,        {.R32,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x2D, 0xFF, .W1,   .LIG,  .VCVTSD2SI,        {.R64,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x51, 0xFF, .WIG,  .LIG,  .VSQRTSD,          {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x58, 0xFF, .WIG,  .LIG,  .VADDSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x59, 0xFF, .WIG,  .LIG,  .VMULSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x5A, 0xFF, .WIG,  .LIG,  .VCVTSD2SS,        {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x5C, 0xFF, .WIG,  .LIG,  .VSUBSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x5D, 0xFF, .WIG,  .LIG,  .VMINSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x5E, 0xFF, .WIG,  .LIG,  .VDIVSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x5F, 0xFF, .WIG,  .LIG,  .VMAXSD,           {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x70, 0xFF, .WIG,  .L1,   .VPSHUFLW,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x70, 0xFF, .WIG,  .L0,   .VPSHUFLW,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   3, 0x92, 0xFF, .W1,   .L0,   .KMOVQ,            {.K,         .R64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x92, 0xFF, .W0,   .L0,   .KMOVD,            {.K,         .R32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x93, 0xFF, .W0,   .L0,   .KMOVD,            {.R32,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x93, 0xFF, .W1,   .L0,   .KMOVQ,            {.R64,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0xC2, 0xFF, .WIG,  .LIG,  .VCMPSD,           {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=4, needs_modrm=true}},
+	{._0F,   3, 0xE6, 0xFF, .WIG,  .L1,   .VCVTPD2DQ,        {.XMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0xE6, 0xFF, .WIG,  .L0,   .VCVTPD2DQ,        {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF2, 0xFF, .W1,   .L0,   .ANDN,             {.R64,       .R64,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 0, 0xF2, 0xFF, .W0,   .L0,   .ANDN,             {.R32,       .R32,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 0, 0xF3, 0x01, .W1,   .L0,   .BLSR,             {.R64,       .RM64,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF3, 0x01, .W0,   .L0,   .BLSR,             {.R32,       .RM32,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF3, 0x02, .W0,   .L0,   .BLSMSK,           {.R32,       .RM32,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF3, 0x02, .W1,   .L0,   .BLSMSK,           {.R64,       .RM64,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF3, 0x03, .W1,   .L0,   .BLSI,             {.R64,       .RM64,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF3, 0x03, .W0,   .L0,   .BLSI,             {.R32,       .RM32,      .NONE,      .NONE}, {.VVVV, .MR,   .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}},
+	{._0F38, 0, 0xF5, 0xFF, .W0,   .L0,   .BZHI,             {.R32,       .RM32,      .R32,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 0, 0xF5, 0xFF, .W1,   .L0,   .BZHI,             {.R64,       .RM64,      .R64,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 0, 0xF7, 0xFF, .W1,   .L0,   .BEXTR,            {.R64,       .RM64,      .R64,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 0, 0xF7, 0xFF, .W0,   .L0,   .BEXTR,            {.R32,       .RM32,      .R32,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x00, 0xFF, .WIG,  .L0,   .VPSHUFB,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x00, 0xFF, .WIG,  .L1,   .VPSHUFB,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x01, 0xFF, .WIG,  .L0,   .VPHADDW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x01, 0xFF, .WIG,  .L1,   .VPHADDW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x02, 0xFF, .WIG,  .L1,   .VPHADDD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x02, 0xFF, .WIG,  .L0,   .VPHADDD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x03, 0xFF, .WIG,  .L0,   .VPHADDSW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x03, 0xFF, .WIG,  .L1,   .VPHADDSW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x04, 0xFF, .WIG,  .L0,   .VPMADDUBSW,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x04, 0xFF, .WIG,  .L1,   .VPMADDUBSW,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x05, 0xFF, .WIG,  .L0,   .VPHSUBW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x05, 0xFF, .WIG,  .L1,   .VPHSUBW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x06, 0xFF, .WIG,  .L1,   .VPHSUBD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x06, 0xFF, .WIG,  .L0,   .VPHSUBD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x07, 0xFF, .WIG,  .L1,   .VPHSUBSW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x07, 0xFF, .WIG,  .L0,   .VPHSUBSW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x08, 0xFF, .WIG,  .L1,   .VPSIGNB,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x08, 0xFF, .WIG,  .L0,   .VPSIGNB,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x09, 0xFF, .WIG,  .L0,   .VPSIGNW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x09, 0xFF, .WIG,  .L1,   .VPSIGNW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x0A, 0xFF, .WIG,  .L0,   .VPSIGND,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x0A, 0xFF, .WIG,  .L1,   .VPSIGND,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x0B, 0xFF, .WIG,  .L1,   .VPMULHRSW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x0B, 0xFF, .WIG,  .L0,   .VPMULHRSW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x0E, 0xFF, .WIG,  .L1,   .VTESTPS,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x0E, 0xFF, .WIG,  .L0,   .VTESTPS,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x0F, 0xFF, .WIG,  .L0,   .VTESTPD,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x0F, 0xFF, .WIG,  .L1,   .VTESTPD,          {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x13, 0xFF, .WIG,  .L0,   .VCVTPH2PS,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x13, 0xFF, .WIG,  .L1,   .VCVTPH2PS,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x16, 0xFF, .W0,   .L1,   .VPERMPS,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x17, 0xFF, .WIG,  .L0,   .VPTEST,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x17, 0xFF, .WIG,  .L1,   .VPTEST,           {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x18, 0xFF, .WIG,  .L1,   .VBROADCASTSS,     {.YMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x18, 0xFF, .WIG,  .L0,   .VBROADCASTSS,     {.XMM,       .M32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x18, 0xFF, .WIG,  .L1,   .VBROADCASTSS,     {.YMM,       .M32,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x18, 0xFF, .WIG,  .L0,   .VBROADCASTSS,     {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x19, 0xFF, .WIG,  .L1,   .VBROADCASTSD,     {.YMM,       .M64,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x19, 0xFF, .WIG,  .L1,   .VBROADCASTSD,     {.YMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x1A, 0xFF, .WIG,  .L1,   .VBROADCASTF128,   {.YMM,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x1C, 0xFF, .WIG,  .L1,   .VPABSB,           {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x1C, 0xFF, .WIG,  .L0,   .VPABSB,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x1D, 0xFF, .WIG,  .L0,   .VPABSW,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x1D, 0xFF, .WIG,  .L1,   .VPABSW,           {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x1E, 0xFF, .WIG,  .L0,   .VPABSD,           {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x1E, 0xFF, .WIG,  .L1,   .VPABSD,           {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x20, 0xFF, .WIG,  .L1,   .VPMOVSXBW,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x20, 0xFF, .WIG,  .L0,   .VPMOVSXBW,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x21, 0xFF, .WIG,  .L0,   .VPMOVSXBD,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x21, 0xFF, .WIG,  .L1,   .VPMOVSXBD,        {.YMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x22, 0xFF, .WIG,  .L1,   .VPMOVSXBQ,        {.YMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x22, 0xFF, .WIG,  .L0,   .VPMOVSXBQ,        {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x23, 0xFF, .WIG,  .L0,   .VPMOVSXWD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x23, 0xFF, .WIG,  .L1,   .VPMOVSXWD,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x24, 0xFF, .WIG,  .L0,   .VPMOVSXWQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x24, 0xFF, .WIG,  .L1,   .VPMOVSXWQ,        {.YMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x25, 0xFF, .WIG,  .L1,   .VPMOVSXDQ,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x25, 0xFF, .WIG,  .L0,   .VPMOVSXDQ,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x28, 0xFF, .WIG,  .L1,   .VPMULDQ,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x28, 0xFF, .WIG,  .L0,   .VPMULDQ,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x29, 0xFF, .WIG,  .L1,   .VPCMPEQQ,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x29, 0xFF, .WIG,  .L0,   .VPCMPEQQ,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2A, 0xFF, .WIG,  .L0,   .VMOVNTDQA,        {.XMM,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x2A, 0xFF, .WIG,  .L1,   .VMOVNTDQA,        {.YMM,       .M256,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x2B, 0xFF, .WIG,  .L1,   .VPACKUSDW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2B, 0xFF, .WIG,  .L0,   .VPACKUSDW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2C, 0xFF, .WIG,  .L0,   .VMASKMOVPS,       {.XMM,       .XMM,       .M128,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2C, 0xFF, .WIG,  .L1,   .VMASKMOVPS,       {.YMM,       .YMM,       .M256,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2D, 0xFF, .WIG,  .L1,   .VMASKMOVPD,       {.YMM,       .YMM,       .M256,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2D, 0xFF, .WIG,  .L0,   .VMASKMOVPD,       {.XMM,       .XMM,       .M128,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2E, 0xFF, .WIG,  .L0,   .VMASKMOVPS,       {.M128,      .XMM,       .XMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2E, 0xFF, .WIG,  .L1,   .VMASKMOVPS,       {.M256,      .YMM,       .YMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2F, 0xFF, .WIG,  .L1,   .VMASKMOVPD,       {.M256,      .YMM,       .YMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2F, 0xFF, .WIG,  .L0,   .VMASKMOVPD,       {.M128,      .XMM,       .XMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x30, 0xFF, .WIG,  .L1,   .VPMOVZXBW,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x30, 0xFF, .WIG,  .L0,   .VPMOVZXBW,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x31, 0xFF, .WIG,  .L1,   .VPMOVZXBD,        {.YMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x31, 0xFF, .WIG,  .L0,   .VPMOVZXBD,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x32, 0xFF, .WIG,  .L1,   .VPMOVZXBQ,        {.YMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x32, 0xFF, .WIG,  .L0,   .VPMOVZXBQ,        {.XMM,       .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x33, 0xFF, .WIG,  .L0,   .VPMOVZXWD,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x33, 0xFF, .WIG,  .L1,   .VPMOVZXWD,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x34, 0xFF, .WIG,  .L0,   .VPMOVZXWQ,        {.XMM,       .XMM_M32,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x34, 0xFF, .WIG,  .L1,   .VPMOVZXWQ,        {.YMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x35, 0xFF, .WIG,  .L1,   .VPMOVZXDQ,        {.YMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x35, 0xFF, .WIG,  .L0,   .VPMOVZXDQ,        {.XMM,       .XMM_M64,   .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x36, 0xFF, .W0,   .L1,   .VPERMD,           {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x37, 0xFF, .WIG,  .L0,   .VPCMPGTQ,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x37, 0xFF, .WIG,  .L1,   .VPCMPGTQ,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x38, 0xFF, .WIG,  .L0,   .VPMINSB,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x38, 0xFF, .WIG,  .L1,   .VPMINSB,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x39, 0xFF, .WIG,  .L0,   .VPMINSD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x39, 0xFF, .WIG,  .L1,   .VPMINSD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3A, 0xFF, .WIG,  .L0,   .VPMINUW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3A, 0xFF, .WIG,  .L1,   .VPMINUW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3B, 0xFF, .WIG,  .L0,   .VPMINUD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3B, 0xFF, .WIG,  .L1,   .VPMINUD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3C, 0xFF, .WIG,  .L1,   .VPMAXSB,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3C, 0xFF, .WIG,  .L0,   .VPMAXSB,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3D, 0xFF, .WIG,  .L0,   .VPMAXSD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3D, 0xFF, .WIG,  .L1,   .VPMAXSD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3E, 0xFF, .WIG,  .L1,   .VPMAXUW,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3E, 0xFF, .WIG,  .L0,   .VPMAXUW,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3F, 0xFF, .WIG,  .L0,   .VPMAXUD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x3F, 0xFF, .WIG,  .L1,   .VPMAXUD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x40, 0xFF, .WIG,  .L1,   .VPMULLD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x40, 0xFF, .WIG,  .L0,   .VPMULLD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x41, 0xFF, .WIG,  .L0,   .VPHMINPOSUW,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x45, 0xFF, .W1,   .L0,   .VPSRLVQ,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x45, 0xFF, .W0,   .L1,   .VPSRLVD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x45, 0xFF, .W1,   .L1,   .VPSRLVQ,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x45, 0xFF, .W0,   .L0,   .VPSRLVD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x46, 0xFF, .W0,   .L0,   .VPSRAVD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x46, 0xFF, .W0,   .L1,   .VPSRAVD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x47, 0xFF, .W1,   .L1,   .VPSLLVQ,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x47, 0xFF, .W1,   .L0,   .VPSLLVQ,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x47, 0xFF, .W0,   .L0,   .VPSLLVD,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x47, 0xFF, .W0,   .L1,   .VPSLLVD,          {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x5A, 0xFF, .WIG,  .L1,   .VBROADCASTI128,   {.YMM,       .M128,      .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8C, 0xFF, .W1,   .L1,   .VPMASKMOVQ,       {.YMM,       .YMM,       .M256,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8C, 0xFF, .W0,   .L0,   .VPMASKMOVD,       {.XMM,       .XMM,       .M128,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8C, 0xFF, .W0,   .L1,   .VPMASKMOVD,       {.YMM,       .YMM,       .M256,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8C, 0xFF, .W1,   .L0,   .VPMASKMOVQ,       {.XMM,       .XMM,       .M128,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8E, 0xFF, .W0,   .L0,   .VPMASKMOVD,       {.M128,      .XMM,       .XMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8E, 0xFF, .W1,   .L1,   .VPMASKMOVQ,       {.M256,      .YMM,       .YMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8E, 0xFF, .W1,   .L0,   .VPMASKMOVQ,       {.M128,      .XMM,       .XMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8E, 0xFF, .W0,   .L1,   .VPMASKMOVD,       {.M256,      .YMM,       .YMM,       .NONE}, {.MR,   .VVVV, .REG,  .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x90, 0xFF, .W0,   .L1,   .VPGATHERDD,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x90, 0xFF, .W0,   .L0,   .VPGATHERDD,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x90, 0xFF, .W1,   .L1,   .VPGATHERDQ,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x90, 0xFF, .W1,   .L0,   .VPGATHERDQ,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x91, 0xFF, .W1,   .L1,   .VPGATHERQQ,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x91, 0xFF, .W0,   .L1,   .VPGATHERQD,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x91, 0xFF, .W1,   .L0,   .VPGATHERQQ,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x91, 0xFF, .W0,   .L0,   .VPGATHERQD,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x92, 0xFF, .W1,   .L0,   .VGATHERDPD,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x92, 0xFF, .W0,   .L0,   .VGATHERDPS,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x92, 0xFF, .W0,   .L1,   .VGATHERDPS,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x92, 0xFF, .W1,   .L1,   .VGATHERDPD,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x93, 0xFF, .W1,   .L0,   .VGATHERQPD,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x93, 0xFF, .W0,   .L0,   .VGATHERQPS,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x93, 0xFF, .W1,   .L1,   .VGATHERQPD,       {.YMM,       .M,         .YMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x93, 0xFF, .W0,   .L1,   .VGATHERQPS,       {.XMM,       .M,         .XMM,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x96, 0xFF, .W1,   .L0,   .VFMADDSUB132PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x96, 0xFF, .W0,   .L1,   .VFMADDSUB132PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x96, 0xFF, .W1,   .L1,   .VFMADDSUB132PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x96, 0xFF, .W0,   .L0,   .VFMADDSUB132PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x97, 0xFF, .W1,   .L0,   .VFMSUBADD132PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x97, 0xFF, .W1,   .L1,   .VFMSUBADD132PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x97, 0xFF, .W0,   .L1,   .VFMSUBADD132PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x97, 0xFF, .W0,   .L0,   .VFMSUBADD132PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x98, 0xFF, .W1,   .L0,   .VFMADD132PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x98, 0xFF, .W1,   .L1,   .VFMADD132PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x98, 0xFF, .W0,   .L0,   .VFMADD132PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x98, 0xFF, .W0,   .L1,   .VFMADD132PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x99, 0xFF, .W1,   .LIG,  .VFMADD132SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x99, 0xFF, .W0,   .LIG,  .VFMADD132SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9A, 0xFF, .W1,   .L0,   .VFMSUB132PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9A, 0xFF, .W0,   .L1,   .VFMSUB132PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9A, 0xFF, .W1,   .L1,   .VFMSUB132PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9A, 0xFF, .W0,   .L0,   .VFMSUB132PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9B, 0xFF, .W0,   .LIG,  .VFMSUB132SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9B, 0xFF, .W1,   .LIG,  .VFMSUB132SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9C, 0xFF, .W0,   .L0,   .VFNMADD132PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9C, 0xFF, .W1,   .L1,   .VFNMADD132PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9C, 0xFF, .W0,   .L1,   .VFNMADD132PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9C, 0xFF, .W1,   .L0,   .VFNMADD132PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9D, 0xFF, .W1,   .LIG,  .VFNMADD132SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9D, 0xFF, .W0,   .LIG,  .VFNMADD132SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9E, 0xFF, .W0,   .L1,   .VFNMSUB132PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9E, 0xFF, .W0,   .L0,   .VFNMSUB132PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9E, 0xFF, .W1,   .L0,   .VFNMSUB132PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9E, 0xFF, .W1,   .L1,   .VFNMSUB132PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9F, 0xFF, .W0,   .LIG,  .VFNMSUB132SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x9F, 0xFF, .W1,   .LIG,  .VFNMSUB132SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA6, 0xFF, .W1,   .L1,   .VFMADDSUB213PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA6, 0xFF, .W0,   .L0,   .VFMADDSUB213PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA6, 0xFF, .W1,   .L0,   .VFMADDSUB213PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA6, 0xFF, .W0,   .L1,   .VFMADDSUB213PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA7, 0xFF, .W1,   .L0,   .VFMSUBADD213PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA7, 0xFF, .W1,   .L1,   .VFMSUBADD213PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA7, 0xFF, .W0,   .L0,   .VFMSUBADD213PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA7, 0xFF, .W0,   .L1,   .VFMSUBADD213PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA8, 0xFF, .W1,   .L0,   .VFMADD213PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA8, 0xFF, .W1,   .L1,   .VFMADD213PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA8, 0xFF, .W0,   .L1,   .VFMADD213PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA8, 0xFF, .W0,   .L0,   .VFMADD213PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA9, 0xFF, .W0,   .LIG,  .VFMADD213SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA9, 0xFF, .W1,   .LIG,  .VFMADD213SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAA, 0xFF, .W1,   .L0,   .VFMSUB213PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAA, 0xFF, .W0,   .L0,   .VFMSUB213PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAA, 0xFF, .W0,   .L1,   .VFMSUB213PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAA, 0xFF, .W1,   .L1,   .VFMSUB213PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAB, 0xFF, .W1,   .LIG,  .VFMSUB213SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAB, 0xFF, .W0,   .LIG,  .VFMSUB213SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAC, 0xFF, .W0,   .L1,   .VFNMADD213PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAC, 0xFF, .W1,   .L1,   .VFNMADD213PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAC, 0xFF, .W0,   .L0,   .VFNMADD213PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAC, 0xFF, .W1,   .L0,   .VFNMADD213PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAD, 0xFF, .W1,   .LIG,  .VFNMADD213SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAD, 0xFF, .W0,   .LIG,  .VFNMADD213SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAE, 0xFF, .W0,   .L1,   .VFNMSUB213PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAE, 0xFF, .W1,   .L0,   .VFNMSUB213PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAE, 0xFF, .W1,   .L1,   .VFNMSUB213PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAE, 0xFF, .W0,   .L0,   .VFNMSUB213PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAF, 0xFF, .W0,   .LIG,  .VFNMSUB213SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xAF, 0xFF, .W1,   .LIG,  .VFNMSUB213SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB6, 0xFF, .W0,   .L1,   .VFMADDSUB231PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB6, 0xFF, .W0,   .L0,   .VFMADDSUB231PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB6, 0xFF, .W1,   .L0,   .VFMADDSUB231PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB6, 0xFF, .W1,   .L1,   .VFMADDSUB231PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB7, 0xFF, .W1,   .L0,   .VFMSUBADD231PD,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB7, 0xFF, .W0,   .L1,   .VFMSUBADD231PS,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB7, 0xFF, .W0,   .L0,   .VFMSUBADD231PS,   {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB7, 0xFF, .W1,   .L1,   .VFMSUBADD231PD,   {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB8, 0xFF, .W1,   .L1,   .VFMADD231PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB8, 0xFF, .W0,   .L1,   .VFMADD231PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB8, 0xFF, .W0,   .L0,   .VFMADD231PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB8, 0xFF, .W1,   .L0,   .VFMADD231PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB9, 0xFF, .W1,   .LIG,  .VFMADD231SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xB9, 0xFF, .W0,   .LIG,  .VFMADD231SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBA, 0xFF, .W1,   .L1,   .VFMSUB231PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBA, 0xFF, .W1,   .L0,   .VFMSUB231PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBA, 0xFF, .W0,   .L1,   .VFMSUB231PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBA, 0xFF, .W0,   .L0,   .VFMSUB231PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBB, 0xFF, .W1,   .LIG,  .VFMSUB231SD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBB, 0xFF, .W0,   .LIG,  .VFMSUB231SS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBC, 0xFF, .W1,   .L0,   .VFNMADD231PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBC, 0xFF, .W1,   .L1,   .VFNMADD231PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBC, 0xFF, .W0,   .L0,   .VFNMADD231PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBC, 0xFF, .W0,   .L1,   .VFNMADD231PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBD, 0xFF, .W1,   .LIG,  .VFNMADD231SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBD, 0xFF, .W0,   .LIG,  .VFNMADD231SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBE, 0xFF, .W1,   .L1,   .VFNMSUB231PD,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBE, 0xFF, .W1,   .L0,   .VFNMSUB231PD,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBE, 0xFF, .W0,   .L1,   .VFNMSUB231PS,     {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBE, 0xFF, .W0,   .L0,   .VFNMSUB231PS,     {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBF, 0xFF, .W1,   .LIG,  .VFNMSUB231SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xBF, 0xFF, .W0,   .LIG,  .VFNMSUB231SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xDB, 0xFF, .WIG,  .L0,   .VAESIMC,          {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xDC, 0xFF, .WIG,  .L0,   .VAESENC,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xDD, 0xFF, .WIG,  .L0,   .VAESENCLAST,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xDE, 0xFF, .WIG,  .L0,   .VAESDEC,          {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xDF, 0xFF, .WIG,  .L0,   .VAESDECLAST,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xF7, 0xFF, .W1,   .L0,   .SHLX,             {.R64,       .RM64,      .R64,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xF7, 0xFF, .W0,   .L0,   .SHLX,             {.R32,       .RM32,      .R32,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0xF5, 0xFF, .W1,   .L0,   .PEXT,             {.R64,       .R64,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0xF5, 0xFF, .W0,   .L0,   .PEXT,             {.R32,       .R32,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0xF7, 0xFF, .W0,   .L0,   .SARX,             {.R32,       .RM32,      .R32,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0xF7, 0xFF, .W1,   .L0,   .SARX,             {.R64,       .RM64,      .R64,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 3, 0xF5, 0xFF, .W0,   .L0,   .PDEP,             {.R32,       .R32,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 3, 0xF5, 0xFF, .W1,   .L0,   .PDEP,             {.R64,       .R64,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 3, 0xF6, 0xFF, .W1,   .L0,   .MULX,             {.R64,       .R64,       .RM64,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 3, 0xF6, 0xFF, .W0,   .L0,   .MULX,             {.R32,       .R32,       .RM32,      .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 3, 0xF7, 0xFF, .W0,   .L0,   .SHRX,             {.R32,       .RM32,      .R32,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 3, 0xF7, 0xFF, .W1,   .L0,   .SHRX,             {.R64,       .RM64,      .R64,       .NONE}, {.REG,  .MR,   .VVVV, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x00, 0xFF, .W1,   .L1,   .VPERMQ,           {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x01, 0xFF, .W1,   .L1,   .VPERMPD,          {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x02, 0xFF, .W0,   .L1,   .VPBLENDD,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x02, 0xFF, .W0,   .L0,   .VPBLENDD,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x06, 0xFF, .WIG,  .L1,   .VPERM2F128,       {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x08, 0xFF, .WIG,  .L1,   .VROUNDPS,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x08, 0xFF, .WIG,  .L0,   .VROUNDPS,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x09, 0xFF, .WIG,  .L0,   .VROUNDPD,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x09, 0xFF, .WIG,  .L1,   .VROUNDPD,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x0A, 0xFF, .WIG,  .LIG,  .VROUNDSS,         {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x0B, 0xFF, .WIG,  .LIG,  .VROUNDSD,         {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x0C, 0xFF, .WIG,  .L0,   .VBLENDPS,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x0C, 0xFF, .WIG,  .L1,   .VBLENDPS,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x0D, 0xFF, .WIG,  .L1,   .VBLENDPD,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x0D, 0xFF, .WIG,  .L0,   .VBLENDPD,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x0E, 0xFF, .WIG,  .L1,   .VPBLENDW,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x0E, 0xFF, .WIG,  .L0,   .VPBLENDW,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x0F, 0xFF, .WIG,  .L1,   .VPALIGNR,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x0F, 0xFF, .WIG,  .L0,   .VPALIGNR,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x14, 0xFF, .WIG,  .L0,   .VPEXTRB,          {.RM8,       .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x15, 0xFF, .WIG,  .L0,   .VPEXTRW,          {.RM16,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x16, 0xFF, .WIG,  .L0,   .VPEXTRD,          {.RM32,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x16, 0xFF, .W1,   .L0,   .VPEXTRQ,          {.RM64,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x17, 0xFF, .WIG,  .L0,   .VEXTRACTPS,       {.RM32,      .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x18, 0xFF, .WIG,  .L1,   .VINSERTF128,      {.YMM,       .YMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x19, 0xFF, .WIG,  .L1,   .VEXTRACTF128,     {.XMM_M128,  .YMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x1D, 0xFF, .WIG,  .L1,   .VCVTPS2PH,        {.XMM_M128,  .YMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x1D, 0xFF, .WIG,  .L0,   .VCVTPS2PH,        {.XMM_M64,   .XMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x20, 0xFF, .WIG,  .L0,   .VPINSRB,          {.XMM,       .XMM,       .RM8,       .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x21, 0xFF, .WIG,  .L0,   .VINSERTPS,        {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x22, 0xFF, .WIG,  .L0,   .VPINSRD,          {.XMM,       .XMM,       .RM32,      .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x22, 0xFF, .W1,   .L0,   .VPINSRQ,          {.XMM,       .XMM,       .RM64,      .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x30, 0xFF, .W0,   .L0,   .KSHIFTRB,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x30, 0xFF, .W1,   .L0,   .KSHIFTRW,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x31, 0xFF, .W0,   .L0,   .KSHIFTRD,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x31, 0xFF, .W1,   .L0,   .KSHIFTRQ,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x32, 0xFF, .W1,   .L0,   .KSHIFTLW,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x32, 0xFF, .W0,   .L0,   .KSHIFTLB,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x33, 0xFF, .W0,   .L0,   .KSHIFTLD,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x33, 0xFF, .W1,   .L0,   .KSHIFTLQ,         {.K,         .K,         .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x38, 0xFF, .WIG,  .L1,   .VINSERTI128,      {.YMM,       .YMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x39, 0xFF, .WIG,  .L1,   .VEXTRACTI128,     {.XMM_M128,  .YMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x40, 0xFF, .WIG,  .L1,   .VDPPS,            {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x40, 0xFF, .WIG,  .L0,   .VDPPS,            {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x41, 0xFF, .WIG,  .L0,   .VDPPD,            {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x42, 0xFF, .WIG,  .L0,   .VMPSADBW,         {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x42, 0xFF, .WIG,  .L1,   .VMPSADBW,         {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x44, 0xFF, .WIG,  .L0,   .VPCLMULQDQ,       {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x44, 0xFF, .WIG,  .L1,   .VPCLMULQDQ,       {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x46, 0xFF, .WIG,  .L1,   .VPERM2I128,       {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x4A, 0xFF, .W0,   .L0,   .VBLENDVPS,        {.XMM,       .XMM,       .XMM_M128,  .XMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x4A, 0xFF, .W0,   .L1,   .VBLENDVPS,        {.YMM,       .YMM,       .YMM_M256,  .YMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x4B, 0xFF, .W0,   .L1,   .VBLENDVPD,        {.YMM,       .YMM,       .YMM_M256,  .YMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x4B, 0xFF, .W0,   .L0,   .VBLENDVPD,        {.XMM,       .XMM,       .XMM_M128,  .XMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x4C, 0xFF, .W0,   .L1,   .VPBLENDVB,        {.YMM,       .YMM,       .YMM_M256,  .YMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x4C, 0xFF, .W0,   .L0,   .VPBLENDVB,        {.XMM,       .XMM,       .XMM_M128,  .XMM}, {.REG,  .VVVV, .MR,   .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0xDF, 0xFF, .WIG,  .L0,   .VAESKEYGENASSIST, {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 3, 0xF0, 0xFF, .W0,   .L0,   .RORX,             {.R32,       .RM32,      .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 3, 0xF0, 0xFF, .W1,   .L0,   .RORX,             {.R64,       .RM64,      .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
 }
 
 @(rodata)
 EVEX_DECODE_ENTRIES := [418]lib.VEX_Decode_Entry{
-	{._0F,   1, 0x6F, 0xFF, .W0,   .L1,   .VMOVDQA32,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   1, 0x6F, 0xFF, .W0,   .L0,   .VMOVDQA32,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   1, 0x6F, 0xFF, .W1,   .L0,   .VMOVDQA64,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   1, 0x6F, 0xFF, .W1,   .L2,   .VMOVDQA64,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F,   1, 0x6F, 0xFF, .W1,   .L1,   .VMOVDQA64,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   1, 0x6F, 0xFF, .W0,   .L2,   .VMOVDQA32,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F,   1, 0x72, 0x01, .W0,   .L2,   .VPROLD,         {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x01, .W0,   .L0,   .VPROLD,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x01, .W0,   .L1,   .VPROLD,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x01, .W1,   .L2,   .VPROLQ,         {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x01, .W1,   .L0,   .VPROLQ,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0x01, .W1,   .L1,   .VPROLQ,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, modrm_reg_ext=true}},
-	{._0F,   1, 0x72, 0xFF, .W0,   .L2,   .VPRORD,         {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F,   1, 0x72, 0xFF, .W1,   .L0,   .VPRORQ,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   1, 0x72, 0xFF, .W1,   .L2,   .VPRORQ,         {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F,   1, 0x72, 0xFF, .W0,   .L0,   .VPRORD,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   1, 0x72, 0xFF, .W0,   .L1,   .VPRORD,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   1, 0x72, 0xFF, .W1,   .L1,   .VPRORQ,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   1, 0x7F, 0xFF, .W1,   .L0,   .VMOVDQA64,      {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   1, 0x7F, 0xFF, .W1,   .L1,   .VMOVDQA64,      {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   1, 0x7F, 0xFF, .W1,   .L2,   .VMOVDQA64,      {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F,   1, 0x7F, 0xFF, .W0,   .L1,   .VMOVDQA32,      {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   1, 0x7F, 0xFF, .W0,   .L2,   .VMOVDQA32,      {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F,   1, 0x7F, 0xFF, .W0,   .L0,   .VMOVDQA32,      {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   2, 0x6F, 0xFF, .W1,   .L1,   .VMOVDQU64,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   2, 0x6F, 0xFF, .W0,   .L0,   .VMOVDQU32,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   2, 0x6F, 0xFF, .W1,   .L2,   .VMOVDQU64,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F,   2, 0x6F, 0xFF, .W0,   .L2,   .VMOVDQU32,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F,   2, 0x6F, 0xFF, .W0,   .L1,   .VMOVDQU32,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   2, 0x6F, 0xFF, .W1,   .L0,   .VMOVDQU64,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   2, 0x7F, 0xFF, .W1,   .L0,   .VMOVDQU64,      {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   2, 0x7F, 0xFF, .W0,   .L1,   .VMOVDQU32,      {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   2, 0x7F, 0xFF, .W1,   .L1,   .VMOVDQU64,      {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   2, 0x7F, 0xFF, .W0,   .L2,   .VMOVDQU32,      {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F,   2, 0x7F, 0xFF, .W0,   .L0,   .VMOVDQU32,      {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   2, 0x7F, 0xFF, .W1,   .L2,   .VMOVDQU64,      {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F,   3, 0x6F, 0xFF, .W1,   .L1,   .VMOVDQU16,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F,   3, 0x6F, 0xFF, .W1,   .L0,   .VMOVDQU16,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   3, 0x6F, 0xFF, .W0,   .L2,   .VMOVDQU8,       {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F,   3, 0x6F, 0xFF, .W0,   .L1,   .VMOVDQU8,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   3, 0x6F, 0xFF, .W0,   .L0,   .VMOVDQU8,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   3, 0x6F, 0xFF, .W1,   .L2,   .VMOVDQU16,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F,   3, 0x7F, 0xFF, .W1,   .L2,   .VMOVDQU16,      {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F,   3, 0x7F, 0xFF, .W1,   .L0,   .VMOVDQU16,      {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F,   3, 0x7F, 0xFF, .W0,   .L0,   .VMOVDQU8,       {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F,   3, 0x7F, 0xFF, .W0,   .L1,   .VMOVDQU8,       {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F,   3, 0x7F, 0xFF, .W0,   .L2,   .VMOVDQU8,       {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F,   3, 0x7F, 0xFF, .W1,   .L1,   .VMOVDQU16,      {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x10, 0xFF, .W1,   .L2,   .VPSRLVW,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x10, 0xFF, .W1,   .L0,   .VPSRLVW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x10, 0xFF, .W1,   .L1,   .VPSRLVW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x11, 0xFF, .W1,   .L2,   .VPSRAVW,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x11, 0xFF, .W1,   .L0,   .VPSRAVW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x11, 0xFF, .W1,   .L1,   .VPSRAVW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x12, 0xFF, .W1,   .L1,   .VPSLLVW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x12, 0xFF, .W1,   .L2,   .VPSLLVW,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x12, 0xFF, .W1,   .L0,   .VPSLLVW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x13, 0xFF, .WIG,  .L2,   .VCVTPH2PS,      {.ZMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_l=.L2}},
-	{._0F38, 1, 0x14, 0xFF, .W0,   .L0,   .VPRORVD,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x14, 0xFF, .W1,   .L0,   .VPRORVQ,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x14, 0xFF, .W0,   .L2,   .VPRORVD,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x14, 0xFF, .W1,   .L2,   .VPRORVQ,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x14, 0xFF, .W0,   .L1,   .VPRORVD,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x14, 0xFF, .W1,   .L1,   .VPRORVQ,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x15, 0xFF, .W0,   .L1,   .VPROLVD,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x15, 0xFF, .W1,   .L1,   .VPROLVQ,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x15, 0xFF, .W1,   .L0,   .VPROLVQ,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x15, 0xFF, .W0,   .L0,   .VPROLVD,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x15, 0xFF, .W0,   .L2,   .VPROLVD,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x15, 0xFF, .W1,   .L2,   .VPROLVQ,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x26, 0xFF, .W1,   .L1,   .VPTESTMW,       {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x26, 0xFF, .W1,   .L2,   .VPTESTMW,       {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x26, 0xFF, .W0,   .L2,   .VPTESTMB,       {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x26, 0xFF, .W0,   .L1,   .VPTESTMB,       {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x26, 0xFF, .W1,   .L0,   .VPTESTMW,       {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x26, 0xFF, .W0,   .L0,   .VPTESTMB,       {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x27, 0xFF, .W0,   .L0,   .VPTESTMD,       {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x27, 0xFF, .W0,   .L2,   .VPTESTMD,       {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x27, 0xFF, .W1,   .L2,   .VPTESTMQ,       {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x27, 0xFF, .W1,   .L0,   .VPTESTMQ,       {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x27, 0xFF, .W1,   .L1,   .VPTESTMQ,       {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x27, 0xFF, .W0,   .L1,   .VPTESTMD,       {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x2C, 0xFF, .W0,   .L1,   .VSCALEFPS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x2C, 0xFF, .W1,   .L1,   .VSCALEFPD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x2C, 0xFF, .W0,   .L0,   .VSCALEFPS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x2C, 0xFF, .W1,   .L0,   .VSCALEFPD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x2C, 0xFF, .W1,   .L2,   .VSCALEFPD,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x2C, 0xFF, .W0,   .L2,   .VSCALEFPS,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x2D, 0xFF, .W1,   .LIG,  .VSCALEFSD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}},
-	{._0F38, 1, 0x2D, 0xFF, .W0,   .LIG,  .VSCALEFSS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}},
-	{._0F38, 1, 0x42, 0xFF, .W0,   .L2,   .VGETEXPPS,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x42, 0xFF, .W0,   .L0,   .VGETEXPPS,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x42, 0xFF, .W1,   .L1,   .VGETEXPPD,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x42, 0xFF, .W0,   .L1,   .VGETEXPPS,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x42, 0xFF, .W1,   .L0,   .VGETEXPPD,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x42, 0xFF, .W1,   .L2,   .VGETEXPPD,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x43, 0xFF, .W1,   .LIG,  .VGETEXPSD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}},
-	{._0F38, 1, 0x43, 0xFF, .W0,   .LIG,  .VGETEXPSS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}},
-	{._0F38, 1, 0x44, 0xFF, .W0,   .L0,   .VPLZCNTD,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x44, 0xFF, .W0,   .L2,   .VPLZCNTD,       {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x44, 0xFF, .W1,   .L0,   .VPLZCNTQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x44, 0xFF, .W0,   .L1,   .VPLZCNTD,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x44, 0xFF, .W1,   .L1,   .VPLZCNTQ,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x44, 0xFF, .W1,   .L2,   .VPLZCNTQ,       {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x46, 0xFF, .W1,   .L0,   .VPSRAVQ,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x46, 0xFF, .W1,   .L2,   .VPSRAVQ,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x46, 0xFF, .W1,   .L1,   .VPSRAVQ,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x4C, 0xFF, .W1,   .L0,   .VRCP14PD,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x4C, 0xFF, .W0,   .L2,   .VRCP14PS,       {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x4C, 0xFF, .W1,   .L2,   .VRCP14PD,       {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x4C, 0xFF, .W0,   .L1,   .VRCP14PS,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x4C, 0xFF, .W0,   .L0,   .VRCP14PS,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x4C, 0xFF, .W1,   .L1,   .VRCP14PD,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x4D, 0xFF, .W0,   .LIG,  .VRCP14SS,       {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}},
-	{._0F38, 1, 0x4D, 0xFF, .W1,   .LIG,  .VRCP14SD,       {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}},
-	{._0F38, 1, 0x4E, 0xFF, .W1,   .L0,   .VRSQRT14PD,     {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x4E, 0xFF, .W1,   .L2,   .VRSQRT14PD,     {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x4E, 0xFF, .W1,   .L1,   .VRSQRT14PD,     {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x4E, 0xFF, .W0,   .L1,   .VRSQRT14PS,     {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x4E, 0xFF, .W0,   .L2,   .VRSQRT14PS,     {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x4E, 0xFF, .W0,   .L0,   .VRSQRT14PS,     {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x4F, 0xFF, .W1,   .LIG,  .VRSQRT14SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}},
-	{._0F38, 1, 0x4F, 0xFF, .W0,   .LIG,  .VRSQRT14SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}},
-	{._0F38, 1, 0x64, 0xFF, .W1,   .L0,   .VPBLENDMQ,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x64, 0xFF, .W0,   .L2,   .VPBLENDMD,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x64, 0xFF, .W1,   .L1,   .VPBLENDMQ,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x64, 0xFF, .W0,   .L0,   .VPBLENDMD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x64, 0xFF, .W1,   .L2,   .VPBLENDMQ,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x64, 0xFF, .W0,   .L1,   .VPBLENDMD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x65, 0xFF, .W1,   .L0,   .VBLENDMPD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x65, 0xFF, .W0,   .L1,   .VBLENDMPS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x65, 0xFF, .W0,   .L0,   .VBLENDMPS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x65, 0xFF, .W0,   .L2,   .VBLENDMPS,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x65, 0xFF, .W1,   .L1,   .VBLENDMPD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x65, 0xFF, .W1,   .L2,   .VBLENDMPD,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x66, 0xFF, .W1,   .L1,   .VPBLENDMW,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x66, 0xFF, .W1,   .L0,   .VPBLENDMW,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x66, 0xFF, .W1,   .L2,   .VPBLENDMW,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x66, 0xFF, .W0,   .L0,   .VPBLENDMB,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x66, 0xFF, .W0,   .L1,   .VPBLENDMB,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x66, 0xFF, .W0,   .L2,   .VPBLENDMB,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x75, 0xFF, .W0,   .L0,   .VPERMI2B,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x75, 0xFF, .W0,   .L1,   .VPERMI2B,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x75, 0xFF, .W0,   .L2,   .VPERMI2B,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x75, 0xFF, .W1,   .L1,   .VPERMI2W,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x75, 0xFF, .W1,   .L0,   .VPERMI2W,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x75, 0xFF, .W1,   .L2,   .VPERMI2W,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x76, 0xFF, .W0,   .L0,   .VPERMI2D,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x76, 0xFF, .W0,   .L1,   .VPERMI2D,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x76, 0xFF, .W0,   .L2,   .VPERMI2D,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x76, 0xFF, .W1,   .L0,   .VPERMI2Q,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x76, 0xFF, .W1,   .L2,   .VPERMI2Q,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x76, 0xFF, .W1,   .L1,   .VPERMI2Q,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x77, 0xFF, .W0,   .L1,   .VPERMI2PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x77, 0xFF, .W0,   .L0,   .VPERMI2PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x77, 0xFF, .W1,   .L0,   .VPERMI2PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x77, 0xFF, .W1,   .L1,   .VPERMI2PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x77, 0xFF, .W1,   .L2,   .VPERMI2PD,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x77, 0xFF, .W0,   .L2,   .VPERMI2PS,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x7D, 0xFF, .W0,   .L1,   .VPERMT2B,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x7D, 0xFF, .W0,   .L2,   .VPERMT2B,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x7D, 0xFF, .W1,   .L0,   .VPERMT2W,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x7D, 0xFF, .W1,   .L1,   .VPERMT2W,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x7D, 0xFF, .W1,   .L2,   .VPERMT2W,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x7D, 0xFF, .W0,   .L0,   .VPERMT2B,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x7E, 0xFF, .W0,   .L0,   .VPERMT2D,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x7E, 0xFF, .W0,   .L2,   .VPERMT2D,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x7E, 0xFF, .W0,   .L1,   .VPERMT2D,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x7E, 0xFF, .W1,   .L1,   .VPERMT2Q,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x7E, 0xFF, .W1,   .L0,   .VPERMT2Q,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x7E, 0xFF, .W1,   .L2,   .VPERMT2Q,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x7F, 0xFF, .W0,   .L1,   .VPERMT2PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x7F, 0xFF, .W0,   .L0,   .VPERMT2PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x7F, 0xFF, .W0,   .L2,   .VPERMT2PS,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x7F, 0xFF, .W1,   .L0,   .VPERMT2PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x7F, 0xFF, .W1,   .L1,   .VPERMT2PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x7F, 0xFF, .W1,   .L2,   .VPERMT2PD,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x83, 0xFF, .W1,   .L1,   .VPMULTISHIFTQB, {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x83, 0xFF, .W1,   .L0,   .VPMULTISHIFTQB, {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x83, 0xFF, .W1,   .L2,   .VPMULTISHIFTQB, {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x88, 0xFF, .W1,   .L2,   .VEXPANDPD,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x88, 0xFF, .W1,   .L0,   .VEXPANDPD,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x88, 0xFF, .W0,   .L2,   .VEXPANDPS,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x88, 0xFF, .W1,   .L1,   .VEXPANDPD,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x88, 0xFF, .W0,   .L0,   .VEXPANDPS,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x88, 0xFF, .W0,   .L1,   .VEXPANDPS,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x89, 0xFF, .W1,   .L2,   .VPEXPANDQ,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x89, 0xFF, .W1,   .L0,   .VPEXPANDQ,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x89, 0xFF, .W0,   .L2,   .VPEXPANDD,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x89, 0xFF, .W1,   .L1,   .VPEXPANDQ,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x89, 0xFF, .W0,   .L0,   .VPEXPANDD,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x89, 0xFF, .W0,   .L1,   .VPEXPANDD,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x8A, 0xFF, .W1,   .L2,   .VCOMPRESSPD,    {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x8A, 0xFF, .W1,   .L1,   .VCOMPRESSPD,    {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x8A, 0xFF, .W0,   .L2,   .VCOMPRESSPS,    {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x8A, 0xFF, .W0,   .L0,   .VCOMPRESSPS,    {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x8A, 0xFF, .W0,   .L1,   .VCOMPRESSPS,    {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x8A, 0xFF, .W1,   .L0,   .VCOMPRESSPD,    {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x8B, 0xFF, .W1,   .L2,   .VPCOMPRESSQ,    {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0x8B, 0xFF, .W0,   .L0,   .VPCOMPRESSD,    {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x8B, 0xFF, .W0,   .L1,   .VPCOMPRESSD,    {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x8B, 0xFF, .W0,   .L2,   .VPCOMPRESSD,    {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x8B, 0xFF, .W1,   .L0,   .VPCOMPRESSQ,    {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x8B, 0xFF, .W1,   .L1,   .VPCOMPRESSQ,    {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x8D, 0xFF, .W0,   .L0,   .VPERMB,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0x8D, 0xFF, .W1,   .L1,   .VPERMW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0x8D, 0xFF, .W0,   .L2,   .VPERMB,         {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0x8D, 0xFF, .W0,   .L1,   .VPERMB,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0x8D, 0xFF, .W1,   .L0,   .VPERMW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0x8D, 0xFF, .W1,   .L2,   .VPERMW,         {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0xA0, 0xFF, .W1,   .L2,   .VPSCATTERDQ,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0xA0, 0xFF, .W1,   .L0,   .VPSCATTERDQ,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xA0, 0xFF, .W1,   .L1,   .VPSCATTERDQ,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xA0, 0xFF, .W0,   .L2,   .VPSCATTERDD,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0xA0, 0xFF, .W0,   .L1,   .VPSCATTERDD,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xA0, 0xFF, .W0,   .L0,   .VPSCATTERDD,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xA1, 0xFF, .W0,   .L0,   .VPSCATTERQD,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xA1, 0xFF, .W1,   .L0,   .VPSCATTERQQ,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xA1, 0xFF, .W0,   .L1,   .VPSCATTERQD,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xA1, 0xFF, .W1,   .L1,   .VPSCATTERQQ,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xA1, 0xFF, .W1,   .L2,   .VPSCATTERQQ,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0xA1, 0xFF, .W0,   .L2,   .VPSCATTERQD,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0xA2, 0xFF, .W1,   .L2,   .VSCATTERDPD,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0xA2, 0xFF, .W0,   .L1,   .VSCATTERDPS,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xA2, 0xFF, .W0,   .L0,   .VSCATTERDPS,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xA2, 0xFF, .W0,   .L2,   .VSCATTERDPS,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0xA2, 0xFF, .W1,   .L0,   .VSCATTERDPD,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xA2, 0xFF, .W1,   .L1,   .VSCATTERDPD,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xA3, 0xFF, .W0,   .L0,   .VSCATTERQPS,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xA3, 0xFF, .W1,   .L2,   .VSCATTERQPD,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 1, 0xA3, 0xFF, .W0,   .L1,   .VSCATTERQPS,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xA3, 0xFF, .W1,   .L0,   .VSCATTERQPD,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xA3, 0xFF, .W1,   .L1,   .VSCATTERQPD,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xA3, 0xFF, .W0,   .L2,   .VSCATTERQPS,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0xC4, 0xFF, .W0,   .L2,   .VPCONFLICTD,    {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 1, 0xC4, 0xFF, .W0,   .L1,   .VPCONFLICTD,    {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 1, 0xC4, 0xFF, .W1,   .L0,   .VPCONFLICTQ,    {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 1, 0xC4, 0xFF, .W0,   .L0,   .VPCONFLICTD,    {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 1, 0xC4, 0xFF, .W1,   .L1,   .VPCONFLICTQ,    {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 1, 0xC4, 0xFF, .W1,   .L2,   .VPCONFLICTQ,    {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 2, 0x10, 0xFF, .W0,   .L2,   .VPMOVUSWB,      {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x10, 0xFF, .W0,   .L1,   .VPMOVUSWB,      {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x10, 0xFF, .W0,   .L0,   .VPMOVUSWB,      {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x11, 0xFF, .W0,   .L0,   .VPMOVUSDB,      {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x11, 0xFF, .W0,   .L1,   .VPMOVUSDB,      {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x11, 0xFF, .W0,   .L2,   .VPMOVUSDB,      {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x12, 0xFF, .W0,   .L2,   .VPMOVUSQB,      {.XMM_M64,   .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x12, 0xFF, .W0,   .L0,   .VPMOVUSQB,      {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x12, 0xFF, .W0,   .L1,   .VPMOVUSQB,      {.XMM_M32,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x13, 0xFF, .W0,   .L0,   .VPMOVUSDW,      {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x13, 0xFF, .W0,   .L2,   .VPMOVUSDW,      {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x13, 0xFF, .W0,   .L1,   .VPMOVUSDW,      {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x14, 0xFF, .W0,   .L2,   .VPMOVUSQW,      {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x14, 0xFF, .W0,   .L0,   .VPMOVUSQW,      {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x14, 0xFF, .W0,   .L1,   .VPMOVUSQW,      {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x15, 0xFF, .W0,   .L0,   .VPMOVUSQD,      {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x15, 0xFF, .W0,   .L1,   .VPMOVUSQD,      {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x15, 0xFF, .W0,   .L2,   .VPMOVUSQD,      {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x20, 0xFF, .W0,   .L1,   .VPMOVSWB,       {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x20, 0xFF, .W0,   .L2,   .VPMOVSWB,       {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x20, 0xFF, .W0,   .L0,   .VPMOVSWB,       {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x21, 0xFF, .W0,   .L2,   .VPMOVSDB,       {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x21, 0xFF, .W0,   .L0,   .VPMOVSDB,       {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x21, 0xFF, .W0,   .L1,   .VPMOVSDB,       {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x22, 0xFF, .W0,   .L2,   .VPMOVSQB,       {.XMM_M64,   .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x22, 0xFF, .W0,   .L0,   .VPMOVSQB,       {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x22, 0xFF, .W0,   .L1,   .VPMOVSQB,       {.XMM_M32,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x23, 0xFF, .W0,   .L1,   .VPMOVSDW,       {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x23, 0xFF, .W0,   .L0,   .VPMOVSDW,       {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x23, 0xFF, .W0,   .L2,   .VPMOVSDW,       {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x24, 0xFF, .W0,   .L1,   .VPMOVSQW,       {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x24, 0xFF, .W0,   .L0,   .VPMOVSQW,       {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x24, 0xFF, .W0,   .L2,   .VPMOVSQW,       {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x25, 0xFF, .W0,   .L2,   .VPMOVSQD,       {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x25, 0xFF, .W0,   .L0,   .VPMOVSQD,       {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x25, 0xFF, .W0,   .L1,   .VPMOVSQD,       {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x26, 0xFF, .W1,   .L2,   .VPTESTNMW,      {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 2, 0x26, 0xFF, .W1,   .L0,   .VPTESTNMW,      {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 2, 0x26, 0xFF, .W0,   .L1,   .VPTESTNMB,      {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x26, 0xFF, .W0,   .L0,   .VPTESTNMB,      {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x26, 0xFF, .W0,   .L2,   .VPTESTNMB,      {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x26, 0xFF, .W1,   .L1,   .VPTESTNMW,      {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 2, 0x27, 0xFF, .W1,   .L1,   .VPTESTNMQ,      {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 2, 0x27, 0xFF, .W1,   .L0,   .VPTESTNMQ,      {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 2, 0x27, 0xFF, .W1,   .L2,   .VPTESTNMQ,      {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 2, 0x27, 0xFF, .W0,   .L0,   .VPTESTNMD,      {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x27, 0xFF, .W0,   .L1,   .VPTESTNMD,      {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x27, 0xFF, .W0,   .L2,   .VPTESTNMD,      {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x28, 0xFF, .W1,   .L1,   .VPMOVM2W,       {.YMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 2, 0x28, 0xFF, .W1,   .L0,   .VPMOVM2W,       {.XMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 2, 0x28, 0xFF, .W1,   .L2,   .VPMOVM2W,       {.ZMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 2, 0x28, 0xFF, .W0,   .L1,   .VPMOVM2B,       {.YMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x28, 0xFF, .W0,   .L2,   .VPMOVM2B,       {.ZMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x28, 0xFF, .W0,   .L0,   .VPMOVM2B,       {.XMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x29, 0xFF, .W1,   .L2,   .VPMOVW2M,       {.K,         .ZMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 2, 0x29, 0xFF, .W1,   .L1,   .VPMOVW2M,       {.K,         .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 2, 0x29, 0xFF, .W0,   .L1,   .VPMOVB2M,       {.K,         .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x29, 0xFF, .W0,   .L0,   .VPMOVB2M,       {.K,         .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x29, 0xFF, .W0,   .L2,   .VPMOVB2M,       {.K,         .ZMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x29, 0xFF, .W1,   .L0,   .VPMOVW2M,       {.K,         .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 2, 0x30, 0xFF, .W0,   .L2,   .VPMOVWB,        {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x30, 0xFF, .W0,   .L0,   .VPMOVWB,        {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x30, 0xFF, .W0,   .L1,   .VPMOVWB,        {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x31, 0xFF, .W0,   .L1,   .VPMOVDB,        {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x31, 0xFF, .W0,   .L0,   .VPMOVDB,        {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x31, 0xFF, .W0,   .L2,   .VPMOVDB,        {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x32, 0xFF, .W0,   .L2,   .VPMOVQB,        {.XMM_M64,   .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x32, 0xFF, .W0,   .L1,   .VPMOVQB,        {.XMM_M32,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x32, 0xFF, .W0,   .L0,   .VPMOVQB,        {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x33, 0xFF, .W0,   .L2,   .VPMOVDW,        {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x33, 0xFF, .W0,   .L0,   .VPMOVDW,        {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x33, 0xFF, .W0,   .L1,   .VPMOVDW,        {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x34, 0xFF, .W0,   .L0,   .VPMOVQW,        {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x34, 0xFF, .W0,   .L1,   .VPMOVQW,        {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x34, 0xFF, .W0,   .L2,   .VPMOVQW,        {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x35, 0xFF, .W0,   .L0,   .VPMOVQD,        {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x35, 0xFF, .W0,   .L1,   .VPMOVQD,        {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x35, 0xFF, .W0,   .L2,   .VPMOVQD,        {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x38, 0xFF, .W1,   .L2,   .VPMOVM2Q,       {.ZMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 2, 0x38, 0xFF, .W1,   .L0,   .VPMOVM2Q,       {.XMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F38, 2, 0x38, 0xFF, .W0,   .L2,   .VPMOVM2D,       {.ZMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x38, 0xFF, .W1,   .L1,   .VPMOVM2Q,       {.YMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 2, 0x38, 0xFF, .W0,   .L0,   .VPMOVM2D,       {.XMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x38, 0xFF, .W0,   .L1,   .VPMOVM2D,       {.YMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x39, 0xFF, .W1,   .L2,   .VPMOVQ2M,       {.K,         .ZMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F38, 2, 0x39, 0xFF, .W1,   .L1,   .VPMOVQ2M,       {.K,         .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F38, 2, 0x39, 0xFF, .W0,   .L1,   .VPMOVD2M,       {.K,         .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F38, 2, 0x39, 0xFF, .W0,   .L0,   .VPMOVD2M,       {.K,         .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F38, 2, 0x39, 0xFF, .W0,   .L2,   .VPMOVD2M,       {.K,         .ZMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F38, 2, 0x39, 0xFF, .W1,   .L0,   .VPMOVQ2M,       {.K,         .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x03, 0xFF, .W1,   .L0,   .VALIGNQ,        {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x03, 0xFF, .W0,   .L0,   .VALIGND,        {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x03, 0xFF, .W1,   .L1,   .VALIGNQ,        {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x03, 0xFF, .W0,   .L1,   .VALIGND,        {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x03, 0xFF, .W0,   .L2,   .VALIGND,        {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x03, 0xFF, .W1,   .L2,   .VALIGNQ,        {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x08, 0xFF, .W0,   .L0,   .VRNDSCALEPS,    {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x08, 0xFF, .W0,   .L1,   .VRNDSCALEPS,    {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x08, 0xFF, .W0,   .L2,   .VRNDSCALEPS,    {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x09, 0xFF, .W1,   .L0,   .VRNDSCALEPD,    {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x09, 0xFF, .W1,   .L1,   .VRNDSCALEPD,    {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x09, 0xFF, .W1,   .L2,   .VRNDSCALEPD,    {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x0A, 0xFF, .W0,   .LIG,  .VRNDSCALESS,    {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
-	{._0F3A, 1, 0x0B, 0xFF, .W1,   .LIG,  .VRNDSCALESD,    {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
-	{._0F3A, 1, 0x1D, 0xFF, .WIG,  .L2,   .VCVTPS2PH,      {.YMM_M256,  .ZMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_l=.L2}},
-	{._0F3A, 1, 0x1E, 0xFF, .W1,   .L2,   .VPCMPUQ,        {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x1E, 0xFF, .W1,   .L0,   .VPCMPUQ,        {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x1E, 0xFF, .W1,   .L1,   .VPCMPUQ,        {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x1E, 0xFF, .W0,   .L2,   .VPCMPUD,        {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x1E, 0xFF, .W0,   .L1,   .VPCMPUD,        {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x1E, 0xFF, .W0,   .L0,   .VPCMPUD,        {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x1F, 0xFF, .W1,   .L2,   .VPCMPQ,         {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x1F, 0xFF, .W1,   .L0,   .VPCMPQ,         {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x1F, 0xFF, .W0,   .L2,   .VPCMPD,         {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x1F, 0xFF, .W0,   .L0,   .VPCMPD,         {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x1F, 0xFF, .W0,   .L1,   .VPCMPD,         {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x1F, 0xFF, .W1,   .L1,   .VPCMPQ,         {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x25, 0xFF, .W0,   .L0,   .VPTERNLOGD,     {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x25, 0xFF, .W0,   .L1,   .VPTERNLOGD,     {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x25, 0xFF, .W1,   .L0,   .VPTERNLOGQ,     {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x25, 0xFF, .W1,   .L1,   .VPTERNLOGQ,     {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x25, 0xFF, .W0,   .L2,   .VPTERNLOGD,     {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x25, 0xFF, .W1,   .L2,   .VPTERNLOGQ,     {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x26, 0xFF, .W1,   .L0,   .VGETMANTPD,     {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x26, 0xFF, .W1,   .L1,   .VGETMANTPD,     {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x26, 0xFF, .W0,   .L1,   .VGETMANTPS,     {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x26, 0xFF, .W0,   .L0,   .VGETMANTPS,     {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x26, 0xFF, .W1,   .L2,   .VGETMANTPD,     {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x26, 0xFF, .W0,   .L2,   .VGETMANTPS,     {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x27, 0xFF, .W1,   .LIG,  .VGETMANTSD,     {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
-	{._0F3A, 1, 0x27, 0xFF, .W0,   .LIG,  .VGETMANTSS,     {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
-	{._0F3A, 1, 0x3E, 0xFF, .W1,   .L2,   .VPCMPUW,        {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x3E, 0xFF, .W0,   .L2,   .VPCMPUB,        {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x3E, 0xFF, .W0,   .L0,   .VPCMPUB,        {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x3E, 0xFF, .W1,   .L0,   .VPCMPUW,        {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x3E, 0xFF, .W0,   .L1,   .VPCMPUB,        {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x3E, 0xFF, .W1,   .L1,   .VPCMPUW,        {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x3F, 0xFF, .W1,   .L0,   .VPCMPW,         {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x3F, 0xFF, .W1,   .L1,   .VPCMPW,         {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x3F, 0xFF, .W0,   .L1,   .VPCMPB,         {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x3F, 0xFF, .W0,   .L0,   .VPCMPB,         {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x3F, 0xFF, .W0,   .L2,   .VPCMPB,         {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x3F, 0xFF, .W1,   .L2,   .VPCMPW,         {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x42, 0xFF, .W0,   .L0,   .VDBPSADBW,      {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x42, 0xFF, .W0,   .L1,   .VDBPSADBW,      {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x42, 0xFF, .W0,   .L2,   .VDBPSADBW,      {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x50, 0xFF, .W1,   .L1,   .VRANGEPD,       {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x50, 0xFF, .W0,   .L2,   .VRANGEPS,       {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x50, 0xFF, .W0,   .L1,   .VRANGEPS,       {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x50, 0xFF, .W1,   .L0,   .VRANGEPD,       {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x50, 0xFF, .W1,   .L2,   .VRANGEPD,       {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x50, 0xFF, .W0,   .L0,   .VRANGEPS,       {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x51, 0xFF, .W0,   .LIG,  .VRANGESS,       {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
-	{._0F3A, 1, 0x51, 0xFF, .W1,   .LIG,  .VRANGESD,       {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
-	{._0F3A, 1, 0x54, 0xFF, .W1,   .L2,   .VFIXUPIMMPD,    {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x54, 0xFF, .W1,   .L1,   .VFIXUPIMMPD,    {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x54, 0xFF, .W0,   .L1,   .VFIXUPIMMPS,    {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x54, 0xFF, .W0,   .L0,   .VFIXUPIMMPS,    {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x54, 0xFF, .W0,   .L2,   .VFIXUPIMMPS,    {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x54, 0xFF, .W1,   .L0,   .VFIXUPIMMPD,    {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x55, 0xFF, .W1,   .LIG,  .VFIXUPIMMSD,    {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
-	{._0F3A, 1, 0x55, 0xFF, .W0,   .LIG,  .VFIXUPIMMSS,    {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
-	{._0F3A, 1, 0x56, 0xFF, .W1,   .L2,   .VREDUCEPD,      {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x56, 0xFF, .W1,   .L0,   .VREDUCEPD,      {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x56, 0xFF, .W0,   .L1,   .VREDUCEPS,      {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x56, 0xFF, .W0,   .L0,   .VREDUCEPS,      {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x56, 0xFF, .W0,   .L2,   .VREDUCEPS,      {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x56, 0xFF, .W1,   .L1,   .VREDUCEPD,      {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x57, 0xFF, .W0,   .LIG,  .VREDUCESS,      {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
-	{._0F3A, 1, 0x57, 0xFF, .W1,   .LIG,  .VREDUCESD,      {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
-	{._0F3A, 1, 0x66, 0xFF, .W0,   .L0,   .VFPCLASSPS,     {.K,         .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}},
-	{._0F3A, 1, 0x66, 0xFF, .W0,   .L1,   .VFPCLASSPS,     {.K,         .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}},
-	{._0F3A, 1, 0x66, 0xFF, .W0,   .L2,   .VFPCLASSPS,     {.K,         .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}},
-	{._0F3A, 1, 0x66, 0xFF, .W1,   .L0,   .VFPCLASSPD,     {.K,         .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}},
-	{._0F3A, 1, 0x66, 0xFF, .W1,   .L2,   .VFPCLASSPD,     {.K,         .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}},
-	{._0F3A, 1, 0x66, 0xFF, .W1,   .L1,   .VFPCLASSPD,     {.K,         .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}},
-	{._0F3A, 1, 0x67, 0xFF, .W1,   .LIG,  .VFPCLASSSD,     {.K,         .XMM_M64,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}},
-	{._0F3A, 1, 0x67, 0xFF, .W0,   .LIG,  .VFPCLASSSS,     {.K,         .XMM_M32,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}},
+	{._0F,   1, 0x6F, 0xFF, .W0,   .L1,   .VMOVDQA32,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6F, 0xFF, .W0,   .L0,   .VMOVDQA32,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6F, 0xFF, .W1,   .L0,   .VMOVDQA64,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6F, 0xFF, .W1,   .L2,   .VMOVDQA64,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6F, 0xFF, .W1,   .L1,   .VMOVDQA64,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x6F, 0xFF, .W0,   .L2,   .VMOVDQA32,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x01, .W0,   .L2,   .VPROLD,         {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x01, .W0,   .L0,   .VPROLD,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x01, .W0,   .L1,   .VPROLD,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x01, .W1,   .L2,   .VPROLQ,         {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x01, .W1,   .L0,   .VPROLQ,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0x01, .W1,   .L1,   .VPROLQ,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0xFF, .W0,   .L2,   .VPRORD,         {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0xFF, .W1,   .L0,   .VPRORQ,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0xFF, .W1,   .L2,   .VPRORQ,         {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0xFF, .W0,   .L0,   .VPRORD,         {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0xFF, .W0,   .L1,   .VPRORD,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x72, 0xFF, .W1,   .L1,   .VPRORQ,         {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.VVVV, .MR,   .IB,   .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F,   1, 0x7F, 0xFF, .W1,   .L0,   .VMOVDQA64,      {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7F, 0xFF, .W1,   .L1,   .VMOVDQA64,      {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7F, 0xFF, .W1,   .L2,   .VMOVDQA64,      {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7F, 0xFF, .W0,   .L1,   .VMOVDQA32,      {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7F, 0xFF, .W0,   .L2,   .VMOVDQA32,      {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   1, 0x7F, 0xFF, .W0,   .L0,   .VMOVDQA32,      {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x6F, 0xFF, .W1,   .L1,   .VMOVDQU64,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x6F, 0xFF, .W0,   .L0,   .VMOVDQU32,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x6F, 0xFF, .W1,   .L2,   .VMOVDQU64,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x6F, 0xFF, .W0,   .L2,   .VMOVDQU32,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x6F, 0xFF, .W0,   .L1,   .VMOVDQU32,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x6F, 0xFF, .W1,   .L0,   .VMOVDQU64,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x7F, 0xFF, .W1,   .L0,   .VMOVDQU64,      {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x7F, 0xFF, .W0,   .L1,   .VMOVDQU32,      {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x7F, 0xFF, .W1,   .L1,   .VMOVDQU64,      {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x7F, 0xFF, .W0,   .L2,   .VMOVDQU32,      {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x7F, 0xFF, .W0,   .L0,   .VMOVDQU32,      {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   2, 0x7F, 0xFF, .W1,   .L2,   .VMOVDQU64,      {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x6F, 0xFF, .W1,   .L1,   .VMOVDQU16,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x6F, 0xFF, .W1,   .L0,   .VMOVDQU16,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x6F, 0xFF, .W0,   .L2,   .VMOVDQU8,       {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x6F, 0xFF, .W0,   .L1,   .VMOVDQU8,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x6F, 0xFF, .W0,   .L0,   .VMOVDQU8,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x6F, 0xFF, .W1,   .L2,   .VMOVDQU16,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x7F, 0xFF, .W1,   .L2,   .VMOVDQU16,      {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x7F, 0xFF, .W1,   .L0,   .VMOVDQU16,      {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x7F, 0xFF, .W0,   .L0,   .VMOVDQU8,       {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x7F, 0xFF, .W0,   .L1,   .VMOVDQU8,       {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x7F, 0xFF, .W0,   .L2,   .VMOVDQU8,       {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F,   3, 0x7F, 0xFF, .W1,   .L1,   .VMOVDQU16,      {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x10, 0xFF, .W1,   .L2,   .VPSRLVW,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x10, 0xFF, .W1,   .L0,   .VPSRLVW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x10, 0xFF, .W1,   .L1,   .VPSRLVW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x11, 0xFF, .W1,   .L2,   .VPSRAVW,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x11, 0xFF, .W1,   .L0,   .VPSRAVW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x11, 0xFF, .W1,   .L1,   .VPSRAVW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x12, 0xFF, .W1,   .L1,   .VPSLLVW,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x12, 0xFF, .W1,   .L2,   .VPSLLVW,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x12, 0xFF, .W1,   .L0,   .VPSLLVW,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x13, 0xFF, .WIG,  .L2,   .VCVTPH2PS,      {.ZMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x14, 0xFF, .W0,   .L0,   .VPRORVD,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x14, 0xFF, .W1,   .L0,   .VPRORVQ,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x14, 0xFF, .W0,   .L2,   .VPRORVD,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x14, 0xFF, .W1,   .L2,   .VPRORVQ,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x14, 0xFF, .W0,   .L1,   .VPRORVD,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x14, 0xFF, .W1,   .L1,   .VPRORVQ,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x15, 0xFF, .W0,   .L1,   .VPROLVD,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x15, 0xFF, .W1,   .L1,   .VPROLVQ,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x15, 0xFF, .W1,   .L0,   .VPROLVQ,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x15, 0xFF, .W0,   .L0,   .VPROLVD,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x15, 0xFF, .W0,   .L2,   .VPROLVD,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x15, 0xFF, .W1,   .L2,   .VPROLVQ,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x26, 0xFF, .W1,   .L1,   .VPTESTMW,       {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x26, 0xFF, .W1,   .L2,   .VPTESTMW,       {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x26, 0xFF, .W0,   .L2,   .VPTESTMB,       {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x26, 0xFF, .W0,   .L1,   .VPTESTMB,       {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x26, 0xFF, .W1,   .L0,   .VPTESTMW,       {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x26, 0xFF, .W0,   .L0,   .VPTESTMB,       {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x27, 0xFF, .W0,   .L0,   .VPTESTMD,       {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x27, 0xFF, .W0,   .L2,   .VPTESTMD,       {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x27, 0xFF, .W1,   .L2,   .VPTESTMQ,       {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x27, 0xFF, .W1,   .L0,   .VPTESTMQ,       {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x27, 0xFF, .W1,   .L1,   .VPTESTMQ,       {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x27, 0xFF, .W0,   .L1,   .VPTESTMD,       {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2C, 0xFF, .W0,   .L1,   .VSCALEFPS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2C, 0xFF, .W1,   .L1,   .VSCALEFPD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2C, 0xFF, .W0,   .L0,   .VSCALEFPS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2C, 0xFF, .W1,   .L0,   .VSCALEFPD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2C, 0xFF, .W1,   .L2,   .VSCALEFPD,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2C, 0xFF, .W0,   .L2,   .VSCALEFPS,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2D, 0xFF, .W1,   .LIG,  .VSCALEFSD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x2D, 0xFF, .W0,   .LIG,  .VSCALEFSS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x42, 0xFF, .W0,   .L2,   .VGETEXPPS,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x42, 0xFF, .W0,   .L0,   .VGETEXPPS,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x42, 0xFF, .W1,   .L1,   .VGETEXPPD,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x42, 0xFF, .W0,   .L1,   .VGETEXPPS,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x42, 0xFF, .W1,   .L0,   .VGETEXPPD,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x42, 0xFF, .W1,   .L2,   .VGETEXPPD,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x43, 0xFF, .W1,   .LIG,  .VGETEXPSD,      {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x43, 0xFF, .W0,   .LIG,  .VGETEXPSS,      {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x44, 0xFF, .W0,   .L0,   .VPLZCNTD,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x44, 0xFF, .W0,   .L2,   .VPLZCNTD,       {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x44, 0xFF, .W1,   .L0,   .VPLZCNTQ,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x44, 0xFF, .W0,   .L1,   .VPLZCNTD,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x44, 0xFF, .W1,   .L1,   .VPLZCNTQ,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x44, 0xFF, .W1,   .L2,   .VPLZCNTQ,       {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x46, 0xFF, .W1,   .L0,   .VPSRAVQ,        {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x46, 0xFF, .W1,   .L2,   .VPSRAVQ,        {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x46, 0xFF, .W1,   .L1,   .VPSRAVQ,        {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x4C, 0xFF, .W1,   .L0,   .VRCP14PD,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4C, 0xFF, .W0,   .L2,   .VRCP14PS,       {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4C, 0xFF, .W1,   .L2,   .VRCP14PD,       {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4C, 0xFF, .W0,   .L1,   .VRCP14PS,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4C, 0xFF, .W0,   .L0,   .VRCP14PS,       {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4C, 0xFF, .W1,   .L1,   .VRCP14PD,       {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4D, 0xFF, .W0,   .LIG,  .VRCP14SS,       {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x4D, 0xFF, .W1,   .LIG,  .VRCP14SD,       {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x4E, 0xFF, .W1,   .L0,   .VRSQRT14PD,     {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4E, 0xFF, .W1,   .L2,   .VRSQRT14PD,     {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4E, 0xFF, .W1,   .L1,   .VRSQRT14PD,     {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4E, 0xFF, .W0,   .L1,   .VRSQRT14PS,     {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4E, 0xFF, .W0,   .L2,   .VRSQRT14PS,     {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4E, 0xFF, .W0,   .L0,   .VRSQRT14PS,     {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x4F, 0xFF, .W1,   .LIG,  .VRSQRT14SD,     {.XMM,       .XMM,       .XMM_M64,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x4F, 0xFF, .W0,   .LIG,  .VRSQRT14SS,     {.XMM,       .XMM,       .XMM_M32,   .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x64, 0xFF, .W1,   .L0,   .VPBLENDMQ,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x64, 0xFF, .W0,   .L2,   .VPBLENDMD,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x64, 0xFF, .W1,   .L1,   .VPBLENDMQ,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x64, 0xFF, .W0,   .L0,   .VPBLENDMD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x64, 0xFF, .W1,   .L2,   .VPBLENDMQ,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x64, 0xFF, .W0,   .L1,   .VPBLENDMD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x65, 0xFF, .W1,   .L0,   .VBLENDMPD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x65, 0xFF, .W0,   .L1,   .VBLENDMPS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x65, 0xFF, .W0,   .L0,   .VBLENDMPS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x65, 0xFF, .W0,   .L2,   .VBLENDMPS,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x65, 0xFF, .W1,   .L1,   .VBLENDMPD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x65, 0xFF, .W1,   .L2,   .VBLENDMPD,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x66, 0xFF, .W1,   .L1,   .VPBLENDMW,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x66, 0xFF, .W1,   .L0,   .VPBLENDMW,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x66, 0xFF, .W1,   .L2,   .VPBLENDMW,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x66, 0xFF, .W0,   .L0,   .VPBLENDMB,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x66, 0xFF, .W0,   .L1,   .VPBLENDMB,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x66, 0xFF, .W0,   .L2,   .VPBLENDMB,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x75, 0xFF, .W0,   .L0,   .VPERMI2B,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x75, 0xFF, .W0,   .L1,   .VPERMI2B,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x75, 0xFF, .W0,   .L2,   .VPERMI2B,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x75, 0xFF, .W1,   .L1,   .VPERMI2W,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x75, 0xFF, .W1,   .L0,   .VPERMI2W,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x75, 0xFF, .W1,   .L2,   .VPERMI2W,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x76, 0xFF, .W0,   .L0,   .VPERMI2D,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x76, 0xFF, .W0,   .L1,   .VPERMI2D,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x76, 0xFF, .W0,   .L2,   .VPERMI2D,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x76, 0xFF, .W1,   .L0,   .VPERMI2Q,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x76, 0xFF, .W1,   .L2,   .VPERMI2Q,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x76, 0xFF, .W1,   .L1,   .VPERMI2Q,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x77, 0xFF, .W0,   .L1,   .VPERMI2PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x77, 0xFF, .W0,   .L0,   .VPERMI2PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x77, 0xFF, .W1,   .L0,   .VPERMI2PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x77, 0xFF, .W1,   .L1,   .VPERMI2PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x77, 0xFF, .W1,   .L2,   .VPERMI2PD,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x77, 0xFF, .W0,   .L2,   .VPERMI2PS,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7D, 0xFF, .W0,   .L1,   .VPERMT2B,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7D, 0xFF, .W0,   .L2,   .VPERMT2B,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7D, 0xFF, .W1,   .L0,   .VPERMT2W,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7D, 0xFF, .W1,   .L1,   .VPERMT2W,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7D, 0xFF, .W1,   .L2,   .VPERMT2W,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7D, 0xFF, .W0,   .L0,   .VPERMT2B,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7E, 0xFF, .W0,   .L0,   .VPERMT2D,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7E, 0xFF, .W0,   .L2,   .VPERMT2D,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7E, 0xFF, .W0,   .L1,   .VPERMT2D,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7E, 0xFF, .W1,   .L1,   .VPERMT2Q,       {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7E, 0xFF, .W1,   .L0,   .VPERMT2Q,       {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7E, 0xFF, .W1,   .L2,   .VPERMT2Q,       {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7F, 0xFF, .W0,   .L1,   .VPERMT2PS,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7F, 0xFF, .W0,   .L0,   .VPERMT2PS,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7F, 0xFF, .W0,   .L2,   .VPERMT2PS,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7F, 0xFF, .W1,   .L0,   .VPERMT2PD,      {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7F, 0xFF, .W1,   .L1,   .VPERMT2PD,      {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x7F, 0xFF, .W1,   .L2,   .VPERMT2PD,      {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x83, 0xFF, .W1,   .L1,   .VPMULTISHIFTQB, {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x83, 0xFF, .W1,   .L0,   .VPMULTISHIFTQB, {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x83, 0xFF, .W1,   .L2,   .VPMULTISHIFTQB, {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x88, 0xFF, .W1,   .L2,   .VEXPANDPD,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x88, 0xFF, .W1,   .L0,   .VEXPANDPD,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x88, 0xFF, .W0,   .L2,   .VEXPANDPS,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x88, 0xFF, .W1,   .L1,   .VEXPANDPD,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x88, 0xFF, .W0,   .L0,   .VEXPANDPS,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x88, 0xFF, .W0,   .L1,   .VEXPANDPS,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x89, 0xFF, .W1,   .L2,   .VPEXPANDQ,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x89, 0xFF, .W1,   .L0,   .VPEXPANDQ,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x89, 0xFF, .W0,   .L2,   .VPEXPANDD,      {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x89, 0xFF, .W1,   .L1,   .VPEXPANDQ,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x89, 0xFF, .W0,   .L0,   .VPEXPANDD,      {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x89, 0xFF, .W0,   .L1,   .VPEXPANDD,      {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8A, 0xFF, .W1,   .L2,   .VCOMPRESSPD,    {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8A, 0xFF, .W1,   .L1,   .VCOMPRESSPD,    {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8A, 0xFF, .W0,   .L2,   .VCOMPRESSPS,    {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8A, 0xFF, .W0,   .L0,   .VCOMPRESSPS,    {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8A, 0xFF, .W0,   .L1,   .VCOMPRESSPS,    {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8A, 0xFF, .W1,   .L0,   .VCOMPRESSPD,    {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8B, 0xFF, .W1,   .L2,   .VPCOMPRESSQ,    {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8B, 0xFF, .W0,   .L0,   .VPCOMPRESSD,    {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8B, 0xFF, .W0,   .L1,   .VPCOMPRESSD,    {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8B, 0xFF, .W0,   .L2,   .VPCOMPRESSD,    {.ZMM_M512,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8B, 0xFF, .W1,   .L0,   .VPCOMPRESSQ,    {.XMM_M128,  .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8B, 0xFF, .W1,   .L1,   .VPCOMPRESSQ,    {.YMM_M256,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0x8D, 0xFF, .W0,   .L0,   .VPERMB,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8D, 0xFF, .W1,   .L1,   .VPERMW,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8D, 0xFF, .W0,   .L2,   .VPERMB,         {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8D, 0xFF, .W0,   .L1,   .VPERMB,         {.YMM,       .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8D, 0xFF, .W1,   .L0,   .VPERMW,         {.XMM,       .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0x8D, 0xFF, .W1,   .L2,   .VPERMW,         {.ZMM,       .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 1, 0xA0, 0xFF, .W1,   .L2,   .VPSCATTERDQ,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA0, 0xFF, .W1,   .L0,   .VPSCATTERDQ,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA0, 0xFF, .W1,   .L1,   .VPSCATTERDQ,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA0, 0xFF, .W0,   .L2,   .VPSCATTERDD,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA0, 0xFF, .W0,   .L1,   .VPSCATTERDD,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA0, 0xFF, .W0,   .L0,   .VPSCATTERDD,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA1, 0xFF, .W0,   .L0,   .VPSCATTERQD,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA1, 0xFF, .W1,   .L0,   .VPSCATTERQQ,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA1, 0xFF, .W0,   .L1,   .VPSCATTERQD,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA1, 0xFF, .W1,   .L1,   .VPSCATTERQQ,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA1, 0xFF, .W1,   .L2,   .VPSCATTERQQ,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA1, 0xFF, .W0,   .L2,   .VPSCATTERQD,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA2, 0xFF, .W1,   .L2,   .VSCATTERDPD,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA2, 0xFF, .W0,   .L1,   .VSCATTERDPS,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA2, 0xFF, .W0,   .L0,   .VSCATTERDPS,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA2, 0xFF, .W0,   .L2,   .VSCATTERDPS,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA2, 0xFF, .W1,   .L0,   .VSCATTERDPD,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA2, 0xFF, .W1,   .L1,   .VSCATTERDPD,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA3, 0xFF, .W0,   .L0,   .VSCATTERQPS,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA3, 0xFF, .W1,   .L2,   .VSCATTERQPD,    {.M,         .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA3, 0xFF, .W0,   .L1,   .VSCATTERQPS,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA3, 0xFF, .W1,   .L0,   .VSCATTERQPD,    {.M,         .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA3, 0xFF, .W1,   .L1,   .VSCATTERQPD,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xA3, 0xFF, .W0,   .L2,   .VSCATTERQPS,    {.M,         .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xC4, 0xFF, .W0,   .L2,   .VPCONFLICTD,    {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xC4, 0xFF, .W0,   .L1,   .VPCONFLICTD,    {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xC4, 0xFF, .W1,   .L0,   .VPCONFLICTQ,    {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xC4, 0xFF, .W0,   .L0,   .VPCONFLICTD,    {.XMM,       .XMM_M128,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xC4, 0xFF, .W1,   .L1,   .VPCONFLICTQ,    {.YMM,       .YMM_M256,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 1, 0xC4, 0xFF, .W1,   .L2,   .VPCONFLICTQ,    {.ZMM,       .ZMM_M512,  .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x10, 0xFF, .W0,   .L2,   .VPMOVUSWB,      {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x10, 0xFF, .W0,   .L1,   .VPMOVUSWB,      {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x10, 0xFF, .W0,   .L0,   .VPMOVUSWB,      {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x11, 0xFF, .W0,   .L0,   .VPMOVUSDB,      {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x11, 0xFF, .W0,   .L1,   .VPMOVUSDB,      {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x11, 0xFF, .W0,   .L2,   .VPMOVUSDB,      {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x12, 0xFF, .W0,   .L2,   .VPMOVUSQB,      {.XMM_M64,   .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x12, 0xFF, .W0,   .L0,   .VPMOVUSQB,      {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x12, 0xFF, .W0,   .L1,   .VPMOVUSQB,      {.XMM_M32,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x13, 0xFF, .W0,   .L0,   .VPMOVUSDW,      {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x13, 0xFF, .W0,   .L2,   .VPMOVUSDW,      {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x13, 0xFF, .W0,   .L1,   .VPMOVUSDW,      {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x14, 0xFF, .W0,   .L2,   .VPMOVUSQW,      {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x14, 0xFF, .W0,   .L0,   .VPMOVUSQW,      {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x14, 0xFF, .W0,   .L1,   .VPMOVUSQW,      {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x15, 0xFF, .W0,   .L0,   .VPMOVUSQD,      {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x15, 0xFF, .W0,   .L1,   .VPMOVUSQD,      {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x15, 0xFF, .W0,   .L2,   .VPMOVUSQD,      {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x20, 0xFF, .W0,   .L1,   .VPMOVSWB,       {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x20, 0xFF, .W0,   .L2,   .VPMOVSWB,       {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x20, 0xFF, .W0,   .L0,   .VPMOVSWB,       {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x21, 0xFF, .W0,   .L2,   .VPMOVSDB,       {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x21, 0xFF, .W0,   .L0,   .VPMOVSDB,       {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x21, 0xFF, .W0,   .L1,   .VPMOVSDB,       {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x22, 0xFF, .W0,   .L2,   .VPMOVSQB,       {.XMM_M64,   .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x22, 0xFF, .W0,   .L0,   .VPMOVSQB,       {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x22, 0xFF, .W0,   .L1,   .VPMOVSQB,       {.XMM_M32,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x23, 0xFF, .W0,   .L1,   .VPMOVSDW,       {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x23, 0xFF, .W0,   .L0,   .VPMOVSDW,       {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x23, 0xFF, .W0,   .L2,   .VPMOVSDW,       {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x24, 0xFF, .W0,   .L1,   .VPMOVSQW,       {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x24, 0xFF, .W0,   .L0,   .VPMOVSQW,       {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x24, 0xFF, .W0,   .L2,   .VPMOVSQW,       {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x25, 0xFF, .W0,   .L2,   .VPMOVSQD,       {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x25, 0xFF, .W0,   .L0,   .VPMOVSQD,       {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x25, 0xFF, .W0,   .L1,   .VPMOVSQD,       {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x26, 0xFF, .W1,   .L2,   .VPTESTNMW,      {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x26, 0xFF, .W1,   .L0,   .VPTESTNMW,      {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x26, 0xFF, .W0,   .L1,   .VPTESTNMB,      {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x26, 0xFF, .W0,   .L0,   .VPTESTNMB,      {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x26, 0xFF, .W0,   .L2,   .VPTESTNMB,      {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x26, 0xFF, .W1,   .L1,   .VPTESTNMW,      {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x27, 0xFF, .W1,   .L1,   .VPTESTNMQ,      {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x27, 0xFF, .W1,   .L0,   .VPTESTNMQ,      {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x27, 0xFF, .W1,   .L2,   .VPTESTNMQ,      {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x27, 0xFF, .W0,   .L0,   .VPTESTNMD,      {.K,         .XMM,       .XMM_M128,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x27, 0xFF, .W0,   .L1,   .VPTESTNMD,      {.K,         .YMM,       .YMM_M256,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x27, 0xFF, .W0,   .L2,   .VPTESTNMD,      {.K,         .ZMM,       .ZMM_M512,  .NONE}, {.REG,  .VVVV, .MR,   .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F38, 2, 0x28, 0xFF, .W1,   .L1,   .VPMOVM2W,       {.YMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x28, 0xFF, .W1,   .L0,   .VPMOVM2W,       {.XMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x28, 0xFF, .W1,   .L2,   .VPMOVM2W,       {.ZMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x28, 0xFF, .W0,   .L1,   .VPMOVM2B,       {.YMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x28, 0xFF, .W0,   .L2,   .VPMOVM2B,       {.ZMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x28, 0xFF, .W0,   .L0,   .VPMOVM2B,       {.XMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x29, 0xFF, .W1,   .L2,   .VPMOVW2M,       {.K,         .ZMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x29, 0xFF, .W1,   .L1,   .VPMOVW2M,       {.K,         .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x29, 0xFF, .W0,   .L1,   .VPMOVB2M,       {.K,         .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x29, 0xFF, .W0,   .L0,   .VPMOVB2M,       {.K,         .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x29, 0xFF, .W0,   .L2,   .VPMOVB2M,       {.K,         .ZMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x29, 0xFF, .W1,   .L0,   .VPMOVW2M,       {.K,         .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x30, 0xFF, .W0,   .L2,   .VPMOVWB,        {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x30, 0xFF, .W0,   .L0,   .VPMOVWB,        {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x30, 0xFF, .W0,   .L1,   .VPMOVWB,        {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x31, 0xFF, .W0,   .L1,   .VPMOVDB,        {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x31, 0xFF, .W0,   .L0,   .VPMOVDB,        {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x31, 0xFF, .W0,   .L2,   .VPMOVDB,        {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x32, 0xFF, .W0,   .L2,   .VPMOVQB,        {.XMM_M64,   .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x32, 0xFF, .W0,   .L1,   .VPMOVQB,        {.XMM_M32,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x32, 0xFF, .W0,   .L0,   .VPMOVQB,        {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x33, 0xFF, .W0,   .L2,   .VPMOVDW,        {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x33, 0xFF, .W0,   .L0,   .VPMOVDW,        {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x33, 0xFF, .W0,   .L1,   .VPMOVDW,        {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x34, 0xFF, .W0,   .L0,   .VPMOVQW,        {.XMM_M32,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x34, 0xFF, .W0,   .L1,   .VPMOVQW,        {.XMM_M64,   .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x34, 0xFF, .W0,   .L2,   .VPMOVQW,        {.XMM_M128,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x35, 0xFF, .W0,   .L0,   .VPMOVQD,        {.XMM_M64,   .XMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x35, 0xFF, .W0,   .L1,   .VPMOVQD,        {.XMM_M128,  .YMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x35, 0xFF, .W0,   .L2,   .VPMOVQD,        {.YMM_M256,  .ZMM,       .NONE,      .NONE}, {.MR,   .REG,  .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x38, 0xFF, .W1,   .L2,   .VPMOVM2Q,       {.ZMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x38, 0xFF, .W1,   .L0,   .VPMOVM2Q,       {.XMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x38, 0xFF, .W0,   .L2,   .VPMOVM2D,       {.ZMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x38, 0xFF, .W1,   .L1,   .VPMOVM2Q,       {.YMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x38, 0xFF, .W0,   .L0,   .VPMOVM2D,       {.XMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x38, 0xFF, .W0,   .L1,   .VPMOVM2D,       {.YMM,       .K,         .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x39, 0xFF, .W1,   .L2,   .VPMOVQ2M,       {.K,         .ZMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x39, 0xFF, .W1,   .L1,   .VPMOVQ2M,       {.K,         .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x39, 0xFF, .W0,   .L1,   .VPMOVD2M,       {.K,         .YMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x39, 0xFF, .W0,   .L0,   .VPMOVD2M,       {.K,         .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x39, 0xFF, .W0,   .L2,   .VPMOVD2M,       {.K,         .ZMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}},
+	{._0F38, 2, 0x39, 0xFF, .W1,   .L0,   .VPMOVQ2M,       {.K,         .XMM,       .NONE,      .NONE}, {.REG,  .MR,   .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}},
+	{._0F3A, 1, 0x03, 0xFF, .W1,   .L0,   .VALIGNQ,        {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x03, 0xFF, .W0,   .L0,   .VALIGND,        {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x03, 0xFF, .W1,   .L1,   .VALIGNQ,        {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x03, 0xFF, .W0,   .L1,   .VALIGND,        {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x03, 0xFF, .W0,   .L2,   .VALIGND,        {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x03, 0xFF, .W1,   .L2,   .VALIGNQ,        {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x08, 0xFF, .W0,   .L0,   .VRNDSCALEPS,    {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x08, 0xFF, .W0,   .L1,   .VRNDSCALEPS,    {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x08, 0xFF, .W0,   .L2,   .VRNDSCALEPS,    {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x09, 0xFF, .W1,   .L0,   .VRNDSCALEPD,    {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x09, 0xFF, .W1,   .L1,   .VRNDSCALEPD,    {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x09, 0xFF, .W1,   .L2,   .VRNDSCALEPD,    {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x0A, 0xFF, .W0,   .LIG,  .VRNDSCALESS,    {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x0B, 0xFF, .W1,   .LIG,  .VRNDSCALESD,    {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1D, 0xFF, .WIG,  .L2,   .VCVTPS2PH,      {.YMM_M256,  .ZMM,       .IMM8,      .NONE}, {.MR,   .REG,  .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x1E, 0xFF, .W1,   .L2,   .VPCMPUQ,        {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1E, 0xFF, .W1,   .L0,   .VPCMPUQ,        {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1E, 0xFF, .W1,   .L1,   .VPCMPUQ,        {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1E, 0xFF, .W0,   .L2,   .VPCMPUD,        {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1E, 0xFF, .W0,   .L1,   .VPCMPUD,        {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1E, 0xFF, .W0,   .L0,   .VPCMPUD,        {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1F, 0xFF, .W1,   .L2,   .VPCMPQ,         {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1F, 0xFF, .W1,   .L0,   .VPCMPQ,         {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1F, 0xFF, .W0,   .L2,   .VPCMPD,         {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1F, 0xFF, .W0,   .L0,   .VPCMPD,         {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1F, 0xFF, .W0,   .L1,   .VPCMPD,         {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x1F, 0xFF, .W1,   .L1,   .VPCMPQ,         {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x25, 0xFF, .W0,   .L0,   .VPTERNLOGD,     {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x25, 0xFF, .W0,   .L1,   .VPTERNLOGD,     {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x25, 0xFF, .W1,   .L0,   .VPTERNLOGQ,     {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x25, 0xFF, .W1,   .L1,   .VPTERNLOGQ,     {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x25, 0xFF, .W0,   .L2,   .VPTERNLOGD,     {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x25, 0xFF, .W1,   .L2,   .VPTERNLOGQ,     {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x26, 0xFF, .W1,   .L0,   .VGETMANTPD,     {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x26, 0xFF, .W1,   .L1,   .VGETMANTPD,     {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x26, 0xFF, .W0,   .L1,   .VGETMANTPS,     {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x26, 0xFF, .W0,   .L0,   .VGETMANTPS,     {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x26, 0xFF, .W1,   .L2,   .VGETMANTPD,     {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x26, 0xFF, .W0,   .L2,   .VGETMANTPS,     {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x27, 0xFF, .W1,   .LIG,  .VGETMANTSD,     {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x27, 0xFF, .W0,   .LIG,  .VGETMANTSS,     {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3E, 0xFF, .W1,   .L2,   .VPCMPUW,        {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3E, 0xFF, .W0,   .L2,   .VPCMPUB,        {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3E, 0xFF, .W0,   .L0,   .VPCMPUB,        {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3E, 0xFF, .W1,   .L0,   .VPCMPUW,        {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3E, 0xFF, .W0,   .L1,   .VPCMPUB,        {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3E, 0xFF, .W1,   .L1,   .VPCMPUW,        {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3F, 0xFF, .W1,   .L0,   .VPCMPW,         {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3F, 0xFF, .W1,   .L1,   .VPCMPW,         {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3F, 0xFF, .W0,   .L1,   .VPCMPB,         {.K,         .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3F, 0xFF, .W0,   .L0,   .VPCMPB,         {.K,         .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3F, 0xFF, .W0,   .L2,   .VPCMPB,         {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x3F, 0xFF, .W1,   .L2,   .VPCMPW,         {.K,         .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x42, 0xFF, .W0,   .L0,   .VDBPSADBW,      {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x42, 0xFF, .W0,   .L1,   .VDBPSADBW,      {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x42, 0xFF, .W0,   .L2,   .VDBPSADBW,      {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x50, 0xFF, .W1,   .L1,   .VRANGEPD,       {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x50, 0xFF, .W0,   .L2,   .VRANGEPS,       {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x50, 0xFF, .W0,   .L1,   .VRANGEPS,       {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x50, 0xFF, .W1,   .L0,   .VRANGEPD,       {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x50, 0xFF, .W1,   .L2,   .VRANGEPD,       {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x50, 0xFF, .W0,   .L0,   .VRANGEPS,       {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x51, 0xFF, .W0,   .LIG,  .VRANGESS,       {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x51, 0xFF, .W1,   .LIG,  .VRANGESD,       {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x54, 0xFF, .W1,   .L2,   .VFIXUPIMMPD,    {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x54, 0xFF, .W1,   .L1,   .VFIXUPIMMPD,    {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x54, 0xFF, .W0,   .L1,   .VFIXUPIMMPS,    {.YMM,       .YMM,       .YMM_M256,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x54, 0xFF, .W0,   .L0,   .VFIXUPIMMPS,    {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x54, 0xFF, .W0,   .L2,   .VFIXUPIMMPS,    {.ZMM,       .ZMM,       .ZMM_M512,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x54, 0xFF, .W1,   .L0,   .VFIXUPIMMPD,    {.XMM,       .XMM,       .XMM_M128,  .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x55, 0xFF, .W1,   .LIG,  .VFIXUPIMMSD,    {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x55, 0xFF, .W0,   .LIG,  .VFIXUPIMMSS,    {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x56, 0xFF, .W1,   .L2,   .VREDUCEPD,      {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x56, 0xFF, .W1,   .L0,   .VREDUCEPD,      {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x56, 0xFF, .W0,   .L1,   .VREDUCEPS,      {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x56, 0xFF, .W0,   .L0,   .VREDUCEPS,      {.XMM,       .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x56, 0xFF, .W0,   .L2,   .VREDUCEPS,      {.ZMM,       .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x56, 0xFF, .W1,   .L1,   .VREDUCEPD,      {.YMM,       .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x57, 0xFF, .W0,   .LIG,  .VREDUCESS,      {.XMM,       .XMM,       .XMM_M32,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x57, 0xFF, .W1,   .LIG,  .VREDUCESD,      {.XMM,       .XMM,       .XMM_M64,   .IMM8}, {.REG,  .VVVV, .MR,   .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=4, needs_modrm=true}},
+	{._0F3A, 1, 0x66, 0xFF, .W0,   .L0,   .VFPCLASSPS,     {.K,         .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x66, 0xFF, .W0,   .L1,   .VFPCLASSPS,     {.K,         .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x66, 0xFF, .W0,   .L2,   .VFPCLASSPS,     {.K,         .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x66, 0xFF, .W1,   .L0,   .VFPCLASSPD,     {.K,         .XMM_M128,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x66, 0xFF, .W1,   .L2,   .VFPCLASSPD,     {.K,         .ZMM_M512,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x66, 0xFF, .W1,   .L1,   .VFPCLASSPD,     {.K,         .YMM_M256,  .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x67, 0xFF, .W1,   .LIG,  .VFPCLASSSD,     {.K,         .XMM_M64,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=3, needs_modrm=true}},
+	{._0F3A, 1, 0x67, 0xFF, .W0,   .LIG,  .VFPCLASSSS,     {.K,         .XMM_M32,   .IMM8,      .NONE}, {.REG,  .MR,   .IB,   .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=3, needs_modrm=true}},
 }
 
 @(rodata)