diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index e975455c4..3347c3cf7 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -152,6 +152,9 @@ find_and_decode :: proc(word: u32, mode: Mode, ilen: u32, inst: ^Instruction, in // back to the index within ENCODING_TABLE[mnemonic]. Stored as // (form_idx + 1) so a zero hint means "not set". inst.form_id = DECODE_FORM_IDX[entry_idx] + 1 + // Carry the `.i32` suffix out with the instruction, so a decoded + // instruction re-encodes to the same form without needing form_id. + inst.dt = e.dt // Cond: A32 entries with bits[31:28] variable in mask take cond from word if mode == .A32 && (e.mask >> 28) == 0 { diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 065213e6d..80a699c8a 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -160,6 +160,7 @@ encode_one_inline :: #force_inline proc( if inst.form_id != 0 && int(inst.form_id) - 1 < len(forms) { f := &forms[inst.form_id - 1] if f.mode == inst.mode && + (inst.dt[0] == .NONE || f.dt == inst.dt) && (want_len == 0 || inst_size_from_bits(f.bits, f.mode) == want_len) && encoding_matches_inline(inst, f) && inst.flags.sets_flags == f.flags.sets_flags && @@ -170,6 +171,11 @@ encode_one_inline :: #force_inline proc( if form == nil { for &f in forms { if f.mode != inst.mode { continue } + // The `.i32` / `.s32.f32` suffix. NEON reuses one operand shape + // across every element width, so without this the scan can only + // ever reach the first form of a shape. .NONE means the caller did + // not say, and every form of the shape stays eligible. + if inst.dt[0] != .NONE && f.dt != inst.dt { continue } if want_len > 0 && inst_size_from_bits(f.bits, f.mode) != want_len { continue } if !encoding_matches_inline(inst, &f) { continue } if inst.flags.sets_flags && !f.flags.sets_flags { continue } diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index 671389265..f0563547f 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -397,6 +397,30 @@ Operand_Encoding :: enum u8 { // ---- Encoding struct ------------------------------------------------------- +// The data type an A32 mnemonic carries as a suffix: `vadd.i32`, `vcvt.s32.f32`, +// `vstrb.8`. Unlike A64 -- where the arrangement belongs to each operand +// (`add v0.4s, v1.4s, v2.4s`) -- in A32 it belongs to the INSTRUCTION, which is +// why it lives here and on Instruction rather than on Operand. +// +// It is not decoration: NEON reuses one operand shape across every element +// width, so `vadd.i8` and `vadd.f32` are both DPR,DPR,DPR and the type is the +// only thing that separates their encodings. Without it the encoder can only +// ever reach the first form of each shape. +Data_Type :: enum u8 { + NONE, + S8, S16, S32, S64, // signed integer + U8, U16, U32, U64, // unsigned integer + I8, I16, I32, I64, // sign-agnostic integer + F16, F32, F64, // floating point + P8, P16, // polynomial + BF16, // bfloat16 + SZ8, SZ16, SZ32, SZ64, // bare element size (`vmov.32`, `vstrb.8`) +} + +// Two slots because the convert family names both ends: `vcvt.s32.f32`. +// Everything else leaves dt[1] as .NONE. +Data_Types :: [2]Data_Type + Encoding :: struct #packed { mnemonic: Mnemonic, // 2 ops: [4]Operand_Type, // 4 @@ -406,8 +430,9 @@ Encoding :: struct #packed { feature: Feature, // 1 mode: Mode, // 1 flags: Encoding_Flags, // 1 + dt: Data_Types, // 2 } -#assert(size_of(Encoding) == 21) +#assert(size_of(Encoding) == 23) // ---- Length introspection -------------------------------------------------- // diff --git a/core/rexcode/isa/arm32/instructions.odin b/core/rexcode/isa/arm32/instructions.odin index 1c343d583..192513a70 100644 --- a/core/rexcode/isa/arm32/instructions.odin +++ b/core/rexcode/isa/arm32/instructions.odin @@ -35,7 +35,13 @@ Instruction :: struct #packed { // bits). User-constructed instructions leave it at 0; the encoder then // falls back to first-shape-match. Stored as u16 over the two padding bytes. form_id: u16, - _: [7]u8, + // The `.i32` / `.s32.f32` suffix. Zero (.NONE) means "unspecified": the + // encoder then takes the first form of the matching shape, which is what + // every instruction did before this field existed. Set it and the encoder + // picks the encoding for that type. Fits in what was already padding, so + // Instruction does not grow. + dt: Data_Types, + _: [5]u8, } #assert(size_of(Instruction) == 88) diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 21c374197..8428dc513 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -108,21 +108,26 @@ sbprint :: proc( strings.write_string(sb, " ") - // Compute the .
suffix from the matched decoder entry (if any) - // and from the operand kinds when no entry is available. + // The `.
` suffix. It is data on the instruction now, so there is + // nothing to reconstruct: read it straight off. This is also what + // makes the convert family print correctly -- `vcvt.s32.f32` names + // both ends, and the old bit-pattern inference only ever produced one. dt_suffix := "" - if i < len(inst_info) { + dt := inst.dt + if dt[0] == .NONE && i < len(inst_info) { de_idx := int(inst_info[i].decode_entry) if de_idx < len(DECODE_ENTRIES) { - dt_suffix = infer_dt_suffix(&DECODE_ENTRIES[de_idx], inst) + dt = DECODE_ENTRIES[de_idx].dt } } - if dt_suffix == "" { + if dt[0] == .NONE { dt_suffix = infer_dt_suffix_from_inst(inst) } write_mnemonic(sb, inst.mnemonic, inst.cond, inst.flags.sets_flags, opts.uppercase) - if dt_suffix != "" { + if dt[0] != .NONE { + write_data_type(sb, dt, opts.uppercase) + } else if dt_suffix != "" { strings.write_string(sb, dt_suffix) } @@ -391,6 +396,35 @@ wprintln :: proc( // Writers // ============================================================================= +// `.i32`, `.s32.f32`, `.8`. Both slots print when the second is set. +@(private="file") +write_data_type :: proc(sb: ^strings.Builder, dt: Data_Types, uppercase: bool) { + for d in dt { + if d == .NONE { continue } + strings.write_byte(sb, '.') + name := DATA_TYPE_NAMES[d] + for i in 0 ..< len(name) { + c := name[i] + if uppercase && c >= 'a' && c <= 'z' { + strings.write_byte(sb, c - 'a' + 'A') + } else { + strings.write_byte(sb, c) + } + } + } +} + +@(rodata, private="file") +DATA_TYPE_NAMES := [Data_Type]string{ + .NONE = "", + .S8 = "s8", .S16 = "s16", .S32 = "s32", .S64 = "s64", + .U8 = "u8", .U16 = "u16", .U32 = "u32", .U64 = "u64", + .I8 = "i8", .I16 = "i16", .I32 = "i32", .I64 = "i64", + .F16 = "f16", .F32 = "f32", .F64 = "f64", + .P8 = "p8", .P16 = "p16", .BF16 = "bf16", + .SZ8 = "8", .SZ16 = "16", .SZ32 = "32", .SZ64 = "64", +} + @(private="file") write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, cond: u8, sets_flags: bool, uppercase: bool) { name, _ := reflect.enum_name_from_value(m) diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 105a7ba47..bcaf0a76f 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -71,233 +71,233 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // ---------- ADD ---------- .ADD = { // ADD imm: cond 0010 0100 S Rn Rd imm12_mod - {.ADD, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02800000, 0x0FE00000, .BASE, .A32, {}}, + {.ADD, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02800000, 0x0FE00000, .BASE, .A32, {}, {}}, // ADD reg: cond 0000 0100 S Rn Rd shift_imm shift_type 0 Rm - {.ADD, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00800000, 0x0FE00010, .BASE, .A32, {}}, + {.ADD, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00800000, 0x0FE00010, .BASE, .A32, {}, {}}, // ADD rsr: cond 0000 0100 S Rn Rd Rs 0 shift_type 1 Rm - {.ADD, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00800010, 0x0FE00090, .BASE, .A32, {}}, + {.ADD, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00800010, 0x0FE00090, .BASE, .A32, {}, {}}, // ADDS variants - {.ADD, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.ADD, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.ADD, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.ADD, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.ADD, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.ADD, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 2 ADD reg (3-reg): 00011 00 Rm Rn Rd - {.ADD, {.GPR_LOW, .GPR_LOW, .GPR_LOW, .NONE}, {.RD_T16_LO, .RN_T16_LO, .RM_T16_LO, .NONE}, 0x00001800, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR_LOW, .GPR_LOW, .GPR_LOW, .NONE}, {.RD_T16_LO, .RN_T16_LO, .RM_T16_LO, .NONE}, 0x00001800, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 2 ADD imm3: 00011 10 imm3 Rn Rd - {.ADD, {.GPR_LOW, .GPR_LOW, .IMM3, .NONE}, {.RD_T16_LO, .RN_T16_LO, .NONE, .NONE}, 0x00001C00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR_LOW, .GPR_LOW, .IMM3, .NONE}, {.RD_T16_LO, .RN_T16_LO, .NONE, .NONE}, 0x00001C00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 3 ADD imm8: 00110 Rd imm8 - {.ADD, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00003000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00003000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 5 hi-reg ADD: 010001 00 H1 H2 Rm Rd - {.ADD, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004400, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004400, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 12 ADD SP+imm: 10101 Rd imm8 (ADD Rd, SP, #imm8 << 2) - {.ADD, {.GPR_LOW, .GPR, .IMM8, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x0000A800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR_LOW, .GPR, .IMM8, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x0000A800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 13 ADD SP, #imm7: 10110000 0 imm7 - {.ADD, {.GPR, .IMM8, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000B000, 0x0000FF80, .THUMB, .T32, {cond_in_28=false}}, + {.ADD, {.GPR, .IMM8, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000B000, 0x0000FF80, .THUMB, .T32, {cond_in_28=false}, {}}, }, .ADC = { - {.ADC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {}}, - {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00A00000, 0x0FE00010, .BASE, .A32, {}}, - {.ADC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00A00010, 0x0FE00090, .BASE, .A32, {}}, - {.ADC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02B00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00B00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.ADC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00B00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.ADC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00A00000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.ADC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00A00010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.ADC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02B00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00B00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.ADC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00B00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 ADC: 010000 0101 Rm Rd - {.ADC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004140, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.ADC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004140, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ADC imm/reg (op=1010) - {.ADC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1400000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEB400000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ADC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1400000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ADC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEB400000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SUB = { - {.SUB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02400000, 0x0FE00000, .BASE, .A32, {}}, - {.SUB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {}}, - {.SUB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {}}, - {.SUB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.SUB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.SUB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.SUB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02400000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.SUB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.SUB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.SUB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.SUB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.SUB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 2 SUB reg (3-reg): 00011 01 Rm Rn Rd - {.SUB, {.GPR_LOW, .GPR_LOW, .GPR_LOW, .NONE}, {.RD_T16_LO, .RN_T16_LO, .RM_T16_LO, .NONE}, 0x00001A00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.SUB, {.GPR_LOW, .GPR_LOW, .GPR_LOW, .NONE}, {.RD_T16_LO, .RN_T16_LO, .RM_T16_LO, .NONE}, 0x00001A00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 2 SUB imm3: 00011 11 imm3 Rn Rd - {.SUB, {.GPR_LOW, .GPR_LOW, .IMM3, .NONE}, {.RD_T16_LO, .RN_T16_LO, .NONE, .NONE}, 0x00001E00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.SUB, {.GPR_LOW, .GPR_LOW, .IMM3, .NONE}, {.RD_T16_LO, .RN_T16_LO, .NONE, .NONE}, 0x00001E00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 3 SUB imm8: 00111 Rd imm8 - {.SUB, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00003800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.SUB, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00003800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 13 SUB SP, #imm7: 10110000 1 imm7 - {.SUB, {.GPR, .IMM8, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000B080, 0x0000FF80, .THUMB, .T32, {cond_in_28=false}}, + {.SUB, {.GPR, .IMM8, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000B080, 0x0000FF80, .THUMB, .T32, {cond_in_28=false}, {}}, }, .SBC = { - {.SBC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02C00000, 0x0FE00000, .BASE, .A32, {}}, - {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00C00000, 0x0FE00010, .BASE, .A32, {}}, - {.SBC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00C00010, 0x0FE00090, .BASE, .A32, {}}, - {.SBC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.SBC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.SBC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02C00000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00C00000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.SBC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00C00010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.SBC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.SBC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 SBC: 010000 0110 Rm Rd - {.SBC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004180, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.SBC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004180, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 SBC imm/reg (op=1011) - {.SBC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1600000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEB600000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SBC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1600000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.SBC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEB600000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .RSB = { - {.RSB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}}, - {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {}}, - {.RSB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {}}, - {.RSB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.RSB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.RSB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.RSB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.RSB, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.RSB, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T32 RSB imm/reg (op=1110) - {.RSB, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1C00000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEBC00000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.RSB, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF1C00000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.RSB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEBC00000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .RSC = { - {.RSC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02E00000, 0x0FE00000, .BASE, .A32, {}}, - {.RSC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00E00000, 0x0FE00010, .BASE, .A32, {}}, - {.RSC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00E00010, 0x0FE00090, .BASE, .A32, {}}, - {.RSC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02F00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.RSC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.RSC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.RSC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02E00000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.RSC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00E00000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.RSC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00E00010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.RSC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02F00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.RSC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.RSC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, }, .AND = { - {.AND, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}}, - {.AND, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}}, - {.AND, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02100000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.AND, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.AND, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.AND, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.AND, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02100000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.AND, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 AND: 010000 0000 Rm Rd - {.AND, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.AND, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 AND imm12: high=11110 i 0 0000 S Rn low=0 imm3 Rd imm8 - {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}}, + {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.AND, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, // T32 AND reg: high=11101 01 0000 S Rn low=imm3 Rd imm2 type Rm - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.AND, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, }, .EOR = { - {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}}, - {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {}}, - {.EOR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00200010, 0x0FE00090, .BASE, .A32, {}}, - {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02300000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.EOR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.EOR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00200010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.EOR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x02300000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.EOR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 EOR: 010000 0001 Rm Rd - {.EOR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004040, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.EOR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004040, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 EOR imm/reg - {.EOR, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA800000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.EOR, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.EOR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA800000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ORR = { - {.ORR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {}}, - {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01800000, 0x0FE00010, .BASE, .A32, {}}, - {.ORR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01800010, 0x0FE00090, .BASE, .A32, {}}, - {.ORR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.ORR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.ORR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01800000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.ORR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01800010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.ORR, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.ORR, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 ORR: 010000 1100 Rm Rd - {.ORR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004300, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.ORR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004300, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ORR imm/reg (op=0010) - {.ORR, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0400000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA400000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ORR, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0400000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.ORR, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA400000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .BIC = { - {.BIC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}}, - {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}}, - {.BIC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01C00010, 0x0FE00090, .BASE, .A32, {}}, - {.BIC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}}, - {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}}, - {.BIC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}}, + {.BIC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}, {}}, + {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}, {}}, + {.BIC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01C00010, 0x0FE00090, .BASE, .A32, {}, {}}, + {.BIC, {.GPR, .GPR, .IMM_MOD, .NONE}, {.RD, .RN_A32, .A32_IMM_MOD, .NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {}}, + {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {}}, + {.BIC, {.GPR, .GPR, .GPR_RSR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 BIC: 010000 1110 Rm Rd - {.BIC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004380, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.BIC, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004380, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 BIC imm/reg (op=0001) - {.BIC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0200000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA200000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.BIC, {.GPR, .GPR, .IMM_T32_MOD, .NONE}, {.RD_T32, .RN_T32, .T32_IMM_MOD, .NONE}, 0xF0200000, 0xFBE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.BIC, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xEA200000, 0xFFE08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // MOV and MVN have Rn unused (encoded as 0). The MOV-immediate form // additionally has ARMv6T2 MOVW (low half, no shift) and MOVT (high half). .MOV = { - {.MOV, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}}, - {.MOV, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00000, 0x0FEF0010, .BASE, .A32, {}}, - {.MOV, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00010, 0x0FEF0090, .BASE, .A32, {}}, - {.MOV, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}}, - {.MOV, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01B00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}}, - {.MOV, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}}, + {.MOV, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {}}, + {.MOV, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00000, 0x0FEF0010, .BASE, .A32, {}, {}}, + {.MOV, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00010, 0x0FEF0090, .BASE, .A32, {}, {}}, + {.MOV, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {}}, + {.MOV, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01B00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}, {}}, + {.MOV, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 3 MOV imm8: 00100 Rd imm8 - {.MOV, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.MOV, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 5 hi-reg MOV: 010001 10 H1 H2 Rm Rd - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}}, + {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 MOV imm12-mod (encoding T2): high=11110 i 0 0010 S 1111 low=0 imm3 Rd imm8 - {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}}, + {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.MOV, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, // T32 MOV reg (encoding T3): high=11101 01 0010 S 1111 low=0 imm3 Rd imm2 00 Rm - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}}, + {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.MOV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false, sets_flags=true}, {}}, }, .MVN = { - {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}}, - {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01E00000, 0x0FEF0010, .BASE, .A32, {}}, - {.MVN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01E00010, 0x0FEF0090, .BASE, .A32, {}}, - {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}}, - {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01F00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}}, - {.MVN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01F00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}}, + {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {}}, + {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01E00000, 0x0FEF0010, .BASE, .A32, {}, {}}, + {.MVN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01E00010, 0x0FEF0090, .BASE, .A32, {}, {}}, + {.MVN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RD, .A32_IMM_MOD, .NONE, .NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {}}, + {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01F00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}, {}}, + {.MVN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01F00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 MVN: 010000 1111 Rm Rd - {.MVN, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000043C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.MVN, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000043C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 MVN imm/reg (op=0011, Rn=15) - {.MVN, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA6F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MVN, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RD_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.MVN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA6F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // MOVW / MOVT (ARMv6T2): 16-bit imm split as imm4(19:16) + imm12(11:0) .MOVW = { - {.MOVW, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x03000000, 0x0FF00000, .V6T2, .A32, {}}, + {.MOVW, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x03000000, 0x0FF00000, .V6T2, .A32, {}, {}}, // T32 MOVW: high=11110 i 1 0010 0 imm4 low=0 imm3 Rd imm8 - {.MOVW, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF2400000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MOVW, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF2400000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .MOVT = { - {.MOVT, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x03400000, 0x0FF00000, .V6T2, .A32, {}}, + {.MOVT, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x03400000, 0x0FF00000, .V6T2, .A32, {}, {}}, // T32 MOVT: high=11110 i 1 0110 0 imm4 - {.MOVT, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF2C00000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MOVT, {.GPR, .IMM16_LO_HI, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF2C00000, 0xFBF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Comparison-only ops: S is implicit-1, Rd is unused (encoded as 0). .TST = { - {.TST, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03100000, 0x0FF0F000, .BASE, .A32, {}}, - {.TST, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01100000, 0x0FF0F010, .BASE, .A32, {}}, - {.TST, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01100010, 0x0FF0F090, .BASE, .A32, {}}, + {.TST, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03100000, 0x0FF0F000, .BASE, .A32, {}, {}}, + {.TST, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01100000, 0x0FF0F010, .BASE, .A32, {}, {}}, + {.TST, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01100010, 0x0FF0F090, .BASE, .A32, {}, {}}, // T16 Format 4 TST: 010000 1000 Rm Rn - {.TST, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004200, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.TST, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004200, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 TST imm/reg (op=0000, S=1, Rd=15) - {.TST, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF0100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.TST, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEA100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.TST, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF0100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.TST, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEA100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .TEQ = { - {.TEQ, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03300000, 0x0FF0F000, .BASE, .A32, {}}, - {.TEQ, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01300000, 0x0FF0F010, .BASE, .A32, {}}, - {.TEQ, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01300010, 0x0FF0F090, .BASE, .A32, {}}, + {.TEQ, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03300000, 0x0FF0F000, .BASE, .A32, {}, {}}, + {.TEQ, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01300000, 0x0FF0F010, .BASE, .A32, {}, {}}, + {.TEQ, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01300010, 0x0FF0F090, .BASE, .A32, {}, {}}, // T32 TEQ imm/reg (op=0100, S=1, Rd=15) - {.TEQ, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.TEQ, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEA900F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.TEQ, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.TEQ, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEA900F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CMP = { - {.CMP, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03500000, 0x0FF0F000, .BASE, .A32, {}}, - {.CMP, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {}}, - {.CMP, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {}}, + {.CMP, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03500000, 0x0FF0F000, .BASE, .A32, {}, {}}, + {.CMP, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {}, {}}, + {.CMP, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {}, {}}, // T16 Format 3 CMP imm8: 00101 Rn imm8 - {.CMP, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00002800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.CMP, {.GPR_LOW, .IMM8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x00002800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 4 CMP reg: 010000 1010 Rm Rn - {.CMP, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004280, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.CMP, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004280, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 5 hi-reg CMP: 010001 01 H1 H2 Rm Rn - {.CMP, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004500, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}}, + {.CMP, {.GPR, .GPR, .NONE, .NONE}, {.RD_T16_HI, .RM_T16_HI, .NONE, .NONE}, 0x00004500, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 CMP imm/reg (op=1101, S=1, Rd=15) - {.CMP, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.CMP, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEBB00F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.CMP, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.CMP, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEBB00F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CMN = { - {.CMN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03700000, 0x0FF0F000, .BASE, .A32, {}}, - {.CMN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {}}, - {.CMN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {}}, + {.CMN, {.GPR, .IMM_MOD, .NONE, .NONE}, {.RN_A32, .A32_IMM_MOD, .NONE, .NONE}, 0x03700000, 0x0FF0F000, .BASE, .A32, {}, {}}, + {.CMN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {}, {}}, + {.CMN, {.GPR, .GPR_RSR, .NONE, .NONE}, {.RN_A32, .RM_A32, .NONE, .NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {}, {}}, // T16 Format 4 CMN: 010000 1011 Rm Rn - {.CMN, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000042C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.CMN, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RN_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000042C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 CMN imm/reg (op=1000, S=1, Rd=15) - {.CMN, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF1100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.CMN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEB100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.CMN, {.GPR, .IMM_T32_MOD, .NONE, .NONE}, {.RN_T32, .T32_IMM_MOD, .NONE, .NONE}, 0xF1100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.CMN, {.GPR, .GPR_SHIFTED, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xEB100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ========================================================================= @@ -312,105 +312,105 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // The 1001 nibble at bits 7-4 is the discriminator from data-proc reg. .MUL = { - {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}}, - {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x00100090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x00100090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T16 Format 4 MUL: 010000 1101 Rm Rd - {.MUL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004340, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.MUL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004340, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 MUL: high=11111011 0000 Rn low=1111 Rd 0000 Rm - {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MUL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .MLA = { - {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00200090, 0x0FE000F0, .BASE, .A32, {}}, - {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00300090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00200090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00300090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T32 MLA: high=11111011 0000 Rn low=Ra Rd 0000 Rm - {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RD_T32, .RN_T32, .RM_T32, .RA_T32}, 0xFB000000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MLA, {.GPR, .GPR, .GPR, .GPR}, {.RD_T32, .RN_T32, .RM_T32, .RA_T32}, 0xFB000000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .MLS = { - {.MLS, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {}}, + {.MLS, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {}, {}}, // T32 MLS: high=11111011 0000 Rn low=Ra Rd 0001 Rm - {.MLS, {.GPR, .GPR, .GPR, .GPR}, {.RD_T32, .RN_T32, .RM_T32, .RA_T32}, 0xFB000010, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MLS, {.GPR, .GPR, .GPR, .GPR}, {.RD_T32, .RN_T32, .RM_T32, .RA_T32}, 0xFB000010, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UMULL = { - {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {}}, - {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00900090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00900090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T32 UMULL: high=11111011 1010 Rn low=RdLo RdHi 0000 Rm - {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBA00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UMULL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBA00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UMLAL = { - {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00A00090, 0x0FE000F0, .BASE, .A32, {}}, - {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00B00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00A00090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00B00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T32 UMLAL: high=11111011 1110 Rn low=RdLo RdHi 0000 Rm - {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBE00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBE00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SMULL = { - {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00C00090, 0x0FE000F0, .BASE, .A32, {}}, - {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00D00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00C00090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00D00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T32 SMULL: high=11111011 1000 Rn low=RdLo RdHi 0000 Rm - {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFB800000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SMULL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFB800000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SMLAL = { - {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00E00090, 0x0FE000F0, .BASE, .A32, {}}, - {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}}, + {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00E00090, 0x0FE000F0, .BASE, .A32, {}, {}}, + {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {}}, // T32 SMLAL: high=11111011 1100 Rn low=RdLo RdHi 0000 Rm - {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBC00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SMLAL, {.GPR, .GPR, .GPR, .GPR}, {.RT_T32, .RD_T32, .RN_T32, .RM_T32}, 0xFBC00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // (MLA/MLS/UMULL/UMLAL/SMULL/SMLAL declared earlier in MUL block region.) .UMAAL = { - {.UMAAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {}}, + {.UMAAL, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {}, {}}, }, // ARMv5TE halfword multiply (SMLAxy / SMULxy / SMLAWy / SMULWy / SMLALxy) // Encoding: cond 00010 op0 op1 Rd Rn Rs 1 y x 0 Rm // op0/op1 distinguishes family. x/y selects top/bottom halfword of Rm/Rs. - .SMLABB = { {.SMLABB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLABT = { {.SMLABT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLATB = { {.SMLATB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000A0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLATT = { {.SMLATT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000E0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLAWB = { {.SMLAWB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x01200080, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLAWT = { {.SMLAWT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x012000C0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMULBB = { {.SMULBB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x01600080, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMULBT = { {.SMULBT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000C0, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMULTB = { {.SMULTB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMULTT = { {.SMULTT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMULWB = { {.SMULWB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x012000A0, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMULWT = { {.SMULWT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x012000E0, 0x0FF0F0F0, .V5TE, .A32, {}} }, - .SMLALBB = { {.SMLALBB, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x01400080, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLALBT = { {.SMLALBT, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000C0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLALTB = { {.SMLALTB, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {}} }, - .SMLALTT = { {.SMLALTT, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {}} }, + .SMLABB = { {.SMLABB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLABT = { {.SMLABT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLATB = { {.SMLATB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000A0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLATT = { {.SMLATT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x010000E0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLAWB = { {.SMLAWB, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x01200080, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLAWT = { {.SMLAWT, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x012000C0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMULBB = { {.SMULBB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x01600080, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMULBT = { {.SMULBT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000C0, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMULTB = { {.SMULTB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMULTT = { {.SMULTT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMULWB = { {.SMULWB, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x012000A0, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMULWT = { {.SMULWT, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x012000E0, 0x0FF0F0F0, .V5TE, .A32, {}, {}} }, + .SMLALBB = { {.SMLALBB, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x01400080, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLALBT = { {.SMLALBT, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000C0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLALTB = { {.SMLALTB, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, + .SMLALTT = { {.SMLALTT, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {}, {}} }, // ARMv6: dual multiply - .SMUAD = { {.SMUAD, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F010, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMUADX = { {.SMUADX, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F030, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMUSD = { {.SMUSD, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F050, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMUSDX = { {.SMUSDX, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F070, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMLAD = { {.SMLAD, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000010, 0x0FF000F0, .V6, .A32, {}} }, - .SMLADX = { {.SMLADX, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000030, 0x0FF000F0, .V6, .A32, {}} }, - .SMLSD = { {.SMLSD, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000050, 0x0FF000F0, .V6, .A32, {}} }, - .SMLSDX = { {.SMLSDX, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000070, 0x0FF000F0, .V6, .A32, {}} }, - .SMLALD = { {.SMLALD, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400010, 0x0FF000F0, .V6, .A32, {}} }, - .SMLALDX = { {.SMLALDX, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400030, 0x0FF000F0, .V6, .A32, {}} }, - .SMLSLD = { {.SMLSLD, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400050, 0x0FF000F0, .V6, .A32, {}} }, - .SMLSLDX = { {.SMLSLDX, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400070, 0x0FF000F0, .V6, .A32, {}} }, + .SMUAD = { {.SMUAD, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F010, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMUADX = { {.SMUADX, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F030, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMUSD = { {.SMUSD, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F050, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMUSDX = { {.SMUSDX, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0700F070, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMLAD = { {.SMLAD, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000010, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLADX = { {.SMLADX, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000030, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLSD = { {.SMLSD, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000050, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLSDX = { {.SMLSDX, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07000070, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLALD = { {.SMLALD, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400010, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLALDX = { {.SMLALDX, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400030, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLSLD = { {.SMLSLD, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400050, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMLSLDX = { {.SMLSLDX, {.GPR, .GPR, .GPR, .GPR}, {.RDLO_A32, .RDHI_A32, .RM_A32, .RS_A32}, 0x07400070, 0x0FF000F0, .V6, .A32, {}, {}} }, // Most-significant-word multiply (ARMv6) - .SMMUL = { {.SMMUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0750F010, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMMULR = { {.SMMULR, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0750F030, 0x0FF0F0F0, .V6, .A32, {}} }, - .SMMLA = { {.SMMLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07500010, 0x0FF000F0, .V6, .A32, {}} }, - .SMMLAR = { {.SMMLAR, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07500030, 0x0FF000F0, .V6, .A32, {}} }, - .SMMLS = { {.SMMLS, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x075000D0, 0x0FF000F0, .V6, .A32, {}} }, - .SMMLSR = { {.SMMLSR, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x075000F0, 0x0FF000F0, .V6, .A32, {}} }, + .SMMUL = { {.SMMUL, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0750F010, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMMULR = { {.SMMULR, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0750F030, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .SMMLA = { {.SMMLA, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07500010, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMMLAR = { {.SMMLAR, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07500030, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMMLS = { {.SMMLS, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x075000D0, 0x0FF000F0, .V6, .A32, {}, {}} }, + .SMMLSR = { {.SMMLSR, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x075000F0, 0x0FF000F0, .V6, .A32, {}, {}} }, // ARMv7-A optional / ARMv7-R/M: integer division .SDIV = { - {.SDIV, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0710F010, 0x0FF0F0F0, .DIV, .A32, {}}, + {.SDIV, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0710F010, 0x0FF0F0F0, .DIV, .A32, {}, {}}, // T32 SDIV: high=11111011 1001 Rn low=1111 Rd 1111 Rm - {.SDIV, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB90F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true, cond_in_28=false}}, + {.SDIV, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB90F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UDIV = { - {.UDIV, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0730F010, 0x0FF0F0F0, .DIV, .A32, {}}, + {.UDIV, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0730F010, 0x0FF0F0F0, .DIV, .A32, {}, {}}, // T32 UDIV: high=11111011 1011 Rn low=1111 Rd 1111 Rm - {.UDIV, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFBB0F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true, cond_in_28=false}}, + {.UDIV, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFBB0F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ========================================================================= @@ -419,24 +419,24 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // ARMv5TE saturating arithmetic .QADD = { - {.QADD, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}}, + {.QADD, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}, {}}, // T32 QADD: high=11111010 1000 Rn low=1111 Rd 1000 Rm - {.QADD, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QADD, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QSUB = { - {.QSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01200050, 0x0FF000F0, .V5TE, .A32, {}}, + {.QSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01200050, 0x0FF000F0, .V5TE, .A32, {}, {}}, // T32 QSUB: bits 5:4 = 10 - {.QSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QDADD = { - {.QDADD, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01400050, 0x0FF000F0, .V5TE, .A32, {}}, + {.QDADD, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01400050, 0x0FF000F0, .V5TE, .A32, {}, {}}, // T32 QDADD: bits 5:4 = 01 - {.QDADD, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QDADD, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QDSUB = { - {.QDSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {}}, + {.QDSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RN_A32, .NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {}, {}}, // T32 QDSUB: bits 5:4 = 11 - {.QDSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QDSUB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RM_T32, .RN_T32, .NONE}, 0xFA80F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 signed parallel arithmetic (8-bit and 16-bit lanes) @@ -445,191 +445,191 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 0001 ADD16 0011 ASX 0101 SAX 0111 SUB16 // 1001 ADD8 1111 SUB8 .SADD16 = { - {.SADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F10, 0x0FF00FF0, .V6, .A32, {}}, + {.SADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F10, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SADD16: high=11111010 1001 Rn low=1111 Rd 0000 Rm - {.SADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SASX = { - {.SASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F30, 0x0FF00FF0, .V6, .A32, {}}, + {.SASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F30, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SASX: 0xFAA0F000 - {.SASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SSAX = { - {.SSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F50, 0x0FF00FF0, .V6, .A32, {}}, + {.SSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F50, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SSAX: 0xFAE0F000 - {.SSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SSUB16 = { - {.SSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F70, 0x0FF00FF0, .V6, .A32, {}}, + {.SSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F70, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SSUB16: 0xFAD0F000 - {.SSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SADD8 = { - {.SADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F90, 0x0FF00FF0, .V6, .A32, {}}, + {.SADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100F90, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SADD8: 0xFA80F000 - {.SADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SSUB8 = { - {.SSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100FF0, 0x0FF00FF0, .V6, .A32, {}}, + {.SSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06100FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SSUB8: 0xFAC0F000 - {.SSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 saturating parallel arithmetic (op family 0110 0010) // Q* (signed saturating): T32 bits 6:4 = 001 .QADD16 = { - {.QADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F10, 0x0FF00FF0, .V6, .A32, {}}, - {.QADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F10, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QASX = { - {.QASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F30, 0x0FF00FF0, .V6, .A32, {}}, - {.QASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QSAX = { - {.QSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F50, 0x0FF00FF0, .V6, .A32, {}}, - {.QSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F50, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QSUB16 = { - {.QSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F70, 0x0FF00FF0, .V6, .A32, {}}, - {.QSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F70, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QADD8 = { - {.QADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F90, 0x0FF00FF0, .V6, .A32, {}}, - {.QADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200F90, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .QSUB8 = { - {.QSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.QSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.QSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06200FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.QSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 signed halving (T32 bits 6:4 = 010) .SHADD16 = { - {.SHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F10, 0x0FF00FF0, .V6, .A32, {}}, - {.SHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F10, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SHASX = { - {.SHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F30, 0x0FF00FF0, .V6, .A32, {}}, - {.SHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SHSAX = { - {.SHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F50, 0x0FF00FF0, .V6, .A32, {}}, - {.SHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F50, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SHSUB16 = { - {.SHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F70, 0x0FF00FF0, .V6, .A32, {}}, - {.SHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F70, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SHADD8 = { - {.SHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F90, 0x0FF00FF0, .V6, .A32, {}}, - {.SHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300F90, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SHSUB8 = { - {.SHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.SHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06300FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.SHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 unsigned parallel arithmetic (op family 0110 0101) .UADD16 = { - {.UADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F10, 0x0FF00FF0, .V6, .A32, {}}, + {.UADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F10, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 UADD16: high=11111010 1001 Rn low=1111 Rd 0100 Rm - {.UADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UASX = { - {.UASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F30, 0x0FF00FF0, .V6, .A32, {}}, - {.UASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USAX = { - {.USAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F50, 0x0FF00FF0, .V6, .A32, {}}, - {.USAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.USAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F50, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.USAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USUB16 = { - {.USUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F70, 0x0FF00FF0, .V6, .A32, {}}, - {.USUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.USUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F70, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.USUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UADD8 = { - {.UADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F90, 0x0FF00FF0, .V6, .A32, {}}, - {.UADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500F90, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USUB8 = { - {.USUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.USUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.USUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06500FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.USUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 unsigned saturating (T32 bits 6:4 = 101) .UQADD16 = { - {.UQADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F10, 0x0FF00FF0, .V6, .A32, {}}, - {.UQADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F10, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UQASX = { - {.UQASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F30, 0x0FF00FF0, .V6, .A32, {}}, - {.UQASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UQSAX = { - {.UQSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F50, 0x0FF00FF0, .V6, .A32, {}}, - {.UQSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F50, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UQSUB16 = { - {.UQSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F70, 0x0FF00FF0, .V6, .A32, {}}, - {.UQSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F70, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UQADD8 = { - {.UQADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F90, 0x0FF00FF0, .V6, .A32, {}}, - {.UQADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600F90, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UQSUB8 = { - {.UQSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.UQSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UQSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06600FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UQSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 unsigned halving (T32 bits 6:4 = 110) .UHADD16 = { - {.UHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F10, 0x0FF00FF0, .V6, .A32, {}}, - {.UHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F10, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHADD16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA90F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UHASX = { - {.UHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F30, 0x0FF00FF0, .V6, .A32, {}}, - {.UHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHASX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAA0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UHSAX = { - {.UHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F50, 0x0FF00FF0, .V6, .A32, {}}, - {.UHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F50, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHSAX, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAE0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UHSUB16 = { - {.UHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F70, 0x0FF00FF0, .V6, .A32, {}}, - {.UHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F70, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHSUB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAD0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UHADD8 = { - {.UHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F90, 0x0FF00FF0, .V6, .A32, {}}, - {.UHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700F90, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHADD8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA80F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UHSUB8 = { - {.UHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700FF0, 0x0FF00FF0, .V6, .A32, {}}, - {.UHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06700FF0, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.UHSUB8, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFAC0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 saturate to width .SSAT = { - {.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00010, 0x0FE00030, .V6, .A32, {}}, + {.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00010, 0x0FE00030, .V6, .A32, {}, {}}, // T32 SSAT: high=11110 0 1 1000 0 Rn low=0 imm3 Rd imm2 0 sat_imm - {.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SSAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USAT = { - {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}}, - {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {}}, + {.USAT, {.GPR, .IMM4_SAT, .GPR_SHIFTED, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SSAT16 = { - {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {}}, + {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {}, {}}, // T32 SSAT16: high=11110 0 1 1001 0 Rn low=0 000 Rd 0000 sat_imm - {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SSAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .USAT16 = { - {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}}, - {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD, .SAT_IMM5, .RM_A32, .NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {}}, + {.USAT16, {.GPR, .IMM4_SAT, .GPR, .NONE}, {.RD_T32, .SAT_IMM5_T32, .RN_T32, .NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv6 USAD8 / USADA8 - .USAD8 = { {.USAD8, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {}} }, - .USADA8 = { {.USADA8, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {}} }, + .USAD8 = { {.USAD8, {.GPR, .GPR, .GPR, .NONE}, {.RN_A32, .RM_A32, .RS_A32, .NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {}, {}} }, + .USADA8 = { {.USADA8, {.GPR, .GPR, .GPR, .GPR}, {.RN_A32, .RM_A32, .RS_A32, .RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {}, {}} }, // ========================================================================= // §4 -- Extends + bit-field + REV + CLZ + RBIT + SEL + PKHBT/TB @@ -638,130 +638,130 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // PKHBT / PKHTB (pack halfword) // PKHBT: cond 0110 1000 Rn Rd shift_imm 001 Rm // PKHTB: cond 0110 1000 Rn Rd shift_imm 101 Rm - .PKHBT = { {.PKHBT, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800010, 0x0FF00070, .V6, .A32, {}} }, - .PKHTB = { {.PKHTB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800050, 0x0FF00070, .V6, .A32, {}} }, + .PKHBT = { {.PKHBT, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800010, 0x0FF00070, .V6, .A32, {}, {}} }, + .PKHTB = { {.PKHTB, {.GPR, .GPR, .GPR_SHIFTED, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800050, 0x0FF00070, .V6, .A32, {}, {}} }, // Sign-extend / zero-extend (with optional rotation of Rm by 0/8/16/24) // Encoding: cond 0110 1xx0 1111 Rd rotate 0 0 0111 Rm -- variant 1 (no Rn) // cond 0110 1xx0 Rn Rd rotate 0 0 0111 Rm -- variant 2 (with Rn = SXTAB/etc.) .SXTB = { - {.SXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06AF0070, 0x0FFF0070, .V6, .A32, {}}, + {.SXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06AF0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T16 SXTB: 1011 0010 01 Rm Rd - {.SXTB, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.SXTB, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 SXTB (with rotate): high=11111010 0100 1111 low=1111 Rd 1 0 rot Rm - {.SXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA4FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA4FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SXTB16 = { - {.SXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x068F0070, 0x0FFF0070, .V6, .A32, {}}, + {.SXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x068F0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T32 SXTB16 - {.SXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA2FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA2FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SXTH = { - {.SXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0070, 0x0FFF0070, .V6, .A32, {}}, + {.SXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T16 SXTH: 1011 0010 00 Rm Rd - {.SXTH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B200, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.SXTH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B200, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 SXTH: 0xFA0FF080 - {.SXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA0FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA0FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTB = { - {.UXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06EF0070, 0x0FFF0070, .V6, .A32, {}}, + {.UXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06EF0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T16 UXTB: 1011 0010 11 Rm Rd - {.UXTB, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B2C0, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.UXTB, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B2C0, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 UXTB: 0xFA5FF080 - {.UXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA5FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTB, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA5FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTB16 = { - {.UXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06CF0070, 0x0FFF0070, .V6, .A32, {}}, + {.UXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06CF0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T32 UXTB16 - {.UXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA3FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTB16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA3FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTH = { - {.UXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0070, 0x0FFF0070, .V6, .A32, {}}, + {.UXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0070, 0x0FFF0070, .V6, .A32, {}, {}}, // T16 UXTH: 1011 0010 10 Rm Rd - {.UXTH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B280, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.UXTH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000B280, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 UXTH: 0xFA1FF080 - {.UXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA1FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA1FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SXTAB = { - {.SXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06A00070, 0x0FF00070, .V6, .A32, {}}, + {.SXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06A00070, 0x0FF00070, .V6, .A32, {}, {}}, // T32 SXTAB: high=11111010 0100 Rn low=1111 Rd 1 0 rot Rm - {.SXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SXTAB16 = { - {.SXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800070, 0x0FF00070, .V6, .A32, {}}, - {.SXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800070, 0x0FF00070, .V6, .A32, {}, {}}, + {.SXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SXTAH = { - {.SXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06B00070, 0x0FF00070, .V6, .A32, {}}, - {.SXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06B00070, 0x0FF00070, .V6, .A32, {}, {}}, + {.SXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTAB = { - {.UXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06E00070, 0x0FF00070, .V6, .A32, {}}, - {.UXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA50F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06E00070, 0x0FF00070, .V6, .A32, {}, {}}, + {.UXTAB, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA50F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTAB16 = { - {.UXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06C00070, 0x0FF00070, .V6, .A32, {}}, - {.UXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA30F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06C00070, 0x0FF00070, .V6, .A32, {}, {}}, + {.UXTAB16, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA30F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UXTAH = { - {.UXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06F00070, 0x0FF00070, .V6, .A32, {}}, - {.UXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA10F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06F00070, 0x0FF00070, .V6, .A32, {}, {}}, + {.UXTAH, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA10F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Byte-reverse / count leading zeros / select / reverse bits .REV = { - {.REV, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0F30, 0x0FFF0FF0, .V6, .A32, {}}, + {.REV, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0F30, 0x0FFF0FF0, .V6, .A32, {}, {}}, // T16 REV: 1011 1010 00 Rm Rd - {.REV, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BA00, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.REV, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BA00, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 REV: high=11111010 1001 Rm low=1111 Rd 1000 Rm - {.REV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.REV, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .REV16 = { - {.REV16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0FB0, 0x0FFF0FF0, .V6, .A32, {}}, + {.REV16, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06BF0FB0, 0x0FFF0FF0, .V6, .A32, {}, {}}, // T16 REV16: 1011 1010 01 Rm Rd - {.REV16, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BA40, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.REV16, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BA40, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 REV16: bits 5:4 = 01 - {.REV16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.REV16, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .REVSH = { - {.REVSH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0FB0, 0x0FFF0FF0, .V6, .A32, {}}, + {.REVSH, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0FB0, 0x0FFF0FF0, .V6, .A32, {}, {}}, // T16 REVSH: 1011 1010 11 Rm Rd - {.REVSH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BAC0, 0x0000FFC0, .V6, .T32, {cond_in_28=false}}, + {.REVSH, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x0000BAC0, 0x0000FFC0, .V6, .T32, {cond_in_28=false}, {}}, // T32 REVSH: bits 5:4 = 11 - {.REVSH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.REVSH, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .RBIT = { - {.RBIT, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0F30, 0x0FFF0FF0, .V6T2, .A32, {}}, + {.RBIT, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x06FF0F30, 0x0FFF0FF0, .V6T2, .A32, {}, {}}, // T32 RBIT: bits 5:4 = 10 - {.RBIT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.RBIT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFA90F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CLZ = { - {.CLZ, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x016F0F10, 0x0FFF0FF0, .V5T, .A32, {}}, + {.CLZ, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x016F0F10, 0x0FFF0FF0, .V5T, .A32, {}, {}}, // T32 CLZ: high=11111010 1011 Rm low=1111 Rd 1000 Rm - {.CLZ, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFAB0F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.CLZ, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xFAB0F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, - .SEL = { {.SEL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800FB0, 0x0FF00FF0, .V6, .A32, {}} }, + .SEL = { {.SEL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x06800FB0, 0x0FF00FF0, .V6, .A32, {}, {}} }, // Bit field operations (ARMv6T2) .BFC = { - {.BFC, {.GPR, .IMM5, .IMM5_W, .NONE}, {.RD, .BFI_LSB, .BFI_MSB, .NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {}}, + {.BFC, {.GPR, .IMM5, .IMM5_W, .NONE}, {.RD, .BFI_LSB, .BFI_MSB, .NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {}, {}}, // T32 BFC: high=11110 0 1 1011 0 1111 low=0 imm3 Rd imm2 0 msb - {.BFC, {.GPR, .IMM5, .IMM5_W, .NONE}, {.RD_T32, .BFI_LSB_T32, .BFI_MSB, .NONE}, 0xF36F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.BFC, {.GPR, .IMM5, .IMM5_W, .NONE}, {.RD_T32, .BFI_LSB_T32, .BFI_MSB, .NONE}, 0xF36F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .BFI = { - {.BFI, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}}, + {.BFI, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}, {}}, // T32 BFI: high=11110 0 1 1011 0 Rn low=0 imm3 Rd imm2 0 msb - {.BFI, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.BFI, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SBFX = { - {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}}, + {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {}}, // T32 SBFX - {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .UBFX = { - {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}}, + {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD, .RM_A32, .BFI_LSB, .BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {}}, // T32 UBFX - {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UBFX, {.GPR, .GPR, .IMM5, .IMM5_W}, {.RD_T32, .RN_T32, .BFI_LSB_T32, .BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ========================================================================= @@ -770,139 +770,139 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // B / BL: cond 101 L imm24 .B = { - {.B, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}}, + {.B, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {}}, // T16 Format 16 B: 1101 cond imm8 - {.B, {.REL8, .COND, .NONE, .NONE}, {.BRANCH_8_T16, .NONE, .NONE, .NONE}, 0x0000D000, 0x0000F000, .THUMB, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}}, + {.B, {.REL8, .COND, .NONE, .NONE}, {.BRANCH_8_T16, .NONE, .NONE, .NONE}, 0x0000D000, 0x0000F000, .THUMB, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}, {}}, // T16 Format 18 B unconditional: 11100 imm11 - {.B, {.REL11, .NONE, .NONE, .NONE}, {.BRANCH_11_T16, .NONE, .NONE, .NONE}, 0x0000E000, 0x0000F800, .THUMB, .T32, {branch=true, writes_pc=true, cond_in_28=false}}, + {.B, {.REL11, .NONE, .NONE, .NONE}, {.BRANCH_11_T16, .NONE, .NONE, .NONE}, 0x0000E000, 0x0000F800, .THUMB, .T32, {branch=true, writes_pc=true, cond_in_28=false}, {}}, // T32 B: high=11110 S cond imm6 low=10 J1 0 J2 imm11 - {.B, {.REL20, .COND, .NONE, .NONE}, {.BRANCH_20_T32, .NONE, .NONE, .NONE}, 0xF0008000, 0xF800D000, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, thumb32=true, cond_in_28=false}}, + {.B, {.REL20, .COND, .NONE, .NONE}, {.BRANCH_20_T32, .NONE, .NONE, .NONE}, 0xF0008000, 0xF800D000, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, thumb32=true, cond_in_28=false}, {}}, // T32 B unconditional: high=11110 S imm10 low=10 J1 1 J2 imm11 - {.B, {.REL24_T32, .NONE, .NONE, .NONE}, {.BRANCH_24_T32, .NONE, .NONE, .NONE}, 0xF0009000, 0xF800D000, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}}, + {.B, {.REL24_T32, .NONE, .NONE, .NONE}, {.BRANCH_24_T32, .NONE, .NONE, .NONE}, 0xF0009000, 0xF800D000, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}, {}}, }, .BL = { - {.BL, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}}, + {.BL, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {}}, // Thumb-1 / Thumb-2 BL (4 bytes): high=11110 S imm10 low=11 J1 1 J2 imm11 - {.BL, {.REL24_T32, .NONE, .NONE, .NONE}, {.BRANCH_24_T32, .NONE, .NONE, .NONE}, 0xF000D000, 0xF800D000, .THUMB, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}}, + {.BL, {.REL24_T32, .NONE, .NONE, .NONE}, {.BRANCH_24_T32, .NONE, .NONE, .NONE}, 0xF000D000, 0xF800D000, .THUMB, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}, {}}, }, // BX / BLX (register form) -- ARMv4T+ for BX, ARMv5T+ for BLX_reg .BX = { - {.BX, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF10, 0x0FFFFFF0, .BASE, .A32, {branch=true, writes_pc=true}}, + {.BX, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF10, 0x0FFFFFF0, .BASE, .A32, {branch=true, writes_pc=true}, {}}, // T16 Format 5 BX: 010001 11 0 Rm 000 - {.BX, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004700, 0x0000FF87, .THUMB, .T32, {branch=true, writes_pc=true, cond_in_28=false}}, + {.BX, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004700, 0x0000FF87, .THUMB, .T32, {branch=true, writes_pc=true, cond_in_28=false}, {}}, }, .BLX = { // BLX register: cond 0001 0010 1111 1111 1111 0011 Rm - {.BLX, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF30, 0x0FFFFFF0, .V5T, .A32, {branch=true, writes_pc=true}}, + {.BLX, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF30, 0x0FFFFFF0, .V5T, .A32, {branch=true, writes_pc=true}, {}}, // BLX immediate (unconditional class): 1111 101 H imm24 -- H=bit24 toggles ARM/Thumb - {.BLX, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true, cond_in_28=false}}, + {.BLX, {.REL24, .NONE, .NONE, .NONE}, {.BRANCH_24, .NONE, .NONE, .NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true, cond_in_28=false}, {}}, // T16 Format 5 BLX reg: 010001 11 1 Rm 000 - {.BLX, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004780, 0x0000FF87, .V5T, .T32, {branch=true, writes_pc=true, cond_in_28=false}}, + {.BLX, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004780, 0x0000FF87, .V5T, .T32, {branch=true, writes_pc=true, cond_in_28=false}, {}}, }, - .BXJ = { {.BXJ, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF20, 0x0FFFFFF0, .V5TEJ, .A32, {branch=true, writes_pc=true, deprecated=true}} }, + .BXJ = { {.BXJ, {.GPR, .NONE, .NONE, .NONE}, {.RM_A32, .NONE, .NONE, .NONE}, 0x012FFF20, 0x0FFFFFF0, .V5TEJ, .A32, {branch=true, writes_pc=true, deprecated=true}, {}} }, // SVC (was SWI): cond 1111 imm24 .SVC = { - {.SVC, {.IMM, .NONE, .NONE, .NONE}, {.A32_IMM24, .NONE, .NONE, .NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {}}, + {.SVC, {.IMM, .NONE, .NONE, .NONE}, {.A32_IMM24, .NONE, .NONE, .NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {}, {}}, // T16 Format 17 SVC: 11011111 imm8 - {.SVC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000DF00, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}}, + {.SVC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000DF00, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, }, // BKPT (unconditional class but uses cond=NV reserved encoding traditionally): // cond 0001 0010 imm12 0111 imm4 (cond=AL only) .BKPT = { - {.BKPT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1200070, 0xFFF000F0, .V5T, .A32, {cond_in_28=false}}, + {.BKPT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1200070, 0xFFF000F0, .V5T, .A32, {cond_in_28=false}, {}}, // T16 BKPT: 1011 1110 imm8 - {.BKPT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BE00, 0x0000FF00, .V5T, .T32, {cond_in_28=false}}, + {.BKPT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BE00, 0x0000FF00, .V5T, .T32, {cond_in_28=false}, {}}, }, // HVC: 0001 0100 imm12 0111 imm4 - .HVC = { {.HVC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1400070, 0xFFF000F0, .V7VE, .A32, {cond_in_28=false}} }, + .HVC = { {.HVC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1400070, 0xFFF000F0, .V7VE, .A32, {cond_in_28=false}, {}} }, // SMC: cond 0001 0110 0000 0000 0000 0111 imm4 - .SMC = { {.SMC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01600070, 0x0FFFFFF0, .V7, .A32, {}} }, + .SMC = { {.SMC, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01600070, 0x0FFFFFF0, .V7, .A32, {}, {}} }, // UDF: 1111 0111 1111 imm12 1111 imm4 (permanently undefined) .UDF = { - {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {cond_in_28=false}}, + {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {cond_in_28=false}, {}}, // T16 UDF: 1101 1110 imm8 - {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}}, + {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 UDF: high=11110 0 1111 1111 imm4 low=10 1 0 imm12 - {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF7F0A000, 0xFFF0F000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.UDF, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF7F0A000, 0xFFF0F000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // HLT (ARMv8 AArch32): 0001 0000 imm12 0111 imm4 - .HLT = { {.HLT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {cond_in_28=false}} }, + .HLT = { {.HLT, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {cond_in_28=false}, {}} }, // MSR / MRS (status reg access) .MRS = { - {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}}, + {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {}}, // T32 MRS: high=11110011 1110 1111 low=10 0 0 Rd 0000 0000 - {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .MSR = { // MSR APSR_, #imm12_mod (immediate form) - {.MSR, {.PSR_FIELD, .IMM_MOD, .NONE, .NONE}, {.PSR_FIELD_MASK, .A32_IMM_MOD, .NONE, .NONE}, 0x0320F000, 0x0FB0F000, .BASE, .A32, {}}, + {.MSR, {.PSR_FIELD, .IMM_MOD, .NONE, .NONE}, {.PSR_FIELD_MASK, .A32_IMM_MOD, .NONE, .NONE}, 0x0320F000, 0x0FB0F000, .BASE, .A32, {}, {}}, // MSR APSR_, Rn (register form) - {.MSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.PSR_FIELD_MASK, .RM_A32, .NONE, .NONE}, 0x0120F000, 0x0FB0FFF0, .BASE, .A32, {}}, + {.MSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.PSR_FIELD_MASK, .RM_A32, .NONE, .NONE}, 0x0120F000, 0x0FB0FFF0, .BASE, .A32, {}, {}}, // T32 MSR: high=11110011 1000 Rn low=10 0 0 mask 0000 0000 - {.MSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.PSR_FIELD_MASK, .RN_T32, .NONE, .NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.MSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.PSR_FIELD_MASK, .RN_T32, .NONE, .NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // CPS (change processor state, ARMv6): 1111 0001 0000 imod M iflags mode_field - .CPS = { {.CPS, {.IMM_IFLAGS, .NONE, .NONE, .NONE}, {.CPS_IFLAGS, .NONE, .NONE, .NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {cond_in_28=false}} }, + .CPS = { {.CPS, {.IMM_IFLAGS, .NONE, .NONE, .NONE}, {.CPS_IFLAGS, .NONE, .NONE, .NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {cond_in_28=false}, {}} }, // SETEND (deprecated in ARMv8): 1111 0001 0000 0001 0000 000E 0000 0000 - .SETEND = { {.SETEND, {.IMM_ENDIAN, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {cond_in_28=false, deprecated=true}} }, + .SETEND = { {.SETEND, {.IMM_ENDIAN, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {cond_in_28=false, deprecated=true}, {}} }, // SETPAN (ARMv8.1): A32 = 1111 0001 0001 0000 0000 0000 imm1 0000 0000 → bit 9 = imm // T16: 1011 0110 0001 0 imm1 000 → bit 3 = imm .SETPAN = { - {.SETPAN, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xF1100000, 0xFFFFFDFF, .V8, .A32, {cond_in_28=false}}, - {.SETPAN, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0000B610, 0x0000FFF7, .V8, .T32, {cond_in_28=false}}, + {.SETPAN, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0xF1100000, 0xFFFFFDFF, .V8, .A32, {cond_in_28=false}, {}}, + {.SETPAN, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0000B610, 0x0000FFF7, .V8, .T32, {cond_in_28=false}, {}}, }, // ---- Hint instructions (cond 0011 0010 0000 1111 0000 0000 imm8 OR encoded form) .NOP = { - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {}}, + {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {}, {}}, // T16 NOP: 1011 1111 0000 0000 - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}}, + {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}, {}}, // T32 NOP: high=11110011 1010 1111 low=10000000 hint - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8000, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8000, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .YIELD = { - {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F001, 0x0FFFFFFF, .V6K, .A32, {}}, - {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF10, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}}, - {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8001, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F001, 0x0FFFFFFF, .V6K, .A32, {}, {}}, + {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF10, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}, {}}, + {.YIELD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8001, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .WFE = { - {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F002, 0x0FFFFFFF, .V6K, .A32, {}}, - {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF20, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}}, - {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8002, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F002, 0x0FFFFFFF, .V6K, .A32, {}, {}}, + {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF20, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}, {}}, + {.WFE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8002, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .WFI = { - {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F003, 0x0FFFFFFF, .V6K, .A32, {}}, - {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF30, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}}, - {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8003, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F003, 0x0FFFFFFF, .V6K, .A32, {}, {}}, + {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF30, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}, {}}, + {.WFI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8003, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SEV = { - {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F004, 0x0FFFFFFF, .V6K, .A32, {}}, - {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF40, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}}, - {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8004, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F004, 0x0FFFFFFF, .V6K, .A32, {}, {}}, + {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0000BF40, 0x0000FFFF, .V6T2, .T32, {cond_in_28=false}, {}}, + {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8004, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, - .SEVL = { {.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}} }, - .DBG = { {.DBG, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}} }, - .HINT = { {.HINT, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}} }, + .SEVL = { {.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}, {}} }, + .DBG = { {.DBG, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {}} }, + .HINT = { {.HINT, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {}} }, // Memory barriers (ARMv7): 1111 0101 0111 1111 1111 0000 type imm4 .DMB = { - {.DMB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF050, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}}, + {.DMB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF050, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}, {}}, // T32 DMB: F3BF 8F50 + type - {.DMB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F50, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}}, + {.DMB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F50, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .DSB = { - {.DSB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF040, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}}, - {.DSB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F40, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}}, + {.DSB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF040, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}, {}}, + {.DSB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F40, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ISB = { - {.ISB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF060, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}}, - {.ISB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F60, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}}, + {.ISB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF57FF060, 0xFFFFFFF0, .V7, .A32, {cond_in_28=false}, {}}, + {.ISB, {.IMM_BARRIER, .NONE, .NONE, .NONE}, {.BARRIER_TYPE, .NONE, .NONE, .NONE}, 0xF3BF8F60, 0xFFFFFFF0, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ---- HINT-family barriers (ARMv8 FEAT_RAS / FEAT_SPE / FEAT_TRF / FEAT_CSV2) ---- @@ -911,58 +911,58 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // ESB (Error Synchronization Barrier, FEAT_RAS) -- HINT #16 .ESB = { - {.ESB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {}}, - {.ESB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8010, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}}, + {.ESB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {}, {}}, + {.ESB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8010, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // PSB CSYNC (Profiling Synchronization Barrier, FEAT_SPE) -- HINT #17 .PSB_CSYNC = { - {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {}}, - {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8011, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}}, + {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {}, {}}, + {.PSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8011, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // TSB CSYNC (Trace Synchronization Barrier, FEAT_TRF) -- HINT #18 .TSB_CSYNC = { - {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {}}, - {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8012, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}}, + {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {}, {}}, + {.TSB_CSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8012, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // CSDB (Consumption of Speculative Data Barrier, FEAT_CSV2) -- HINT #20 .CSDB = { - {.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {}}, - {.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8014, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}}, + {.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {}, {}}, + {.CSDB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8014, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // SB (Synchronization Barrier, FEAT_SB, ARMv8.5) -- dedicated barrier encoding // A32: 1111 0101 0111 1111 1111 0000 0111 0000 = 0xF57FF070 // T32: 1111 0011 1011 1111 1000 1111 0111 0000 = 0xF3BF8F70 .SB = { - {.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF57FF070, 0xFFFFFFFF, .V8, .A32, {cond_in_28=false}}, - {.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3BF8F70, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}}, + {.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF57FF070, 0xFFFFFFFF, .V8, .A32, {cond_in_28=false}, {}}, + {.SB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3BF8F70, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // CLREX (clear exclusive monitor, ARMv6K+) .CLREX = { - {.CLREX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF57FF01F, 0xFFFFFFFF, .V6K, .A32, {cond_in_28=false}}, + {.CLREX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF57FF01F, 0xFFFFFFFF, .V6K, .A32, {cond_in_28=false}, {}}, // T32 CLREX - {.CLREX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3BF8F2F, 0xFFFFFFFF, .V6K, .T32, {thumb32=true, cond_in_28=false}}, + {.CLREX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3BF8F2F, 0xFFFFFFFF, .V6K, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Preload data / instruction (PLD/PLDW/PLI) .PLD = { - {.PLD, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF5D0F000, 0xFFF0F000, .V5T, .A32, {cond_in_28=false}}, + {.PLD, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF5D0F000, 0xFFF0F000, .V5T, .A32, {cond_in_28=false}, {}}, // T32 PLD imm12: 0xF890F000 - {.PLD, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF890F000, 0xFFF0F000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.PLD, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF890F000, 0xFFF0F000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .PLDW = { - {.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {cond_in_28=false}}, + {.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {cond_in_28=false}, {}}, // T32 PLDW imm12: 0xF830F000 - {.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}}, + {.PLDW, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .PLI = { - {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {cond_in_28=false}}, + {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {cond_in_28=false}, {}}, // T32 PLI imm12: 0xF990F000 - {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}}, + {.PLI, {.MEM, .NONE, .NONE, .NONE}, {.MEM_IMM12_OFFSET, .NONE, .NONE, .NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ERET (exception return, ARMv7VE+) - .ERET = { {.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0160006E, 0x0FFFFFFF, .V7VE, .A32, {writes_pc=true}} }, + .ERET = { {.ERET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0160006E, 0x0FFFFFFF, .V7VE, .A32, {writes_pc=true}, {}} }, // ========================================================================= // §6 -- Load / Store (single + multiple) @@ -973,139 +973,139 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // We split into three variants per direction: imm-offset, pre-index, post-index. .LDR = { // LDR imm12 offset: P=1 W=0 - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}, {}}, // LDR imm12 pre-index: P=1 W=1 - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}, {}}, // LDR imm12 post-index: P=0 W=0 - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}, {}}, // LDR reg offset: cond 011 P U 0 W 1 Rn Rt shift_imm shift_type 0 Rm - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 6 LDR PC-relative: 01001 Rd imm8 (LDR Rd, [PC, #imm8 << 2]) - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_LITERAL, .NONE, .NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_LITERAL, .NONE, .NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 7 LDR reg-offset: 0101 100 Rm Rb Rd - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 9 LDR imm5: 01101 imm5 Rb Rd (offset = imm5 << 2) - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 11 LDR SP-relative: 10011 Rd imm8 (LDR Rd, [SP, #imm8 << 2]) - {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00009800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00009800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDR imm12 offset: high=11111000 1101 Rn low=Rt imm12 - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8D00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8D00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LDR reg offset: high=11111000 0101 Rn low=Rt 000000 imm2 Rm - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8500000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8500000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LDR literal: high=11111000 X101 1111 low=Rt imm12 (PC-relative) - {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_LITERAL, .NONE, .NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_LITERAL, .NONE, .NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STR = { - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}}, - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 7 STR reg-offset: 0101 000 Rm Rb Rd - {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 9 STR imm5: 01100 imm5 Rb Rd (offset = imm5 << 2) - {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 11 STR SP-relative: 10010 Rd imm8 (STR Rd, [SP, #imm8 << 2]) - {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.STR, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_HI, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 STR imm12: 0xF8C00000 - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8C00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8C00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 STR reg: 0xF8400000 base - {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STR, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDRB = { - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 7 LDRB reg-offset: 0101 110 Rm Rb Rd - {.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 9 LDRB imm5: 01111 imm5 Rb Rd - {.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDRB imm12 / reg - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8900000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8900000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LDRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STRB = { - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {}, {}}, // T16 Format 7 STRB reg-offset: 0101 010 Rm Rb Rd - {.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 9 STRB imm5: 01110 imm5 Rb Rd - {.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00007000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.STRB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00007000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 STRB imm12 / reg - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8800000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8000000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8800000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.STRB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8000000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // LDRH / STRH / LDRSB / LDRSH / LDRD / STRD: cond 000 P U I W L Rn Rt imm4H 1 op2 1 imm4L // where op2 = 01 (halfword), 10 (signed byte), 11 (signed half / doubleword) .LDRH = { // LDRH imm offset (P=1 W=0): cond 000 1 U 1 0 1 Rn Rt imm4H 1011 imm4L - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000B0, 0x0F7000F0, .BASE, .A32, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, // LDRH reg offset: cond 000 1 U 0 0 1 Rn Rt 0000 1011 Rm - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000B0, 0x0F700FF0, .BASE, .A32, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000B0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRH reg-offset: 0101 101 Rm Rb Rd - {.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005A00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005A00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 10 LDRH imm5: 10001 imm5 Rb Rd (offset = imm5 << 1) - {.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00008800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00008800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDRH imm12 / reg - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LDRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STRH = { - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000B0, 0x0F7000F0, .BASE, .A32, {}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000B0, 0x0F700FF0, .BASE, .A32, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000B0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000B0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 STRH reg-offset: 0101 001 Rm Rb Rd - {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005200, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005200, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 10 STRH imm5: 10000 imm5 Rb Rd - {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00008000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.STRH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x00008000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 STRH imm12 / reg - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8A00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8200000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF8A00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.STRH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF8200000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDRSB = { - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000D0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000D0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000D0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000D0, 0x0F700FF0, .BASE, .A32, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000D0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000D0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRSB reg-offset: 0101 011 Rm Rb Rd - {.LDRSB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.LDRSB, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDRSB imm12 / reg - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF9900000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF9900000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LDRSB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDRSH = { - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000F0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000F0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000F0, 0x0F7000F0, .BASE, .A32, {}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000F0, 0x0F700FF0, .BASE, .A32, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01D000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01F000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00D000F0, 0x0F7000F0, .BASE, .A32, {}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x019000F0, 0x0F700FF0, .BASE, .A32, {}, {}}, // T16 Format 7 LDRSH reg-offset: 0101 111 Rm Rb Rd - {.LDRSH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.LDRSH, {.GPR_LOW, .MEM, .NONE, .NONE}, {.RD_T16_LO, .MEM_REG_OFFSET, .NONE, .NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDRSH imm12 / reg - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF9B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, - {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xF9B00000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.LDRSH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .MEM_REG_OFFSET, .NONE, .NONE}, 0xF9300000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDRD = { // LDRD imm offset (ARMv5TE+): cond 000 P U 1 W 0 Rn Rt imm4H 1101 imm4L - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000D0, 0x0F7000F0, .V5TE, .A32, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000D0, 0x0F7000F0, .V5TE, .A32, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000D0, 0x0F7000F0, .V5TE, .A32, {}}, - {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000D0, 0x0F700FF0, .V5TE, .A32, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000D0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.LDRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000D0, 0x0F700FF0, .V5TE, .A32, {}, {}}, // T32 LDRD imm8: high=11101001 X101 Rn low=Rt Rt2 imm8 - {.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9500000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STRD = { - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000F0, 0x0F7000F0, .V5TE, .A32, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000F0, 0x0F7000F0, .V5TE, .A32, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000F0, 0x0F7000F0, .V5TE, .A32, {}}, - {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000F0, 0x0F700FF0, .V5TE, .A32, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x01C000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_PRE_INDEX, .NONE, .NONE}, 0x01E000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00C000F0, 0x0F7000F0, .V5TE, .A32, {}, {}}, + {.STRD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_REG_OFFSET, .NONE, .NONE}, 0x018000F0, 0x0F700FF0, .V5TE, .A32, {}, {}}, // T32 STRD imm8: high=11101001 X100 Rn low=Rt Rt2 imm8 - {.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STRD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE9400000, 0xFE500000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Load/Store multiple (LDM/STM family). cond 100 P U S W L Rn register_list @@ -1116,64 +1116,64 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // base register + register-list into Rn + register_list operand slots. .LDM = { // LDM IA (default) - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {}}, // LDMIA writeback (LDM Rn!, {reglist}): W=1 - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {}}, // LDMIB - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {}}, // LDMDA - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {}}, // LDMDB - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {}}, // T16 Format 15 LDMIA: 11001 Rb reg_list8 - {.LDM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LDM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LDMIA: high=11101000 1001 Rn low=PM 0 reg_list14 - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LDMDB: high=11101001 0001 Rn low=PM 0 reg_list14 - {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STM = { - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}}, - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_A32, .A32_REG_LIST, .NONE, .NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {}}, // T16 Format 15 STMIA: 11000 Rb reg_list8 - {.STM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.STM, {.GPR_LOW, .GPR_LIST, .NONE, .NONE}, {.RD_T16_HI, .A32_REG_LIST, .NONE, .NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 STMIA: 0xE8800000 - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 STMDB: 0xE9000000 - {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STM, {.GPR, .GPR_LIST, .NONE, .NONE}, {.RN_T32, .A32_REG_LIST, .NONE, .NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // PUSH / POP are conventional aliases for STMDB SP! / LDMIA SP! .PUSH = { - {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}}, + {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {}}, // T16 Format 14 PUSH: 1011010 R reg_list8 (R bit selects LR included) - {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 PUSH (STMDB SP!, reglist): 0xE92D0000 - {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0xE92D0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.PUSH, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0xE92D0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .POP = { - {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}}, + {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}, {}}, // T16 Format 14 POP: 1011110 R reg_list8 (R bit selects PC included) - {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x0000BC00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}}, + {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0x0000BC00, 0x0000FE00, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 POP (LDMIA SP!, reglist): 0xE8BD0000 - {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0xE8BD0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.POP, {.GPR_LIST, .NONE, .NONE, .NONE}, {.A32_REG_LIST, .NONE, .NONE, .NONE}, 0xE8BD0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // SWP / SWPB (deprecated since ARMv6) - .SWP = { {.SWP, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}} }, - .SWPB = { {.SWPB, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}} }, + .SWP = { {.SWP, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {}} }, + .SWPB = { {.SWPB, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {}} }, // RFE / SRS (return-from-exception / store return state) .RFE = { // 1111 100 P U 0 W 1 Rn 0000 1010 0000 0000 - {.RFE, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32, .NONE, .NONE, .NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {cond_in_28=false}}, + {.RFE, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32, .NONE, .NONE, .NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {cond_in_28=false}, {}}, }, .SRS = { // 1111 100 P U 1 W 0 1101 0000 0101 000 mode4 - {.SRS, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {cond_in_28=false}}, + {.SRS, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {cond_in_28=false}, {}}, }, // ========================================================================= @@ -1182,94 +1182,94 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // LDREX family (ARMv6K+, then ARMv7 added all widths) .LDREX = { - {.LDREX, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900F9F, 0x0FF00FFF, .V6K, .A32, {}}, + {.LDREX, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900F9F, 0x0FF00FFF, .V6K, .A32, {}, {}}, // T32 LDREX: high=11101000 0101 Rn low=Rt 1111 imm8 - {.LDREX, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8500F00, 0xFFF00F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDREX, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8500F00, 0xFFF00F00, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STREX = { - {.STREX, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {}}, + {.STREX, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {}, {}}, // T32 STREX: high=11101000 0100 Rn low=Rt Rd imm8 - {.STREX, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8400000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STREX, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8400000, 0xFFF00000, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDREXB = { - {.LDREXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00F9F, 0x0FF00FFF, .V6K, .A32, {}}, + {.LDREXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00F9F, 0x0FF00FFF, .V6K, .A32, {}, {}}, // T32 LDREXB: high=11101000 1101 Rn low=Rt 1111 0100 1111 - {.LDREXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8D00F4F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDREXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8D00F4F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STREXB = { - {.STREXB, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01C00F90, 0x0FF00FF0, .V6K, .A32, {}}, + {.STREXB, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01C00F90, 0x0FF00FF0, .V6K, .A32, {}, {}}, // T32 STREXB: high=11101000 1100 Rn low=Rt 1111 0100 Rd - {.STREXB, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8C00F40, 0xFFF00FF0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STREXB, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8C00F40, 0xFFF00FF0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDREXH = { - {.LDREXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00F9F, 0x0FF00FFF, .V6K, .A32, {}}, - {.LDREXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8D00F5F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDREXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00F9F, 0x0FF00FFF, .V6K, .A32, {}, {}}, + {.LDREXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_T32, .RN_T32, .NONE, .NONE}, 0xE8D00F5F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STREXH = { - {.STREXH, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01E00F90, 0x0FF00FF0, .V6K, .A32, {}}, - {.STREXH, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8C00F50, 0xFFF00FF0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STREXH, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01E00F90, 0x0FF00FF0, .V6K, .A32, {}, {}}, + {.STREXH, {.GPR, .GPR, .MEM, .NONE}, {.RD_T32, .RT_T32, .RN_T32, .NONE}, 0xE8C00F50, 0xFFF00FF0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LDREXD = { - {.LDREXD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01B00F9F, 0x0FF00FFF, .V6K, .A32, {}}, + {.LDREXD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01B00F9F, 0x0FF00FFF, .V6K, .A32, {}, {}}, // T32 LDREXD: high=11101000 1101 Rn low=Rt Rt2 0111 1111 - {.LDREXD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE8D0007F, 0xFFF000FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LDREXD, {.GPR, .GPR, .MEM, .NONE}, {.RT_T32, .RT2_T32, .RN_T32, .NONE}, 0xE8D0007F, 0xFFF000FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .STREXD = { - {.STREXD, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01A00F90, 0x0FF00FF0, .V6K, .A32, {}}, + {.STREXD, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01A00F90, 0x0FF00FF0, .V6K, .A32, {}, {}}, // T32 STREXD: high=11101000 1100 Rn low=Rt Rt2 0111 Rd - {.STREXD, {.GPR, .GPR, .GPR, .MEM}, {.RD_T32, .RT_T32, .RT2_T32, .RN_T32}, 0xE8C00070, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.STREXD, {.GPR, .GPR, .GPR, .MEM}, {.RD_T32, .RT_T32, .RT2_T32, .RN_T32}, 0xE8C00070, 0xFFF000F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ARMv8 acquire/release (LDA/STL family, exclusive too) - .LDA = { {.LDA, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {}} }, + .LDA = { {.LDA, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, // STL/STLB/STLH: per ARMv8 ARM, Rt is at bits 3:0 (NOT 15:12); bits 15:12 are // 0xF fixed. Use RM_A32 enc for Rt to place it correctly. - .STL = { {.STL, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {}} }, - .LDAB = { {.LDAB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00C9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLB = { {.STLB, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x01C0FC90, 0x0FF0FFF0, .V8, .A32, {}} }, - .LDAH = { {.LDAH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00C9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLH = { {.STLH, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x01E0FC90, 0x0FF0FFF0, .V8, .A32, {}} }, - .LDAEX = { {.LDAEX, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900E9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLEX = { {.STLEX, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {}} }, - .LDAEXB = { {.LDAEXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00E9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLEXB = { {.STLEXB, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01C00E90, 0x0FF00FF0, .V8, .A32, {}} }, - .LDAEXH = { {.LDAEXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00E9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLEXH = { {.STLEXH, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01E00E90, 0x0FF00FF0, .V8, .A32, {}} }, - .LDAEXD = { {.LDAEXD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01B00E9F, 0x0FF00FFF, .V8, .A32, {}} }, - .STLEXD = { {.STLEXD, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {}} }, + .STL = { {.STL, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {}, {}} }, + .LDAB = { {.LDAB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00C9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLB = { {.STLB, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x01C0FC90, 0x0FF0FFF0, .V8, .A32, {}, {}} }, + .LDAH = { {.LDAH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00C9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLH = { {.STLH, {.GPR, .MEM, .NONE, .NONE}, {.RM_A32, .RN_A32, .NONE, .NONE}, 0x01E0FC90, 0x0FF0FFF0, .V8, .A32, {}, {}} }, + .LDAEX = { {.LDAEX, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01900E9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLEX = { {.STLEX, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {}, {}} }, + .LDAEXB = { {.LDAEXB, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01D00E9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLEXB = { {.STLEXB, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01C00E90, 0x0FF00FF0, .V8, .A32, {}, {}} }, + .LDAEXH = { {.LDAEXH, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01F00E9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLEXH = { {.STLEXH, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01E00E90, 0x0FF00FF0, .V8, .A32, {}, {}} }, + .LDAEXD = { {.LDAEXD, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .RN_A32, .NONE, .NONE}, 0x01B00E9F, 0x0FF00FFF, .V8, .A32, {}, {}} }, + .STLEXD = { {.STLEXD, {.GPR, .GPR, .MEM, .NONE}, {.RD, .RT_A32, .RN_A32, .NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {}, {}} }, // ========================================================================= // §8 -- Coprocessor + CRC32 + Crypto // ========================================================================= // CDP / CDP2: cond 1110 opc1 CRn CRd cp_num opc2 0 CRm - .CDP = { {.CDP, {.COPROC_NUM, .IMM_COPROC_OP, .COPROC_REG, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .COPROC_CRN_FIELD, .COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}} }, - .CDP2 = { {.CDP2, {.COPROC_NUM, .IMM_COPROC_OP, .COPROC_REG, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .COPROC_CRN_FIELD, .COPROC_CRM_FIELD}, 0xFE000000, 0xFF000010, .V5T, .A32, {cond_in_28=false}} }, + .CDP = { {.CDP, {.COPROC_NUM, .IMM_COPROC_OP, .COPROC_REG, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .COPROC_CRN_FIELD, .COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}, {}} }, + .CDP2 = { {.CDP2, {.COPROC_NUM, .IMM_COPROC_OP, .COPROC_REG, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .COPROC_CRN_FIELD, .COPROC_CRM_FIELD}, 0xFE000000, 0xFF000010, .V5T, .A32, {cond_in_28=false}, {}} }, // MCR / MCR2 / MRC / MRC2: cond 1110 opc1 L CRn Rt cp_num opc2 1 CRm - .MCR = { {.MCR, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {}} }, - .MCR2 = { {.MCR2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {cond_in_28=false}} }, - .MRC = { {.MRC, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {}} }, - .MRC2 = { {.MRC2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {cond_in_28=false}} }, + .MCR = { {.MCR, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {}, {}} }, + .MCR2 = { {.MCR2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {cond_in_28=false}, {}} }, + .MRC = { {.MRC, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {}, {}} }, + .MRC2 = { {.MRC2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .COPROC_REG}, {.COPROC_NUM_FIELD, .COPROC_OPC1_FIELD, .RT_A32, .COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {cond_in_28=false}, {}} }, // MCRR / MCRR2 / MRRC / MRRC2: cond 1100 010 0/1 Rt2 Rt cp_num opc CRm - .MCRR = { {.MCRR, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}} }, - .MCRR2 = { {.MCRR2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {cond_in_28=false}} }, - .MRRC = { {.MRRC, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}} }, - .MRRC2 = { {.MRRC2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {cond_in_28=false}} }, + .MCRR = { {.MCRR, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}, {}} }, + .MCRR2 = { {.MCRR2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {cond_in_28=false}, {}} }, + .MRRC = { {.MRRC, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}, {}} }, + .MRRC2 = { {.MRRC2, {.COPROC_NUM, .IMM_COPROC_OP, .GPR, .GPR}, {.COPROC_NUM_FIELD, .COPROC_OPC_MCRR, .RT_A32, .RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {cond_in_28=false}, {}} }, // LDC / STC: cond 110 P U N W L Rn CRd cp_num imm8 - .LDC = { {.LDC, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0x0C100000, 0x0F100000, .BASE, .A32, {}} }, - .LDC2 = { {.LDC2, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0xFC100000, 0xFF100000, .V5T, .A32, {cond_in_28=false}} }, - .STC = { {.STC, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0x0C000000, 0x0F100000, .BASE, .A32, {}} }, - .STC2 = { {.STC2, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0xFC000000, 0xFF100000, .V5T, .A32, {cond_in_28=false}} }, + .LDC = { {.LDC, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0x0C100000, 0x0F100000, .BASE, .A32, {}, {}} }, + .LDC2 = { {.LDC2, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0xFC100000, 0xFF100000, .V5T, .A32, {cond_in_28=false}, {}} }, + .STC = { {.STC, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0x0C000000, 0x0F100000, .BASE, .A32, {}, {}} }, + .STC2 = { {.STC2, {.COPROC_NUM, .COPROC_REG, .MEM, .NONE}, {.COPROC_NUM_FIELD, .COPROC_CRN_FIELD, .MEM_IMM8_OFFSET, .NONE}, 0xFC000000, 0xFF100000, .V5T, .A32, {cond_in_28=false}, {}} }, // ARMv8 CRC32 family // cond 0001 0 sz 0 Rn Rd 0000 0 0 1 0 0 Rm sz=00 byte / 01 half / 10 word // bit 9 selects CRC32 (0) vs CRC32C (1). - .CRC32B = { {.CRC32B, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}} }, - .CRC32H = { {.CRC32H, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200040, 0x0FF00FF0, .CRC32, .A32, {}} }, - .CRC32W = { {.CRC32W, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400040, 0x0FF00FF0, .CRC32, .A32, {}} }, - .CRC32CB = { {.CRC32CB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}} }, - .CRC32CH = { {.CRC32CH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200240, 0x0FF00FF0, .CRC32, .A32, {}} }, - .CRC32CW = { {.CRC32CW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400240, 0x0FF00FF0, .CRC32, .A32, {}} }, + .CRC32B = { {.CRC32B, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, + .CRC32H = { {.CRC32H, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200040, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, + .CRC32W = { {.CRC32W, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400040, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, + .CRC32CB = { {.CRC32CB, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, + .CRC32CH = { {.CRC32CH, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01200240, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, + .CRC32CW = { {.CRC32CW, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RN_A32, .RM_A32, .NONE}, 0x01400240, 0x0FF00FF0, .CRC32, .A32, {}, {}} }, // ========================================================================= @@ -1302,121 +1302,121 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // forms. The matcher dispatches on operand types. .VADD = { // VFP scalar - {.VADD, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VADD, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar (FEAT_FP16): cp=1001 - {.VADD, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VADD, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON F16 vector: 1111 0010 0 D 1 0 Vn Vd 1101 N Q M 0 Vm (bit 4 = 0 for VADD) - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // NEON integer (D-reg), size = 00/01/10/11 - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // NEON integer (Q-reg) - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // NEON F32 (D and Q) - {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer: Q-only, T32, 1110 1111 0 0 sz Qn Qd 1000 N 1 M 0 Qm - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000840, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000840, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, // MVE FP: 1110 1111 0 0 sz Qn Qd 1101 N 1 M 1 Qm - {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, // MVE scalar Rm (Qd, Qn, Rt): per LLVM vadd.i8 q1,q2,r3 = 0xEE05_2F43 -> base 0xEE010F40 - {.VADD, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADD, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, }, .VSUB = { // VFP scalar - {.VSUB, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VSUB, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VSUB, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VSUB, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON F16 (bit 4 = 0 for VSUB; bit 21 = 1 selects sub) - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // NEON integer (D-reg) - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300800, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // NEON integer (Q-reg) - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // NEON F32 (D and Q) - {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer / FP / scalar - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000840, 0xFF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000840, 0xFF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, + {.VSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, // VSUB MVE scalar: per LLVM 0xEE05_3F43 -> base 0xEE011F40 - {.VSUB, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSUB, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, }, // (VMUL/VMLA/VMLS are declared further below with both VFP scalar and // NEON vector forms in a single block.) .VDIV = { - {.VDIV, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VDIV, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VDIV, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VDIV, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VDIV, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VDIV, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, }, .VNMUL = { - {.VNMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VNMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VNMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VNMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, }, .VNMLS = { - {.VNMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VNMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VNMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VNMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, }, .VNMLA = { - {.VNMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VNMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VNMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VNMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, }, // VFPv4 fused multiply-add .VFMA = { - {.VFMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}}, + {.VFMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}}, + {.VFMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VFMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VFMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON F32: 1111 0010 0 D 0 0 Vn Vd 1100 N Q M 1 Vm - {.VFMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VFMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE FP vector + scalar - {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, - {.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, - {.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, - {.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, - {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, + {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, + {.VFMA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, + {.VFMA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VFMA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VFMA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}}, }, .VFMS = { - {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}}, + {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}}, + {.VFMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VFMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON F32 (bit 21 = 1) - {.VFMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VFMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE FP vector - {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, - {.VFMS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, - {.VFMS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}}, + {.VFMS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, + {.VFMS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VFMS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VFNMS = { - {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFNMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {}}, + {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}}, + {.VFNMS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VFNMS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, }, .VFNMA = { - {.VFNMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {}}, - {.VFNMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}}, + {.VFNMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32, .NONE}}, + {.VFNMA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VFNMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900940, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VFNMA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E900940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, }, // ---- 2-operand unary FP (opc1=1011 op2=xxxx) ---- @@ -1424,27 +1424,27 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // opc2 (bits 19:16): 0000 VMOV, 0001 VNEG, 0010 VSQRT, etc. // (VABS / VNEG: VFP scalar + NEON forms declared together further below.) .VSQRT = { - {.VSQRT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VSQRT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VSQRT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VSQRT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar (cp=1001) - {.VSQRT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}}, + {.VSQRT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .NONE}}, }, // VMOV reg-reg (opc2=0000, op=0) .VMOV = { - {.VMOV, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VMOV, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VMOV, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VMOV, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // VMOV imm (opc1=1011 opc2=0000 op=0, imm in (19:16)+(3:0) split) - {.VMOV, {.SPR, .IMM8, .NONE, .NONE}, {.VD_S, .VFP_IMM8, .NONE, .NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}}, - {.VMOV, {.DPR, .IMM8, .NONE, .NONE}, {.VD_D, .VFP_IMM8, .NONE, .NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}}, + {.VMOV, {.SPR, .IMM8, .NONE, .NONE}, {.VD_S, .VFP_IMM8, .NONE, .NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F32, .NONE}}, + {.VMOV, {.DPR, .IMM8, .NONE, .NONE}, {.VD_D, .VFP_IMM8, .NONE, .NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64, .NONE}}, // VMOV GPR <-> S reg: cond 1110 000 op L Vn Rt 1010 N 0010000 - {.VMOV, {.SPR, .GPR, .NONE, .NONE}, {.VN_S, .RT_A32, .NONE, .NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}}, - {.VMOV, {.GPR, .SPR, .NONE, .NONE}, {.RT_A32, .VN_S, .NONE, .NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {}}, + {.VMOV, {.SPR, .GPR, .NONE, .NONE}, {.VN_S, .RT_A32, .NONE, .NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {}}, + {.VMOV, {.GPR, .SPR, .NONE, .NONE}, {.RT_A32, .VN_S, .NONE, .NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {}, {}}, // VMOV two GPRs <-> D reg (VMOV Rt, Rt2, Dm) - {.VMOV, {.GPR, .GPR, .DPR, .NONE}, {.RT_A32, .RT2_A32, .VM_D, .NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}}, - {.VMOV, {.DPR, .GPR, .GPR, .NONE}, {.VM_D, .RT_A32, .RT2_A32, .NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}}, + {.VMOV, {.GPR, .GPR, .DPR, .NONE}, {.RT_A32, .RT2_A32, .VM_D, .NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, + {.VMOV, {.DPR, .GPR, .GPR, .NONE}, {.VM_D, .RT_A32, .RT2_A32, .NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, // VMOV two GPRs <-> two consecutive S regs - {.VMOV, {.GPR, .GPR, .SPR, .SPR}, {.RT_A32, .RT2_A32, .VM_S, .NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}}, - {.VMOV, {.SPR, .SPR, .GPR, .GPR}, {.VM_S, .NONE, .RT_A32, .RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}}, + {.VMOV, {.GPR, .GPR, .SPR, .SPR}, {.RT_A32, .RT2_A32, .VM_S, .NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, + {.VMOV, {.SPR, .SPR, .GPR, .GPR}, {.VM_S, .NONE, .RT_A32, .RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {}}, // ---- VMOV NEON modified immediate ---- // 1111 0010 1 D 000 imm3 Vd cmode 0 Q op 1 imm4 (op=0 VMOV, op=1 VMVN) // cmode mappings (8 forms when op=0): @@ -1459,79 +1459,79 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 1110 .I8 → 0xF2800E10 // 1111 .F32 (special: high bit = 0) → 0xF2800F10 (limited to specific imm patterns) // 1110 op=1 + bit 5 set → .I64 → 0xF2800E30 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=0000 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=0010 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=0100 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=0110 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I16 cmode=1000 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I16 cmode=1010 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=1100 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=1101 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I8 cmode=1110 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .F32 cmode=1111 - {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I64 (op=0+bit5=1) + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0010 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0100 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0110 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1010 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1100 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=1101 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 cmode=1110 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 cmode=1111 + {.VMOV, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 (op=0+bit5=1) // Q forms (Q=1, bit 6 = 1) - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, // .I32 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, // .I16 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, // .I8 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, // .F32 Q - {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, // .I64 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // .I8 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // .F32 Q + {.VMOV, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 Q // ---- VMOV scalar to/from GPR (lane access) ---- // VMOV. Rt, Dn[idx]: cond 1110 U opc1 1 Vn Rt 1011 N opc2 1 0000 // VMOV. Dn[idx], Rt: cond 1110 0 opc1 0 Vn Rt 1011 N opc2 1 0000 // .8 / .16 / .32 selected by opc1+opc2 split bits in encoding. // 32-bit lane move (.32): - {.VMOV, {.GPR, .DPR_ELEM, .NONE, .NONE}, {.RT_A32, .VN_D, .NONE, .NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}}, - {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VN_D, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}}, + {.VMOV, {.GPR, .DPR_ELEM, .NONE, .NONE}, {.RT_A32, .VN_D, .NONE, .NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}}, + {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VN_D, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}}, // VMOV. Qd[i], Rt -- single lane Rt -> Qd[i] - {.VMOV, {.QPR_ELEM, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOV, {.QPR_ELEM, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, // VMOV. Rt, Qd[i] - {.VMOV, {.GPR, .QPR_ELEM, .NONE, .NONE}, {.RT_T32, .VD_Q, .NONE, .NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOV, {.GPR, .QPR_ELEM, .NONE, .NONE}, {.RT_T32, .VD_Q, .NONE, .NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, // VMOV Qd[2*i], Qd[2*i+1], Rt, Rt2 -- pair move - {.VMOV, {.QPR_ELEM, .QPR_ELEM, .GPR, .GPR}, {.VD_Q, .VD_Q, .RT_T32, .RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOV, {.QPR_ELEM, .QPR_ELEM, .GPR, .GPR}, {.VD_Q, .VD_Q, .RT_T32, .RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ---- VMVN NEON modified immediate (op=1 form) ---- // bit 5 = 1 distinguishes VMVN from VMOV .VMVN = { - {.VMVN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VMVN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}}, + {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}}, // VMVN immediate: 1111 0010 1 D 000 imm3 Vd cmode 0 Q 1 1 imm4 (op=1) - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I32 cmode=0000 - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, // .I16 cmode=1000 - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 cmode=0000 + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 cmode=1000 + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // Q forms - {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, - {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}}, + {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMVN, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NONE, .NONE, .NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // MVE VMVN Qd, Qm - {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMVN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // VCMP / VCMPE: cond 1110 1011 D 0100 Vd 101 sz E 1 M 0 Vm (E=1 raises invalid op on QNaN) .VCMP = { - {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}}, - {.VCMP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}}, + {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VCMP with zero: cond 1110 1011 D 0101 Vd 101 sz E 1 (0) 0 0000 - {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}}, - {.VCMP, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}}, + {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMP, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}}, - {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}}, + {.VCMP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, + {.VCMP, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16, .NONE}}, // MVE VCMP Qn, Qm -- writes VPR.P0. Per LLVM: // vcmp.i8 eq,q2,q3 -> 0xFE05_0F06 base 0xFE01_0F00 // vcmp.f32 eq,q2,q3 -> 0xEE35_0F06 base 0xEE31_0F00 - {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xFE010F00, 0xFE818FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xFE010F00, 0xFE818FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, + {.VCMP, {.QPR, .QPR, .NONE, .NONE}, {.VN_Q, .VM_Q, .NONE, .NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VCMPE = { - {.VCMPE, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}}, - {.VCMPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}}, - {.VCMPE, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}}, - {.VCMPE, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}}, + {.VCMPE, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64, .NONE}}, + {.VCMPE, {.SPR, .NONE, .NONE, .NONE}, {.VD_S, .NONE, .NONE, .NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VCMPE, {.DPR, .NONE, .NONE, .NONE}, {.VD_D, .NONE, .NONE, .NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64, .NONE}}, }, // VCVT family: int<->float and float<->float @@ -1540,164 +1540,164 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // F32<->half-prec: VCVTB/VCVTT .VCVT = { // VCVT.F64.F32 Dd, Sm (cond 1110 1011 D 0111 Vd 1010 11 M 0 Vm) sz=0 (output F32)... actually inverse: - {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .F32}}, // VCVT.F32.F64 Sd, Dm (sz=1 output F64; opc2=0111) - {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .F64}}, // VCVT.S32.F32 Sd, Sm (opc2=1101 op=1) - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32, .F32}}, // VCVT.U32.F32 Sd, Sm (opc2=1100 op=1) - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32, .F32}}, // VCVT.S32.F64 Sd, Dm - {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32, .F64}}, // VCVT.U32.F64 Sd, Dm - {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32, .F64}}, // VCVT.F32.S32 Sd, Sm (opc2=1000 op=1) - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .S32}}, // VCVT.F32.U32 Sd, Sm (opc2=1000 op=0) - {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .U32}}, // VCVT.F64.S32 Dd, Sm - {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .S32}}, // VCVT.F64.U32 Dd, Sm - {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVT, {.DPR, .SPR, .NONE, .NONE}, {.VD_D, .VM_S, .NONE, .NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .U32}}, // VCVT.BF16.F32 D, Q // vcvt.bf16.f32 d0, q1 = 0xF3B6_0642 -> base 0xF3B60600 - {.VCVT, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {cond_in_28=false}}, + {.VCVT, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {cond_in_28=false}, {.F16, .F32}}, // VCVT.S32.F32 Sd, Sd, #fbits -- to signed 32-bit fixed-point - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F32}}, // VCVT.U32.F32 Sd, Sd, #fbits - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16, .F32}}, // VCVT.F32.S32 Sd, Sd, #fbits -- from signed 32-bit fixed - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .S16}}, // VCVT.F32.U32 Sd, Sd, #fbits - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .U16}}, // VCVT.S16.F32 Sd, Sd, #fbits (sx=0 selects 16-bit fixed-point) - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16, .F32}}, // VCVT.F32.S16 Sd, Sd, #fbits - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32, .S16}}, // F64 variants (sz=1): change cp to 1011 (bit 8 = 1) - {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16, .F64}}, + {.VCVT, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64, .S16}}, // F16 variants (cp=1001, FEAT_FP16) - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}}, - {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16, .F16}}, + {.VCVT, {.SPR, .SPR, .IMM, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16, .S16}}, }, .VCVTB = { // VCVTB.F32.F16 / .F16.F32 - {.VCVTB, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVTB, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVTB, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .F16}}, + {.VCVTB, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16, .F32}}, }, .VCVTT = { - {.VCVTT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}}, - {.VCVTT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}}, + {.VCVTT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32, .F16}}, + {.VCVTT, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16, .F32}}, }, // ARMv8: VCVTA/N/P/M (rounding-mode FP-to-int) - cond=1111 (unconditional class) .VCVTA = { - {.VCVTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VCVTA, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VCVTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, + {.VCVTA, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, .VCVTN = { - {.VCVTN, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VCVTN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VCVTN, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, + {.VCVTN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, .VCVTP = { - {.VCVTP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VCVTP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VCVTP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, + {.VCVTP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, .VCVTM = { - {.VCVTM, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VCVTM, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VCVTM, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F32}}, + {.VCVTM, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.U32, .F64}}, }, // VMRS / VMSR (access FPSCR + friends as GPR) // VMRS: cond 1110 1111 0001 Rt 1010 0001 0000 (Rt=PC means transfer to APSR.NZCV) - .VMRS = { {.VMRS, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}} }, - .VMSR = { {.VMSR, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}} }, + .VMRS = { {.VMRS, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {}} }, + .VMSR = { {.VMSR, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {}} }, // VLDR / VSTR (single / double): cond 1101 U D 0 1 Rn Vd 101 sz imm8 .VLDR = { - {.VLDR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}}, - {.VLDR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}}, + {.VLDR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {}}, + {.VLDR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {}}, }, .VSTR = { - {.VSTR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}}, - {.VSTR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}}, + {.VSTR, {.SPR, .MEM, .NONE, .NONE}, {.VD_S, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {}}, + {.VSTR, {.DPR, .MEM, .NONE, .NONE}, {.VD_D, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {}}, }, // VLDM / VSTM (multiple S or D regs): cond 110 P U D W L Rn Vd 101 sz imm8 // IA = P=0 U=1 ; DB = P=1 U=0 ; W=1 writeback; L=1 load / 0 store. .VLDM = { - {.VLDM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}}, - {.VLDM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}}, + {.VLDM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {}}, + {.VLDM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {}}, }, .VSTM = { - {.VSTM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}}, - {.VSTM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}}, + {.VSTM, {.GPR, .SPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_S_LIST, .NONE, .NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {}}, + {.VSTM, {.GPR, .DPR_LIST, .NONE, .NONE}, {.RN_A32, .VFP_D_LIST, .NONE, .NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {}}, }, .VPUSH = { - {.VPUSH, {.SPR_LIST, .NONE, .NONE, .NONE}, {.VFP_S_LIST, .NONE, .NONE, .NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}}, - {.VPUSH, {.DPR_LIST, .NONE, .NONE, .NONE}, {.VFP_D_LIST, .NONE, .NONE, .NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}}, + {.VPUSH, {.SPR_LIST, .NONE, .NONE, .NONE}, {.VFP_S_LIST, .NONE, .NONE, .NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {}}, + {.VPUSH, {.DPR_LIST, .NONE, .NONE, .NONE}, {.VFP_D_LIST, .NONE, .NONE, .NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {}}, }, .VPOP = { - {.VPOP, {.SPR_LIST, .NONE, .NONE, .NONE}, {.VFP_S_LIST, .NONE, .NONE, .NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}}, - {.VPOP, {.DPR_LIST, .NONE, .NONE, .NONE}, {.VFP_D_LIST, .NONE, .NONE, .NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}}, + {.VPOP, {.SPR_LIST, .NONE, .NONE, .NONE}, {.VFP_S_LIST, .NONE, .NONE, .NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {}}, + {.VPOP, {.DPR_LIST, .NONE, .NONE, .NONE}, {.VFP_D_LIST, .NONE, .NONE, .NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {}}, }, // ARMv8 FP min/max NaN-aware (VMAXNM/VMINNM), VSEL, VRINT* .VMAXNM = { - {.VMAXNM, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {cond_in_28=false}}, - {.VMAXNM, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {cond_in_28=false}}, + {.VMAXNM, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMAXNM, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, }, .VMINNM = { - {.VMINNM, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {cond_in_28=false}}, - {.VMINNM, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {cond_in_28=false}}, + {.VMINNM, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMINNM, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, }, .VSEL = { // VSEL.F32/F64 Sd, Sn, Sm -- cond field at bits 21-20 + 7 - {.VSEL, {.SPR, .SPR, .SPR, .COND}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {cond_in_28=false}}, - {.VSEL, {.DPR, .DPR, .DPR, .COND}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {cond_in_28=false}}, + {.VSEL, {.SPR, .SPR, .SPR, .COND}, {.VD_S, .VN_S, .VM_S, .NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VSEL, {.DPR, .DPR, .DPR, .COND}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, }, .VRINTA = { - {.VRINTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VRINTA, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VRINTA, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRINTA, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, // MVE Q-form (FEAT_MVE_FP): per LLVM `vrinta.f32 q1, q3` -> 0xFFBA_0540 - {.VRINTA, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTA, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VRINTN = { - {.VRINTN, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VRINTN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VRINTN, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRINTN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, // MVE - {.VRINTN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA0440, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA0440, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VRINTP = { - {.VRINTP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VRINTP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VRINTP, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRINTP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, // MVE - {.VRINTP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA07C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA07C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VRINTM = { - {.VRINTM, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, - {.VRINTM, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}}, + {.VRINTM, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRINTM, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {cond_in_28=false}, {.F64, .NONE}}, // MVE - {.VRINTM, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA06C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTM, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA06C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VRINTR = { - {.VRINTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}}, - {.VRINTR, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}}, + {.VRINTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32, .NONE}}, + {.VRINTR, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64, .NONE}}, }, .VRINTZ = { - {.VRINTZ, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}}, - {.VRINTZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}}, + {.VRINTZ, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32, .NONE}}, + {.VRINTZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64, .NONE}}, // MVE - {.VRINTZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA05C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA05C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VRINTX = { - {.VRINTX, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}}, - {.VRINTX, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}}, + {.VRINTX, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32, .NONE}}, + {.VRINTX, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64, .NONE}}, // MVE - {.VRINTX, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA04C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VRINTX, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFBA04C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, // VJCVT (ARMv8.3): F64 -> S32 with JS-style rounding - .VJCVT = { {.VJCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}} }, + .VJCVT = { {.VJCVT, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {}} }, // ---- VFP F16 scalar arithmetic (FEAT_FP16) ---- // Uses coproc 9 (cp_num = 1001) instead of 10/11 used by F32/F64. @@ -1724,526 +1724,526 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // ---- VMUL (integer + F32) ---- .VMUL = { // VFP scalar - {.VMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VMUL, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON F16 - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D10, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100D50, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D10, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100D50, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // NEON integer (.I8/.I16/.I32) D form: 1111 0010 0 size Vn Vd 1001 N 0 M 1 Vm - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // NEON integer Q form - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // NEON polynomial (.P8): U=1 bit 24 - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.P8, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.P8, .NONE}}, // NEON F32 - {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer / FP / scalar - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, + {.VMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, // VMUL MVE scalar: per LLVM 0xEE05_3E63 -> base 0xEE011E60 - {.VMUL, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMUL, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, // Integer D-form .I16/.I32 - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // Integer Q-form .I16/.I32 (bit 24 = 1) - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // FP .F32 D-form / Q-form (F=1, size=10) - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VMLA / VMLS (integer + F32) ---- .VMLA = { - {.VMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VMLA, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON integer (multiply-accumulate) - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // NEON F32 - {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE VMLA Qda, Qn, Rm (scalar) - {.VMLA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // FP .F32 (F=1) - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VMLS = { - {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}}, - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}}, + {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64, .NONE}}, // VFP F16 scalar - {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}}, + {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16, .NONE}}, // NEON integer (op-bit at 24 distinguishes VMLA vs VMLS for U=1) - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200900, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // NEON F32 (bit 21 = 1 distinguishes FMLS from FMLA) - {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // FP .F32 - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VAND / VBIC / VORR / VORN / VEOR (bitwise, no size variants) ---- .VAND = { // VAND D: 1111 0010 0000 Vn Vd 0001 N 0 M 1 Vm (no size; always byte-wise) - {.VAND, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VAND, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, + {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VBIC = { // VBIC D: 1111 0010 0100 Vn Vd 0001 N 0 M 1 Vm - {.VBIC, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VBIC, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, + {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VORR = { - {.VORR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VORR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, + {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VORN = { - {.VORN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VORN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VORN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF300150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VORN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VORN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, + {.VORN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF300150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VEOR = { // U=1 distinguishes VEOR from VAND family - {.VEOR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VEOR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VEOR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VEOR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VEOR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, + {.VEOR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ---- VBSL / VBIT / VBIF (predicated bitwise select) ---- .VBSL = { - {.VBSL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VBSL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VBSL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VBSL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, }, .VBIT = { - {.VBIT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VBIT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VBIT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VBIT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, }, .VBIF = { - {.VBIF, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VBIF, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VBIF, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, + {.VBIF, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, }, // ---- VMAX / VMIN (integer + F32) ---- .VMAX = { // NEON integer signed (U=0) - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // NEON integer unsigned (U=1) - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // NEON F32 - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // NEON F16 (sz bit 20 = 1) - {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // MVE integer (VMAX.F32 doesn't exist in MVE; use VMAXNM.F32 instead) - {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000640, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMAX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000640, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMIN = { // bit 4 distinguishes MAX (0) vs MIN (1) within the 0x6_0 op family - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000650, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // F32 (bit 21 = 1 selects MIN) - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // NEON F16 (sz=1) - {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // MVE integer (VMIN.F32 doesn't exist; use VMINNM.F32) - {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000650, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMIN, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000650, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // ---- VCEQ / VCGT / VCGE (compare) ---- .VCEQ = { // NEON integer (op family 0x8_0) - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // NEON F32 - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // NEON F16 - {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VCEQ, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCEQ, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, // Integer: 0xF3B10100 base for .I8, opc=000 - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, // Float: 0xF3B90500 base (.F32, opc=010) - {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCEQ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCEQ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGT = { // signed: 0xF200_0300; unsigned: 0xF300_0300 - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // unsigned - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // F32 - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // F16 - {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCGE = { // signed: 0xF200_0310; unsigned: 0xF300_0310 - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // F32 - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // F16 - {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCGE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCGE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // ---- VQADD / VQSUB (saturating) ---- .VQADD = { // signed: F200_0010; unsigned: F300_0010 - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, // unsigned - {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000010, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000050, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000050, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000050, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQSUB = { - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2300210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000210, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000250, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000250, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000250, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // ---- VHADD / VHSUB / VRHADD ---- .VHADD = { - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000040, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000040, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VHSUB = { - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VHSUB, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000240, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VHSUB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000240, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VRHADD = { - {.VRHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000100, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VRHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000140, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VRHADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000100, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VRHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000140, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // MVE - {.VRHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000140, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRHADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000140, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // ---- VPADD (pairwise add, D-form only) ---- .VPADD = { // NEON integer (op 0xB10, bit 4 = 1) - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // F32 - {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VPADD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // (VPADD MVE form doesn't exist; MVE uses VADDV reduction instead) }, // ---- VPMAX / VPMIN (D-form only) ---- .VPMAX = { - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // F32 - {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VPMAX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // (VPMAX MVE form doesn't exist; MVE uses VMAXV reduction) }, .VPMIN = { - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, + {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VPMIN, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200F00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // (VPMIN MVE form doesn't exist; MVE uses VMINV reduction) }, // ---- VTST (test bits) ---- .VTST = { - {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTST, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200810, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTST, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200850, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // ---- VABD (absolute difference) ---- .VABD = { // signed - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // unsigned - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // F32 (bit 21=1 selects FP) - {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VABD, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VABD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // ---- VABA (accumulate absolute difference) ---- .VABA = { - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABA, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000710, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VABA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000750, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, // ---- VSHL register (variable shift) ---- .VSHL = { // signed: F200_0400; unsigned: F300_0400 - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2300400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2300440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2300400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2300440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, // unsigned shift by reg - {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000440, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000440, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // VSHR immediate (signed/unsigned, .I8/.I16/.I32/.I64) .VSHR = { - {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // unsigned - {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE imm form (imm6 at bits 21:16) - {.VSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}}, }, // VSRA imm .VSRA = { - {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, - {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE (imm6 at bits 21:16) - {.VSRA, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSRA, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}}, }, // VQSHL imm (saturating shift left) .VQSHL = { // register form (signed): F200_0410 - {.VQSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000410, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000410, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // unsigned: F300_0410 - {.VQSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000410, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000450, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000410, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000450, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // immediate form: F2800710 - {.VQSHL, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800710, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VQSHL, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VQSHL, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800710, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VQSHL, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE - {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // VRSHL (rounding shift left) .VRSHL = { - {.VRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000540, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000500, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000540, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000540, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000500, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000540, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // MVE - {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000540, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000540, 0xEF810F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // VRSHR (rounding shift right immediate) .VRSHR = { - {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, - {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VRSHR, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VRSHR, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // MVE - {.VRSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRSHR, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I32, .NONE}}, }, // VSLI / VSRI (shift left/right and insert) .VSLI = { - {.VSLI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSLI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VSLI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSLI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VSRI = { - {.VSRI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VSRI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VSRI, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VSRI, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VABS / VNEG / VMVN / VCNT / VCLZ / VCLS (NEON unary) ---- // (VABS/VNEG VFP scalar already declared; here we add NEON forms.) .VABS = { // VFP scalar (already declared near top of §9, here we extend the block) - {.VABS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VABS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // NEON integer: 1111 0011 1011 size 01 Vd 0011 0 Q M 0 Vm - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // NEON F32 (size=10, bit 10 = 1) - {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VABS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer + FP. Per LLVM: vabs.s8 q,q = FFB1_0340; vabs.f32 q,q = FFB9_0740 (bit 19 = 1 for FP). - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, + {.VABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VNEG = { - {.VNEG, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VNEG, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64, .NONE}}, // NEON integer (bit 7 = 1 distinguishes VNEG from VABS) - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // NEON F32 - {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VNEG, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE integer + FP. Per LLVM: vneg.s8 q,q = FFB1_03C0; vneg.f32 q,q = FFB9_07C0. - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, + {.VNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, // (VMVN declared earlier in VMOV neighbourhood with reg + immediate forms.) .VCNT = { // Byte-only: 1111 0011 1011 0000 size00 Vd 0101 0 Q M 0 Vm - {.VCNT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCNT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VCNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VCLZ = { - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCLZ, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VCLZ, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VCLS = { - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLS, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // ---- VREV16 / VREV32 / VREV64 (byte/half/word reverse within block) ---- .VREV64 = { - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV64, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV64, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VREV32 = { - {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV32, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV32, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, }, .VREV16 = { - {.VREV16, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VREV16, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VREV16, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VREV16, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, // ---- VEXT (vector extract) ---- .VEXT = { // 1111 0010 1011 Vn Vd imm4 N Q M 0 Vm - {.VEXT, {.DPR, .DPR, .DPR, .IMM4}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {cond_in_28=false}}, - {.VEXT, {.QPR, .QPR, .QPR, .IMM4}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {cond_in_28=false}}, + {.VEXT, {.DPR, .DPR, .DPR, .IMM4}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VEXT, {.QPR, .QPR, .QPR, .IMM4}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {cond_in_28=false}, {.SZ64, .NONE}}, }, // ---- VDUP (duplicate scalar/reg to vector) ---- @@ -2253,37 +2253,37 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // Variant: vector D[lane] form (1111 0011 1011 imm4 Vd 1100 0 Q M 0 Vm) // We list the common scalar/Rt form for V_8B/V_16B/V_4H/V_8H/V_2S/V_4S. // (encoder picks based on operand kinds) - {.VDUP, {.DPR, .GPR, .NONE, .NONE}, {.VD_D, .RT_A32, .NONE, .NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}}, - {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_A32, .NONE, .NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}}, + {.VDUP, {.DPR, .GPR, .NONE, .NONE}, {.VD_D, .RT_A32, .NONE, .NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, + {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_A32, .NONE, .NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, // VDUP from vector lane (.D form): 1111 0011 1011 imm4 Vd 1100 0 Q M 0 Vm - {.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}}, - {.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}}, + {.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, + {.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, // MVE VDUP Qd, Rt - {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, }, // ---- VTRN / VUZP / VZIP (interleave / deinterleave) ---- .VTRN = { - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTRN, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VTRN, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VUZP = { - {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VUZP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VUZP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VZIP = { - {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VZIP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VZIP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // ---- VTBL / VTBX (table lookup) ---- @@ -2291,46 +2291,46 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // len = 00,01,10,11 selects 1/2/3/4-vec table; op=0 TBL, 1 TBX .VTBL = { // 1-vec table - {.VTBL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, + {.VTBL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 2-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 3-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // 4-vec table - {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, + {.VTBL, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VTBX = { - {.VTBX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, - {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}}, + {.VTBX, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VTBX, {.DPR, .DPR_LIST, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, // ---- VRECPE / VRSQRTE (reciprocal estimates) ---- .VRECPE = { // Integer: 1111 0011 1011 1011 Vd 0100 0 Q M 0 Vm; FP: bit 8 = 1 - {.VRECPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRECPE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRECPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VRECPE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, // FP form - {.VRECPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRECPE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRECPE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRECPE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // (VRECPE MVE form doesn't exist in current MVE spec) }, .VRSQRTE = { - {.VRSQRTE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRSQRTE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRSQRTE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRSQRTE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRSQRTE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VRSQRTE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VRSQRTE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRSQRTE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // (VRSQRTE MVE form doesn't exist) }, // VRECPS / VRSQRTS (reciprocal step) .VRECPS = { - {.VRECPS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000F10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VRECPS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VRECPS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2000F10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRECPS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VRSQRTS = { - {.VRSQRTS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200F10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSQRTS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VRSQRTS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200F10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRSQRTS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // ---- VLD1 / VST1 (most-used load/store multiple structures) ---- @@ -2339,307 +2339,307 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // have distinct opcode bits; included as separate entries. .VLD1 = { // VLD1 multiple (1-reg list, type=0111, size=00/01/10/11, D form) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 multiple (2-reg list, type=1010) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 multiple (3-reg list, type=0110) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 multiple (4-reg list, type=0010) - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 single lane to all lanes (VLD1R): 1111 0100 1 D 10 Rn Vd 1100 size T a Rm // size 00 .8 / 01 .16 / 10 .32; T=0 single, T=1 pair - {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 single lane: 1111 0100 1 D 10 Rn Vd 0X00 size idx_align Rm (X = 8/16/32 size selector) - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .8 - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .16 - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .32 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 }, .VST1 = { // VST1 multiple (1-reg list) - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VST1 single lane: 1111 0100 1 D 00 Rn Vd 0X00 size idx_align Rm - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .8 - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .16 - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}}, // .32 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 }, // VLD2 / VST2 / VLD3 / VST3 / VLD4 / VST4 - similar pattern with different "type" bits .VLD2 = { - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VST2 = { - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD3 = { - {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VST3 = { - {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD4 = { - {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VST4 = { - {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, - {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VFP_D_LIST, .RN_A32, .NONE, .NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, // ---- VMULL / VMLAL / VMLSL (widening multiplies) ---- .VMULL = { // signed: 1111 0010 1U sz Vn Vd 1100 N 0 M 0 Vm - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // unsigned - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, // polynomial: U=0, op=10 - {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.P8, .NONE}}, // signed .S16/.S32 - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // unsigned .U16/.U32 (top byte 0xF3) - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, // VMLAL / VMLSL (widening multiply-accumulate) // VMLAL: signed F2800800 / unsigned F3800800; op=1000 (no minus); minus bit at 21 .VMLAL = { - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VMLSL = { // VMLSL: op=1010 (bit 9 = 1) - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, // ---- VQDMULH / VQRDMULH (saturating doubling multiply, high half) ---- // 1111 0010 0 D size Vn Vd 1011 N Q M 0 Vm (VQDMULH) // 1111 0011 0 D size Vn Vd 1011 N Q M 0 Vm (VQRDMULH) .VQDMULH = { - {.VQDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, .VQRDMULH = { - {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, + {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMULH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMULH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMULH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMULH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // ---- VQRDMLAH / VQRDMLSH (ARMv8.1 FEAT_RDM, rounding doubling MAC) ---- // VQRDMLAH: 1111 0011 0 D size Vn Vd 1011 N Q M 1 Vm (size = 01 .S16 or 10 .S32) // VQRDMLSH: 1111 0011 0 D size Vn Vd 1100 N Q M 1 Vm .VQRDMLAH = { - {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100B10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100B10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, .VQRDMLSH = { - {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // VQDMULL: 1111 0010 1 D size Vn Vd 1101 N 0 M 0 Vm .VQDMULL = { - {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // VQDMLAL / VQDMLSL (saturating doubling multiply-accumulate long) .VQDMLAL = { // signed: 1111 0010 1 D size Vn Vd 1001 N 0 M 0 Vm - {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, .VQDMLSL = { // signed: 1111 0010 1 D size Vn Vd 1011 N 0 M 0 Vm - {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // ---- VMOVL / VMOVN / VQMOVN / VQMOVUN (widening/narrowing moves) ---- .VMOVL = { // VMOVL.S Q, D : 1111 0010 1 D imm3 0 0 0 Vd 1010 0 0 M 1 Vm (imm3 = size) // We list signed/unsigned × 3 sizes (.S8/.S16/.S32 and .U variants) - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .S8 - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .S16 - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2A00A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .S32 - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3880A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .U8 - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3900A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .U16 - {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3A00A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}}, // .U32 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // .S8 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, // .S16 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF2A00A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // .S32 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3880A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, // .U8 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3900A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, // .U16 + {.VMOVL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3A00A10, 0xFFB80FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, // .U32 }, .VMOVN = { // VMOVN.I D, Q : 1111 0011 1 D 11 size 10 Vd 0010 0 0 M 0 Vm - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, // .I16 - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, // .I32 - {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, // .I64 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // .I16 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // .I32 + {.VMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I64, .NONE}}, // .I64 }, .VQMOVN = { // VQMOVN. (signed saturating narrowing move) // .S: 1111 0011 1 D 11 size 10 Vd 0010 1 0 M 0 Vm // .U: same with op bit 6 = 1 - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VQMOVN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}}, }, .VQMOVUN = { // VQMOVUN (signed input, unsigned saturating output): 1111 0011 1 D 11 size 10 Vd 0010 0 1 M 0 Vm (bit 6=1, bit 7=0) - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQMOVUN, {.DPR, .QPR, .NONE, .NONE}, {.VD_D, .VM_Q, .NONE, .NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, }, // ---- VSHLL / VSHRN / VRSHRN / VQSHRN / VQRSHRN ---- .VSHLL = { // VSHLL.S Q, D, #imm: 1111 0010 1 D imm6 Vd 1010 0 0 M 1 Vm // imm6 encodes sh + size: 001sss for sh<8, 01sss for sh<16, 1sss for sh<32 - {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, - {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, // U=1 + {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VSHLL, {.QPR, .DPR, .IMM, .NONE}, {.VD_Q, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // U=1 // VSHLL by max (#size) variant: 1111 0011 1 D 11 size 10 Vd 0011 0 0 M 0 Vm - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I8, .NONE}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VSHLL, {.QPR, .DPR, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VSHRN = { // 1111 0010 1 D imm6 Vd 1000 0 0 M 1 Vm - {.VSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VRSHRN = { // 1111 0010 1 D imm6 Vd 1000 0 1 M 1 Vm - {.VRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQSHRN = { // signed: 1111 0010 1 D imm6 Vd 1001 0 0 M 1 Vm; unsigned: U=1 - {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VQSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQRSHRN = { // 1111 0010 1 D imm6 Vd 1001 0 1 M 1 Vm - {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VQRSHRN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQSHRUN = { // signed input, unsigned saturating shift right narrow: // 1111 0011 1 D imm6 Vd 1000 0 0 M 1 Vm - {.VQSHRUN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQSHRUN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, .VQRSHRUN = { - {.VQRSHRUN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {cond_in_28=false}}, + {.VQRSHRUN, {.DPR, .QPR, .IMM, .NONE}, {.VD_D, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, }, // ---- VPADDL / VPADAL (pairwise add long / accumulate) ---- // 1111 0011 1 D 11 size 00 Vd 0010 op Q M 0 Vm (op=0 add long, op=1 accumulate) .VPADDL = { // .S: - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // Q form - {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // .U variants: bit 7 = 1 - {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VPADDL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VPADDL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, .VPADAL = { // op4=0110 instead of 0010 (bit 8=1) - {.VPADAL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VPADAL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VPADAL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VPADAL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, // unsigned - {.VPADAL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VPADAL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VPADAL, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VPADAL, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, // ---- VSWP (swap) ---- // 1111 0011 1 D 11 size 10 Vd 0000 0 Q M 0 Vm .VSWP = { - {.VSWP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VSWP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VSWP, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}}, + {.VSWP, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {}}, }, // ---- VACGE / VACGT (FP absolute compare) ---- .VACGE = { // 1111 0011 0 D 0 sz Vn Vd 1110 N Q M 1 Vm - {.VACGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VACGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VACGE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VACGE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VACGT = { // sz bit 21 = 1 - {.VACGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200E10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VACGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, + {.VACGT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200E10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VACGT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, // NEON crypto (ARMv8 FEAT_AES / FEAT_SHA1 / FEAT_SHA256) // AESE/AESD/AESMC/AESIMC: 1111 0011 1011 size 00 Vd 0011 op M 0 Vm (op=0 AESE, 1 AESD; bit 7 selects MC) - .AESE = { {.AESE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .AESD = { {.AESD, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .AESMC = { {.AESMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .AESIMC = { {.AESIMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}} }, + .AESE = { {.AESE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .AESD = { {.AESD, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .AESMC = { {.AESMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .AESIMC = { {.AESIMC, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, // SHA1 family - .SHA1H = { {.SHA1H, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA1SU1 = { {.SHA1SU1, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA256SU0 = { {.SHA256SU0, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA1C = { {.SHA1C, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA1P = { {.SHA1P, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA1M = { {.SHA1M, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA1SU0 = { {.SHA1SU0, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA256H = { {.SHA256H, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA256H2 = { {.SHA256H2, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, - .SHA256SU1 = { {.SHA256SU1, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}} }, + .SHA1H = { {.SHA1H, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA1SU1 = { {.SHA1SU1, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA256SU0 = { {.SHA256SU0, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA1C = { {.SHA1C, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA1P = { {.SHA1P, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA1M = { {.SHA1M, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA1SU0 = { {.SHA1SU0, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA256H = { {.SHA256H, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA256H2 = { {.SHA256H2, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, + .SHA256SU1 = { {.SHA256SU1, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {cond_in_28=false}, {}} }, // ========================================================================= // §11 -- T16 Thumb-1 + T32 Thumb-2 (Thumb-only mnemonics) @@ -2662,74 +2662,74 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 010000 op4 Rs Rd op4=0010 LSL, 0011 LSR, 0100 ASR, 0111 ROR .LSL = { // A32: MOV reg with LSL #imm (cond 00011010 0000 Rd imm5 000 Rm) - {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00000, 0x0FFF0070, .BASE, .A32, {}}, + {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00000, 0x0FFF0070, .BASE, .A32, {}, {}}, // A32: MOV reg with LSL Rs (RSR form) - {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {}}, + {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {}, {}}, // T16 Format 1: LSL imm - {.LSL, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LSL, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 4: LSL reg (Rd = Rd <<= Rs) - {.LSL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.LSL, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LSL imm (encoded as MOV with shift LSL): high=11101010 0100 1111 low=0 imm3 Rd imm2 00 Rm - {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LSL, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LSL reg: high=11111010 0000 Rn low=1111 Rd 0000 Rm - {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LSL, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .LSR = { - {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}}, - {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}}, + {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {}}, + {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}, {}}, // T16 Format 1: LSR imm - {.LSR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.LSR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 4: LSR reg - {.LSR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.LSR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 LSR imm (MOV with shift LSR): bits 5:4 = 01 - {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LSR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 LSR reg: 0xFA20F000 - {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.LSR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ASR = { - {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}}, - {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}}, + {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {}}, + {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}, {}}, // T16 Format 1: ASR imm - {.ASR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.ASR, {.GPR_LOW, .GPR_LOW, .IMM5, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, // T16 Format 4: ASR reg - {.ASR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.ASR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ASR imm: bits 5:4 = 10 - {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ASR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 ASR reg: 0xFA40F000 - {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ASR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .ROR = { - {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}}, - {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {}}, + {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD, .RM_A32, .A32_IMM_SHIFT, .NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}, {}}, + {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD, .RM_A32, .RS_A32, .NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {}, {}}, // T16 Format 4: ROR reg - {.ROR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.ROR, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, // T32 ROR imm: bits 5:4 = 11 - {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ROR, {.GPR, .GPR, .IMM5, .NONE}, {.RD_T32, .RM_T32, .NONE, .NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, // T32 ROR reg: 0xFA60F000 - {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}}, + {.ROR, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .RRX = { // RRX is ROR with imm=0 (cond 00011010 0000 Rd 00000110 Rm) - {.RRX, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}}, + {.RRX, {.GPR, .GPR, .NONE, .NONE}, {.RD, .RM_A32, .NONE, .NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}, {}}, }, // T16 Format 12: ADR (ADD Rd, PC, #imm8 << 2) .ADR = { // A32 ADR forms (ADD/SUB to PC); handled via ADD encoded with Rn=PC. // T16 Format 12 form (10100 Rd imm8): - {.ADR, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x0000A000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}}, + {.ADR, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_HI, .NONE, .NONE, .NONE}, 0x0000A000, 0x0000F800, .THUMB, .T32, {cond_in_28=false}, {}}, }, // T16 NEG Rd, Rm = RSB Rd, Rm, #0 (Format 4, op=1001) .NEG = { - {.NEG, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004240, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}}, + {.NEG, {.GPR_LOW, .GPR_LOW, .NONE, .NONE}, {.RD_T16_LO, .RM_T16_LO, .NONE, .NONE}, 0x00004240, 0x0000FFC0, .THUMB, .T32, {cond_in_28=false}, {}}, }, - .CBZ = { {.CBZ, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_LO, .BRANCH_CBZ, .NONE, .NONE}, 0x0000B100, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}} }, - .CBNZ = { {.CBNZ, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_LO, .BRANCH_CBZ, .NONE, .NONE}, 0x0000B900, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}} }, - .IT = { {.IT, {.COND, .IMM4, .NONE, .NONE}, {.NONE, .IT_MASK, .NONE, .NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {cond_in_28=false}} }, - .TBB = { {.TBB, {.GPR, .GPR, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xE8D0F000, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}} }, - .TBH = { {.TBH, {.GPR, .GPR, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xE8D0F010, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}} }, + .CBZ = { {.CBZ, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_LO, .BRANCH_CBZ, .NONE, .NONE}, 0x0000B100, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}, {}} }, + .CBNZ = { {.CBNZ, {.GPR_LOW, .REL8, .NONE, .NONE}, {.RD_T16_LO, .BRANCH_CBZ, .NONE, .NONE}, 0x0000B900, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, cond_in_28=false}, {}} }, + .IT = { {.IT, {.COND, .IMM4, .NONE, .NONE}, {.NONE, .IT_MASK, .NONE, .NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {cond_in_28=false}, {}} }, + .TBB = { {.TBB, {.GPR, .GPR, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xE8D0F000, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}, {}} }, + .TBH = { {.TBH, {.GPR, .GPR, .NONE, .NONE}, {.RN_T32, .RM_T32, .NONE, .NONE}, 0xE8D0F010, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true, cond_in_28=false}, {}} }, // ========================================================================= // §14 -- Extensions: Dot product / FCMA / FHM / BF16 @@ -2738,19 +2738,19 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // FEAT_DotProd (ARMv8.2-A): VSDOT/VUDOT (8-bit signed/unsigned dot product) .VSDOT = { // VSDOT.S8 D: 0xFC200D00 - {.VSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, - {.VSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, - {.VSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, - {.VSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, + {.VSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, // VUDOT (unsigned): bit 4 = 1 distinguishes from VSDOT (bit 4 = 0). // vudot.u8 d0,d1,d2 = 0xFC21_0D12 -> base 0xFC200D10 .VUDOT = { - {.VUDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, - {.VUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, + {.VUDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, // vudot.u8 d0,d1,d2[0] = 0xFE21_0D12 -> base 0xFE200D10 (bit 4 = 1 for U) - {.VUDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}}, - {.VUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}}, + {.VUDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, // FEAT_FCMA (ARMv8.3): VCMLA / VCADD (complex multiply-add + add) @@ -2758,36 +2758,36 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VCADD: rotation in bit 24 only (2 values: 90, 270 deg) .VCMLA = { // Mask 0xFC800F10 leaves bits 24:23 variable for rotation operand - {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {cond_in_28=false}}, - {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}}, - {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}}, - {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}}, - {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, }, .VCADD = { // Mask 0xFE800F10 leaves bit 24 variable for rotation operand (90 or 270) - {.VCADD, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {cond_in_28=false}}, - {.VCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {cond_in_28=false}}, + {.VCADD, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, }, // FEAT_FHM (ARMv8.2): FP16 fused multiply-add long .VFMAL = { - {.VFMAL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}}, - {.VFMAL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}}, + {.VFMAL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}, {}}, + {.VFMAL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}, {}}, }, .VFMSL = { - {.VFMSL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}}, - {.VFMSL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}}, + {.VFMSL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {cond_in_28=false}, {}}, + {.VFMSL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {cond_in_28=false}, {}}, }, // FEAT_BF16 (ARMv8.6): BFloat16 arithmetic and conversion .VDOT = { // VDOT.BF16 D, D, D - {.VDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {cond_in_28=false}}, - {.VDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, + {.VDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}}, + {.VDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}}, }, .VMMLA = { - {.VMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}}, + {.VMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {cond_in_28=false}, {.BF16, .NONE}}, }, // ========================================================================= @@ -2797,13 +2797,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VUMMLA Qd, Qn, Qm: 1111 1100 0 D 1 0 Vn Vd 1100 N 1 M 1 Vm (unsigned) // VUSMMLA Qd, Qn, Qm: 1111 1100 1 D 1 0 Vn Vd 1100 N 1 M 0 Vm (mixed) .VSMMLA = { - {.VSMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VSMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, .VUMMLA = { - {.VUMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VUMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, .VUSMMLA = { - {.VUSMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VUSMMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, // VSUDOT Qd, Qn, Qm[idx]: 1111 1110 1 D 00 Vn Vd 1101 N Q M 1 Vm // VUSDOT Qd, Qn, Qm: 1111 1100 0 D 10 Vn Vd 1101 N Q M 0 Vm @@ -2811,14 +2811,14 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vusdot.s8 d0,d1,d2 = 0xFCA1_0D02 -> base 0xFCA00D00 // vsudot.u8 q0,q1,d2[0] = 0xFE82_0D52 -> base 0xFE800D50 (lane only) .VSUDOT = { - {.VSUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VSUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VSUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {}}, + {.VSUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, .VUSDOT = { - {.VUSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VUSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, - {.VUSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}}, - {.VUSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}}, + {.VUSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VUSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VUSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VUSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, // ========================================================================= @@ -2848,21 +2848,21 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VQABS Qd, Qm: 1111 1111 1 D 11 size 00 Vd 0111 1 1 M 0 Vm // VQNEG Qd, Qm: 1111 1111 1 D 11 size 00 Vd 0111 1 1 M 1 Vm .VQABS = { - {.VQABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQABS, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQNEG = { - {.VQNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB007C0, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQNEG, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFFB007C0, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // VMOVX Sd, Sm (extract high F16 lane to bottom of Sd) -- ARMv8.2 FP16 // 1111 1110 1 D 11 0000 Vd 1010 01 M 0 Vm .VMOVX = { - {.VMOVX, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB00A40, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOVX, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB00A40, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, }, // VINS Sd, Sm (insert F16 from Sm into high half of Sd) // 1111 1110 1 D 11 0000 Vd 1010 11 M 0 Vm .VINS = { - {.VINS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB00AC0, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VINS, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0xFEB00AC0, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, }, // ---- MVE gather/scatter (vector offset addressing) ---------------------- @@ -2902,13 +2902,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vld3.8 {d1[], d2[], d3[]}, [r2] = 0xF4A2_1E0F -> base 0xF4A0_0E0F // vld4.8 {d1[], d2[], d3[], d4[]}, [r2] = 0xF4A2_1F0F -> base 0xF4A0_0F0F .VLD2R = { - {.VLD2R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}}, + {.VLD2R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD3R = { - {.VLD3R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}}, + {.VLD3R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD4R = { - {.VLD4R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}}, + {.VLD4R, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, }, // ========================================================================= @@ -2918,45 +2918,45 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // N=00 VLDx1, 01 VLDx2, 10 VLDx3, 11 VLDx4 (x = 1..4) // VLD1_LANE Dd[i], [Rn]: size=00 (.8) 0xF4A00000, size=01 (.16) 0xF4A00400, size=10 (.32) 0xF4A00800 .VLD1_LANE = { - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, + {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VLD2_LANE = { - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VLD3_LANE = { - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VLD4_LANE = { - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // VST1/2/3/4 single-lane: bit 21 = 0 (store, not load) .VST1_LANE = { - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}}, + {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST2_LANE = { - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST3_LANE = { - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST4_LANE = { - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}}, + {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // ========================================================================= @@ -2970,29 +2970,29 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // TTAT : A=1 T=1 -> 0xE840F0C0 // mask 0xFFF0FFC0 keeps Rn and Rd variable, fixes A and T bits per mnemonic. .TT = { - {.TT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F000, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}}, + {.TT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F000, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .TTT = { - {.TTT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F040, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}}, + {.TTT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F040, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .TTA = { - {.TTA, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F080, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}}, + {.TTA, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F080, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .TTAT = { - {.TTAT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F0C0, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}}, + {.TTAT, {.GPR, .GPR, .NONE, .NONE}, {.RD_T32, .RN_T32, .NONE, .NONE}, 0xE840F0C0, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // SG: Secure Gateway -- 32-bit T32 instruction that looks like two NOPs // bits = 0xE97F E97F .SG = { - {.SG, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}}, + {.SG, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // BXNS Rm: T16 16-bit, 0100 0111 0 Rm[3:0] 100 = 0x4704 base, bit 2 = 1 .BXNS = { - {.BXNS, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004704, 0x0000FF87, .V8M_SE, .T32, {cond_in_28=false, branch=true}}, + {.BXNS, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004704, 0x0000FF87, .V8M_SE, .T32, {cond_in_28=false, branch=true}, {}}, }, // BLXNS Rm: T16, 0100 0111 1 Rm[3:0] 100 = 0x4784 base .BLXNS = { - {.BLXNS, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004784, 0x0000FF87, .V8M_SE, .T32, {cond_in_28=false, branch=true}}, + {.BLXNS, {.GPR, .NONE, .NONE, .NONE}, {.RM_T16_HI, .NONE, .NONE, .NONE}, 0x00004784, 0x0000FF87, .V8M_SE, .T32, {cond_in_28=false, branch=true}, {}}, }, // ========================================================================= @@ -3004,20 +3004,20 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // AUTG Rd, Rn, Rm: more general form using FB50F000 base // BTI: HINT #15 = 0xF3AF80F0 .PAC = { - {.PAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF801D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.PAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF801D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .PACBTI = { - {.PACBTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF800D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.PACBTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF800D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .AUT = { - {.AUT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF802D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.AUT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF802D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .AUTG = { // AUTG Rd, Rn, Rm: 1111 1011 0101 Rn 1111 Rd 0000 Rm - {.AUTG, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB50F000, 0xFFF0F0F0, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.AUTG, {.GPR, .GPR, .GPR, .NONE}, {.RD_T32, .RN_T32, .RM_T32, .NONE}, 0xFB50F000, 0xFFF0F0F0, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .BTI = { - {.BTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF80F0, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.BTI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF80F0, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ========================================================================= @@ -3030,26 +3030,26 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // LETP / WLSTP / DLSTP: same family with TP variant bit // LCTP: 1111 0000 0000 1111 1110 0 0000 0000 0000 1 .WLS = { - {.WLS, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.WLS, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, .WLSTP = { // WLSTP.: bits 22:20 carry size selector (B/H/W/D) - {.WLSTP, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.WLSTP, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {.SZ8, .NONE}}, }, .DLS = { - {.DLS, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.DLS, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .DLSTP = { - {.DLSTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.DLSTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .LE = { - {.LE, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.LE, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, .LETP = { - {.LETP, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.LETP, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, .LCTP = { - {.LCTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.LCTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // BF / BFL / BFLX / BFX (Branch Future, ARMv8.1-M). T32, word = hw0<<16|hw1. @@ -3057,22 +3057,22 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // (label-(PC+4))/2 with J at hw1[11] and imm10 at hw1[10:1]; BFLX/BFX target // is a register Rm at hw0[3:0]. (BFCSEL has an extra else-target + condition.) .BF = { - {.BF, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.BF, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, .BFL = { - {.BFL, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.BFL, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {.SZ8, .NONE}}, }, .BFLX = { - {.BFLX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.BFLX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, .BFX = { - {.BFX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.BFX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {}}, }, // BFCSEL: bf-point + true-target (hw1, like BF) + 4-bit condition at hw0[5:2]; // hw0[1] is a static marker. The else-target is the architectural fall-through // (implicit) so it is not a separate operand. .BFCSEL = { - {.BFCSEL, {.REL_BF, .REL_BF, .IMM4, .NONE}, {.BF_BOFF, .BF_BLOC, .BFCSEL_COND, .NONE}, 0xF002E001, 0xF843F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.BFCSEL, {.REL_BF, .REL_BF, .IMM4, .NONE}, {.BF_BOFF, .BF_BLOC, .BFCSEL_COND, .NONE}, 0xF002E001, 0xF843F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}, {.SZ8, .NONE}}, }, // ========================================================================= @@ -3093,66 +3093,66 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // Base T32 prefix 0xEE/0xEC selects which coproc encoding family. Bit 16 // (A bit) distinguishes accumulator variants (CX1A from CX1, etc.). .CX1 = { - {.CX1, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xEE000000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX1, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xEE000000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX1A = { - {.CX1A, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xFE000000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX1A, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xFE000000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX1D = { - {.CX1D, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xEE800000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX1D, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xEE800000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX1DA = { - {.CX1DA, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xFE800000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX1DA, {.IMM_COPROC, .GPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .RD_T32, .CDE_IMM_FIELD, .NONE}, 0xFE800000, 0xFF800000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX2 = { - {.CX2, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE400000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX2, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE400000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX2A = { - {.CX2A, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xFE400000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX2A, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xFE400000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX2D = { - {.CX2D, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX2D, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX2DA = { - {.CX2DA, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX2DA, {.IMM_COPROC, .GPR, .GPR, .IMM}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .CDE_IMM_FIELD}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // CX3 has Rn and Rm inputs (Rm placed at bits 3:0 of low half) .CX3 = { - {.CX3, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xEE800000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX3, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xEE800000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX3A = { - {.CX3A, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xFE800000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX3A, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xFE800000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX3D = { - {.CX3D, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX3D, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .CX3DA = { - {.CX3DA, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.CX3DA, {.IMM_COPROC, .GPR, .GPR, .GPR}, {.CDE_COPROC_FIELD, .RD_T32, .RN_T32, .RM_T32}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // VCX variants -- VFP/FP-register destination using S or D form .VCX1 = { - {.VCX1, {.IMM_COPROC, .SPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_S, .CDE_IMM_FIELD, .NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX1, {.IMM_COPROC, .DPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_D, .CDE_IMM_FIELD, .NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX1, {.IMM_COPROC, .SPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_S, .CDE_IMM_FIELD, .NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX1, {.IMM_COPROC, .DPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_D, .CDE_IMM_FIELD, .NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VCX1A = { - {.VCX1A, {.IMM_COPROC, .SPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_S, .CDE_IMM_FIELD, .NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX1A, {.IMM_COPROC, .DPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_D, .CDE_IMM_FIELD, .NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX1A, {.IMM_COPROC, .SPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_S, .CDE_IMM_FIELD, .NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX1A, {.IMM_COPROC, .DPR, .IMM, .NONE}, {.CDE_COPROC_FIELD, .VD_D, .CDE_IMM_FIELD, .NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VCX2 = { - {.VCX2, {.IMM_COPROC, .SPR, .SPR, .IMM}, {.CDE_COPROC_FIELD, .VD_S, .VM_S, .CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX2, {.IMM_COPROC, .DPR, .DPR, .IMM}, {.CDE_COPROC_FIELD, .VD_D, .VM_D, .CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX2, {.IMM_COPROC, .SPR, .SPR, .IMM}, {.CDE_COPROC_FIELD, .VD_S, .VM_S, .CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX2, {.IMM_COPROC, .DPR, .DPR, .IMM}, {.CDE_COPROC_FIELD, .VD_D, .VM_D, .CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VCX2A = { - {.VCX2A, {.IMM_COPROC, .SPR, .SPR, .IMM}, {.CDE_COPROC_FIELD, .VD_S, .VM_S, .CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX2A, {.IMM_COPROC, .DPR, .DPR, .IMM}, {.CDE_COPROC_FIELD, .VD_D, .VM_D, .CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX2A, {.IMM_COPROC, .SPR, .SPR, .IMM}, {.CDE_COPROC_FIELD, .VD_S, .VM_S, .CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX2A, {.IMM_COPROC, .DPR, .DPR, .IMM}, {.CDE_COPROC_FIELD, .VD_D, .VM_D, .CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VCX3 = { - {.VCX3, {.IMM_COPROC, .SPR, .SPR, .SPR}, {.CDE_COPROC_FIELD, .VD_S, .VN_S, .VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX3, {.IMM_COPROC, .DPR, .DPR, .DPR}, {.CDE_COPROC_FIELD, .VD_D, .VN_D, .VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX3, {.IMM_COPROC, .SPR, .SPR, .SPR}, {.CDE_COPROC_FIELD, .VD_S, .VN_S, .VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX3, {.IMM_COPROC, .DPR, .DPR, .DPR}, {.CDE_COPROC_FIELD, .VD_D, .VN_D, .VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VCX3A = { - {.VCX3A, {.IMM_COPROC, .SPR, .SPR, .SPR}, {.CDE_COPROC_FIELD, .VD_S, .VN_S, .VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, - {.VCX3A, {.IMM_COPROC, .DPR, .DPR, .DPR}, {.CDE_COPROC_FIELD, .VD_D, .VN_D, .VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}}, + {.VCX3A, {.IMM_COPROC, .SPR, .SPR, .SPR}, {.CDE_COPROC_FIELD, .VD_S, .VN_S, .VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VCX3A, {.IMM_COPROC, .DPR, .DPR, .DPR}, {.CDE_COPROC_FIELD, .VD_D, .VN_D, .VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ========================================================================= @@ -3171,296 +3171,296 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // where mask in bits 13-11 encodes then/else pattern + length // VPT (LLVM-verified): vpt.i8 eq, q2, q3 = 0xFE45_0F06 -> base 0xFE010F00 .VPT = { - {.VPT, {.MVE_VPT_MASK, .COND, .QPR, .QPR}, {.MVE_VPT_MASK_FIELD, .NONE, .VN_Q, .VM_Q}, 0xFE010F00, 0xFE018FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VPT, {.MVE_VPT_MASK, .COND, .QPR, .QPR}, {.MVE_VPT_MASK_FIELD, .NONE, .VN_Q, .VM_Q}, 0xFE010F00, 0xFE018FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, }, // VPST = 0xFE71_0F4D .VPST = { - {.VPST, {.MVE_VPT_MASK, .NONE, .NONE, .NONE}, {.MVE_VPT_MASK_FIELD, .NONE, .NONE, .NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VPST, {.MVE_VPT_MASK, .NONE, .NONE, .NONE}, {.MVE_VPT_MASK_FIELD, .NONE, .NONE, .NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // VPSEL (LLVM): vpsel q1, q2, q3 = 0xFE35_2F07 -> base 0xFE010F01 .VPSEL = { - {.VPSEL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE010F01, 0xFFB10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VPSEL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE010F01, 0xFFB10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, // VPNOT = 0xFE31_0F4D .VPNOT = { - {.VPNOT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VPNOT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // VCTP (LLVM): vctp.8 r3 = 0xF003_E801 -> base 0xF000E801 with Rn at bits 19:16 .VCTP = { - {.VCTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E801, 0xFFC0FFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VCTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E801, 0xFFC0FFFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, // ---- MVE reductions (single Q -> GPR or pair) ----------------------------- // MVE reductions (LLVM-verified bases for size-00 .S8 forms). .VADDV = { // vaddv.s8 r0, q3 = 0xEEF1_0F06 -> base 0xEEF10F00 - {.VADDV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEF10F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADDV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEF10F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VADDVA = { // vaddva.s8 r0, q3 = 0xEEF1_0F26 -> base 0xEEF10F20 - {.VADDVA, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEF10F20, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADDVA, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEF10F20, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VADDLV = { // vaddlv.s32 r0,r1,q3 = 0xEE89_0F06 -> base 0xEE890F00 (Rd=R0 at 11:8, Rn=R1 implicit pair) - {.VADDLV, {.GPR, .GPR, .QPR, .NONE}, {.RD_T32, .RN_T32, .VM_Q, .NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADDLV, {.GPR, .GPR, .QPR, .NONE}, {.RD_T32, .RN_T32, .VM_Q, .NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VADDLVA = { - {.VADDLVA, {.GPR, .GPR, .QPR, .NONE}, {.RD_T32, .RN_T32, .VM_Q, .NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VADDLVA, {.GPR, .GPR, .QPR, .NONE}, {.RD_T32, .RN_T32, .VM_Q, .NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMAXV = { // vmaxv.s8 r0, q3 = 0xEEE2_0F06 -> base 0xEEE20F00 - {.VMAXV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE20F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMAXV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE20F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMAXAV = { - {.VMAXAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE00F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMAXAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE00F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMINV = { // vminv.s8 r0, q3 = 0xEEE2_0F86 -> base 0xEEE20F80 - {.VMINV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE20F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMINV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE20F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMINAV = { - {.VMINAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE00F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMINAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEE00F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMAXNMV = { // vmaxnmv.f32 r0, q3 = 0xEEEE_0F06 -> base 0xEEEE0F00 - {.VMAXNMV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMAXNMV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VMAXNMAV = { - {.VMAXNMAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEC0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMAXNMAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEC0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VMINNMV = { // vminnmv.f32 r0, q3 = 0xEEEE_0F86 -> base 0xEEEE0F80 - {.VMINNMV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEE0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMINNMV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEE0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, .VMINNMAV = { - {.VMINNMAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEC0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VMINNMAV, {.GPR, .QPR, .NONE, .NONE}, {.RD_T32, .VM_Q, .NONE, .NONE}, 0xEEEC0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F32, .NONE}}, }, // ---- MVE dual MAC reductions (representative; full B/T/X variants encoded similarly) ---- // MVE MAC reductions (LLVM-verified for .S8 sizes; size bits in 21:20): // vabav.s8 r0, q2, q3 = 0xEE84_0F07 -> base 0xEE800F01 .VABAV = { - {.VABAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEE800F01, 0xEFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VABAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEE800F01, 0xEFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // vmlav.s8 r0,q2,q3 = 0xEEF4_0F06 -> base 0xEEB00F00 // vmladav.s8 = same encoding as vmlav (alias) .VMLAV = { - {.VMLAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLAVA = { - {.VMLAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLADAV = { - {.VMLADAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLADAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLADAVA = { // vmladava.s8 = 0xEEF4_0F26 -> base 0xEEB00F20 - {.VMLADAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLADAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLADAVX = { // vmladavx.s8 = 0xEEF4_1F06 -> base 0xEEB01F00 - {.VMLADAVX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB01F00, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLADAVX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB01F00, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLADAVAX = { - {.VMLADAVAX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB01F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLADAVAX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xEEB01F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLSDAV = { // vmlsdav.s8 r0,q2,q3 = 0xFEF4_0E07 -> base 0xFEB00E01 - {.VMLSDAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB00E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSDAV, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB00E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLSDAVA = { - {.VMLSDAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB00E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSDAVA, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB00E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLSDAVX = { - {.VMLSDAVX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB01E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSDAVX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB01E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VMLSDAVAX = { - {.VMLSDAVAX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB01E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSDAVAX, {.GPR, .QPR, .QPR, .NONE}, {.RD_T32, .VN_Q, .VM_Q, .NONE}, 0xFEB01E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, // Long-version (64-bit pair RdaLo, RdaHi) // vmlaldav.s32 r0,r1,q2,q3 = 0xEE85_0E06 -> base 0xEE800E00 (with Qn at 19:17 expanded view) // Need to verify exact base after Rn at bits 11:8 + Rd at bits 15:12. .VMLALDAV = { - {.VMLALDAV, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALDAV, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLALDAVA = { - {.VMLALDAVA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALDAVA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLALDAVX = { - {.VMLALDAVX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALDAVX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLALDAVAX = { - {.VMLALDAVAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALDAVAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLSLDAV = { // vmlsldav.s32 r0,r1,q2,q3 = 0xEE85_0E07 -> base 0xEE800E01 - {.VMLSLDAV, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E01, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLDAV, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E01, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLSLDAVA = { - {.VMLSLDAVA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E21, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLDAVA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800E21, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLSLDAVX = { // vmlsldavx.s32 = 0xEE85_1E07 -> base 0xEE801E01 - {.VMLSLDAVX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLDAVX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VMLSLDAVAX = { - {.VMLSLDAVAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLDAVAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, // High-half rounding reductions: // vrmlaldavh.s32 r0,r1,q2,q3 = 0xEE84_0F06 -> base 0xEE800F00 // vrmlsldavh.s32 r0,r1,q2,q3 = 0xFE84_0E07 -> base 0xFE800E01 .VRMLALDAVH = { - {.VRMLALDAVH, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLALDAVH, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLALDAVHA = { - {.VRMLALDAVHA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLALDAVHA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE800F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLALDAVHX = { - {.VRMLALDAVHX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLALDAVHX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLALDAVHAX = { - {.VRMLALDAVHAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLALDAVHAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xEE801F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLSLDAVH = { - {.VRMLSLDAVH, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE800E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLSLDAVH, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE800E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLSLDAVHA = { - {.VRMLSLDAVHA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE800E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLSLDAVHA, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE800E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLSLDAVHX = { - {.VRMLSLDAVHX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLSLDAVHX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, .VRMLSLDAVHAX = { - {.VRMLSLDAVHAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRMLSLDAVHAX, {.GPR, .GPR, .QPR, .QPR}, {.RD_T32, .RN_T32, .VN_Q, .VM_Q}, 0xFE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S32, .NONE}}, }, // ---- MVE complex arithmetic ------------------------------------------------ .VCMUL = { - {.VCMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE300E00, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}}, + {.VCMUL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE300E00, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, }, .VHCADD = { - {.VHCADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VHCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VHCADD, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, + {.VHCADD, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // ---- MVE shifts (specialized) --------------------------------------------- .VSHLC = { // VSHLC Qd, Rdm, #imm5 -- vector shift left with carry from GPR - {.VSHLC, {.QPR, .GPR, .IMM5, .NONE}, {.VD_Q, .RM_T32, .A32_IMM_SHIFT, .NONE}, 0xEE000FC0, 0xFFC00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHLC, {.QPR, .GPR, .IMM5, .NONE}, {.VD_Q, .RM_T32, .A32_IMM_SHIFT, .NONE}, 0xEE000FC0, 0xFFC00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VBRSR = { // VBRSR Qd, Qn, Rm -- bit reverse with shift right - {.VBRSR, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811F71, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VBRSR, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811F71, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, }, // ---- MVE counter init duplicates ------------------------------------------ .VDDUP = { - {.VDDUP, {.QPR, .GPR, .IMM, .NONE}, {.VD_Q, .RM_T32, .CDE_IMM_FIELD, .NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VDDUP, {.QPR, .GPR, .IMM, .NONE}, {.VD_Q, .RM_T32, .CDE_IMM_FIELD, .NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, .VIDUP = { - {.VIDUP, {.QPR, .GPR, .IMM, .NONE}, {.VD_Q, .RM_T32, .CDE_IMM_FIELD, .NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VIDUP, {.QPR, .GPR, .IMM, .NONE}, {.VD_Q, .RM_T32, .CDE_IMM_FIELD, .NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, .VDWDUP = { - {.VDWDUP, {.QPR, .GPR, .GPR, .IMM}, {.VD_Q, .RM_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE011F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VDWDUP, {.QPR, .GPR, .GPR, .IMM}, {.VD_Q, .RM_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE011F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, .VIWDUP = { - {.VIWDUP, {.QPR, .GPR, .GPR, .IMM}, {.VD_Q, .RM_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE010F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VIWDUP, {.QPR, .GPR, .GPR, .IMM}, {.VD_Q, .RM_T32, .RN_T32, .CDE_IMM_FIELD}, 0xEE010F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, // MVE narrow B/T (LLVM-verified for .S16 sizes; T-form bit 12 = 1): .VMOVNB = { // vmovnb.s16 q1, q3 = 0xFE31_2E87 -> base 0xFE310E81 - {.VMOVNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOVNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I16, .NONE}}, }, .VMOVNT = { - {.VMOVNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMOVNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xFE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I16, .NONE}}, }, .VQMOVNB = { // vqmovnb.s16 q1, q3 = 0xEE33_2E07 -> base 0xEE330E01 - {.VQMOVNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE330E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQMOVNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE330E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VQMOVNT = { - {.VQMOVNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE331E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQMOVNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE331E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VQMOVUNB = { // vqmovunb.s16 q1, q3 = 0xEE31_2E87 -> base 0xEE310E81 - {.VQMOVUNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQMOVUNB, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, .VQMOVUNT = { - {.VQMOVUNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQMOVUNT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xEE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S16, .NONE}}, }, // MVE widening (long) B/T forms: .VSHLLB = { // vshllb.s8 q1, q3, #4 = 0xEEAC_2F46 -> base 0xEE800F40 (imm6 in 21:16, // includes the size-prefix 101sss for .S8) - {.VSHLLB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHLLB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VSHLLT = { - {.VSHLLT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHLLT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VMULLB = { // vmullb.s8 q1, q2, q3 = 0xEE05_2E06 -> base 0xEE000E00 - {.VMULLB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMULLB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VMULLT = { - {.VMULLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMULLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // VMLALB/T/VMLSLB/T: LLVM doesn't seem to support direct mnemonics in // its assembler; encodings derived heuristically from VMULL B/T pattern .VMLALB = { - {.VMLALB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VMLALT = { - {.VMLALT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLALT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VMLSLB = { - {.VMLSLB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLB, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VMLSLT = { - {.VMLSLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VMLSLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Narrow shift B/T forms (LLVM-verified): // vshrnb.i16 q,q,#shift = 0xEE8F_2EC7 base 0xEE800EC1 (imm6 = 16-shift) // vshrnt.i16 = bit 12 = 1 .VSHRNB = { - {.VSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VSHRNT = { - {.VSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VRSHRNB = { - {.VRSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE800EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE800EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VRSHRNT = { - {.VRSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE801EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VRSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE801EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQSHRNB = { // vqshrnb.s16 q,q,#4 = 0xEE8C_2F46 -> base 0xEE800F40 - {.VQSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQSHRNT = { - {.VQSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQRSHRNB = { // vqrshrnb.s16 q,q,#4 = 0xEE8C_2F47 -> base 0xEE800F41 - {.VQRSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRSHRNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQRSHRNT = { - {.VQRSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRSHRNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQSHRUNB = { // vqshrunb.s16 q,q,#4 = 0xEE8C_2FC6 -> base 0xEE800FC0 - {.VQSHRUNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSHRUNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE800FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQSHRUNT = { - {.VQSHRUNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQSHRUNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xEE801FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQRSHRUNB = { // vqrshrunb.s16 q,q,#4 = 0xFE8C_2FC6 -> base 0xFE800FC0 - {.VQRSHRUNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE800FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRSHRUNB, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE800FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VQRSHRUNT = { - {.VQRSHRUNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE801FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRSHRUNT, {.QPR, .QPR, .IMM5, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xFE801FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // ---- MVE Q-lane GPR move --------------------------------------------------- @@ -3471,28 +3471,28 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vqdmlsdh = top byte 0xFE (vs 0xEE) // vqrdmladh = bit 0 = 1 (vs 0) .VQDMLADH = { - {.VQDMLADH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQDMLADH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQDMLADHX = { - {.VQDMLADHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQDMLADHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQDMLSDH = { - {.VQDMLSDH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE000E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQDMLSDH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE000E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQDMLSDHX = { - {.VQDMLSDHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE001E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQDMLSDHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE001E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQRDMLADH = { - {.VQRDMLADH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRDMLADH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE000E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQRDMLADHX = { - {.VQRDMLADHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRDMLADHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEE001E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQRDMLSDH = { - {.VQRDMLSDH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE000E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRDMLSDH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE000E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, .VQRDMLSDHX = { - {.VQRDMLSDHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE001E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VQRDMLSDHX, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFE001E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.S8, .NONE}}, }, // ---- MVE load/store -------------------------------------------------------- @@ -3502,124 +3502,124 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vldrw.u32 q1, [r2] = 0xED92_3F00 -> base 0xED901F00 // vstrb.8 q1, [r2] = 0xED82_3E00 -> base 0xED801E00 .VLDRB = { - {.VLDRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VLDRB, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, + {.VLDRB, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U8, .NONE}}, }, .VLDRH = { - {.VLDRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VLDRH, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U16, .NONE}}, + {.VLDRH, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U16, .NONE}}, }, .VLDRW = { - {.VLDRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VLDRW, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U32, .NONE}}, + {.VLDRW, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U32, .NONE}}, }, .VLDRD = { - {.VLDRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VLDRD, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLDRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VLDRD, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.U64, .NONE}}, }, .VSTRB = { - {.VSTRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VSTRB, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRB, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, + {.VSTRB, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VSTRH = { - {.VSTRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VSTRH, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRH, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ16, .NONE}}, + {.VSTRH, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VSTRW = { - {.VSTRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VSTRW, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRW, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, + {.VSTRW, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VSTRD = { - {.VSTRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, - {.VSTRD, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VSTRD, {.QPR, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM12_OFFSET, .NONE, .NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VSTRD, {.QPR, .MEM, .QPR, .NONE}, {.VD_Q, .RN_T32, .VM_Q, .NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, // Interleaved load/store -- 2-vector .VLD20 = { - {.VLD20, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD20, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD21 = { - {.VLD21, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD21, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD40 = { - {.VLD40, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD40, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD41 = { - {.VLD41, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD41, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD42 = { - {.VLD42, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD42, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VLD43 = { - {.VLD43, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VLD43, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC901E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST20 = { - {.VST20, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST20, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST21 = { - {.VST21, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST21, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST40 = { - {.VST40, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST40, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST41 = { - {.VST41, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST41, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST42 = { - {.VST42, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST42, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, .VST43 = { - {.VST43, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}}, + {.VST43, {.QPR_MVE_LIST, .MEM, .NONE, .NONE}, {.VD_Q, .MEM_IMM8_OFFSET, .NONE, .NONE}, 0xFC801E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ8, .NONE}}, }, // Unprivileged (translate) post-indexed loads/stores: the post-index form // with the W bit (21) set. Word/byte use imm12, half/signed use imm8 split. - .LDRT = { {.LDRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}} }, - .LDRBT = { {.LDRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}} }, - .STRT = { {.STRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}} }, - .STRBT = { {.STRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}} }, - .LDRHT = { {.LDRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}} }, - .STRHT = { {.STRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}} }, - .LDRSBT = { {.LDRSBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}} }, - .LDRSHT = { {.LDRSHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}} }, + .LDRT = { {.LDRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}, {}} }, + .LDRBT = { {.LDRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}, {}} }, + .STRT = { {.STRT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}, {}} }, + .STRBT = { {.STRBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}, {}} }, + .LDRHT = { {.LDRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .STRHT = { {.STRHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .LDRSBT = { {.LDRSBT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}, {}} }, + .LDRSHT = { {.LDRSHT, {.GPR, .MEM, .NONE, .NONE}, {.RT_A32, .MEM_POST_INDEX, .NONE, .NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}, {}} }, // NEON rounding shift-right-accumulate (imm); FP reciprocal/rsqrt estimate; // FP pairwise add; VFP convert-to-integer using the FPSCR rounding mode. .VRSRA = { - {.VRSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {cond_in_28=false}}, - {.VRSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {cond_in_28=false}}, + {.VRSRA, {.DPR, .DPR, .IMM, .NONE}, {.VD_D, .VM_D, .NEON_SHIFT_IMM6, .NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VRSRA, {.QPR, .QPR, .IMM, .NONE}, {.VD_Q, .VM_Q, .NEON_SHIFT_IMM6, .NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VRECPE_F = { - {.VRECPE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRECPE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRECPE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRECPE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VRSQRTE_F = { - {.VRSQRTE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, - {.VRSQRTE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}}, + {.VRSQRTE_F, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VRSQRTE_F, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VPADD_F = { - {.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}}, - {.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}}, + {.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VPADD_F, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {cond_in_28=false}, {.F16, .NONE}}, }, .VCVTR = { - {.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVTR, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, - {.VCVTR, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}}, + {.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32, .F32}}, + {.VCVTR, {.SPR, .SPR, .NONE, .NONE}, {.VD_S, .VM_S, .NONE, .NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32, .F32}}, + {.VCVTR, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32, .F64}}, + {.VCVTR, {.SPR, .DPR, .NONE, .NONE}, {.VD_S, .VM_D, .NONE, .NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32, .F64}}, }, // Debug change PE state (T32, fixed encoding, no operands). - .DCPS1 = { {.DCPS1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8001, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}} }, - .DCPS2 = { {.DCPS2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8002, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}} }, - .DCPS3 = { {.DCPS3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8003, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}} }, + .DCPS1 = { {.DCPS1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8001, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}} }, + .DCPS2 = { {.DCPS2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8002, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}} }, + .DCPS3 = { {.DCPS3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8003, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}, {}} }, // NEON (saturating) doubling multiply-high by scalar Dm[lane]: // .16 -> Dm in D0..D7 (bits 2:0), lane at bit5:bit3; .32 -> D0..D15, lane bit5. // VMOV (ARM core register to scalar): Dd[lane], Rt. The lane bits depend on // the element size (see VMOV_LANE_8/16/32); bit22/bit5 carry the size. .VMOV_LANE = { - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_8, .RT_A32, .NONE, .NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}}, - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_16, .RT_A32, .NONE, .NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}}, - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_32, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}}, + {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_8, .RT_A32, .NONE, .NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8, .NONE}}, + {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_16, .RT_A32, .NONE, .NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16, .NONE}}, + {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_32, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32, .NONE}}, }, // MVE (M-profile vector) multiply-subtract-across-vector reduce, halving @@ -3629,123 +3629,123 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // mask (the MVE convention); the complex ops encode the rotation immediate. // MVE multiply-subtract reduce (Rd at 15:12, Qn at 19:17, Qm at 3:1 -- the // proper 3-bit MVE Q fields, .s16 form). VMLSVA accumulates (bit 5). - .VMLSV = { {.VMLSV, {.GPR, .QPR, .QPR, .NONE}, {.RDLO_A32, .VN_Q_MVE, .VM_Q_MVE, .NONE}, 0xEEF00E01, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}} }, - .VMLSVA = { {.VMLSVA, {.GPR, .QPR, .QPR, .NONE}, {.RDLO_A32, .VN_Q_MVE, .VM_Q_MVE, .NONE}, 0xEEF00E21, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}} }, + .VMLSV = { {.VMLSV, {.GPR, .QPR, .QPR, .NONE}, {.RDLO_A32, .VN_Q_MVE, .VM_Q_MVE, .NONE}, 0xEEF00E01, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}} }, + .VMLSVA = { {.VMLSVA, {.GPR, .QPR, .QPR, .NONE}, {.RDLO_A32, .VN_Q_MVE, .VM_Q_MVE, .NONE}, 0xEEF00E21, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}} }, // SPECGEN:BEGIN .VADDL = { - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VSUBL = { - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VSUBL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VABAL = { - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VABAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VABDL = { - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, - {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VABDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VADDW = { - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2900100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2A00100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3800100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2900100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2A00100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3800100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VADDW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00100, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VSUBW = { - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2900300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2A00300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3800300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, - {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2900300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF2A00300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3800300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VSUBW, {.QPR, .QPR, .DPR, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00300, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VCLE = { - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VCLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLE, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLE, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VCLT = { - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, - {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VCLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VCLT, {.DPR, .DPR, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VCLT, {.QPR, .QPR, .NONE, .NONE}, {.VD_Q, .VM_Q, .NONE, .NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VACLE = { - {.VACLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VACLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, + {.VACLE, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VACLE, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VACLT = { - {.VACLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VACLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, + {.VACLT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, + {.VACLT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, }, .VQRSHL = { - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2300510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2300550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3300510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}}, - {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2000550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2200550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF2300510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF2300550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.S64, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3100510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3100550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VQRSHL, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VM_D, .VN_D, .NONE}, 0xF3300510, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}}, + {.VQRSHL, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VM_Q, .VN_Q, .NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {cond_in_28=false}, {.U64, .NONE}}, }, // SPECGEN:END } diff --git a/core/rexcode/isa/arm32/tablegen/gen.odin b/core/rexcode/isa/arm32/tablegen/gen.odin index 8558edcee..617d4a749 100644 --- a/core/rexcode/isa/arm32/tablegen/gen.odin +++ b/core/rexcode/isa/arm32/tablegen/gen.odin @@ -65,6 +65,7 @@ Entry :: struct { feature: lib.Feature, mode: lib.Mode, flags: lib.Encoding_Flags, + dt: lib.Data_Types, is_thumb32: bool, key: u16, // primary dispatch key (8 bits A32, 7 bits T32, 6 bits T16) ilen: u8, @@ -101,7 +102,7 @@ emit_encode_tables :: proc() -> (total: int) { if len(forms) == 0 { continue } fmt.sbprintfln(&sb, "\t// .%v", m) for f in forms { - write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.mode, f.flags) + write_row(&sb, f.mnemonic, f.ops, f.enc, f.bits, f.mask, f.feature, f.mode, f.flags, f.dt) } } strings.write_string(&sb, "}\n\n") @@ -170,6 +171,7 @@ emit_decode_tables :: proc() -> (total: int) { feature = f.feature, mode = f.mode, flags = f.flags, + dt = f.dt, is_thumb32 = f.flags.thumb32, ilen = ilen, form_idx = u16(fi), @@ -301,7 +303,7 @@ emit_decode_tables :: proc() -> (total: int) { strings.write_string(&sb, "@(rodata)\n") fmt.sbprintfln(&sb, "DECODE_ENTRIES := [%d]lib.Decode_Entry{{", len(all)) for e in all { - write_row(&sb, e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.mode, e.flags) + write_row(&sb, e.mnemonic, e.ops, e.enc, e.bits, e.mask, e.feature, e.mode, e.flags, e.dt) } strings.write_string(&sb, "}\n\n") @@ -351,10 +353,11 @@ emit_range :: proc(sb: ^strings.Builder, name: string, ranges: []Range) { write_row :: proc(sb: ^strings.Builder, mn: lib.Mnemonic, ops: [4]lib.Operand_Type, enc: [4]lib.Operand_Encoding, bits, mask: u32, - feature: lib.Feature, mode: lib.Mode, flags: lib.Encoding_Flags) { - fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, .%v, {{%s}} }},\n", + feature: lib.Feature, mode: lib.Mode, flags: lib.Encoding_Flags, + dt: lib.Data_Types) { + fmt.sbprintf(sb, "\t{{ .%v, {{.%v,.%v,.%v,.%v}}, {{.%v,.%v,.%v,.%v}}, 0x%08X, 0x%08X, .%v, .%v, {{%s}}, {{.%v,.%v}} }},\n", mn, ops[0], ops[1], ops[2], ops[3], enc[0], enc[1], enc[2], enc[3], - bits, mask, feature, mode, flags_lit(flags)) + bits, mask, feature, mode, flags_lit(flags), dt[0], dt[1]) } flags_lit :: proc(f: lib.Encoding_Flags) -> string { @@ -412,8 +415,9 @@ Decode_Entry :: struct #packed { feature: Feature, // 1 mode: Mode, // 1 flags: Encoding_Flags, // 1 + dt: Data_Types, // 2 -- see Data_Type in encoding_types.odin } -#assert(size_of(Decode_Entry) == 21) +#assert(size_of(Decode_Entry) == 23) Decode_Index :: struct #packed { start: u16, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index c2a2a77e5..73edb4aa0 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -9,1686 +9,1686 @@ import lib "../.." @(rodata) DECODE_ENTRIES := [1680]lib.Decode_Entry{ - { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {} }, - { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {} }, - { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00100090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00200090, 0x0FE000F0, .BASE, .A32, {} }, - { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200010, 0x0FE00090, .BASE, .A32, {} }, - { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {} }, - { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00300090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .UMAAL, {.GPR,.GPR,.GPR,.GPR}, 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0x00005200, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRSB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005600, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005A00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRSH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005E00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00008000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRH, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00008800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADR, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR_LOW,.GPR,.IMM8,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .SXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .SXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B200, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .UXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B2C0, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .UXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B280, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B080, 0x0000FF80, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B000, 0x0000FF80, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .CBZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B100, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0000B610, 0x0000FFF7, .V8, .T32, {}, {.NONE,.NONE} }, + { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .REV, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA00, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .REV16, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA40, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .REVSH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BAC0, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .CBNZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B900, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF10, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF20, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF30, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF40, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .BKPT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BE00, 0x0000FF00, .V5T, .T32, {}, {.NONE,.NONE} }, + { .IT, {.COND,.IMM4,.NONE,.NONE}, {.NONE,.IT_MASK,.NONE,.NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000BC00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .B, {.REL8,.COND,.NONE,.NONE}, {.BRANCH_8_T16,.NONE,.NONE,.NONE}, 0x0000D000, 0x0000F000, .THUMB, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DF00, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .B, {.REL11,.NONE,.NONE,.NONE}, {.BRANCH_11_T16,.NONE,.NONE,.NONE}, 0x0000E000, 0x0000F800, .THUMB, .T32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, } @(rodata) diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index f41e57c92..7a423c5d2 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -10,2275 +10,2275 @@ import lib "../.." @(rodata) ENCODE_FORMS := [1680]lib.Encoding{ // .AND - { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {} }, - { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {} }, - { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02100000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .AND, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {sets_flags=true, thumb32=true} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, - { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {sets_flags=true, thumb32=true} }, + { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02100000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00100010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .AND, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004000, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA000000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA100000, 0xFFE08000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, // .EOR - { .EOR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {} }, - { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {} }, - { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200010, 0x0FE00090, .BASE, .A32, {} }, - { .EOR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02300000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .EOR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004040, 0x0000FFC0, .THUMB, .T32, {} }, - { .EOR, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA800000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .EOR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02200000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00200010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02300000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00300010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .EOR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004040, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .EOR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA800000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SUB - { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02400000, 0x0FE00000, .BASE, .A32, {} }, - { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {} }, - { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {} }, - { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .SUB, {.GPR_LOW,.GPR_LOW,.GPR_LOW,.NONE}, {.RD_T16_LO,.RN_T16_LO,.RM_T16_LO,.NONE}, 0x00001A00, 0x0000FE00, .THUMB, .T32, {} }, - { .SUB, {.GPR_LOW,.GPR_LOW,.IMM3,.NONE}, {.RD_T16_LO,.RN_T16_LO,.NONE,.NONE}, 0x00001E00, 0x0000FE00, .THUMB, .T32, {} }, - { .SUB, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00003800, 0x0000F800, .THUMB, .T32, {} }, - { .SUB, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B080, 0x0000FF80, .THUMB, .T32, {} }, + { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02400000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00400010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SUB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SUB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00500010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SUB, {.GPR_LOW,.GPR_LOW,.GPR_LOW,.NONE}, {.RD_T16_LO,.RN_T16_LO,.RM_T16_LO,.NONE}, 0x00001A00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR_LOW,.GPR_LOW,.IMM3,.NONE}, {.RD_T16_LO,.RN_T16_LO,.NONE,.NONE}, 0x00001E00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00003800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .SUB, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B080, 0x0000FF80, .THUMB, .T32, {}, {.NONE,.NONE} }, // .RSB - { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {} }, - { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {} }, - { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {} }, - { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .RSB, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1C00000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEBC00000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00600010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00700010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1C00000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .RSB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEBC00000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ADD - { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02800000, 0x0FE00000, .BASE, .A32, {} }, - { .ADD, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00800000, 0x0FE00010, .BASE, .A32, {} }, - { .ADD, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00800010, 0x0FE00090, .BASE, .A32, {} }, - { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .ADD, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00900000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .ADD, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00900010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .ADD, {.GPR_LOW,.GPR_LOW,.GPR_LOW,.NONE}, {.RD_T16_LO,.RN_T16_LO,.RM_T16_LO,.NONE}, 0x00001800, 0x0000FE00, .THUMB, .T32, {} }, - { .ADD, {.GPR_LOW,.GPR_LOW,.IMM3,.NONE}, {.RD_T16_LO,.RN_T16_LO,.NONE,.NONE}, 0x00001C00, 0x0000FE00, .THUMB, .T32, {} }, - { .ADD, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00003000, 0x0000F800, .THUMB, .T32, {} }, - { .ADD, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004400, 0x0000FF00, .THUMB, .T32, {} }, - { .ADD, {.GPR_LOW,.GPR,.IMM8,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A800, 0x0000F800, .THUMB, .T32, {} }, - { .ADD, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B000, 0x0000FF80, .THUMB, .T32, {} }, + { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02800000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00800000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00800010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADD, {.GPR_LOW,.GPR_LOW,.GPR_LOW,.NONE}, {.RD_T16_LO,.RN_T16_LO,.RM_T16_LO,.NONE}, 0x00001800, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR_LOW,.GPR_LOW,.IMM3,.NONE}, {.RD_T16_LO,.RN_T16_LO,.NONE,.NONE}, 0x00001C00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00003000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004400, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR_LOW,.GPR,.IMM8,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADD, {.GPR,.IMM8,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000B000, 0x0000FF80, .THUMB, .T32, {}, {.NONE,.NONE} }, // .ADC - { .ADC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {} }, - { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00A00000, 0x0FE00010, .BASE, .A32, {} }, - { .ADC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00A00010, 0x0FE00090, .BASE, .A32, {} }, - { .ADC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02B00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .ADC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .ADC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004140, 0x0000FFC0, .THUMB, .T32, {} }, - { .ADC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1400000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEB400000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .ADC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00A00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00A00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02B00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00B00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ADC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004140, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1400000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ADC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEB400000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SBC - { .SBC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02C00000, 0x0FE00000, .BASE, .A32, {} }, - { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00000, 0x0FE00010, .BASE, .A32, {} }, - { .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00010, 0x0FE00090, .BASE, .A32, {} }, - { .SBC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .SBC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004180, 0x0000FFC0, .THUMB, .T32, {} }, - { .SBC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1600000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEB600000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .SBC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02C00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00C00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SBC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004180, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF1600000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .SBC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEB600000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .RSC - { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02E00000, 0x0FE00000, .BASE, .A32, {} }, - { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00000, 0x0FE00010, .BASE, .A32, {} }, - { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00010, 0x0FE00090, .BASE, .A32, {} }, - { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02F00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, + { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02E00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00E00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RSC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02F00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, // .TST - { .TST, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03100000, 0x0FF0F000, .BASE, .A32, {} }, - { .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100000, 0x0FF0F010, .BASE, .A32, {} }, - { .TST, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100010, 0x0FF0F090, .BASE, .A32, {} }, - { .TST, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004200, 0x0000FFC0, .THUMB, .T32, {} }, - { .TST, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true} }, - { .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true} }, + { .TST, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03100000, 0x0FF0F000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TST, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01100010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TST, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004200, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .TST, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .TST, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .TEQ - { .TEQ, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03300000, 0x0FF0F000, .BASE, .A32, {} }, - { .TEQ, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01300000, 0x0FF0F010, .BASE, .A32, {} }, - { .TEQ, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01300010, 0x0FF0F090, .BASE, .A32, {} }, - { .TEQ, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true} }, - { .TEQ, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA900F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true} }, + { .TEQ, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03300000, 0x0FF0F000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TEQ, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01300000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TEQ, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01300010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .TEQ, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .TEQ, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEA900F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CMP - { .CMP, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03500000, 0x0FF0F000, .BASE, .A32, {} }, - { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {} }, - { .CMP, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {} }, - { .CMP, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00002800, 0x0000F800, .THUMB, .T32, {} }, - { .CMP, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004280, 0x0000FFC0, .THUMB, .T32, {} }, - { .CMP, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004500, 0x0000FF00, .THUMB, .T32, {} }, - { .CMP, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true} }, - { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEBB00F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true} }, + { .CMP, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03500000, 0x0FF0F000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01500010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00002800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004280, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004500, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .CMP, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .CMP, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEBB00F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CMN - { .CMN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03700000, 0x0FF0F000, .BASE, .A32, {} }, - { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {} }, - { .CMN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {} }, - { .CMN, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000042C0, 0x0000FFC0, .THUMB, .T32, {} }, - { .CMN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true} }, - { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEB100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true} }, + { .CMN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RN_A32,.A32_IMM_MOD,.NONE,.NONE}, 0x03700000, 0x0FF0F000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700000, 0x0FF0F010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RN_A32,.RM_A32,.NONE,.NONE}, 0x01700010, 0x0FF0F090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .CMN, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RN_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000042C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .CMN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .CMN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xEB100F00, 0xFFF08F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ORR - { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {} }, - { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800000, 0x0FE00010, .BASE, .A32, {} }, - { .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800010, 0x0FE00090, .BASE, .A32, {} }, - { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .ORR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004300, 0x0000FFC0, .THUMB, .T32, {} }, - { .ORR, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0400000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA400000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03800000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01800010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01900010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .ORR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004300, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0400000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ORR, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA400000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MOV - { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {} }, - { .MOV, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00000, 0x0FEF0010, .BASE, .A32, {} }, - { .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00010, 0x0FEF0090, .BASE, .A32, {} }, - { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true} }, - { .MOV, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01B00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true} }, - { .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true} }, - { .MOV, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true} }, - { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true} }, - { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true} }, + { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00000, 0x0FEF0010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00010, 0x0FEF0090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01B00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01B00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MOV, {.GPR_LOW,.IMM8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x00002000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T16_HI,.RM_T16_HI,.NONE,.NONE}, 0x00004600, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MOV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA5F0000, 0xFFEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true}, {.NONE,.NONE} }, // .BIC - { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {} }, - { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {} }, - { .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00010, 0x0FE00090, .BASE, .A32, {} }, - { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, - { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true} }, - { .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true} }, - { .BIC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004380, 0x0000FFC0, .THUMB, .T32, {} }, - { .BIC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0200000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, - { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA200000, 0xFFE08000, .V6T2, .T32, {thumb32=true} }, + { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01C00010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01D00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .BIC, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004380, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0200000, 0xFBE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .BIC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xEA200000, 0xFFE08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MVN - { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {} }, - { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00000, 0x0FEF0010, .BASE, .A32, {} }, - { .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00010, 0x0FEF0090, .BASE, .A32, {} }, - { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true} }, - { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true} }, - { .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true} }, - { .MVN, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000043C0, 0x0000FFC0, .THUMB, .T32, {} }, - { .MVN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true} }, - { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA6F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true} }, + { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00000, 0x0FEF0010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01E00010, 0x0FEF0090, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00000, 0x0FFF0010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MVN, {.GPR,.GPR_RSR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01F00010, 0x0FFF0090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MVN, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000043C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .MVN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .MVN, {.GPR,.GPR_SHIFTED,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA6F0000, 0xFFEF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LSL - { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00000, 0x0FFF0070, .BASE, .A32, {} }, - { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {} }, - { .LSL, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {} }, - { .LSL, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {} }, - { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true} }, - { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true} }, + { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00000, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00010, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LSL, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LSL, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004080, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0000, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LSR - { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {} }, - { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {} }, - { .LSR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {} }, - { .LSR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {} }, - { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true} }, - { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true} }, + { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00020, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00030, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LSR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00000800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LSR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000040C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0010, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LSR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ASR - { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {} }, - { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {} }, - { .ASR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {} }, - { .ASR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {} }, - { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true} }, - { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true} }, + { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00040, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00050, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ASR, {.GPR_LOW,.GPR_LOW,.IMM5,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00001000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ASR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004100, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0020, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ASR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ROR - { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {} }, - { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {} }, - { .ROR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {} }, - { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true} }, - { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true} }, + { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RM_A32,.A32_IMM_SHIFT,.NONE}, 0x01A00060, 0x0FFF0070, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RS_A32,.NONE}, 0x01A00070, 0x0FFF00F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .ROR, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x000041C0, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.IMM5,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xEA4F0030, 0xFFEF8030, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .ROR, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA60F000, 0xFFE0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .RRX - { .RRX, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {} }, + { .RRX, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x01A00060, 0x0FFF0FF0, .BASE, .A32, {}, {.NONE,.NONE} }, // .ADR - { .ADR, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A000, 0x0000F800, .THUMB, .T32, {} }, + { .ADR, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_HI,.NONE,.NONE,.NONE}, 0x0000A000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, // .NEG - { .NEG, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004240, 0x0000FFC0, .THUMB, .T32, {} }, + { .NEG, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004240, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, // .MOVW - { .MOVW, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x03000000, 0x0FF00000, .V6T2, .A32, {} }, - { .MOVW, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF2400000, 0xFBF08000, .V6T2, .T32, {thumb32=true} }, + { .MOVW, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x03000000, 0x0FF00000, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .MOVW, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF2400000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MOVT - { .MOVT, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x03400000, 0x0FF00000, .V6T2, .A32, {} }, - { .MOVT, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF2C00000, 0xFBF08000, .V6T2, .T32, {thumb32=true} }, + { .MOVT, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x03400000, 0x0FF00000, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .MOVT, {.GPR,.IMM16_LO_HI,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF2C00000, 0xFBF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .BFC - { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD,.BFI_LSB,.BFI_MSB,.NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {} }, - { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD_T32,.BFI_LSB_T32,.BFI_MSB,.NONE}, 0xF36F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true} }, + { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD,.BFI_LSB,.BFI_MSB,.NONE}, 0x07C0001F, 0x0FE0007F, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .BFC, {.GPR,.IMM5,.IMM5_W,.NONE}, {.RD_T32,.BFI_LSB_T32,.BFI_MSB,.NONE}, 0xF36F0000, 0xFFFF8000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .BFI - { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {} }, - { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true} }, + { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07C00010, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .BFI, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3600000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SBFX - { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {} }, - { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true} }, + { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07A00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .SBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3400000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UBFX - { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {} }, - { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true} }, + { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFI_MSB}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD_T32,.RN_T32,.BFI_LSB_T32,.BFI_MSB}, 0xF3C00000, 0xFFF08000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTB - { .SXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06AF0070, 0x0FFF0070, .V6, .A32, {} }, - { .SXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {} }, - { .SXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA4FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06AF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B240, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .SXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA4FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTB16 - { .SXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x068F0070, 0x0FFF0070, .V6, .A32, {} }, - { .SXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA2FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x068F0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA2FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTH - { .SXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0070, 0x0FFF0070, .V6, .A32, {} }, - { .SXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B200, 0x0000FFC0, .V6, .T32, {} }, - { .SXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA0FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B200, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .SXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA0FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTB - { .UXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06EF0070, 0x0FFF0070, .V6, .A32, {} }, - { .UXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B2C0, 0x0000FFC0, .V6, .T32, {} }, - { .UXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA5FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06EF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTB, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B2C0, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .UXTB, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA5FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTB16 - { .UXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06CF0070, 0x0FFF0070, .V6, .A32, {} }, - { .UXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA3FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06CF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTB16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA3FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTH - { .UXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0070, 0x0FFF0070, .V6, .A32, {} }, - { .UXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B280, 0x0000FFC0, .V6, .T32, {} }, - { .UXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA1FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0070, 0x0FFF0070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000B280, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .UXTH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA1FF080, 0xFFFFF0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTAB - { .SXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06A00070, 0x0FF00070, .V6, .A32, {} }, - { .SXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06A00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA40F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTAB16 - { .SXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800070, 0x0FF00070, .V6, .A32, {} }, - { .SXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA20F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SXTAH - { .SXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06B00070, 0x0FF00070, .V6, .A32, {} }, - { .SXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .SXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06B00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .SXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA00F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTAB - { .UXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06E00070, 0x0FF00070, .V6, .A32, {} }, - { .UXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA50F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06E00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTAB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA50F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTAB16 - { .UXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06C00070, 0x0FF00070, .V6, .A32, {} }, - { .UXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA30F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06C00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTAB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA30F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UXTAH - { .UXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06F00070, 0x0FF00070, .V6, .A32, {} }, - { .UXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA10F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true} }, + { .UXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06F00070, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, + { .UXTAH, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA10F080, 0xFFF0F0C0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CLZ - { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x016F0F10, 0x0FFF0FF0, .V5T, .A32, {} }, - { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFAB0F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x016F0F10, 0x0FFF0FF0, .V5T, .A32, {}, {.NONE,.NONE} }, + { .CLZ, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFAB0F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .RBIT - { .RBIT, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0F30, 0x0FFF0FF0, .V6T2, .A32, {} }, - { .RBIT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .RBIT, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0F30, 0x0FFF0FF0, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .RBIT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .REV - { .REV, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0F30, 0x0FFF0FF0, .V6, .A32, {} }, - { .REV, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA00, 0x0000FFC0, .V6, .T32, {} }, - { .REV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .REV, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0F30, 0x0FFF0FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .REV, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA00, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .REV, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .REV16 - { .REV16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0FB0, 0x0FFF0FF0, .V6, .A32, {} }, - { .REV16, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA40, 0x0000FFC0, .V6, .T32, {} }, - { .REV16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .REV16, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06BF0FB0, 0x0FFF0FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .REV16, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BA40, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .REV16, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .REVSH - { .REVSH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0FB0, 0x0FFF0FF0, .V6, .A32, {} }, - { .REVSH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BAC0, 0x0000FFC0, .V6, .T32, {} }, - { .REVSH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .REVSH, {.GPR,.GPR,.NONE,.NONE}, {.RD,.RM_A32,.NONE,.NONE}, 0x06FF0FB0, 0x0FFF0FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .REVSH, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x0000BAC0, 0x0000FFC0, .V6, .T32, {}, {.NONE,.NONE} }, + { .REVSH, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RM_T32,.NONE,.NONE}, 0xFA90F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SEL - { .SEL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800FB0, 0x0FF00FF0, .V6, .A32, {} }, + { .SEL, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800FB0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, // .PKHBT - { .PKHBT, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800010, 0x0FF00070, .V6, .A32, {} }, + { .PKHBT, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800010, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, // .PKHTB - { .PKHTB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800050, 0x0FF00070, .V6, .A32, {} }, + { .PKHTB, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06800050, 0x0FF00070, .V6, .A32, {}, {.NONE,.NONE} }, // .USAD8 - { .USAD8, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {} }, + { .USAD8, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0780F010, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .USADA8 - { .USADA8, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {} }, + { .USADA8, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07800010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SSAT - { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00010, 0x0FE00030, .V6, .A32, {} }, - { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true} }, + { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} }, + { .SSAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3000000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USAT - { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {} }, - { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true} }, + { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00010, 0x0FE00030, .V6, .A32, {}, {.NONE,.NONE} }, + { .USAT, {.GPR,.IMM4_SAT,.GPR_SHIFTED,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3800000, 0xFFD08020, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SSAT16 - { .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {} }, - { .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06A00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SSAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3200000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USAT16 - { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {} }, - { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD,.SAT_IMM5,.RM_A32,.NONE}, 0x06E00F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .USAT16, {.GPR,.IMM4_SAT,.GPR,.NONE}, {.RD_T32,.SAT_IMM5_T32,.RN_T32,.NONE}, 0xF3A00000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QADD - { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {} }, - { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01000050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .QADD, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F080, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QSUB - { .QSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01200050, 0x0FF000F0, .V5TE, .A32, {} }, - { .QSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01200050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .QSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F0A0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QDADD - { .QDADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01400050, 0x0FF000F0, .V5TE, .A32, {} }, - { .QDADD, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QDADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01400050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .QDADD, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F090, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QDSUB - { .QDSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {} }, - { .QDSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QDSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RM_A32,.RN_A32,.NONE}, 0x01600050, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, + { .QDSUB, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RM_T32,.RN_T32,.NONE}, 0xFA80F0B0, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SADD8 - { .SADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F90, 0x0FF00FF0, .V6, .A32, {} }, - { .SADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SADD16 - { .SADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F10, 0x0FF00FF0, .V6, .A32, {} }, - { .SADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SASX - { .SASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F30, 0x0FF00FF0, .V6, .A32, {} }, - { .SASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SSAX - { .SSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F50, 0x0FF00FF0, .V6, .A32, {} }, - { .SSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SSUB8 - { .SSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .SSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SSUB16 - { .SSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F70, 0x0FF00FF0, .V6, .A32, {} }, - { .SSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06100F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UADD8 - { .UADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F90, 0x0FF00FF0, .V6, .A32, {} }, - { .UADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UADD16 - { .UADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F10, 0x0FF00FF0, .V6, .A32, {} }, - { .UADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UASX - { .UASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F30, 0x0FF00FF0, .V6, .A32, {} }, - { .UASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USAX - { .USAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F50, 0x0FF00FF0, .V6, .A32, {} }, - { .USAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .USAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .USAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USUB8 - { .USUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .USUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .USUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .USUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .USUB16 - { .USUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F70, 0x0FF00FF0, .V6, .A32, {} }, - { .USUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .USUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06500F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .USUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F040, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QADD8 - { .QADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F90, 0x0FF00FF0, .V6, .A32, {} }, - { .QADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QADD16 - { .QADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F10, 0x0FF00FF0, .V6, .A32, {} }, - { .QADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QASX - { .QASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F30, 0x0FF00FF0, .V6, .A32, {} }, - { .QASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QSAX - { .QSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F50, 0x0FF00FF0, .V6, .A32, {} }, - { .QSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QSUB8 - { .QSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .QSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .QSUB16 - { .QSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F70, 0x0FF00FF0, .V6, .A32, {} }, - { .QSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .QSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06200F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .QSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F010, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQADD8 - { .UQADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F90, 0x0FF00FF0, .V6, .A32, {} }, - { .UQADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQADD16 - { .UQADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F10, 0x0FF00FF0, .V6, .A32, {} }, - { .UQADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQASX - { .UQASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F30, 0x0FF00FF0, .V6, .A32, {} }, - { .UQASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQSAX - { .UQSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F50, 0x0FF00FF0, .V6, .A32, {} }, - { .UQSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQSUB8 - { .UQSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .UQSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UQSUB16 - { .UQSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F70, 0x0FF00FF0, .V6, .A32, {} }, - { .UQSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UQSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06600F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UQSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F050, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHADD8 - { .SHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F90, 0x0FF00FF0, .V6, .A32, {} }, - { .SHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHADD16 - { .SHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F10, 0x0FF00FF0, .V6, .A32, {} }, - { .SHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHASX - { .SHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F30, 0x0FF00FF0, .V6, .A32, {} }, - { .SHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHSAX - { .SHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F50, 0x0FF00FF0, .V6, .A32, {} }, - { .SHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHSUB8 - { .SHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .SHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SHSUB16 - { .SHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F70, 0x0FF00FF0, .V6, .A32, {} }, - { .SHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .SHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06300F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F020, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHADD8 - { .UHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F90, 0x0FF00FF0, .V6, .A32, {} }, - { .UHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F90, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHADD8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA80F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHADD16 - { .UHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F10, 0x0FF00FF0, .V6, .A32, {} }, - { .UHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F10, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHADD16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFA90F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHASX - { .UHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F30, 0x0FF00FF0, .V6, .A32, {} }, - { .UHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F30, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHASX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAA0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHSAX - { .UHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F50, 0x0FF00FF0, .V6, .A32, {} }, - { .UHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F50, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHSAX, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAE0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHSUB8 - { .UHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700FF0, 0x0FF00FF0, .V6, .A32, {} }, - { .UHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700FF0, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHSUB8, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAC0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UHSUB16 - { .UHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F70, 0x0FF00FF0, .V6, .A32, {} }, - { .UHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .UHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x06700F70, 0x0FF00FF0, .V6, .A32, {}, {.NONE,.NONE} }, + { .UHSUB16, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFAD0F060, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SMUAD - { .SMUAD, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F010, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMUAD, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F010, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMUADX - { .SMUADX, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F030, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMUADX, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F030, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMUSD - { .SMUSD, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F050, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMUSD, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F050, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMUSDX - { .SMUSDX, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F070, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMUSDX, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0700F070, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLAD - { .SMLAD, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000010, 0x0FF000F0, .V6, .A32, {} }, + { .SMLAD, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLADX - { .SMLADX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000030, 0x0FF000F0, .V6, .A32, {} }, + { .SMLADX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLSD - { .SMLSD, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000050, 0x0FF000F0, .V6, .A32, {} }, + { .SMLSD, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000050, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLSDX - { .SMLSDX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000070, 0x0FF000F0, .V6, .A32, {} }, + { .SMLSDX, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07000070, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLALD - { .SMLALD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400010, 0x0FF000F0, .V6, .A32, {} }, + { .SMLALD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLALDX - { .SMLALDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400030, 0x0FF000F0, .V6, .A32, {} }, + { .SMLALDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLSLD - { .SMLSLD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400050, 0x0FF000F0, .V6, .A32, {} }, + { .SMLSLD, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400050, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLSLDX - { .SMLSLDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400070, 0x0FF000F0, .V6, .A32, {} }, + { .SMLSLDX, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x07400070, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMUL - { .SMMUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F010, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMMUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F010, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMULR - { .SMMULR, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F030, 0x0FF0F0F0, .V6, .A32, {} }, + { .SMMULR, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0750F030, 0x0FF0F0F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMLA - { .SMMLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500010, 0x0FF000F0, .V6, .A32, {} }, + { .SMMLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500010, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMLAR - { .SMMLAR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500030, 0x0FF000F0, .V6, .A32, {} }, + { .SMMLAR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x07500030, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMLS - { .SMMLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000D0, 0x0FF000F0, .V6, .A32, {} }, + { .SMMLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000D0, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMMLSR - { .SMMLSR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000F0, 0x0FF000F0, .V6, .A32, {} }, + { .SMMLSR, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x075000F0, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .MUL - { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {} }, - { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00100090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .MUL, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004340, 0x0000FFC0, .THUMB, .T32, {} }, - { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true} }, + { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00100090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MUL, {.GPR_LOW,.GPR_LOW,.NONE,.NONE}, {.RD_T16_LO,.RM_T16_LO,.NONE,.NONE}, 0x00004340, 0x0000FFC0, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB00F000, 0xFFF0F0F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MLA - { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00200090, 0x0FE000F0, .BASE, .A32, {} }, - { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00300090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RD_T32,.RN_T32,.RM_T32,.RA_T32}, 0xFB000000, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00200090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00300090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .MLA, {.GPR,.GPR,.GPR,.GPR}, {.RD_T32,.RN_T32,.RM_T32,.RA_T32}, 0xFB000000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MLS - { .MLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {} }, - { .MLS, {.GPR,.GPR,.GPR,.GPR}, {.RD_T32,.RN_T32,.RM_T32,.RA_T32}, 0xFB000010, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .MLS, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x00600090, 0x0FF000F0, .V6T2, .A32, {}, {.NONE,.NONE} }, + { .MLS, {.GPR,.GPR,.GPR,.GPR}, {.RD_T32,.RN_T32,.RM_T32,.RA_T32}, 0xFB000010, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UMULL - { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {} }, - { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00900090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBA00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00800090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00900090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .UMULL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBA00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UMLAL - { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00A00090, 0x0FE000F0, .BASE, .A32, {} }, - { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00B00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBE00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00A00090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00B00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .UMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBE00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SMULL - { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00C00090, 0x0FE000F0, .BASE, .A32, {} }, - { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00D00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFB800000, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00C00090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00D00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SMULL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFB800000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SMLAL - { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00E00090, 0x0FE000F0, .BASE, .A32, {} }, - { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true} }, - { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBC00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00E00090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, + { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RT_T32,.RD_T32,.RN_T32,.RM_T32}, 0xFBC00000, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UMAAL - { .UMAAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {} }, + { .UMAAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00400090, 0x0FF000F0, .V6, .A32, {}, {.NONE,.NONE} }, // .SMLABB - { .SMLABB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLABB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x01000080, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLABT - { .SMLABT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLABT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000C0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLATB - { .SMLATB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000A0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLATB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000A0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLATT - { .SMLATT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000E0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLATT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x010000E0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLAWB - { .SMLAWB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x01200080, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLAWB, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x01200080, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLAWT - { .SMLAWT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x012000C0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLAWT, {.GPR,.GPR,.GPR,.GPR}, {.RN_A32,.RM_A32,.RS_A32,.RD}, 0x012000C0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULBB - { .SMULBB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x01600080, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULBB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x01600080, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULBT - { .SMULBT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000C0, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULBT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000C0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULTB - { .SMULTB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULTB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000A0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULTT - { .SMULTT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULTT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x016000E0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULWB - { .SMULWB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x012000A0, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULWB, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x012000A0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMULWT - { .SMULWT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x012000E0, 0x0FF0F0F0, .V5TE, .A32, {} }, + { .SMULWT, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x012000E0, 0x0FF0F0F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLALBB - { .SMLALBB, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x01400080, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLALBB, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x01400080, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLALBT - { .SMLALBT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000C0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLALBT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000C0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLALTB - { .SMLALTB, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLALTB, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000A0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SMLALTT - { .SMLALTT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {} }, + { .SMLALTT, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x014000E0, 0x0FF000F0, .V5TE, .A32, {}, {.NONE,.NONE} }, // .SDIV - { .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0710F010, 0x0FF0F0F0, .DIV, .A32, {} }, - { .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB90F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true} }, + { .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0710F010, 0x0FF0F0F0, .DIV, .A32, {}, {.NONE,.NONE} }, + { .SDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB90F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true}, {.NONE,.NONE} }, // .UDIV - { .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0730F010, 0x0FF0F0F0, .DIV, .A32, {} }, - { .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFBB0F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true} }, + { .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x0730F010, 0x0FF0F0F0, .DIV, .A32, {}, {.NONE,.NONE} }, + { .UDIV, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFBB0F0F0, 0xFFF0F0F0, .DIV, .T32, {thumb32=true}, {.NONE,.NONE} }, // .B - { .B, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true} }, - { .B, {.REL8,.COND,.NONE,.NONE}, {.BRANCH_8_T16,.NONE,.NONE,.NONE}, 0x0000D000, 0x0000F000, .THUMB, .T32, {branch=true, cond_branch=true, writes_pc=true} }, - { .B, {.REL11,.NONE,.NONE,.NONE}, {.BRANCH_11_T16,.NONE,.NONE,.NONE}, 0x0000E000, 0x0000F800, .THUMB, .T32, {branch=true, writes_pc=true} }, - { .B, {.REL20,.COND,.NONE,.NONE}, {.BRANCH_20_T32,.NONE,.NONE,.NONE}, 0xF0008000, 0xF800D000, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, thumb32=true} }, - { .B, {.REL24_T32,.NONE,.NONE,.NONE}, {.BRANCH_24_T32,.NONE,.NONE,.NONE}, 0xF0009000, 0xF800D000, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true} }, + { .B, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .B, {.REL8,.COND,.NONE,.NONE}, {.BRANCH_8_T16,.NONE,.NONE,.NONE}, 0x0000D000, 0x0000F000, .THUMB, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .B, {.REL11,.NONE,.NONE,.NONE}, {.BRANCH_11_T16,.NONE,.NONE,.NONE}, 0x0000E000, 0x0000F800, .THUMB, .T32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .B, {.REL20,.COND,.NONE,.NONE}, {.BRANCH_20_T32,.NONE,.NONE,.NONE}, 0xF0008000, 0xF800D000, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, + { .B, {.REL24_T32,.NONE,.NONE,.NONE}, {.BRANCH_24_T32,.NONE,.NONE,.NONE}, 0xF0009000, 0xF800D000, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, // .BL - { .BL, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true} }, - { .BL, {.REL24_T32,.NONE,.NONE,.NONE}, {.BRANCH_24_T32,.NONE,.NONE,.NONE}, 0xF000D000, 0xF800D000, .THUMB, .T32, {branch=true, writes_pc=true, thumb32=true} }, + { .BL, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .BL, {.REL24_T32,.NONE,.NONE,.NONE}, {.BRANCH_24_T32,.NONE,.NONE,.NONE}, 0xF000D000, 0xF800D000, .THUMB, .T32, {branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, // .BX - { .BX, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF10, 0x0FFFFFF0, .BASE, .A32, {branch=true, writes_pc=true} }, - { .BX, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004700, 0x0000FF87, .THUMB, .T32, {branch=true, writes_pc=true} }, + { .BX, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF10, 0x0FFFFFF0, .BASE, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .BX, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004700, 0x0000FF87, .THUMB, .T32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, // .BLX - { .BLX, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF30, 0x0FFFFFF0, .V5T, .A32, {branch=true, writes_pc=true} }, - { .BLX, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true} }, - { .BLX, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004780, 0x0000FF87, .V5T, .T32, {branch=true, writes_pc=true} }, + { .BLX, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF30, 0x0FFFFFF0, .V5T, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .BLX, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, + { .BLX, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004780, 0x0000FF87, .V5T, .T32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, // .BXJ - { .BXJ, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF20, 0x0FFFFFF0, .V5TEJ, .A32, {branch=true, writes_pc=true, deprecated=true} }, + { .BXJ, {.GPR,.NONE,.NONE,.NONE}, {.RM_A32,.NONE,.NONE,.NONE}, 0x012FFF20, 0x0FFFFFF0, .V5TEJ, .A32, {branch=true, writes_pc=true, deprecated=true}, {.NONE,.NONE} }, // .CBZ - { .CBZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B100, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true} }, + { .CBZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B100, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, // .CBNZ - { .CBNZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B900, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true} }, + { .CBNZ, {.GPR_LOW,.REL8,.NONE,.NONE}, {.RD_T16_LO,.BRANCH_CBZ,.NONE,.NONE}, 0x0000B900, 0x0000FD00, .V6T2, .T32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, // .TBB - { .TBB, {.GPR,.GPR,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xE8D0F000, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true} }, + { .TBB, {.GPR,.GPR,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xE8D0F000, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, // .TBH - { .TBH, {.GPR,.GPR,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xE8D0F010, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true} }, + { .TBH, {.GPR,.GPR,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xE8D0F010, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, // .MSR - { .MSR, {.PSR_FIELD,.IMM_MOD,.NONE,.NONE}, {.PSR_FIELD_MASK,.A32_IMM_MOD,.NONE,.NONE}, 0x0320F000, 0x0FB0F000, .BASE, .A32, {} }, - { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RM_A32,.NONE,.NONE}, 0x0120F000, 0x0FB0FFF0, .BASE, .A32, {} }, - { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RN_T32,.NONE,.NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true} }, + { .MSR, {.PSR_FIELD,.IMM_MOD,.NONE,.NONE}, {.PSR_FIELD_MASK,.A32_IMM_MOD,.NONE,.NONE}, 0x0320F000, 0x0FB0F000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RM_A32,.NONE,.NONE}, 0x0120F000, 0x0FB0FFF0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RN_T32,.NONE,.NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MRS - { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {} }, - { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true} }, + { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CPS - { .CPS, {.IMM_IFLAGS,.NONE,.NONE,.NONE}, {.CPS_IFLAGS,.NONE,.NONE,.NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {} }, + { .CPS, {.IMM_IFLAGS,.NONE,.NONE,.NONE}, {.CPS_IFLAGS,.NONE,.NONE,.NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {}, {.NONE,.NONE} }, // .SETEND - { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true} }, + { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} }, // .NOP - { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {} }, - { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {} }, - { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8000, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true} }, + { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8000, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .YIELD - { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F001, 0x0FFFFFFF, .V6K, .A32, {} }, - { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF10, 0x0000FFFF, .V6T2, .T32, {} }, - { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8001, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true} }, + { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F001, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF10, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .YIELD, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8001, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .WFE - { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F002, 0x0FFFFFFF, .V6K, .A32, {} }, - { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF20, 0x0000FFFF, .V6T2, .T32, {} }, - { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8002, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true} }, + { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F002, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF20, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .WFE, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8002, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .WFI - { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F003, 0x0FFFFFFF, .V6K, .A32, {} }, - { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF30, 0x0000FFFF, .V6T2, .T32, {} }, - { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8003, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true} }, + { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F003, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF30, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .WFI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8003, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SEV - { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F004, 0x0FFFFFFF, .V6K, .A32, {} }, - { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF40, 0x0000FFFF, .V6T2, .T32, {} }, - { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8004, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true} }, + { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F004, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF40, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, + { .SEV, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8004, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SEVL - { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {} }, + { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, // .DBG - { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {} }, + { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, // .HINT - { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {} }, + { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, // .DMB - { .DMB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF050, 0xFFFFFFF0, .V7, .A32, {} }, - { .DMB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F50, 0xFFFFFFF0, .V7, .T32, {thumb32=true} }, + { .DMB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF050, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, + { .DMB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F50, 0xFFFFFFF0, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .DSB - { .DSB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF040, 0xFFFFFFF0, .V7, .A32, {} }, - { .DSB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F40, 0xFFFFFFF0, .V7, .T32, {thumb32=true} }, + { .DSB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF040, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, + { .DSB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F40, 0xFFFFFFF0, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ISB - { .ISB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF060, 0xFFFFFFF0, .V7, .A32, {} }, - { .ISB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F60, 0xFFFFFFF0, .V7, .T32, {thumb32=true} }, + { .ISB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF57FF060, 0xFFFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, + { .ISB, {.IMM_BARRIER,.NONE,.NONE,.NONE}, {.BARRIER_TYPE,.NONE,.NONE,.NONE}, 0xF3BF8F60, 0xFFFFFFF0, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CLREX - { .CLREX, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF01F, 0xFFFFFFFF, .V6K, .A32, {} }, - { .CLREX, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3BF8F2F, 0xFFFFFFFF, .V6K, .T32, {thumb32=true} }, + { .CLREX, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF01F, 0xFFFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .CLREX, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3BF8F2F, 0xFFFFFFFF, .V6K, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PLD - { .PLD, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V5T, .A32, {} }, - { .PLD, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF890F000, 0xFFF0F000, .V6T2, .T32, {thumb32=true} }, + { .PLD, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V5T, .A32, {}, {.NONE,.NONE} }, + { .PLD, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF890F000, 0xFFF0F000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PLDW - { .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {} }, - { .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true} }, + { .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF5D0F000, 0xFFF0F000, .V7, .A32, {}, {.NONE,.NONE} }, + { .PLDW, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF830F000, 0xFFF0F000, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PLI - { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {} }, - { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true} }, + { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF4D0F000, 0xFF70F000, .V7, .A32, {}, {.NONE,.NONE} }, + { .PLI, {.MEM,.NONE,.NONE,.NONE}, {.MEM_IMM12_OFFSET,.NONE,.NONE,.NONE}, 0xF990F000, 0xFFF0F000, .V7, .T32, {thumb32=true}, {.NONE,.NONE} }, // .HLT - { .HLT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {} }, + { .HLT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {}, {.NONE,.NONE} }, // .DCPS1 - { .DCPS1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8001, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .DCPS1, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8001, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .DCPS2 - { .DCPS2, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8002, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .DCPS2, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8002, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .DCPS3 - { .DCPS3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8003, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .DCPS3, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF78F8003, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .ERET - { .ERET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0160006E, 0x0FFFFFFF, .V7VE, .A32, {writes_pc=true} }, + { .ERET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0160006E, 0x0FFFFFFF, .V7VE, .A32, {writes_pc=true}, {.NONE,.NONE} }, // .ESB - { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {} }, - { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8010, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8010, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PSB_CSYNC - { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {} }, - { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8011, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F011, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .PSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8011, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .TSB_CSYNC - { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {} }, - { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8012, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F012, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .TSB_CSYNC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8012, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CSDB - { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {} }, - { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8014, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF8014, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SB - { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF070, 0xFFFFFFFF, .V8, .A32, {} }, - { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3BF8F70, 0xFFFFFFFF, .V8, .T32, {thumb32=true} }, + { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF57FF070, 0xFFFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .SB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3BF8F70, 0xFFFFFFFF, .V8, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SETPAN - { .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xF1100000, 0xFFFFFDFF, .V8, .A32, {} }, - { .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0000B610, 0x0000FFF7, .V8, .T32, {} }, + { .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0xF1100000, 0xFFFFFDFF, .V8, .A32, {}, {.NONE,.NONE} }, + { .SETPAN, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0000B610, 0x0000FFF7, .V8, .T32, {}, {.NONE,.NONE} }, // .SVC - { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.A32_IMM24,.NONE,.NONE,.NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {} }, - { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DF00, 0x0000FF00, .THUMB, .T32, {} }, + { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.A32_IMM24,.NONE,.NONE,.NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DF00, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, // .BKPT - { .BKPT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1200070, 0xFFF000F0, .V5T, .A32, {} }, - { .BKPT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BE00, 0x0000FF00, .V5T, .T32, {} }, + { .BKPT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1200070, 0xFFF000F0, .V5T, .A32, {}, {.NONE,.NONE} }, + { .BKPT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BE00, 0x0000FF00, .V5T, .T32, {}, {.NONE,.NONE} }, // .HVC - { .HVC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1400070, 0xFFF000F0, .V7VE, .A32, {} }, + { .HVC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1400070, 0xFFF000F0, .V7VE, .A32, {}, {.NONE,.NONE} }, // .SMC - { .SMC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x01600070, 0x0FFFFFF0, .V7, .A32, {} }, + { .SMC, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x01600070, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, // .UDF - { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {} }, - { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {} }, - { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF7F0A000, 0xFFF0F000, .V6T2, .T32, {thumb32=true} }, + { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {}, {.NONE,.NONE} }, + { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000DE00, 0x0000FF00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF7F0A000, 0xFFF0F000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDR - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {} }, - { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_LITERAL,.NONE,.NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {} }, - { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {} }, - { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {} }, - { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009800, 0x0000F800, .THUMB, .T32, {} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8D00000, 0xFFF00000, .V6T2, .T32, {thumb32=true} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8500000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true} }, - { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_LITERAL,.NONE,.NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04900000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07900000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_LITERAL,.NONE,.NONE}, 0x00004800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005800, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8D00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8500000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_LITERAL,.NONE,.NONE}, 0xF85F0000, 0xFF7F0000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STR - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {} }, - { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {} }, - { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {} }, - { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8C00000, 0xFFF00000, .V6T2, .T32, {thumb32=true} }, - { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04800000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07800000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005000, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00006000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STR, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_HI,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00009000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8C00000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8400000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRB - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {} }, - { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {} }, - { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8900000, 0xFFF00000, .V6T2, .T32, {thumb32=true} }, - { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04D00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07D00000, 0x0F700010, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005C00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x00007800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xF8900000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.MEM_REG_OFFSET,.NONE,.NONE}, 0xF8100000, 0xFFF00FC0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STRB - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05C00000, 0x0F700000, .BASE, .A32, {} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05E00000, 0x0F700000, .BASE, .A32, {} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04C00000, 0x0F700000, .BASE, .A32, {} }, - { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_REG_OFFSET,.NONE,.NONE}, 0x07C00000, 0x0F700010, .BASE, .A32, {} }, - { .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, {.RD_T16_LO,.MEM_REG_OFFSET,.NONE,.NONE}, 0x00005400, 0x0000FE00, .THUMB, .T32, {} }, - { .STRB, {.GPR_LOW,.MEM,.NONE,.NONE}, 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.T32, {thumb32=true}, {.NONE,.NONE} }, // .LDRT - { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {} }, + { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04B00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .STRT - { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {} }, + { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04A00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRBT - { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {} }, + { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04F00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .STRBT - { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {} }, + { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04E00000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRHT - { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {} }, + { .LDRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .STRHT - { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {} }, + { .STRHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00E000B0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRSBT - { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {} }, + { .LDRSBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000D0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDRSHT - { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {} }, + { .LDRSHT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x00F000F0, 0x0F7000F0, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDA - { .LDA, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDA, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STL - { .STL, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {} }, + { .STL, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x0180FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDAB - { .LDAB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00C9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLB - { .STLB, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01C0FC90, 0x0FF0FFF0, .V8, .A32, {} }, + { .STLB, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01C0FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDAH - { .LDAH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00C9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00C9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLH - { .STLH, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01E0FC90, 0x0FF0FFF0, .V8, .A32, {} }, + { .STLH, {.GPR,.MEM,.NONE,.NONE}, {.RM_A32,.RN_A32,.NONE,.NONE}, 0x01E0FC90, 0x0FF0FFF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDREX - { .LDREX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900F9F, 0x0FF00FFF, .V6K, .A32, {} }, - { .LDREX, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8500F00, 0xFFF00F00, .V6T2, .T32, {thumb32=true} }, + { .LDREX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .LDREX, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8500F00, 0xFFF00F00, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STREX - { .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {} }, - { .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8400000, 0xFFF00000, .V6T2, .T32, {thumb32=true} }, + { .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, + { .STREX, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8400000, 0xFFF00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDREXB - { .LDREXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00F9F, 0x0FF00FFF, .V6K, .A32, {} }, - { .LDREXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8D00F4F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true} }, + { .LDREXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .LDREXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8D00F4F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STREXB - { .STREXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00F90, 0x0FF00FF0, .V6K, .A32, {} }, - { .STREXB, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8C00F40, 0xFFF00FF0, .V6T2, .T32, {thumb32=true} }, + { .STREXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, + { .STREXB, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8C00F40, 0xFFF00FF0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDREXH - { .LDREXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00F9F, 0x0FF00FFF, .V6K, .A32, {} }, - { .LDREXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8D00F5F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true} }, + { .LDREXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .LDREXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_T32,.RN_T32,.NONE,.NONE}, 0xE8D00F5F, 0xFFF00FFF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STREXH - { .STREXH, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01E00F90, 0x0FF00FF0, .V6K, .A32, {} }, - { .STREXH, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8C00F50, 0xFFF00FF0, .V6T2, .T32, {thumb32=true} }, + { .STREXH, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01E00F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, + { .STREXH, {.GPR,.GPR,.MEM,.NONE}, {.RD_T32,.RT_T32,.RN_T32,.NONE}, 0xE8C00F50, 0xFFF00FF0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDREXD - { .LDREXD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01B00F9F, 0x0FF00FFF, .V6K, .A32, {} }, - { .LDREXD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE8D0007F, 0xFFF000FF, .V6T2, .T32, {thumb32=true} }, + { .LDREXD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01B00F9F, 0x0FF00FFF, .V6K, .A32, {}, {.NONE,.NONE} }, + { .LDREXD, {.GPR,.GPR,.MEM,.NONE}, {.RT_T32,.RT2_T32,.RN_T32,.NONE}, 0xE8D0007F, 0xFFF000FF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STREXD - { .STREXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00F90, 0x0FF00FF0, .V6K, .A32, {} }, - { .STREXD, {.GPR,.GPR,.GPR,.MEM}, {.RD_T32,.RT_T32,.RT2_T32,.RN_T32}, 0xE8C00070, 0xFFF000F0, .V6T2, .T32, {thumb32=true} }, + { .STREXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00F90, 0x0FF00FF0, .V6K, .A32, {}, {.NONE,.NONE} }, + { .STREXD, {.GPR,.GPR,.GPR,.MEM}, {.RD_T32,.RT_T32,.RT2_T32,.RN_T32}, 0xE8C00070, 0xFFF000F0, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .LDAEX - { .LDAEX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900E9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAEX, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01900E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLEX - { .STLEX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {} }, + { .STLEX, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01800E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDAEXB - { .LDAEXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00E9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAEXB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01D00E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLEXB - { .STLEXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00E90, 0x0FF00FF0, .V8, .A32, {} }, + { .STLEXB, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01C00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDAEXH - { .LDAEXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00E9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAEXH, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01F00E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLEXH - { .STLEXH, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01E00E90, 0x0FF00FF0, .V8, .A32, {} }, + { .STLEXH, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01E00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDAEXD - { .LDAEXD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01B00E9F, 0x0FF00FFF, .V8, .A32, {} }, + { .LDAEXD, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.RN_A32,.NONE,.NONE}, 0x01B00E9F, 0x0FF00FFF, .V8, .A32, {}, {.NONE,.NONE} }, // .STLEXD - { .STLEXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {} }, + { .STLEXD, {.GPR,.GPR,.MEM,.NONE}, {.RD,.RT_A32,.RN_A32,.NONE}, 0x01A00E90, 0x0FF00FF0, .V8, .A32, {}, {.NONE,.NONE} }, // .LDM - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {} }, - { .LDM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true} }, - { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C800, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8900000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9100000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .STM - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {} }, - { .STM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true} }, - { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .STM, {.GPR_LOW,.GPR_LIST,.NONE,.NONE}, {.RD_T16_HI,.A32_REG_LIST,.NONE,.NONE}, 0x0000C000, 0x0000F800, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE8800000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_T32,.A32_REG_LIST,.NONE,.NONE}, 0xE9000000, 0xFFD00000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PUSH - { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {} }, - { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {} }, - { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0xE92D0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true} }, + { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000B400, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0xE92D0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .POP - { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {} }, - { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000BC00, 0x0000FE00, .THUMB, .T32, {} }, - { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0xE8BD0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true} }, + { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x0000BC00, 0x0000FE00, .THUMB, .T32, {}, {.NONE,.NONE} }, + { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0xE8BD0000, 0xFFFF0000, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SWP - { .SWP, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true} }, + { .SWP, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} }, // .SWPB - { .SWPB, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true} }, + { .SWPB, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} }, // .RFE - { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {} }, + { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}, {.NONE,.NONE} }, // .SRS - { .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {} }, + { .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {}, {.NONE,.NONE} }, // .CDP - { .CDP, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {} }, + { .CDP, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}, {.NONE,.NONE} }, // .CDP2 - { .CDP2, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0xFE000000, 0xFF000010, .V5T, .A32, {} }, + { .CDP2, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0xFE000000, 0xFF000010, .V5T, .A32, {}, {.NONE,.NONE} }, // .MCR - { .MCR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {} }, + { .MCR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {}, {.NONE,.NONE} }, // .MCR2 - { .MCR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {} }, + { .MCR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {}, {.NONE,.NONE} }, // .MRC - { .MRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {} }, + { .MRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {}, {.NONE,.NONE} }, // .MRC2 - { .MRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {} }, + { .MRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {}, {.NONE,.NONE} }, // .MCRR - { .MCRR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {} }, + { .MCRR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, // .MCRR2 - { .MCRR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {} }, + { .MCRR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, // .MRRC - { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {} }, + { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, // .MRRC2 - { .MRRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {} }, + { .MRRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC500000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, // .LDC - { .LDC, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0x0C100000, 0x0F100000, .BASE, .A32, {} }, + { .LDC, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0x0C100000, 0x0F100000, .BASE, .A32, {}, {.NONE,.NONE} }, // .LDC2 - { .LDC2, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0xFC100000, 0xFF100000, .V5T, .A32, {} }, + { .LDC2, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0xFC100000, 0xFF100000, .V5T, .A32, {}, {.NONE,.NONE} }, // .STC - { .STC, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0x0C000000, 0x0F100000, .BASE, .A32, {} }, + { .STC, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0x0C000000, 0x0F100000, .BASE, .A32, {}, {.NONE,.NONE} }, // .STC2 - { .STC2, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0xFC000000, 0xFF100000, .V5T, .A32, {} }, + { .STC2, {.COPROC_NUM,.COPROC_REG,.MEM,.NONE}, {.COPROC_NUM_FIELD,.COPROC_CRN_FIELD,.MEM_IMM8_OFFSET,.NONE}, 0xFC000000, 0xFF100000, .V5T, .A32, {}, {.NONE,.NONE} }, // .CRC32B - { .CRC32B, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32B, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .CRC32H - { .CRC32H, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01200040, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32H, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01200040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .CRC32W - { .CRC32W, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01400040, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32W, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01400040, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .CRC32CB - { .CRC32CB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32CB, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01000240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .CRC32CH - { .CRC32CH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01200240, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32CH, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01200240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .CRC32CW - { .CRC32CW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01400240, 0x0FF00FF0, .CRC32, .A32, {} }, + { .CRC32CW, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x01400240, 0x0FF00FF0, .CRC32, .A32, {}, {.NONE,.NONE} }, // .VADD - { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200800, 0xFFB00F10, .NEON, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300800, 0xFFB00F10, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200840, 0xFFB00F50, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300840, 0xFFB00F50, .NEON, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000840, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VADD, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true} }, + { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200800, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300800, 0xFFB00F10, .NEON, .A32, {}, {.I64,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300840, 0xFFB00F50, .NEON, .A32, {}, {.I64,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000840, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VADD, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, // .VSUB - { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100800, 0xFFB00F10, .NEON, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200800, 0xFFB00F10, .NEON, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300800, 0xFFB00F10, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100840, 0xFFB00F50, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300840, 0xFFB00F50, .NEON, .A32, {} }, - { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D00, 0xFFB00F10, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000840, 0xFF810F51, .MVE_INT, .T32, {thumb32=true} }, - { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VSUB, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true} }, + { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200800, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300800, 0xFFB00F10, .NEON, .A32, {}, {.I64,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300840, 0xFFB00F50, .NEON, .A32, {}, {.I64,.NONE} }, + { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000840, 0xFF810F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200D40, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VSUB, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011F40, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, // .VMUL - { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D10, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100D50, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200910, 0xFFB00F10, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200950, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, - { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VMUL, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D10, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100D50, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200910, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200950, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000950, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VMUL, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A008C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VDIV - { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {} }, + { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, // .VMLA - { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200900, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200940, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VMLS - { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200900, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100900, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200900, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100940, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VNMUL - { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {} }, + { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, // .VNMLA - { .VNMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VNMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {} }, + { .VNMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, // .VNMLS - { .VNMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {} }, - { .VNMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {} }, + { .VNMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, // .VFMA - { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {} }, - { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {} }, - { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VFMA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {} }, + { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, + { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, + { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VFMA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE310E40, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VFMA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, // .VFMS - { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {} }, - { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {} }, - { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {} }, - { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true} }, - { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, - { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {} }, + { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, + { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, + { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VFMS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200C50, 0xEFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, + { .VFMS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, + { .VFMS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .VFPV4, .A32, {}, {.I32,.NONE} }, // .VFNMA - { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFNMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900940, 0x0FB00F50, .HALF_FP, .A32, {} }, + { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, + { .VFNMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, + { .VFNMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, // .VFNMS - { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFNMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {} }, - { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {} }, + { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, + { .VFNMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, + { .VFNMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E900900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, // .VABS - { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true} }, + { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB10340, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB90740, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VNEG - { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true} }, + { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB103C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB907C0, 0xFFBB0F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VSQRT - { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {} }, + { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, // .VCMP - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {} }, - { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {} }, - { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {} }, - { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {} }, - { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xFE010F00, 0xFE818FF0, .MVE_INT, .T32, {thumb32=true} }, - { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xFE010F00, 0xFE818FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, + { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VCMPE - { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {} }, - { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {} }, - { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {} }, - { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {} }, + { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMPE, {.SPR,.NONE,.NONE,.NONE}, {.VD_S,.NONE,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.NONE,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, // .VCVT - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.S32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.U32} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.S32} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} }, + { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.S16,.F32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FC0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.S16,.F16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S16} }, // .VCVTB - { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, + { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, // .VCVTT - { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, + { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, // .VCVTA - { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, + { .VCVTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTN - { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, + { .VCVTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTP - { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, + { .VCVTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTM - { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {} }, + { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, + { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, // .VCVTR - { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, + { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, + { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, + { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, + { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, // .VMOV - { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {} }, - { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {} }, - { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {} }, - { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {} }, - { .VMOV, {.GPR,.SPR,.NONE,.NONE}, {.RT_A32,.VN_S,.NONE,.NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {} }, - { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {} }, - { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {} }, - { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {} }, - { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {} }, - { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {} }, - { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, - { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true} }, - { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true} }, + { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, + { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.GPR,.SPR,.NONE,.NONE}, {.RT_A32,.VN_S,.NONE,.NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.GPR,.GPR,.SPR,.SPR}, {.RT_A32,.RT2_A32,.VM_S,.NONE}, 0x0C500A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.NONE,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, + { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, + { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMRS - { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {} }, + { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VMSR - { .VMSR, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {} }, + { .VMSR, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VLDR - { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {} }, - { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {} }, + { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VSTR - { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {} }, - { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {} }, + { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VLDM - { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {} }, - { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {} }, + { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VSTM - { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {} }, - { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {} }, + { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VPUSH - { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {} }, - { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {} }, + { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VPOP - { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {} }, - { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {} }, + { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VSEL - { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {} }, - { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {} }, + { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, + { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, // .VMAXNM - { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {} }, - { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {} }, + { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, + { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, // .VMINNM - { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {} }, - { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {} }, + { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, + { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, // .VRINTA - { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTA, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTA, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VRINTN - { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0440, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0440, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VRINTP - { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA07C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA07C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VRINTM - { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {} }, - { .VRINTM, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA06C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTM, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA06C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VRINTR - { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {} }, - { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {} }, + { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, // .VRINTZ - { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {} }, - { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {} }, - { .VRINTZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA05C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA05C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VRINTX - { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {} }, - { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {} }, - { .VRINTX, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA04C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTX, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA04C0, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VADDL - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {} }, - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900000, 0xFFB01F50, .NEON, .A32, {} }, - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00000, 0xFFB01F50, .NEON, .A32, {} }, - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800000, 0xFFB01F50, .NEON, .A32, {} }, - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900000, 0xFFB01F50, .NEON, .A32, {} }, - { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00000, 0xFFB01F50, .NEON, .A32, {} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900000, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00000, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800000, 0xFFB01F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900000, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00000, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VADDW - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {} }, - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2900100, 0xFFB11F50, .NEON, .A32, {} }, - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00100, 0xFFB11F50, .NEON, .A32, {} }, - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3800100, 0xFFB11F50, .NEON, .A32, {} }, - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900100, 0xFFB11F50, .NEON, .A32, {} }, - { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00100, 0xFFB11F50, .NEON, .A32, {} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2900100, 0xFFB11F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00100, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3800100, 0xFFB11F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900100, 0xFFB11F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00100, 0xFFB11F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VSUBL - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {} }, - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900200, 0xFFB01F50, .NEON, .A32, {} }, - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {} }, - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800200, 0xFFB01F50, .NEON, .A32, {} }, - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900200, 0xFFB01F50, .NEON, .A32, {} }, - { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900200, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800200, 0xFFB01F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900200, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VSUBW - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {} }, - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2900300, 0xFFB11F50, .NEON, .A32, {} }, - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00300, 0xFFB11F50, .NEON, .A32, {} }, - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3800300, 0xFFB11F50, .NEON, .A32, {} }, - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900300, 0xFFB11F50, .NEON, .A32, {} }, - { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00300, 0xFFB11F50, .NEON, .A32, {} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2900300, 0xFFB11F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00300, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3800300, 0xFFB11F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900300, 0xFFB11F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00300, 0xFFB11F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VHADD - { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {} }, - { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {} }, - { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200000, 0xFFB00F10, .NEON, .A32, {} }, - { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {} }, - { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {} }, - { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200040, 0xFFB00F50, .NEON, .A32, {} }, - { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {} }, - { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {} }, - { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000040, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200000, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200040, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000040, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000040, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VHSUB - { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {} }, - { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100200, 0xFFB00F10, .NEON, .A32, {} }, - { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200200, 0xFFB00F10, .NEON, .A32, {} }, - { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {} }, - { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100240, 0xFFB00F50, .NEON, .A32, {} }, - { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200240, 0xFFB00F50, .NEON, .A32, {} }, - { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {} }, - { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {} }, - { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000240, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100200, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200200, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000240, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000240, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VRHADD - { .VRHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000100, 0xFFB00F10, .NEON, .A32, {} }, - { .VRHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000140, 0xFFB00F50, .NEON, .A32, {} }, - { .VRHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000140, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000100, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VRHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000140, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VRHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000140, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQADD - { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000010, 0xFFB00F10, .NEON, .A32, {} }, - { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100010, 0xFFB00F10, .NEON, .A32, {} }, - { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200010, 0xFFB00F10, .NEON, .A32, {} }, - { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300010, 0xFFB00F10, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000050, 0xFFB00F50, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100050, 0xFFB00F50, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200050, 0xFFB00F50, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300050, 0xFFB00F50, .NEON, .A32, {} }, - { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000010, 0xFFB00F10, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000050, 0xFFB00F50, .NEON, .A32, {} }, - { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000050, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000010, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100010, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200010, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300010, 0xFFB00F10, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000050, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100050, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200050, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300050, 0xFFB00F50, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000010, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000050, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000050, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQSUB - { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000210, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100210, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200210, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300210, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000250, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100250, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200250, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300250, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000210, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000250, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000250, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000210, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100210, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200210, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300210, 0xFFB00F10, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000250, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100250, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200250, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300250, 0xFFB00F50, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000210, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000250, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000250, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMULL - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800C00, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VMLAL - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VMLSL - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VQDMULL - { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMLAL - { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMLSL - { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {} }, + { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMULH - { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {} }, - { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {} }, - { .VQDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {} }, - { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {} }, + { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQRDMULH - { .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100B00, 0xFFB00F10, .NEON, .A32, {} }, - { .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {} }, - { .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {} }, - { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {} }, + { .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100B00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQRDMULH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQRDMLAH - { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100B10, 0xFFB00F10, .V8, .A32, {} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {} }, - { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100B10, 0xFFB00F10, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, // .VQRDMLSH - { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {} }, - { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, // .VABA - { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {} }, - { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {} }, - { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200710, 0xFFB00F10, .NEON, .A32, {} }, - { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000750, 0xFFB00F50, .NEON, .A32, {} }, - { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100750, 0xFFB00F50, .NEON, .A32, {} }, - { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200750, 0xFFB00F50, .NEON, .A32, {} }, - { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000710, 0xFFB00F10, .NEON, .A32, {} }, - { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000750, 0xFFB00F50, .NEON, .A32, {} }, + { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200710, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000750, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100750, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200750, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000710, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VABA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000750, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, // .VABAL - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {} }, - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900500, 0xFFB01F50, .NEON, .A32, {} }, - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {} }, - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800500, 0xFFB01F50, .NEON, .A32, {} }, - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900500, 0xFFB01F50, .NEON, .A32, {} }, - { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900500, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800500, 0xFFB01F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900500, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VABD - { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000700, 0xFFB00F10, .NEON, .A32, {} }, - { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100700, 0xFFB00F10, .NEON, .A32, {} }, - { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200700, 0xFFB00F10, .NEON, .A32, {} }, - { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000740, 0xFFB00F50, .NEON, .A32, {} }, - { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100740, 0xFFB00F50, .NEON, .A32, {} }, - { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200740, 0xFFB00F50, .NEON, .A32, {} }, - { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {} }, - { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {} }, - { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200D00, 0xFFB00F10, .NEON, .A32, {} }, - { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200D40, 0xFFB00F50, .NEON, .A32, {} }, + { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000700, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100700, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200700, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000740, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, // .VABDL - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {} }, - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900700, 0xFFB01F50, .NEON, .A32, {} }, - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {} }, - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800700, 0xFFB01F50, .NEON, .A32, {} }, - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900700, 0xFFB01F50, .NEON, .A32, {} }, - { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900700, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800700, 0xFFB01F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900700, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VAND - { .VAND, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000110, 0xFFB00F10, .NEON, .A32, {} }, - { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000150, 0xFFB00F50, .NEON, .A32, {} }, - { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VAND, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VBIC - { .VBIC, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {} }, - { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {} }, - { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VBIC, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VORR - { .VORR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {} }, - { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {} }, - { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VORR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VORN - { .VORN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300110, 0xFFB00F10, .NEON, .A32, {} }, - { .VORN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300150, 0xFFB00F50, .NEON, .A32, {} }, - { .VORN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF300150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VORN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VORN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VORN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF300150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VEOR - { .VEOR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {} }, - { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {} }, - { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VEOR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VBSL - { .VBSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100110, 0xFFB00F10, .NEON, .A32, {} }, - { .VBSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100150, 0xFFB00F50, .NEON, .A32, {} }, + { .VBSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VBSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, // .VBIT - { .VBIT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200110, 0xFFB00F10, .NEON, .A32, {} }, - { .VBIT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200150, 0xFFB00F50, .NEON, .A32, {} }, + { .VBIT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VBIT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, // .VBIF - { .VBIF, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300110, 0xFFB00F10, .NEON, .A32, {} }, - { .VBIF, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300150, 0xFFB00F50, .NEON, .A32, {} }, + { .VBIF, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VBIF, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, // .VMVN - { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {} }, - { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB005C0, 0xFFB30F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMOVN - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} }, // .VQMOVN - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, // .VQMOVUN - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, // .VMOVL - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {} }, - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {} }, - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2A00A10, 0xFFB80FD0, .NEON, .A32, {} }, - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3880A10, 0xFFB80FD0, .NEON, .A32, {} }, - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3900A10, 0xFFB80FD0, .NEON, .A32, {} }, - { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3A00A10, 0xFFB80FD0, .NEON, .A32, {} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2900A10, 0xFFB80FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2A00A10, 0xFFB80FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3880A10, 0xFFB80FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3900A10, 0xFFB80FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3A00A10, 0xFFB80FD0, .NEON, .A32, {}, {.U32,.NONE} }, // .VTST - { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000810, 0xFFB00F10, .NEON, .A32, {} }, - { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100810, 0xFFB00F10, .NEON, .A32, {} }, - { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200810, 0xFFB00F10, .NEON, .A32, {} }, - { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000850, 0xFFB00F50, .NEON, .A32, {} }, - { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100850, 0xFFB00F50, .NEON, .A32, {} }, - { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200850, 0xFFB00F50, .NEON, .A32, {} }, + { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000810, 0xFFB00F10, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100810, 0xFFB00F10, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTST, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200810, 0xFFB00F10, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000850, 0xFFB00F50, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100850, 0xFFB00F50, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTST, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200850, 0xFFB00F50, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VCEQ - { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100810, 0xFFB00F10, .NEON, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200810, 0xFFB00F10, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100850, 0xFFB00F50, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100810, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200810, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100850, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGE - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000350, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100350, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200350, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000350, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100350, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200350, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCGT - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200340, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200E00, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3300E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3300E40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLE - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200350, 0xFFB11F51, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000350, 0xFFB11F51, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100310, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100350, 0xFFB11F51, .NEON, .A32, {}, {.U16,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VCLT - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200340, 0xFFB11F51, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000340, 0xFFB11F51, .NEON, .A32, {}, {.U8,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100300, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100340, 0xFFB11F51, .NEON, .A32, {}, {.U16,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VACGE - { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {} }, - { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {} }, + { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, // .VACGT - { .VACGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200E10, 0xFFB00F10, .NEON, .A32, {} }, - { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {} }, + { .VACGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, // .VACLE - { .VACLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {} }, - { .VACLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {} }, + { .VACLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VACLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, // .VACLT - { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {} }, - { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {} }, + { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, // .VMAX - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000640, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000640, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000640, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMIN - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000650, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000650, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000650, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2300F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000650, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VPMAX - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, // .VPMIN - { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200F00, 0xFFB00F10, .NEON, .A32, {} }, + { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, // .VPADD - { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000B10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {} }, - { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {} }, + { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000B10, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B10, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, // .VPADDL - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, // .VPADAL - { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, // .VRECPE - { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VRECPS - { .VRECPS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F10, 0xFFB00F10, .NEON, .A32, {} }, - { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {} }, + { .VRECPS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, // .VRSQRTE - { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VRSQRTS - { .VRSQRTS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F10, 0xFFB00F10, .NEON, .A32, {} }, - { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {} }, + { .VRSQRTS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, // .VSHL - { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000400, 0xFFB00F10, .NEON, .A32, {} }, - { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100400, 0xFFB00F10, .NEON, .A32, {} }, - { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200400, 0xFFB00F10, .NEON, .A32, {} }, - { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2300400, 0xFFB00F10, .NEON, .A32, {} }, - { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {} }, - { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2300440, 0xFFB00F50, .NEON, .A32, {} }, - { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {} }, - { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000440, 0xFFB00F50, .NEON, .A32, {} }, - { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000440, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000400, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100400, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, + { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200400, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2300400, 0xFFB00F10, .NEON, .A32, {}, {.S64,.NONE} }, + { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2300440, 0xFFB00F50, .NEON, .A32, {}, {.S64,.NONE} }, + { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000440, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000440, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VSHR - { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {} }, - { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {} }, - { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {} }, - { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {} }, - { .VSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true} }, + { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800010, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800050, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800050, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VSRA - { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {} }, - { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {} }, - { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {} }, - { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {} }, - { .VSRA, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true} }, + { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800110, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800150, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRA, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800150, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VRSHL - { .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {} }, - { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000540, 0xFFB00F50, .NEON, .A32, {} }, - { .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000500, 0xFFB00F10, .NEON, .A32, {} }, - { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000540, 0xFFB00F50, .NEON, .A32, {} }, - { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000540, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000500, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000540, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000500, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000540, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000540, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VRSHR - { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {} }, - { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {} }, - { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {} }, - { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {} }, - { .VRSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800210, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800250, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSHR, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEF800250, 0xEF800F51, .MVE_INT, .T32, {thumb32=true}, {.I32,.NONE} }, // .VRSRA - { .VRSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {} }, - { .VRSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {} }, + { .VRSRA, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800310, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VRSRA, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800350, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VSLI - { .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {} }, - { .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {} }, + { .VSLI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800510, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSLI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800550, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VSRI - { .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {} }, - { .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {} }, + { .VSRI, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800410, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VSRI, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800450, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VQSHL - { .VQSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000410, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000410, 0xFFB00F10, .NEON, .A32, {} }, - { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000450, 0xFFB00F50, .NEON, .A32, {} }, - { .VQSHL, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800710, 0xFE800F10, .NEON, .A32, {} }, - { .VQSHL, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {} }, - { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000410, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000410, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000450, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQSHL, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800710, 0xFE800F10, .NEON, .A32, {}, {.I32,.NONE} }, + { .VQSHL, {.QPR,.QPR,.IMM,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800750, 0xFE800F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000450, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQSHRN - { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {} }, - { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {} }, + { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQSHRUN - { .VQSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {} }, + { .VQSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800810, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQRSHL - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2300510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2300550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {} }, - { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3300510, 0xFFB00F50, .NEON, .A32, {} }, - { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000550, 0xFFB11F51, .NEON, .A32, {}, {.S8,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2200550, 0xFFB11F51, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2300510, 0xFFB00F50, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2300550, 0xFFB11F51, .NEON, .A32, {}, {.S64,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3000550, 0xFFB11F51, .NEON, .A32, {}, {.U8,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3100510, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3100550, 0xFFB11F51, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3300510, 0xFFB00F50, .NEON, .A32, {}, {.U64,.NONE} }, + { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3300550, 0xFFB11F51, .NEON, .A32, {}, {.U64,.NONE} }, // .VQRSHRN - { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {} }, - { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {} }, + { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VQRSHRUN - { .VQRSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {} }, + { .VQRSHRUN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF3800850, 0xFF800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VSHRN - { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {} }, + { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VRSHRN - { .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {} }, + { .VRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800850, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, // .VSHLL - { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {} }, - { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF2800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHIFT_IMM6,.NONE}, 0xF3800A10, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, // .VCLS - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, // .VCLZ - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, // .VCNT - { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VPADD_F - { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {} }, - { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {} }, + { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VPADD_F, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, // .VRECPE_F - { .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VRSQRTE_F - { .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, // .VREV16 - { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VREV32 - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, // .VREV64 - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VEXT - { .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {} }, - { .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {} }, + { .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {}, {.SZ64,.NONE} }, // .VTBL - { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {} }, + { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VTBX - { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {} }, + { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VTRN - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VUZP - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VZIP - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {} }, - { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VDUP - { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {} }, - { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {} }, - { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {} }, - { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {} }, - { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true} }, + { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, // .VSWP - { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {} }, + { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, // .VMOV_LANE - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {} }, + { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, + { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, + { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, // .VLD1 - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD2 - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD3 - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD4 - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VST1 - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST2 - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VST3 - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {} }, - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VST4 - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {} }, - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, // .AESE - { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {} }, + { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .AESD - { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {} }, + { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .AESMC - { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {} }, + { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .AESIMC - { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {} }, + { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1H - { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {} }, + { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1SU0 - { .SHA1SU0, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA1SU0, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2300C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1SU1 - { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {} }, + { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1C - { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1M - { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA1P - { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA256H - { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA256H2 - { .SHA256H2, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA256H2, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA256SU0 - { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {} }, + { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .SHA256SU1 - { .SHA256SU1, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {} }, + { .SHA256SU1, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .VJCVT - { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {} }, + { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, // .VSDOT - { .VSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {} }, - { .VSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {} }, - { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {} }, - { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {} }, + { .VSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, + { .VSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, + { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, + { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, // .VUDOT - { .VUDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {} }, - { .VUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {} }, - { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {} }, - { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {} }, + { .VUDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, + { .VUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, + { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, + { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, // .VDOT - { .VDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {} }, - { .VDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {} }, + { .VDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {}, {.BF16,.NONE} }, + { .VDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, // .VMMLA - { .VMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {} }, + { .VMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000C40, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, // .VFMAL - { .VFMAL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {} }, - { .VFMAL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {} }, + { .VFMAL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200810, 0xFFB00F10, .FHM, .A32, {}, {.NONE,.NONE} }, + { .VFMAL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, // .VFMSL - { .VFMSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {} }, - { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {} }, + { .VFMSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.NONE,.NONE} }, + { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, // .VCMLA - { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {} }, - { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {} }, - { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {} }, - { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {} }, - { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true} }, + { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true}, {.F16,.NONE} }, // .VCADD - { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {} }, - { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {} }, + { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, // .VSMMLA - { .VSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {} }, + { .VSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, // .VUMMLA - { .VUMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C50, 0xFFB00F50, .V8, .A32, {} }, + { .VUMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200C50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, // .VUSMMLA - { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {} }, + { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, // .VSUDOT - { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {} }, - { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {} }, + { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {}, {.NONE,.NONE} }, + { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, // .VUSDOT - { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {} }, - { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {} }, - { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {} }, - { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {} }, + { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, // .VQABS - { .VQABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQNEG - { .VQNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB007C0, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB007C0, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMOVX - { .VMOVX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00A40, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true} }, + { .VMOVX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00A40, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true}, {.F16,.NONE} }, // .VINS - { .VINS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00AC0, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true} }, + { .VINS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB00AC0, 0xFFBF0FD0, .HALF_FP, .T32, {thumb32=true}, {.F16,.NONE} }, // .VLD2R - { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {} }, + { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD3R - { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {} }, + { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD4R - { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {} }, + { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD1_LANE - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {} }, + { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD2_LANE - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD3_LANE - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD4_LANE - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST1_LANE - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {} }, + { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST2_LANE - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {} }, + { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST3_LANE - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {} }, + { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST4_LANE - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {} }, + { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .IT - { .IT, {.COND,.IMM4,.NONE,.NONE}, {.NONE,.IT_MASK,.NONE,.NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {} }, + { .IT, {.COND,.IMM4,.NONE,.NONE}, {.NONE,.IT_MASK,.NONE,.NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {}, {.NONE,.NONE} }, // .TT - { .TT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F000, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true} }, + { .TT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F000, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .TTT - { .TTT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F040, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true} }, + { .TTT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F040, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .TTA - { .TTA, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F080, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true} }, + { .TTA, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F080, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .TTAT - { .TTAT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F0C0, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true} }, + { .TTAT, {.GPR,.GPR,.NONE,.NONE}, {.RD_T32,.RN_T32,.NONE,.NONE}, 0xE840F0C0, 0xFFF0F0C0, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .SG - { .SG, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true} }, + { .SG, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .BXNS - { .BXNS, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004704, 0x0000FF87, .V8M_SE, .T32, {branch=true} }, + { .BXNS, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004704, 0x0000FF87, .V8M_SE, .T32, {branch=true}, {.NONE,.NONE} }, // .BLXNS - { .BLXNS, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004784, 0x0000FF87, .V8M_SE, .T32, {branch=true} }, + { .BLXNS, {.GPR,.NONE,.NONE,.NONE}, {.RM_T16_HI,.NONE,.NONE,.NONE}, 0x00004784, 0x0000FF87, .V8M_SE, .T32, {branch=true}, {.NONE,.NONE} }, // .PAC - { .PAC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF801D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, + { .PAC, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF801D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .PACBTI - { .PACBTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF800D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, + { .PACBTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF800D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .AUT - { .AUT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF802D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, + { .AUT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF802D, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .AUTG - { .AUTG, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB50F000, 0xFFF0F0F0, .V81M, .T32, {thumb32=true} }, + { .AUTG, {.GPR,.GPR,.GPR,.NONE}, {.RD_T32,.RN_T32,.RM_T32,.NONE}, 0xFB50F000, 0xFFF0F0F0, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .BTI - { .BTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF80F0, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, + { .BTI, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF3AF80F0, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .WLS - { .WLS, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {branch=true, thumb32=true} }, + { .WLS, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .WLSTP - { .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {branch=true, thumb32=true} }, + { .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {branch=true, thumb32=true}, {.SZ8,.NONE} }, // .DLS - { .DLS, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true} }, + { .DLS, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .DLSTP - { .DLSTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true} }, + { .DLSTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .LE - { .LE, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} }, + { .LE, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .LETP - { .LETP, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} }, + { .LETP, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .LCTP - { .LCTP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, + { .LCTP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true}, {.NONE,.NONE} }, // .BF - { .BF, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} }, + { .BF, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .BFX - { .BFX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, + { .BFX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .BFL - { .BFL, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} }, + { .BFL, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true}, {.SZ8,.NONE} }, // .BFLX - { .BFLX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, + { .BFLX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true}, {.NONE,.NONE} }, // .BFCSEL - { .BFCSEL, {.REL_BF,.REL_BF,.IMM4,.NONE}, {.BF_BOFF,.BF_BLOC,.BFCSEL_COND,.NONE}, 0xF002E001, 0xF843F001, .V81M, .T32, {branch=true, thumb32=true} }, + { .BFCSEL, {.REL_BF,.REL_BF,.IMM4,.NONE}, {.BF_BOFF,.BF_BLOC,.BFCSEL_COND,.NONE}, 0xF002E001, 0xF843F001, .V81M, .T32, {branch=true, thumb32=true}, {.SZ8,.NONE} }, // .CX1 - { .CX1, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xEE000000, 0xFF800000, .CDE, .T32, {thumb32=true} }, + { .CX1, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xEE000000, 0xFF800000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX1A - { .CX1A, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xFE000000, 0xFF800000, .CDE, .T32, {thumb32=true} }, + { .CX1A, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xFE000000, 0xFF800000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX1D - { .CX1D, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xEE800000, 0xFF800000, .CDE, .T32, {thumb32=true} }, + { .CX1D, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xEE800000, 0xFF800000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX1DA - { .CX1DA, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xFE800000, 0xFF800000, .CDE, .T32, {thumb32=true} }, + { .CX1DA, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xFE800000, 0xFF800000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX2 - { .CX2, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE400000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX2, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE400000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX2A - { .CX2A, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xFE400000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX2A, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xFE400000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX2D - { .CX2D, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX2D, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX2DA - { .CX2DA, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX2DA, {.IMM_COPROC,.GPR,.GPR,.IMM}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.CDE_IMM_FIELD}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX3 - { .CX3, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xEE800000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX3, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xEE800000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX3A - { .CX3A, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xFE800000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX3A, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xFE800000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX3D - { .CX3D, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX3D, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xEEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CX3DA - { .CX3DA, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true} }, + { .CX3DA, {.IMM_COPROC,.GPR,.GPR,.GPR}, {.CDE_COPROC_FIELD,.RD_T32,.RN_T32,.RM_T32}, 0xFEC00000, 0xFFC00000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX1 - { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX1A - { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX2 - { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX2A - { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX3 - { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCX3A - { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VPT - { .VPT, {.MVE_VPT_MASK,.COND,.QPR,.QPR}, {.MVE_VPT_MASK_FIELD,.NONE,.VN_Q,.VM_Q}, 0xFE010F00, 0xFE018FF0, .MVE_INT, .T32, {thumb32=true} }, + { .VPT, {.MVE_VPT_MASK,.COND,.QPR,.QPR}, {.MVE_VPT_MASK_FIELD,.NONE,.VN_Q,.VM_Q}, 0xFE010F00, 0xFE018FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, // .VPST - { .VPST, {.MVE_VPT_MASK,.NONE,.NONE,.NONE}, {.MVE_VPT_MASK_FIELD,.NONE,.NONE,.NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true} }, + { .VPST, {.MVE_VPT_MASK,.NONE,.NONE,.NONE}, {.MVE_VPT_MASK_FIELD,.NONE,.NONE,.NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VPSEL - { .VPSEL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE010F01, 0xFFB10FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VPSEL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE010F01, 0xFFB10FF1, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VPNOT - { .VPNOT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true} }, + { .VPNOT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCTP - { .VCTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E801, 0xFFC0FFFF, .MVE_INT, .T32, {thumb32=true} }, + { .VCTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E801, 0xFFC0FFFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VADDV - { .VADDV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEF10F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VADDV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEF10F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VADDVA - { .VADDVA, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEF10F20, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VADDVA, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEF10F20, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VADDLV - { .VADDLV, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VADDLV, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VADDLVA - { .VADDLVA, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VADDLVA, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F20, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMAXV - { .VMAXV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE20F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMAXV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE20F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMAXAV - { .VMAXAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE00F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMAXAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE00F00, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMINV - { .VMINV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE20F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMINV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE20F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMINAV - { .VMINAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE00F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMINAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEE00F80, 0xEFF30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMAXNMV - { .VMAXNMV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VMAXNMV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEE0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VMAXNMAV - { .VMAXNMAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEC0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VMAXNMAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEC0F00, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VMINNMV - { .VMINNMV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEE0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VMINNMV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEE0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VMINNMAV - { .VMINNMAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEC0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true} }, + { .VMINNMAV, {.GPR,.QPR,.NONE,.NONE}, {.RD_T32,.VM_Q,.NONE,.NONE}, 0xEEEC0F80, 0xEFFF0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, // .VABAV - { .VABAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEE800F01, 0xEFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VABAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEE800F01, 0xEFB11051, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMLADAV - { .VMLADAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLADAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLADAVA - { .VMLADAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLADAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLADAVX - { .VMLADAVX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB01F00, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLADAVX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB01F00, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLADAVAX - { .VMLADAVAX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB01F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLADAVAX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB01F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLALDAV - { .VMLALDAV, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALDAV, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLALDAVA - { .VMLALDAVA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALDAVA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLALDAVX - { .VMLALDAVX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALDAVX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLALDAVAX - { .VMLALDAVAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALDAVAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLSDAV - { .VMLSDAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB00E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSDAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB00E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLSDAVA - { .VMLSDAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB00E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSDAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB00E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLSDAVX - { .VMLSDAVX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB01E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSDAVX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB01E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLSDAVAX - { .VMLSDAVAX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB01E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSDAVAX, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xFEB01E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLSLDAV - { .VMLSLDAV, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E01, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLDAV, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E01, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLSLDAVA - { .VMLSLDAVA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E21, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLDAVA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800E21, 0xFFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLSLDAVX - { .VMLSLDAVX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLDAVX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VMLSLDAVAX - { .VMLSLDAVAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLDAVAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VRMLALDAVH - { .VRMLALDAVH, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLALDAVH, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLALDAVHA - { .VRMLALDAVHA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLALDAVHA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE800F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLALDAVHX - { .VRMLALDAVHX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLALDAVHX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLALDAVHAX - { .VRMLALDAVHAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLALDAVHAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xEE801F20, 0xEFB11F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLSLDAVH - { .VRMLSLDAVH, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE800E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLSLDAVH, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE800E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLSLDAVHA - { .VRMLSLDAVHA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE800E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLSLDAVHA, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE800E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLSLDAVHX - { .VRMLSLDAVHX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLSLDAVHX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE801E01, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VRMLSLDAVHAX - { .VRMLSLDAVHAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true} }, + { .VRMLSLDAVHAX, {.GPR,.GPR,.QPR,.QPR}, {.RD_T32,.RN_T32,.VN_Q,.VM_Q}, 0xFE801E21, 0xFFB11051, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLAV - { .VMLAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLAV, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLAVA - { .VMLAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLAVA, {.GPR,.QPR,.QPR,.NONE}, {.RD_T32,.VN_Q,.VM_Q,.NONE}, 0xEEB00F20, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, // .VMLSV - { .VMLSV, {.GPR,.QPR,.QPR,.NONE}, {.RDLO_A32,.VN_Q_MVE,.VM_Q_MVE,.NONE}, 0xEEF00E01, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSV, {.GPR,.QPR,.QPR,.NONE}, {.RDLO_A32,.VN_Q_MVE,.VM_Q_MVE,.NONE}, 0xEEF00E01, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMLSVA - { .VMLSVA, {.GPR,.QPR,.QPR,.NONE}, {.RDLO_A32,.VN_Q_MVE,.VM_Q_MVE,.NONE}, 0xEEF00E21, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSVA, {.GPR,.QPR,.QPR,.NONE}, {.RDLO_A32,.VN_Q_MVE,.VM_Q_MVE,.NONE}, 0xEEF00E21, 0xFFF10FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VCMUL - { .VCMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE300E00, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true} }, + { .VCMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE300E00, 0xEFB10F51, .MVE_FP, .T32, {thumb32=true}, {.F16,.NONE} }, // .VHCADD - { .VHCADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true} }, - { .VHCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VHCADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000F00, 0xEFB10F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, + { .VHCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_HCADD}, 0xEE000F00, 0xFFE10FF1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VBRSR - { .VBRSR, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811F71, .MVE_INT, .T32, {thumb32=true} }, + { .VBRSR, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811F71, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, // .VSHLC - { .VSHLC, {.QPR,.GPR,.IMM5,.NONE}, {.VD_Q,.RM_T32,.A32_IMM_SHIFT,.NONE}, 0xEE000FC0, 0xFFC00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VSHLC, {.QPR,.GPR,.IMM5,.NONE}, {.VD_Q,.RM_T32,.A32_IMM_SHIFT,.NONE}, 0xEE000FC0, 0xFFC00FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VDDUP - { .VDDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true} }, + { .VDDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VIDUP - { .VIDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true} }, + { .VIDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VDWDUP - { .VDWDUP, {.QPR,.GPR,.GPR,.IMM}, {.VD_Q,.RM_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE011F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true} }, + { .VDWDUP, {.QPR,.GPR,.GPR,.IMM}, {.VD_Q,.RM_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE011F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VIWDUP - { .VIWDUP, {.QPR,.GPR,.GPR,.IMM}, {.VD_Q,.RM_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE010F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true} }, + { .VIWDUP, {.QPR,.GPR,.GPR,.IMM}, {.VD_Q,.RM_T32,.RN_T32,.CDE_IMM_FIELD}, 0xEE010F60, 0xEF811F70, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VMOVNB - { .VMOVNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMOVNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.I16,.NONE} }, // .VMOVNT - { .VMOVNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VMOVNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.I16,.NONE} }, // .VQMOVNB - { .VQMOVNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE330E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQMOVNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE330E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VQMOVNT - { .VQMOVNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE331E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQMOVNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE331E01, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VQMOVUNB - { .VQMOVUNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQMOVUNB, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE310E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VQMOVUNT - { .VQMOVUNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQMOVUNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xEE311E81, 0xFFB31FD1, .MVE_INT, .T32, {thumb32=true}, {.S16,.NONE} }, // .VSHLLB - { .VSHLLB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VSHLLB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSHLLT - { .VSHLLT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VSHLLT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMULLB - { .VMULLB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMULLB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMULLT - { .VMULLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMULLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VMLALB - { .VMLALB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMLALT - { .VMLALT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLALT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E20, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMLSLB - { .VMLSLB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VMLSLT - { .VMLSLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VMLSLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E10, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSHRNB - { .VSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSHRNT - { .VSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801EC1, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VRSHRNB - { .VRSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE800EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VRSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE800EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VRSHRNT - { .VRSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE801EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VRSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE801EC1, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQSHRNB - { .VQSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQSHRNT - { .VQSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F40, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQRSHRNB - { .VQRSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQRSHRNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQRSHRNT - { .VQRSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQRSHRNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801F41, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQSHRUNB - { .VQSHRUNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQSHRUNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE800FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQSHRUNT - { .VQSHRUNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQSHRUNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xEE801FC0, 0xEF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQRSHRUNB - { .VQRSHRUNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE800FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQRSHRUNB, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE800FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQRSHRUNT - { .VQRSHRUNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE801FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VQRSHRUNT, {.QPR,.QPR,.IMM5,.NONE}, {.VD_Q,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xFE801FC0, 0xFF801FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VQDMLADH - { .VQDMLADH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQDMLADH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQDMLADHX - { .VQDMLADHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQDMLADHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E00, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQDMLSDH - { .VQDMLSDH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE000E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQDMLSDH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE000E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQDMLSDHX - { .VQDMLSDHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE001E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQDMLSDHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE001E00, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQRDMLADH - { .VQRDMLADH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQRDMLADH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE000E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQRDMLADHX - { .VQRDMLADHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQRDMLADHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEE001E01, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQRDMLSDH - { .VQRDMLSDH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE000E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQRDMLSDH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE000E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQRDMLSDHX - { .VQRDMLSDHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE001E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true} }, + { .VQRDMLSDHX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFE001E01, 0xFF811F51, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VLDRB - { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true} }, - { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, + { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, // .VLDRH - { .VLDRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VLDRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.U16,.NONE} }, + { .VLDRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U16,.NONE} }, // .VLDRW - { .VLDRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.U32,.NONE} }, + { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U32,.NONE} }, // .VLDRD - { .VLDRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VLDRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U64,.NONE} }, // .VSTRB - { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true} }, - { .VSTRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, + { .VSTRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSTRH - { .VSTRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VSTRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRH, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.SZ16,.NONE} }, + { .VSTRH, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600E90, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSTRW - { .VSTRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VSTRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRW, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F00, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, + { .VSTRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VSTRD - { .VSTRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true} }, - { .VSTRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true} }, + { .VSTRD, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801F80, 0xFFB01F80, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VSTRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xEC600FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VLD20 - { .VLD20, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD20, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VLD21 - { .VLD21, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD21, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VLD40 - { .VLD40, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD40, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VLD41 - { .VLD41, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD41, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VLD42 - { .VLD42, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD42, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VLD43 - { .VLD43, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VLD43, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC901E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST20 - { .VST20, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST20, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E00, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST21 - { .VST21, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST21, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E20, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST40 - { .VST40, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST40, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E01, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST41 - { .VST41, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST41, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E21, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST42 - { .VST42, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST42, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E41, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, // .VST43 - { .VST43, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true} }, + { .VST43, {.QPR_MVE_LIST,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0xFC801E61, 0xFFB01EFF, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, } ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ diff --git a/core/rexcode/isa/arm32/tables.odin b/core/rexcode/isa/arm32/tables.odin index 0798b0603..d9731578d 100644 --- a/core/rexcode/isa/arm32/tables.odin +++ b/core/rexcode/isa/arm32/tables.odin @@ -32,8 +32,9 @@ Decode_Entry :: struct #packed { feature: Feature, // 1 mode: Mode, // 1 flags: Encoding_Flags, // 1 + dt: Data_Types, // 2 -- see Data_Type in encoding_types.odin } -#assert(size_of(Decode_Entry) == 21) +#assert(size_of(Decode_Entry) == 23) Decode_Index :: struct #packed { start: u16, diff --git a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin index 42514bf8a..5c773096e 100644 Binary files a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin and b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin differ diff --git a/core/rexcode/isa/arm32/tables/arm32.entries.bin b/core/rexcode/isa/arm32/tables/arm32.entries.bin index 1f7c993f2..2d9ae78ac 100644 Binary files a/core/rexcode/isa/arm32/tables/arm32.entries.bin and b/core/rexcode/isa/arm32/tables/arm32.entries.bin differ