From 2d85384a16a3c250a76f87e24579fa07350482ed Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Fri, 28 Aug 2026 00:15:56 -0400 Subject: [PATCH] rexcode/arm32: merge the nine *_LANE mnemonics, and make the lane survive No assembler spells these `vld1_lane` or `vmov_lane`; they are `vld1` and `vmov` with a lane-indexed operand. All nine are now their base mnemonic. Merging them meant fixing what the separate names had been hiding. VLD1_LANE and VST1_LANE were byte-for-byte duplicates of forms VLD1 and VST1 already had, with a looser mask, and neither encoded the lane -- both used .VD_D, which has no lane field. `vld1.8 {d0[3]}, [r0]` disassembled as `vld1.8 d0, [r0]`. VMOV had the same shape: its own DPR_ELEM form dropped the index, while VMOV_LANE's three forms carried the per-size encodings that actually work. The lane-dropping forms are gone and the working ones now sit under the base mnemonic. VLD2-4/VST2-4's single-lane forms left bits 9:8 free, and that field is what separates VLD1/2/3/4 -- so VLD4's encoding matched VLD2's entry and disassembled as the wrong instruction. Two more things the lane could not survive. A lane index of 0 printed nothing, because 0 doubled as "no lane" -- `vmov.32 d0[0], r0` came out as `vmov.32 d0, r0`, a different instruction. And a lane inside a register list was dropped entirely, so `{d0[1], d1[1]}` printed as `{d0, d1}`. The whole set is byte-exact against llvm-mc: 27 single-lane forms across VLD1-4/VST1-4 and all three VMOV element sizes. arm32 is 1649/1649 on the sweep and 436/436 on the table checks, with the stale expectations for the forms this corrected updated to the verified values. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 27 + core/rexcode/isa/arm32/encoder.odin | 25 + core/rexcode/isa/arm32/encoding_types.odin | 8 + core/rexcode/isa/arm32/mnemonic_builders.odin | 44 +- core/rexcode/isa/arm32/mnemonics.odin | 5 +- core/rexcode/isa/arm32/operands.odin | 9 +- core/rexcode/isa/arm32/printer.odin | 10 +- .../isa/arm32/tablegen/encoding_table.odin | 80 +- .../tablegen/generated/decode_tables.odin | 1997 ++++++++--------- .../tablegen/generated/encode_tables.odin | 685 +++--- .../isa/arm32/tables/arm32.bucket_list.bin | Bin 10758 -> 10718 bytes .../isa/arm32/tables/arm32.encode_forms.bin | Bin 38088 -> 37927 bytes .../isa/arm32/tables/arm32.encode_runs.bin | Bin 4760 -> 4688 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 38088 -> 37927 bytes .../isa/arm32/tables/arm32.form_idx.bin | Bin 3312 -> 3298 bytes .../isa/arm32/tables/arm32.idx_a32.bin | Bin 1024 -> 1024 bytes .../isa/arm32/tables/arm32.idx_t16.bin | Bin 256 -> 256 bytes .../isa/arm32/tables/arm32.idx_t32.bin | Bin 512 -> 512 bytes .../isa/arm32/tables/arm32.idx_t32_sub.bin | Bin 16384 -> 16384 bytes core/rexcode/isa/arm32/tests/smoke.odin | 28 +- 20 files changed, 1444 insertions(+), 1474 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 0d22f2113..255009b26 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -445,6 +445,12 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op case .NEON_D_LIST_ALL: n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) return op_reg_run(Register(REG_DPR | u16(n)), 1, 1, true) + case .NEON_LANE_D_8, .NEON_LANE_D_16, .NEON_LANE_D_32, .NEON_LANE_D_8_2, .NEON_LANE_D_16_2, .NEON_LANE_D_32_2, .NEON_LANE_D_8_3, .NEON_LANE_D_16_3, .NEON_LANE_D_32_3, .NEON_LANE_D_8_4, .NEON_LANE_D_16_4, .NEON_LANE_D_32_4: + n := ((word >> 22) & 1) << 4 | ((word >> 12) & 0xF) + shift, mask, count := neon_lane_shape(enc) + op := op_dpr_lane(Register(REG_DPR | u16(n)), u8((word >> shift) & mask)) + op.list = {count = count, stride = 1} + return op case .VFP_S_LIST: // {S, ...} -- imm8 counts the registers, and the run starts at Vd. // Both halves matter: keeping only the count printed the wrong bank @@ -604,3 +610,24 @@ decode_reserve :: proc(instructions: ^[dynamic]Instruction, inst_info: ^[dynamic if inst_info != nil { reserve(inst_info, len(inst_info) + n) } if label_defs != nil { reserve(label_defs, len(label_defs) + n) } } + +// The lane field's position and the list length for a NEON single-lane +// load/store. The lane sits just above the alignment bits, and how far above +// follows the element size: bits 7:5 for .8, 7:6 for .16, bit 7 for .32. +@(private="file", require_results) +neon_lane_shape :: #force_inline proc "contextless" (e: Operand_Encoding) -> (shift, mask: u32, count: u8) { + #partial switch e { + case .NEON_LANE_D_8: return 5, 0x7, 1 + case .NEON_LANE_D_16: return 6, 0x3, 1 + case .NEON_LANE_D_32: return 7, 0x1, 1 + case .NEON_LANE_D_8_2: return 5, 0x7, 2 + case .NEON_LANE_D_16_2: return 6, 0x3, 2 + case .NEON_LANE_D_32_2: return 7, 0x1, 2 + case .NEON_LANE_D_8_3: return 5, 0x7, 3 + case .NEON_LANE_D_16_3: return 6, 0x3, 3 + case .NEON_LANE_D_32_3: return 7, 0x1, 3 + case .NEON_LANE_D_8_4: return 5, 0x7, 4 + case .NEON_LANE_D_16_4: return 6, 0x3, 4 + case: return 7, 0x1, 4 + } +} diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 3613d619e..71735a8dd 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -501,6 +501,10 @@ pack_operand_inline :: #force_inline proc( // Only Vd; the count lives in the form's type field. n := u32(reg_hw(op.reg)) & 0x1F return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 + case .NEON_LANE_D_8, .NEON_LANE_D_16, .NEON_LANE_D_32, .NEON_LANE_D_8_2, .NEON_LANE_D_16_2, .NEON_LANE_D_32_2, .NEON_LANE_D_8_3, .NEON_LANE_D_16_3, .NEON_LANE_D_32_3, .NEON_LANE_D_8_4, .NEON_LANE_D_16_4, .NEON_LANE_D_32_4: + n := u32(reg_hw(op.reg)) & 0x1F + shift, mask, _ := neon_lane_shape(enc) + return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | (u32(op.lane) & mask) << shift case .VFP_S_LIST: n := u32(reg_hw(op.reg)) & 0x1F return ((n >> 1) & 0xF) << 12 | (n & 1) << 22 | (u32(op.list.count) & 0xFF) @@ -855,3 +859,24 @@ write_u16_le :: #force_inline proc "contextless" (code: []u8, offset: u32, word: read_u16_le :: #force_inline proc "contextless" (code: []u8, offset: u32) -> u16 { return u16(code[offset+0]) | (u16(code[offset+1]) << 8) } + +// The lane field's position and the list length for a NEON single-lane +// load/store. The lane sits just above the alignment bits, and how far above +// follows the element size: bits 7:5 for .8, 7:6 for .16, bit 7 for .32. +@(private="file", require_results) +neon_lane_shape :: #force_inline proc "contextless" (e: Operand_Encoding) -> (shift, mask: u32, count: u8) { + #partial switch e { + case .NEON_LANE_D_8: return 5, 0x7, 1 + case .NEON_LANE_D_16: return 6, 0x3, 1 + case .NEON_LANE_D_32: return 7, 0x1, 1 + case .NEON_LANE_D_8_2: return 5, 0x7, 2 + case .NEON_LANE_D_16_2: return 6, 0x3, 2 + case .NEON_LANE_D_32_2: return 7, 0x1, 2 + case .NEON_LANE_D_8_3: return 5, 0x7, 3 + case .NEON_LANE_D_16_3: return 6, 0x3, 3 + case .NEON_LANE_D_32_3: return 7, 0x1, 3 + case .NEON_LANE_D_8_4: return 5, 0x7, 4 + case .NEON_LANE_D_16_4: return 6, 0x3, 4 + case: return 7, 0x1, 4 + } +} diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index cf60490c5..b977fe734 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -341,6 +341,14 @@ Operand_Encoding :: enum u8 { NEON_D_LIST_3X, // {d2, d4, d6} -- spaced NEON_D_LIST_4X, // {d2, d4, d6, d8} -- spaced NEON_D_LIST_ALL, // {d2[]} -- to all lanes + // VLD1/VST1 single-lane: Vd plus the lane index, whose width and position + // follow the element size -- bits 7:5 for .8, 7:6 for .16, bit 7 for .32. + // Verified against llvm-mc. + // ..._N is how many registers the list holds: VLD2 writes `{d0[1], d1[1]}`. + NEON_LANE_D_8, NEON_LANE_D_16, NEON_LANE_D_32, + NEON_LANE_D_8_2, NEON_LANE_D_16_2, NEON_LANE_D_32_2, + NEON_LANE_D_8_3, NEON_LANE_D_16_3, NEON_LANE_D_32_3, + NEON_LANE_D_8_4, NEON_LANE_D_16_4, NEON_LANE_D_32_4, // ---- Memory addressing composites ---- MEM_IMM12_OFFSET, // [Rn, #±imm12] diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index ff246fdd8..c8db616d1 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -737,14 +737,14 @@ inst_vmov_s_imm8 :: #force_inline proc "contextless" (dst: Register, i inst_vmov_r_r_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } inst_vmov_r_r_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } inst_vmov_r_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_dpr_lane(src, lane), {}, {}}} } -inst_vmov_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} } +inst_vmov_qlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_reg(src), {}, {}}} } inst_vmov_qlane_qlane_r_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_qpr_lane(src, lane2), op_reg(src2), op_reg(src3)}} } emit_vmov_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmov_s_s(dst, src)) } emit_vmov_s_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmov_s_imm8(dst, imm)) } emit_vmov_r_r_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmov_r_r_d(dst, src, src2)) } emit_vmov_r_r_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmov_r_r_s_s(dst, src, src2, src3)) } emit_vmov_r_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_dlane(dst, src, lane)) } -emit_vmov_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_dlane_r(dst, lane, src)) } +emit_vmov_qlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_qlane_r(dst, lane, src)) } emit_vmov_qlane_qlane_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) { append(instructions, inst_vmov_qlane_qlane_r_r(dst, lane, src, lane2, src2, src3)) } inst_vmrs_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } emit_vmrs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmrs_r(dst)) } @@ -1000,8 +1000,6 @@ emit_vdup_d_r :: #force_inline proc(instructions: ^[dynamic]Instruc emit_vdup_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vdup_d_dlane(dst, src, lane)) } inst_vswp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSWP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vswp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vswp_d_d(dst, src)) } -inst_vmov_lane_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} } -emit_vmov_lane_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_lane_dlane_r(dst, lane, src)) } inst_vld1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } inst_vld1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } emit_vld1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld1_dlist_mem(regs, src)) } @@ -1102,22 +1100,6 @@ inst_vld3r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: emit_vld3r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3r_dlist_mem(regs, src)) } inst_vld4r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } emit_vld4r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4r_dlist_mem(regs, src)) } -inst_vld1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } -emit_vld1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vld1_lane_dlane_mem(dst, lane, src)) } -inst_vld2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2_lane_dlist_mem(regs, src)) } -inst_vld3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3_lane_dlist_mem(regs, src)) } -inst_vld4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vld4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4_lane_dlist_mem(regs, src)) } -inst_vst1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } -emit_vst1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vst1_lane_dlane_mem(dst, lane, src)) } -inst_vst2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst2_lane_dlist_mem(regs, src)) } -inst_vst3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst3_lane_dlist_mem(regs, src)) } -inst_vst4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } -emit_vst4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst4_lane_dlist_mem(regs, src)) } inst_it_cond_imm4 :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .IT, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_imm(imm), op_imm(imm2), {}, {}}} } emit_it_cond_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_it_cond_imm4(imm, imm2)) } inst_tt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } @@ -2009,8 +1991,8 @@ inst_vcvtm :: inst_vcvtm_s_s emit_vcvtm :: emit_vcvtm_s_s inst_vcvtr :: inst_vcvtr_s_s emit_vcvtr :: emit_vcvtr_s_s -inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_dlane_r, inst_vmov_qlane_qlane_r_r } -emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_dlane_r, emit_vmov_qlane_qlane_r_r } +inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_qlane_r, inst_vmov_qlane_qlane_r_r } +emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_qlane_r, emit_vmov_qlane_qlane_r_r } inst_vmrs :: inst_vmrs_r emit_vmrs :: emit_vmrs_r inst_vmsr :: inst_vmsr_r @@ -2223,8 +2205,6 @@ inst_vdup :: proc{ inst_vdup_d_r, inst_vdup_d_dlane } emit_vdup :: proc{ emit_vdup_d_r, emit_vdup_d_dlane } inst_vswp :: inst_vswp_d_d emit_vswp :: emit_vswp_d_d -inst_vmov_lane :: inst_vmov_lane_dlane_r -emit_vmov_lane :: emit_vmov_lane_dlane_r inst_vld1 :: proc{ inst_vld1_dlist_mem, inst_vld1_dlane_mem } emit_vld1 :: proc{ emit_vld1_dlist_mem, emit_vld1_dlane_mem } inst_vld2 :: inst_vld2_dlist_mem @@ -2311,22 +2291,6 @@ inst_vld3r :: inst_vld3r_dlist_mem emit_vld3r :: emit_vld3r_dlist_mem inst_vld4r :: inst_vld4r_dlist_mem emit_vld4r :: emit_vld4r_dlist_mem -inst_vld1_lane :: inst_vld1_lane_dlane_mem -emit_vld1_lane :: emit_vld1_lane_dlane_mem -inst_vld2_lane :: inst_vld2_lane_dlist_mem -emit_vld2_lane :: emit_vld2_lane_dlist_mem -inst_vld3_lane :: inst_vld3_lane_dlist_mem -emit_vld3_lane :: emit_vld3_lane_dlist_mem -inst_vld4_lane :: inst_vld4_lane_dlist_mem -emit_vld4_lane :: emit_vld4_lane_dlist_mem -inst_vst1_lane :: inst_vst1_lane_dlane_mem -emit_vst1_lane :: emit_vst1_lane_dlane_mem -inst_vst2_lane :: inst_vst2_lane_dlist_mem -emit_vst2_lane :: emit_vst2_lane_dlist_mem -inst_vst3_lane :: inst_vst3_lane_dlist_mem -emit_vst3_lane :: emit_vst3_lane_dlist_mem -inst_vst4_lane :: inst_vst4_lane_dlist_mem -emit_vst4_lane :: emit_vst4_lane_dlist_mem inst_it :: inst_it_cond_imm4 emit_it :: emit_it_cond_imm4 inst_tt :: inst_tt_r_r diff --git a/core/rexcode/isa/arm32/mnemonics.odin b/core/rexcode/isa/arm32/mnemonics.odin index f922eeaa4..5494705f4 100644 --- a/core/rexcode/isa/arm32/mnemonics.odin +++ b/core/rexcode/isa/arm32/mnemonics.odin @@ -300,7 +300,7 @@ Mnemonic :: enum u16 { VSWP, // swap // Lane access - VMOV_LANE, // VMOV.
R, D[i] / VMOV.
D[i], R + // VMOV.
R, D[i] / VMOV.
D[i], R // Load/Store structures (NEON) VLD1, VLD2, VLD3, VLD4, @@ -349,9 +349,6 @@ Mnemonic :: enum u16 { VLD2R, VLD3R, VLD4R, // -- NEON single-element-lane load/store (lane form, not multi-vec) ----- - VLD1_LANE, VLD2_LANE, VLD3_LANE, VLD4_LANE, - VST1_LANE, VST2_LANE, VST3_LANE, VST4_LANE, - // -- VFP fixed-point conversions (with #fbits operand) ------------------ // VCVT.
Sd, Sd, #fbits family diff --git a/core/rexcode/isa/arm32/operands.odin b/core/rexcode/isa/arm32/operands.odin index 5950ff3b1..4914fe0af 100644 --- a/core/rexcode/isa/arm32/operands.odin +++ b/core/rexcode/isa/arm32/operands.odin @@ -114,7 +114,10 @@ Operand :: struct #packed { shift_type: Shift_Type | 4, // GPR_SHIFTED; .LSL/0 when plain shift_amt: u8 | 5, // 0..31, or the Rs index for RSR lane: u8 | 5, // SIMD lane for DPR_ELEM / QPR_ELEM - // 3 bits spare + // Whether `lane` means anything. Lane 0 is a real index -- `d0[0]` + // is not `d0` -- so it cannot be spelled by lane == 0. + has_lane: bool | 1, + // 2 bits spare }, mem: Memory, immediate: i64, @@ -178,9 +181,9 @@ op_reg_run :: #force_inline proc "contextless" (first: Register, count: u8, stri } @(require_results) op_dpr_lane :: #force_inline proc "contextless" (d: Register, idx: u8) -> Operand { - return Operand{reg = d, kind = .REGISTER, size = 4, lane = idx} + return Operand{reg = d, kind = .REGISTER, size = 4, lane = idx, has_lane = true} } @(require_results) op_qpr_lane :: #force_inline proc "contextless" (q: Register, idx: u8) -> Operand { - return Operand{reg = q, kind = .REGISTER, size = 4, lane = idx} + return Operand{reg = q, kind = .REGISTER, size = 4, lane = idx, has_lane = true} } diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 7c9a0bad9..492e813ce 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -535,14 +535,20 @@ write_operand :: proc( for n in 0 ..< u16(op.list.count) { if n > 0 { strings.write_string(sb, ", ") } write_register(sb, Register(reg_class(op.reg) | ((reg_hw(op.reg) + n * step) & 0x1F))) - if op.list.all_lanes { strings.write_string(sb, "[]") } + // Every member of a single-lane list carries the index: + // `{d0[1], d1[1]}`. `{d0[]}` is the to-all-lanes form. + if op.list.all_lanes { + strings.write_string(sb, "[]") + } else if op.has_lane { + fmt.sbprintf(sb, "[%d]", op.lane) + } } strings.write_string(sb, "}") return } write_register(sb, op.reg) write_shift(sb, op.shift_type, op.shift_amt) - if op.lane != 0 { + if op.has_lane { fmt.sbprintf(sb, "[%d]", op.lane) } case .IMMEDIATE: diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index f8f540c1a..70ad7ed67 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1465,13 +1465,15 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // .8 / .16 / .32 selected by opc1+opc2 split bits in encoding. // 32-bit lane move (.32): {.VMOV, {.GPR, .DPR_ELEM, .NONE, .NONE}, {.RT_A32, .VN_D, .NONE, .NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}}, - {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VN_D, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32, .NONE}}, // VMOV. Qd[i], Rt -- single lane Rt -> Qd[i] {.VMOV, {.QPR_ELEM, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, // VMOV. Rt, Qd[i] {.VMOV, {.GPR, .QPR_ELEM, .NONE, .NONE}, {.RT_T32, .VD_Q, .NONE, .NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, // VMOV Qd[2*i], Qd[2*i+1], Rt, Rt2 -- pair move {.VMOV, {.QPR_ELEM, .QPR_ELEM, .GPR, .GPR}, {.VD_Q, .VD_Q, .RT_T32, .RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, + {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_8, .RT_A32, .NONE, .NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8, .NONE}}, + {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_16, .RT_A32, .NONE, .NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16, .NONE}}, + {.VMOV, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_32, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32, .NONE}}, }, // ---- VMVN NEON modified immediate (op=1 form) ---- // bit 5 = 1 distinguishes VMVN from VMOV @@ -2318,9 +2320,9 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // size 00 .8 / 01 .16 / 10 .32; T=0 single, T=1 pair {.VLD1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_ALL, .RN_A32, .NONE, .NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VLD1 single lane: 1111 0100 1 D 10 Rn Vd 0X00 size idx_align Rm (X = 8/16/32 size selector) - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 - {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8, .RN_A32, .NONE, .NONE}, 0xF4A0000F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16, .RN_A32, .NONE, .NONE}, 0xF4A0040F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 + {.VLD1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32, .RN_A32, .NONE, .NONE}, 0xF4A0080F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 }, .VST1 = { // VST1 multiple (1-reg list) @@ -2329,36 +2331,54 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VST1, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // VST1 single lane: 1111 0100 1 D 00 Rn Vd 0X00 size idx_align Rm - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 - {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8, .RN_A32, .NONE, .NONE}, 0xF480000F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, // .8 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16, .RN_A32, .NONE, .NONE}, 0xF480040F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, // .16 + {.VST1, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32, .RN_A32, .NONE, .NONE}, 0xF480080F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, // .32 }, // VLD2 / VST2 / VLD3 / VST3 / VLD4 / VST4 - similar pattern with different "type" bits .VLD2 = { {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2X, .RN_A32, .NONE, .NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_2, .RN_A32, .NONE, .NONE}, 0xF4A0010F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_2, .RN_A32, .NONE, .NONE}, 0xF4A0050F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_2, .RN_A32, .NONE, .NONE}, 0xF4A0090F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST2 = { {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2, .RN_A32, .NONE, .NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_2X, .RN_A32, .NONE, .NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_2, .RN_A32, .NONE, .NONE}, 0xF480010F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_2, .RN_A32, .NONE, .NONE}, 0xF480050F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST2, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_2, .RN_A32, .NONE, .NONE}, 0xF480090F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VLD3 = { {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3X, .RN_A32, .NONE, .NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_3, .RN_A32, .NONE, .NONE}, 0xF4A0020F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_3, .RN_A32, .NONE, .NONE}, 0xF4A0060F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_3, .RN_A32, .NONE, .NONE}, 0xF4A00A0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST3 = { {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3, .RN_A32, .NONE, .NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_3X, .RN_A32, .NONE, .NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_3, .RN_A32, .NONE, .NONE}, 0xF480020F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_3, .RN_A32, .NONE, .NONE}, 0xF480060F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST3, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_3, .RN_A32, .NONE, .NONE}, 0xF4800A0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VLD4 = { {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4X, .RN_A32, .NONE, .NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_4, .RN_A32, .NONE, .NONE}, 0xF4A0030F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_4, .RN_A32, .NONE, .NONE}, 0xF4A0070F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VLD4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_4, .RN_A32, .NONE, .NONE}, 0xF4A00B0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, .VST4 = { {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4, .RN_A32, .NONE, .NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_D_LIST_4X, .RN_A32, .NONE, .NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_8_4, .RN_A32, .NONE, .NONE}, 0xF480030F, 0xFFB00F1F, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_16_4, .RN_A32, .NONE, .NONE}, 0xF480070F, 0xFFB00F3F, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, + {.VST4, {.DPR_LIST, .MEM, .NONE, .NONE}, {.NEON_LANE_D_32_4, .RN_A32, .NONE, .NONE}, 0xF4800B0F, 0xFFB00F7F, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, }, // ---- VMULL / VMLAL / VMLSL (widening multiplies) ---- @@ -2882,47 +2902,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // 1111 0100 1 D 10 Rn Vd size{2} N index_align Rm // N=00 VLDx1, 01 VLDx2, 10 VLDx3, 11 VLDx4 (x = 1..4) // VLD1_LANE Dd[i], [Rn]: size=00 (.8) 0xF4A00000, size=01 (.16) 0xF4A00400, size=10 (.32) 0xF4A00800 - .VLD1_LANE = { - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VLD1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VLD2_LANE = { - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VLD2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VLD3_LANE = { - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VLD3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VLD4_LANE = { - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VLD4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - // VST1/2/3/4 single-lane: bit 21 = 0 (store, not load) - .VST1_LANE = { - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VST1_LANE, {.DPR_ELEM, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VST2_LANE = { - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VST2_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VST3_LANE = { - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VST3_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, - .VST4_LANE = { - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ8, .NONE}}, - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ16, .NONE}}, - {.VST4_LANE, {.DPR_LIST, .MEM, .NONE, .NONE}, {.VD_D, .RN_A32, .NONE, .NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {cond_in_28=false}, {.SZ32, .NONE}}, - }, // ========================================================================= // ARMv8-M Security Extensions (TrustZone-M) -- TT / TTT / TTA / TTAT @@ -3569,11 +3548,6 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // .16 -> Dm in D0..D7 (bits 2:0), lane at bit5:bit3; .32 -> D0..D15, lane bit5. // VMOV (ARM core register to scalar): Dd[lane], Rt. The lane bits depend on // the element size (see VMOV_LANE_8/16/32); bit22/bit5 carry the size. - .VMOV_LANE = { - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_8, .RT_A32, .NONE, .NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8, .NONE}}, - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_16, .RT_A32, .NONE, .NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16, .NONE}}, - {.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_32, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32, .NONE}}, - }, // MVE (M-profile vector) multiply-subtract-across-vector reduce, halving // complex add (saturating), and complex multiply-accumulate. T32; the diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index 7d4bace52..11bf858cc 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [1656]lib.Decode_Entry{ +DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -212,11 +212,11 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -262,13 +262,13 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100310, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100300, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100F40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -283,8 +283,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100E00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100310, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100300, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100F00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100600, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100610, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100A10, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -337,8 +337,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, @@ -370,40 +370,40 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -434,12 +434,12 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -467,8 +467,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -518,8 +518,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, @@ -535,8 +535,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000610, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, - { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A00, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000A10, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000400, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, @@ -583,8 +583,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, @@ -597,8 +597,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, @@ -684,135 +684,135 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {}, {.I64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {}, {.U16,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {}, {.U64,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {}, {.S64,.NONE} }, - { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCEQ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCGE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCGT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VCLT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {}, 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{.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, @@ -851,40 +851,34 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .LDRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04500000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04600000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRBT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04700000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32,.RN_A32,.NONE,.NONE}, 0xF480080F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_2,.RN_A32,.NONE,.NONE}, 0xF480090F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_3,.RN_A32,.NONE,.NONE}, 0xF4800A0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4800B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16,.RN_A32,.NONE,.NONE}, 0xF480040F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_2,.RN_A32,.NONE,.NONE}, 0xF480050F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_3,.RN_A32,.NONE,.NONE}, 0xF480060F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF480070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8,.RN_A32,.NONE,.NONE}, 0xF480000F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_2,.RN_A32,.NONE,.NONE}, 0xF480010F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_3,.RN_A32,.NONE,.NONE}, 0xF480020F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_4,.RN_A32,.NONE,.NONE}, 0xF480030F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32,.RN_A32,.NONE,.NONE}, 0xF4A0080F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_2,.RN_A32,.NONE,.NONE}, 0xF4A0090F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_3,.RN_A32,.NONE,.NONE}, 0xF4A00A0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4A00B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16,.RN_A32,.NONE,.NONE}, 0xF4A0040F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_2,.RN_A32,.NONE,.NONE}, 0xF4A0050F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_3,.RN_A32,.NONE,.NONE}, 0xF4A0060F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF4A0070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8,.RN_A32,.NONE,.NONE}, 0xF4A0000F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_2,.RN_A32,.NONE,.NONE}, 0xF4A0010F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_3,.RN_A32,.NONE,.NONE}, 0xF4A0020F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_4,.RN_A32,.NONE,.NONE}, 0xF4A0030F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL,.RN_A32,.NONE,.NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00D0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0x05100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_PRE_INDEX,.NONE,.NONE}, 0x05200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -1037,30 +1031,29 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VFMSL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.NONE,.NONE} }, { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {}, {.NONE,.NONE} }, { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VFMSL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.NONE,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, - { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_OFFSET,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, - { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, @@ -1094,11 +1087,11 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, - { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, + { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, @@ -1132,12 +1125,12 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCVTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, - { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, - { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -1173,12 +1166,12 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.NONE,.NONE} }, { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {}, {.F32,.NONE} }, @@ -1280,8 +1273,8 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VDDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE011F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VIDUP, {.QPR,.GPR,.IMM,.NONE}, {.VD_Q,.RM_T32,.CDE_IMM_FIELD,.NONE}, 0xEE010F6E, 0xEF811F7E, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VCMP, {.QPR,.QPR,.NONE,.NONE}, {.VN_Q,.VM_Q,.NONE,.NONE}, 0xEE310F00, 0xEFB10FF0, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, - { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, + { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1532,12 +1525,12 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U32,.NONE} }, { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U64,.NONE} }, { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, - { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VPST, {.MVE_VPT_MASK,.NONE,.NONE,.NONE}, {.MVE_VPT_MASK_FIELD,.NONE,.NONE,.NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VPNOT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VRINTA, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, @@ -1668,7 +1661,7 @@ DECODE_ENTRIES := [1656]lib.Decode_Entry{ } @(rodata) -DECODE_FORM_IDX := [1656]u16{ +DECODE_FORM_IDX := [1649]u16{ 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 2, 2, 2, 1, 2, 2, 2, 5, 4, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, @@ -1681,102 +1674,102 @@ DECODE_FORM_IDX := [1656]u16{ 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 5, 13, 5, 9, 3, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, + 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 3, 9, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, - 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 4, 11, 4, - 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, - 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, + 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, + 2, 0, 6, 3, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, + 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, - 1, 2, 2, 0, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0, + 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 0, 0, 0, 25, 24, 22, 21, 23, 0, 0, - 0, 0, 10, 11, 15, 20, 18, 17, 14, 12, 10, 11, 19, 13, 16, 0, - 6, 0, 0, 2, 6, 5, 8, 7, 9, 4, 3, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 0, 0, 0, 24, 23, 25, 22, 21, 0, 0, + 0, 0, 11, 10, 19, 20, 17, 18, 10, 12, 14, 16, 13, 15, 11, 0, + 6, 0, 0, 7, 4, 3, 9, 2, 6, 5, 8, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, - 1, 1, 1, 1, 1, 1, 18, 12, 11, 7, 1, 6, 1, 6, 1, 2, + 1, 1, 1, 1, 1, 1, 18, 12, 11, 1, 7, 6, 1, 1, 6, 2, 0, 2, 0, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, - 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 3, 1, 1, 3, 1, 3, + 2, 19, 13, 12, 2, 8, 7, 2, 7, 2, 1, 3, 1, 3, 1, 3, 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 13, 7, 7, 1, 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, - 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, 3, - 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 4, 3, + 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 13, 11, 3, + 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 3, 4, 3, 3, 6, 2, 2, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 4, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 11, 13, - 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 10, 12, 1, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 13, 11, + 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, 20, 14, 13, 9, 4, 4, 8, 4, 8, 6, 6, 3, 5, 5, 7, 7, 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 9, 5, 5, 9, 7, 7, - 0, 10, 0, 3, 1, 2, 0, 1, 3, 2, 0, 0, 0, 9, 7, 4, - 5, 8, 2, 6, 3, 3, 7, 6, 5, 4, 2, 8, 9, 0, 1, 2, - 0, 1, 5, 3, 0, 2, 1, 4, 0, 1, 2, 13, 11, 12, 10, 14, - 13, 15, 12, 14, 15, 13, 12, 17, 15, 16, 14, 15, 16, 17, 14, 4, - 3, 1, 2, 5, 0, 3, 2, 1, 0, 2, 3, 1, 5, 2, 3, 4, - 0, 1, 1, 0, 4, 5, 2, 3, 0, 1, 1, 0, 3, 0, 2, 1, - 2, 1, 3, 4, 5, 0, 0, 3, 1, 5, 4, 2, 3, 2, 4, 1, - 0, 2, 4, 1, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 3, 2, - 3, 2, 0, 1, 2, 3, 3, 0, 3, 0, 3, 3, 2, 0, 1, 0, - 2, 1, 1, 0, 0, 1, 2, 2, 3, 0, 2, 1, 0, 1, 2, 0, - 1, 0, 1, 0, 0, 2, 0, 2, 0, 0, 5, 4, 6, 0, 2, 1, - 0, 1, 2, 2, 1, 0, 1, 0, 2, 4, 0, 0, 0, 6, 5, 7, - 1, 0, 2, 2, 1, 0, 0, 1, 2, 0, 2, 1, 0, 0, 1, 1, - 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, + 0, 10, 0, 2, 1, 3, 1, 2, 0, 3, 0, 0, 0, 9, 5, 4, + 7, 8, 3, 2, 6, 5, 7, 6, 3, 4, 8, 9, 2, 1, 0, 0, + 1, 2, 0, 1, 3, 5, 4, 2, 0, 2, 1, 11, 10, 13, 12, 12, + 15, 13, 14, 14, 12, 15, 13, 16, 14, 17, 15, 17, 16, 14, 15, 5, + 2, 1, 0, 4, 3, 1, 0, 3, 2, 2, 1, 3, 1, 5, 4, 0, + 2, 3, 1, 3, 2, 4, 0, 5, 1, 0, 0, 1, 1, 0, 3, 2, + 5, 2, 1, 0, 4, 3, 1, 0, 2, 3, 4, 5, 2, 1, 0, 4, + 3, 2, 1, 0, 4, 3, 0, 1, 0, 0, 0, 0, 1, 2, 3, 0, + 0, 1, 3, 2, 2, 3, 3, 0, 3, 0, 3, 1, 3, 0, 2, 0, + 2, 1, 1, 0, 1, 0, 2, 2, 2, 0, 1, 3, 0, 1, 2, 0, + 1, 0, 1, 0, 0, 2, 0, 2, 0, 0, 6, 5, 4, 4, 5, 4, + 3, 3, 4, 3, 2, 2, 7, 5, 4, 4, 6, 4, 3, 3, 5, 3, + 2, 2, 4, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, + 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, - 3, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, - 0, 0, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, - 0, 0, 0, 0, 0, 1, 0, 7, 9, 7, 0, 0, 8, 6, 0, 0, - 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 0, 1, 0, 0, 1, - 1, 0, 1, 0, 4, 2, 1, 3, 2, 0, 1, 27, 2, 2, 0, 1, - 0, 1, 0, 0, 0, 0, 5, 26, 0, 1, 1, 0, 0, 0, 3, 3, - 2, 2, 2, 0, 1, 0, 1, 2, 2, 0, 1, 1, 0, 0, 1, 3, - 1, 0, 0, 1, 2, 2, 0, 1, 2, 2, 1, 0, 0, 1, 2, 2, - 0, 1, 1, 0, 5, 2, 3, 3, 2, 1, 0, 1, 0, 1, 0, 0, - 1, 0, 1, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 2, 0, 1, - 19, 18, 20, 17, 14, 12, 9, 11, 13, 5, 4, 6, 2, 0, 1, 3, - 7, 8, 0, 1, 0, 1, 2, 1, 3, 0, 0, 1, 0, 1, 1, 0, - 0, 1, 0, 1, 0, 4, 0, 1, 15, 16, 3, 2, 0, 0, 1, 0, - 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 2, - 2, 1, 3, 3, 1, 1, 4, 4, 4, 4, 4, 3, 5, 4, 7, 5, - 11, 10, 8, 10, 9, 8, 7, 8, 8, 8, 8, 1, 1, 1, 1, 0, - 0, 0, 0, 0, 0, 30, 0, 0, 1, 0, 1, 0, 0, 1, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 4, 0, 0, 0, 0, 7, 29, 28, 2, 2, 2, 2, 0, 0, 0, - 0, 0, 0, 0, 17, 17, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 16, 16, 11, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15, - 8, 8, 2, 10, 10, 12, 12, 8, 4, 6, 0, 0, 2, 2, 2, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 4, 3, 6, 4, 8, 9, 7, 0, 0, 7, 8, 7, 6, 7, 7, - 7, 7, 4, 3, 1, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 2, 9, 8, 7, 7, 7, 7, 6, 6, 1, - 1, 1, 10, 8, 7, 6, 6, 6, 6, 5, 5, 2, 1, 2, 2, 1, - 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, + 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, + 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, + 0, 7, 9, 7, 0, 0, 8, 6, 0, 0, 1, 0, 1, 0, 1, 0, + 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 1, 0, 4, 32, + 31, 3, 2, 1, 0, 2, 2, 0, 1, 0, 1, 0, 0, 0, 0, 5, + 26, 0, 1, 1, 0, 0, 0, 3, 3, 2, 2, 2, 0, 1, 0, 1, + 2, 2, 0, 1, 1, 0, 30, 1, 3, 0, 1, 0, 1, 2, 2, 0, + 1, 2, 2, 1, 0, 0, 1, 2, 2, 0, 1, 1, 0, 5, 2, 3, + 3, 2, 1, 0, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, + 0, 1, 0, 1, 1, 0, 2, 0, 1, 19, 18, 20, 17, 14, 12, 9, + 11, 13, 5, 4, 6, 2, 0, 1, 3, 7, 8, 0, 1, 0, 1, 2, + 1, 3, 0, 0, 1, 1, 0, 1, 0, 1, 0, 0, 1, 0, 4, 0, + 1, 15, 16, 3, 2, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, + 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, + 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, + 8, 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 29, 0, + 0, 1, 0, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 0, 0, 7, + 27, 28, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, + 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, + 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, 10, 10, 12, 12, + 8, 4, 6, 0, 0, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 4, 8, 9, + 7, 0, 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, 3, 1, 2, 2, + 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, + 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, + 9, 8, 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, + 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, - 1, 0, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 2, 1, 2, 2, - 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 1, - 1, 1, 1, 0, 1, 0, 1, 0, 1, 0, 0, 2, 2, 2, 2, 2, - 2, 0, 0, 0, 0, 11, 11, 0, 0, 0, 10, 10, 12, 2, 16, 6, - 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 6, 6, 7, 7, 6, - 3, 8, 8, 6, 6, 6, 6, 3, 4, 3, 6, 6, 6, 3, 3, 3, - 2, 0, 2, 1, 2, 0, 0, 9, 5, 7, 4, 4, 4, 4, 4, 5, - 4, 4, 4, 5, 6, 5, 5, 5, 5, 6, 7, 0, 10, 1, 1, 1, - 1, 9, 11, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, - 0, 1, 2, 2, 1, 1, 1, 2, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 5, 5, 5, 4, 1, + 1, 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 1, 0, 1, 0, + 1, 0, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, + 0, 0, 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, + 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 2, 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, + 3, 4, 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, + 9, 5, 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, + 5, 5, 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, + 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, 2, 1, 1, 1, + 2, } @(rodata) -DECODE_BUCKET_LIST := [5379]u16{ +DECODE_BUCKET_LIST := [5359]u16{ 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, 11, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 23, 24, 25, 26, 27, 28, 29, 30, 31, 25, 26, 32, 33, 34, 35, 32, 36, @@ -1892,228 +1885,226 @@ DECODE_BUCKET_LIST := [5379]u16{ 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 810, 809, 811, 812, 813, 814, 815, 816, 817, 818, 819, 820, 821, 822, 823, 824, 827, 825, 826, 830, 829, 828, 831, 832, 834, 833, 835, 836, 837, 838, 839, - 840, 841, 844, 843, 842, 845, 847, 846, 848, 850, 849, 852, 853, 851, 856, 855, - 854, 822, 823, 857, 858, 859, 860, 862, 861, 863, 865, 866, 864, 867, 869, 868, - 871, 870, 872, 874, 873, 875, 835, 836, 843, 844, 842, 845, 846, 847, 849, 850, - 848, 851, 852, 853, 854, 855, 856, 837, 838, 839, 857, 858, 859, 860, 862, 861, - 863, 866, 865, 864, 867, 868, 869, 871, 870, 872, 874, 873, 875, 840, 841, 876, - 877, 878, 879, 880, 881, 882, 883, 884, 885, 886, 887, 888, 876, 877, 878, 879, - 880, 889, 890, 881, 882, 888, 891, 892, 893, 894, 895, 896, 897, 898, 899, 900, - 901, 902, 903, 904, 905, 906, 907, 908, 909, 910, 911, 912, 913, 914, 915, 916, - 917, 918, 919, 920, 921, 922, 923, 924, 925, 926, 927, 928, 929, 930, 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1327, 1328, 1329, 1330, 1544, 1553, 1293, + 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, 1330, 1542, 1543, + 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, 1328, 1329, + 1330, 1543, 1544, 1292, 1553, 1295, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327, + 1328, 1329, 1330, 1544, 1293, 1553, 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, + 1327, 1328, 1329, 1330, 1544, 1553, 1293, 1296, 1554, 1319, 1320, 1321, 1322, 1323, 1324, 1325, + 1326, 1327, 1328, 1329, 1330, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, + 1335, 1524, 1525, 1526, 1527, 1528, 1529, 1534, 1535, 1536, 1537, 1539, 1540, 1541, 1554, 1333, + 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1554, 1333, 1334, 1335, 1524, 1525, + 1526, 1527, 1528, 1529, 1534, 1535, 1536, 1537, 1539, 1540, 1541, 1554, 1333, 1334, 1335, } DECODE_INDEX_A32 := [256]lib.Decode_Index{ @@ -2189,576 +2180,576 @@ DECODE_INDEX_A32 := [256]lib.Decode_Index{ 0x45 = { 1838, 2}, 0x46 = { 1840, 1}, 0x47 = { 1841, 1}, - 0x48 = { 1842, 16}, - 0x49 = { 1858, 1}, - 0x4A = { 1859, 20}, - 0x4B = { 1879, 1}, - 0x4C = { 1880, 16}, - 0x4D = { 1896, 2}, - 0x4E = { 1898, 20}, - 0x4F = { 1918, 1}, - 0x50 = { 1919, 1}, - 0x51 = { 1920, 1}, - 0x52 = { 1921, 1}, - 0x53 = { 1922, 1}, - 0x54 = { 1923, 1}, - 0x55 = { 1924, 1}, - 0x56 = { 1925, 1}, - 0x57 = { 1926, 6}, - 0x58 = { 1932, 1}, - 0x59 = { 1933, 1}, - 0x5A = { 1934, 1}, - 0x5B = { 1935, 1}, - 0x5C = { 1936, 1}, - 0x5D = { 1937, 3}, - 0x5E = { 1940, 1}, - 0x5F = { 1941, 1}, - 0x61 = { 1942, 6}, - 0x62 = { 1948, 6}, - 0x63 = { 1954, 6}, - 0x65 = { 1960, 6}, - 0x66 = { 1966, 6}, - 0x67 = { 1972, 6}, - 0x68 = { 1978, 5}, - 0x6A = { 1983, 4}, - 0x6B = { 1987, 5}, - 0x6C = { 1992, 2}, - 0x6E = { 1994, 4}, - 0x6F = { 1998, 5}, - 0x70 = { 2003, 9}, - 0x71 = { 2012, 2}, - 0x73 = { 2014, 1}, - 0x74 = { 2015, 5}, - 0x75 = { 2020, 7}, - 0x78 = { 2027, 3}, - 0x79 = { 2030, 1}, - 0x7A = { 2031, 1}, - 0x7B = { 2032, 1}, - 0x7C = { 2033, 3}, - 0x7D = { 2036, 3}, - 0x7E = { 2039, 1}, - 0x7F = { 2040, 2}, - 0x80 = { 2042, 1}, - 0x81 = { 2043, 2}, - 0x82 = { 2045, 1}, - 0x83 = { 2046, 2}, - 0x84 = { 2048, 1}, - 0x85 = { 2049, 1}, - 0x86 = { 2050, 1}, - 0x87 = { 2051, 1}, - 0x88 = { 2052, 2}, - 0x89 = { 2054, 3}, - 0x8A = { 2057, 2}, - 0x8B = { 2059, 4}, - 0x8C = { 2063, 1}, - 0x8D = { 2064, 1}, - 0x8E = { 2065, 1}, - 0x8F = { 2066, 1}, - 0x90 = { 2067, 1}, - 0x91 = { 2068, 2}, - 0x92 = { 2070, 2}, - 0x93 = { 2072, 2}, - 0x94 = { 2074, 1}, - 0x95 = { 2075, 1}, - 0x96 = { 2076, 1}, - 0x97 = { 2077, 1}, - 0x98 = { 2078, 1}, - 0x99 = { 2079, 2}, - 0x9A = { 2081, 1}, - 0x9B = { 2082, 2}, - 0x9C = { 2084, 1}, - 0x9D = { 2085, 1}, - 0x9E = { 2086, 1}, - 0x9F = { 2087, 1}, - 0xA0 = { 2088, 2}, - 0xA1 = { 2090, 2}, - 0xA2 = { 2092, 2}, - 0xA3 = { 2094, 2}, - 0xA4 = { 2096, 2}, - 0xA5 = { 2098, 2}, - 0xA6 = { 2100, 2}, - 0xA7 = { 2102, 2}, - 0xA8 = { 2104, 2}, - 0xA9 = { 2106, 2}, - 0xAA = { 2108, 2}, - 0xAB = { 2110, 2}, - 0xAC = { 2112, 2}, - 0xAD = { 2114, 2}, - 0xAE = { 2116, 2}, - 0xAF = { 2118, 2}, - 0xB0 = { 2120, 2}, - 0xB1 = { 2122, 2}, - 0xB2 = { 2124, 2}, - 0xB3 = { 2126, 2}, - 0xB4 = { 2128, 2}, - 0xB5 = { 2130, 2}, - 0xB6 = { 2132, 2}, - 0xB7 = { 2134, 2}, - 0xB8 = { 2136, 2}, - 0xB9 = { 2138, 2}, - 0xBA = { 2140, 2}, - 0xBB = { 2142, 2}, - 0xBC = { 2144, 2}, - 0xBD = { 2146, 2}, - 0xBE = { 2148, 2}, - 0xBF = { 2150, 2}, - 0xC0 = { 2152, 7}, - 0xC1 = { 2159, 4}, - 0xC2 = { 2163, 12}, - 0xC3 = { 2175, 5}, - 0xC4 = { 2180, 11}, - 0xC5 = { 2191, 8}, - 0xC6 = { 2199, 12}, - 0xC7 = { 2211, 5}, - 0xC8 = { 2216, 6}, - 0xC9 = { 2222, 6}, - 0xCA = { 2228, 12}, - 0xCB = { 2240, 8}, - 0xCC = { 2248, 6}, - 0xCD = { 2254, 6}, - 0xCE = { 2260, 12}, - 0xCF = { 2272, 6}, - 0xD0 = { 2278, 4}, - 0xD1 = { 2282, 4}, - 0xD2 = { 2286, 4}, - 0xD3 = { 2290, 2}, - 0xD4 = { 2292, 4}, - 0xD5 = { 2296, 4}, - 0xD6 = { 2300, 2}, - 0xD7 = { 2302, 2}, - 0xD8 = { 2304, 4}, - 0xD9 = { 2308, 4}, - 0xDA = { 2312, 2}, - 0xDB = { 2314, 2}, - 0xDC = { 2316, 4}, - 0xDD = { 2320, 4}, - 0xDE = { 2324, 2}, - 0xDF = { 2326, 2}, - 0xE0 = { 2328, 20}, - 0xE1 = { 2348, 14}, - 0xE2 = { 2362, 20}, - 0xE3 = { 2382, 15}, - 0xE4 = { 2397, 18}, - 0xE5 = { 2415, 13}, - 0xE6 = { 2428, 19}, - 0xE7 = { 2447, 15}, - 0xE8 = { 2462, 15}, - 0xE9 = { 2477, 11}, - 0xEA = { 2488, 11}, - 0xEB = { 2499, 77}, - 0xEC = { 2576, 16}, - 0xED = { 2592, 11}, - 0xEE = { 2603, 13}, - 0xEF = { 2616, 78}, - 0xF0 = { 2694, 3}, - 0xF1 = { 2697, 3}, - 0xF2 = { 2700, 3}, - 0xF3 = { 2703, 3}, - 0xF4 = { 2706, 3}, - 0xF5 = { 2709, 3}, - 0xF6 = { 2712, 3}, - 0xF7 = { 2715, 3}, - 0xF8 = { 2718, 1}, - 0xF9 = { 2719, 1}, - 0xFA = { 2720, 1}, - 0xFB = { 2721, 1}, - 0xFC = { 2722, 1}, - 0xFD = { 2723, 1}, - 0xFE = { 2724, 1}, - 0xFF = { 2725, 1}, + 0x48 = { 1842, 13}, + 0x49 = { 1855, 1}, + 0x4A = { 1856, 17}, + 0x4B = { 1873, 1}, + 0x4C = { 1874, 13}, + 0x4D = { 1887, 2}, + 0x4E = { 1889, 17}, + 0x4F = { 1906, 1}, + 0x50 = { 1907, 1}, + 0x51 = { 1908, 1}, + 0x52 = { 1909, 1}, + 0x53 = { 1910, 1}, + 0x54 = { 1911, 1}, + 0x55 = { 1912, 1}, + 0x56 = { 1913, 1}, + 0x57 = { 1914, 6}, + 0x58 = { 1920, 1}, + 0x59 = { 1921, 1}, + 0x5A = { 1922, 1}, + 0x5B = { 1923, 1}, + 0x5C = { 1924, 1}, + 0x5D = { 1925, 3}, + 0x5E = { 1928, 1}, + 0x5F = { 1929, 1}, + 0x61 = { 1930, 6}, + 0x62 = { 1936, 6}, + 0x63 = { 1942, 6}, + 0x65 = { 1948, 6}, + 0x66 = { 1954, 6}, + 0x67 = { 1960, 6}, + 0x68 = { 1966, 5}, + 0x6A = { 1971, 4}, + 0x6B = { 1975, 5}, + 0x6C = { 1980, 2}, + 0x6E = { 1982, 4}, + 0x6F = { 1986, 5}, + 0x70 = { 1991, 9}, + 0x71 = { 2000, 2}, + 0x73 = { 2002, 1}, + 0x74 = { 2003, 5}, + 0x75 = { 2008, 7}, + 0x78 = { 2015, 3}, + 0x79 = { 2018, 1}, + 0x7A = { 2019, 1}, + 0x7B = { 2020, 1}, + 0x7C = { 2021, 3}, + 0x7D = { 2024, 3}, + 0x7E = { 2027, 1}, + 0x7F = { 2028, 2}, + 0x80 = { 2030, 1}, + 0x81 = { 2031, 2}, + 0x82 = { 2033, 1}, + 0x83 = { 2034, 2}, + 0x84 = { 2036, 1}, + 0x85 = { 2037, 1}, + 0x86 = { 2038, 1}, + 0x87 = { 2039, 1}, + 0x88 = { 2040, 2}, + 0x89 = { 2042, 3}, + 0x8A = { 2045, 2}, + 0x8B = { 2047, 4}, + 0x8C = { 2051, 1}, + 0x8D = { 2052, 1}, + 0x8E = { 2053, 1}, + 0x8F = { 2054, 1}, + 0x90 = { 2055, 1}, + 0x91 = { 2056, 2}, + 0x92 = { 2058, 2}, + 0x93 = { 2060, 2}, + 0x94 = { 2062, 1}, + 0x95 = { 2063, 1}, + 0x96 = { 2064, 1}, + 0x97 = { 2065, 1}, + 0x98 = { 2066, 1}, + 0x99 = { 2067, 2}, + 0x9A = { 2069, 1}, + 0x9B = { 2070, 2}, + 0x9C = { 2072, 1}, + 0x9D = { 2073, 1}, + 0x9E = { 2074, 1}, + 0x9F = { 2075, 1}, + 0xA0 = { 2076, 2}, + 0xA1 = { 2078, 2}, + 0xA2 = { 2080, 2}, + 0xA3 = { 2082, 2}, + 0xA4 = { 2084, 2}, + 0xA5 = { 2086, 2}, + 0xA6 = { 2088, 2}, + 0xA7 = { 2090, 2}, + 0xA8 = { 2092, 2}, + 0xA9 = { 2094, 2}, + 0xAA = { 2096, 2}, + 0xAB = { 2098, 2}, + 0xAC = { 2100, 2}, + 0xAD = { 2102, 2}, + 0xAE = { 2104, 2}, + 0xAF = { 2106, 2}, + 0xB0 = { 2108, 2}, + 0xB1 = { 2110, 2}, + 0xB2 = { 2112, 2}, + 0xB3 = { 2114, 2}, + 0xB4 = { 2116, 2}, + 0xB5 = { 2118, 2}, + 0xB6 = { 2120, 2}, + 0xB7 = { 2122, 2}, + 0xB8 = { 2124, 2}, + 0xB9 = { 2126, 2}, + 0xBA = { 2128, 2}, + 0xBB = { 2130, 2}, + 0xBC = { 2132, 2}, + 0xBD = { 2134, 2}, + 0xBE = { 2136, 2}, + 0xBF = { 2138, 2}, + 0xC0 = { 2140, 7}, + 0xC1 = { 2147, 4}, + 0xC2 = { 2151, 12}, + 0xC3 = { 2163, 5}, + 0xC4 = { 2168, 11}, + 0xC5 = { 2179, 8}, + 0xC6 = { 2187, 12}, + 0xC7 = { 2199, 5}, + 0xC8 = { 2204, 6}, + 0xC9 = { 2210, 6}, + 0xCA = { 2216, 12}, + 0xCB = { 2228, 8}, + 0xCC = { 2236, 6}, + 0xCD = { 2242, 6}, + 0xCE = { 2248, 12}, + 0xCF = { 2260, 6}, + 0xD0 = { 2266, 4}, + 0xD1 = { 2270, 4}, + 0xD2 = { 2274, 4}, + 0xD3 = { 2278, 2}, + 0xD4 = { 2280, 4}, + 0xD5 = { 2284, 4}, + 0xD6 = { 2288, 2}, + 0xD7 = { 2290, 2}, + 0xD8 = { 2292, 4}, + 0xD9 = { 2296, 4}, + 0xDA = { 2300, 2}, + 0xDB = { 2302, 2}, + 0xDC = { 2304, 4}, + 0xDD = { 2308, 4}, + 0xDE = { 2312, 2}, + 0xDF = { 2314, 2}, + 0xE0 = { 2316, 19}, + 0xE1 = { 2335, 14}, + 0xE2 = { 2349, 19}, + 0xE3 = { 2368, 15}, + 0xE4 = { 2383, 17}, + 0xE5 = { 2400, 13}, + 0xE6 = { 2413, 18}, + 0xE7 = { 2431, 15}, + 0xE8 = { 2446, 14}, + 0xE9 = { 2460, 11}, + 0xEA = { 2471, 10}, + 0xEB = { 2481, 77}, + 0xEC = { 2558, 15}, + 0xED = { 2573, 11}, + 0xEE = { 2584, 12}, + 0xEF = { 2596, 78}, + 0xF0 = { 2674, 3}, + 0xF1 = { 2677, 3}, + 0xF2 = { 2680, 3}, + 0xF3 = { 2683, 3}, + 0xF4 = { 2686, 3}, + 0xF5 = { 2689, 3}, + 0xF6 = { 2692, 3}, + 0xF7 = { 2695, 3}, + 0xF8 = { 2698, 1}, + 0xF9 = { 2699, 1}, + 0xFA = { 2700, 1}, + 0xFB = { 2701, 1}, + 0xFC = { 2702, 1}, + 0xFD = { 2703, 1}, + 0xFE = { 2704, 1}, + 0xFF = { 2705, 1}, } DECODE_INDEX_T32 := [128]lib.Decode_Index{ - 0x74 = { 2726, 23}, - 0x75 = { 2749, 19}, - 0x76 = { 2768, 19}, - 0x77 = { 2787, 104}, - 0x78 = { 2891, 31}, - 0x79 = { 2922, 38}, - 0x7A = { 2960, 23}, - 0x7B = { 2983, 14}, - 0x7C = { 2997, 20}, - 0x7D = { 3017, 71}, - 0x7E = { 3088, 23}, - 0x7F = { 3111, 126}, + 0x74 = { 2706, 23}, + 0x75 = { 2729, 19}, + 0x76 = { 2748, 19}, + 0x77 = { 2767, 104}, + 0x78 = { 2871, 31}, + 0x79 = { 2902, 38}, + 0x7A = { 2940, 23}, + 0x7B = { 2963, 14}, + 0x7C = { 2977, 20}, + 0x7D = { 2997, 71}, + 0x7E = { 3068, 23}, + 0x7F = { 3091, 126}, } DECODE_INDEX_T16 := [64]lib.Decode_Index{ - 0x00 = { 3237, 1}, - 0x01 = { 3238, 1}, - 0x02 = { 3239, 1}, - 0x03 = { 3240, 1}, - 0x04 = { 3241, 1}, - 0x05 = { 3242, 1}, - 0x06 = { 3243, 2}, - 0x07 = { 3245, 2}, - 0x08 = { 3247, 1}, - 0x09 = { 3248, 1}, - 0x0A = { 3249, 1}, - 0x0B = { 3250, 1}, - 0x0C = { 3251, 1}, - 0x0D = { 3252, 1}, - 0x0E = { 3253, 1}, - 0x0F = { 3254, 1}, - 0x10 = { 3255, 16}, - 0x11 = { 3271, 7}, - 0x12 = { 3278, 1}, - 0x13 = { 3279, 1}, - 0x14 = { 3280, 2}, - 0x15 = { 3282, 2}, - 0x16 = { 3284, 2}, - 0x17 = { 3286, 2}, - 0x18 = { 3288, 1}, - 0x19 = { 3289, 1}, - 0x1A = { 3290, 1}, - 0x1B = { 3291, 1}, - 0x1C = { 3292, 1}, - 0x1D = { 3293, 1}, - 0x1E = { 3294, 1}, - 0x1F = { 3295, 1}, - 0x20 = { 3296, 1}, - 0x21 = { 3297, 1}, - 0x22 = { 3298, 1}, - 0x23 = { 3299, 1}, - 0x24 = { 3300, 1}, - 0x25 = { 3301, 1}, - 0x26 = { 3302, 1}, - 0x27 = { 3303, 1}, - 0x28 = { 3304, 1}, - 0x29 = { 3305, 1}, - 0x2A = { 3306, 1}, - 0x2B = { 3307, 1}, - 0x2C = { 3308, 7}, - 0x2D = { 3315, 2}, - 0x2E = { 3317, 4}, - 0x2F = { 3321, 8}, - 0x30 = { 3329, 1}, - 0x31 = { 3330, 1}, - 0x32 = { 3331, 1}, - 0x33 = { 3332, 1}, - 0x34 = { 3333, 1}, - 0x35 = { 3334, 1}, - 0x36 = { 3335, 1}, - 0x37 = { 3336, 3}, - 0x38 = { 3339, 1}, - 0x39 = { 3340, 1}, + 0x00 = { 3217, 1}, + 0x01 = { 3218, 1}, + 0x02 = { 3219, 1}, + 0x03 = { 3220, 1}, + 0x04 = { 3221, 1}, + 0x05 = { 3222, 1}, + 0x06 = { 3223, 2}, + 0x07 = { 3225, 2}, + 0x08 = { 3227, 1}, + 0x09 = { 3228, 1}, + 0x0A = { 3229, 1}, + 0x0B = { 3230, 1}, + 0x0C = { 3231, 1}, + 0x0D = { 3232, 1}, + 0x0E = { 3233, 1}, + 0x0F = { 3234, 1}, + 0x10 = { 3235, 16}, + 0x11 = { 3251, 7}, + 0x12 = { 3258, 1}, + 0x13 = { 3259, 1}, + 0x14 = { 3260, 2}, + 0x15 = { 3262, 2}, + 0x16 = { 3264, 2}, + 0x17 = { 3266, 2}, + 0x18 = { 3268, 1}, + 0x19 = { 3269, 1}, + 0x1A = { 3270, 1}, + 0x1B = { 3271, 1}, + 0x1C = { 3272, 1}, + 0x1D = { 3273, 1}, + 0x1E = { 3274, 1}, + 0x1F = { 3275, 1}, + 0x20 = { 3276, 1}, + 0x21 = { 3277, 1}, + 0x22 = { 3278, 1}, + 0x23 = { 3279, 1}, + 0x24 = { 3280, 1}, + 0x25 = { 3281, 1}, + 0x26 = { 3282, 1}, + 0x27 = { 3283, 1}, + 0x28 = { 3284, 1}, + 0x29 = { 3285, 1}, + 0x2A = { 3286, 1}, + 0x2B = { 3287, 1}, + 0x2C = { 3288, 7}, + 0x2D = { 3295, 2}, + 0x2E = { 3297, 4}, + 0x2F = { 3301, 8}, + 0x30 = { 3309, 1}, + 0x31 = { 3310, 1}, + 0x32 = { 3311, 1}, + 0x33 = { 3312, 1}, + 0x34 = { 3313, 1}, + 0x35 = { 3314, 1}, + 0x36 = { 3315, 1}, + 0x37 = { 3316, 3}, + 0x38 = { 3319, 1}, + 0x39 = { 3320, 1}, } DECODE_INDEX_T32_SUB := [4096]lib.Decode_Index{ - 0xE84 = { 3341, 6}, - 0xE85 = { 3347, 2}, - 0xE86 = { 3349, 1}, - 0xE87 = { 3350, 1}, - 0xE88 = { 3351, 1}, - 0xE89 = { 3352, 1}, - 0xE8A = { 3353, 1}, - 0xE8B = { 3354, 2}, - 0xE8C = { 3356, 4}, - 0xE8D = { 3360, 6}, - 0xE8E = { 3366, 1}, - 0xE8F = { 3367, 1}, - 0xE90 = { 3368, 1}, - 0xE91 = { 3369, 1}, - 0xE92 = { 3370, 2}, - 0xE93 = { 3372, 1}, - 0xE94 = { 3373, 1}, - 0xE95 = { 3374, 1}, - 0xE96 = { 3375, 1}, - 0xE97 = { 3376, 2}, - 0xE9C = { 3378, 1}, - 0xE9D = { 3379, 1}, - 0xE9E = { 3380, 1}, - 0xE9F = { 3381, 1}, - 0xEA0 = { 3382, 2}, - 0xEA1 = { 3384, 3}, - 0xEA2 = { 3387, 1}, - 0xEA3 = { 3388, 1}, - 0xEA4 = { 3389, 7}, - 0xEA5 = { 3396, 7}, - 0xEA6 = { 3403, 1}, - 0xEA7 = { 3404, 1}, - 0xEA8 = { 3405, 1}, - 0xEA9 = { 3406, 2}, - 0xEB1 = { 3408, 1}, - 0xEB4 = { 3409, 1}, - 0xEB5 = { 3410, 1}, - 0xEB6 = { 3411, 1}, - 0xEB7 = { 3412, 1}, - 0xEBB = { 3413, 1}, - 0xEBC = { 3414, 1}, - 0xEBD = { 3415, 1}, - 0xEC0 = { 3416, 2}, - 0xEC1 = { 3418, 1}, - 0xEC2 = { 3419, 3}, - 0xEC3 = { 3422, 2}, - 0xEC4 = { 3424, 2}, - 0xEC5 = { 3426, 1}, - 0xEC6 = { 3427, 7}, - 0xEC7 = { 3434, 2}, - 0xEC8 = { 3436, 1}, - 0xEC9 = { 3437, 1}, - 0xECA = { 3438, 2}, - 0xECB = { 3440, 2}, - 0xECC = { 3442, 1}, - 0xECD = { 3443, 1}, - 0xECE = { 3444, 2}, - 0xECF = { 3446, 2}, - 0xED6 = { 3448, 4}, - 0xED8 = { 3452, 4}, - 0xED9 = { 3456, 4}, - 0xEDC = { 3460, 4}, - 0xEDD = { 3464, 4}, - 0xEE0 = { 3468, 24}, - 0xEE1 = { 3492, 23}, - 0xEE2 = { 3515, 22}, - 0xEE3 = { 3537, 29}, - 0xEE4 = { 3566, 23}, - 0xEE5 = { 3589, 22}, - 0xEE6 = { 3611, 22}, - 0xEE7 = { 3633, 29}, - 0xEE8 = { 3662, 28}, - 0xEE9 = { 3690, 12}, - 0xEEA = { 3702, 13}, - 0xEEB = { 3715, 18}, - 0xEEC = { 3733, 27}, - 0xEED = { 3760, 13}, - 0xEEE = { 3773, 22}, - 0xEEF = { 3795, 23}, - 0xEF0 = { 3818, 15}, - 0xEF1 = { 3833, 15}, - 0xEF2 = { 3848, 15}, - 0xEF3 = { 3863, 15}, - 0xEF4 = { 3878, 15}, - 0xEF5 = { 3893, 15}, - 0xEF6 = { 3908, 15}, - 0xEF7 = { 3923, 15}, - 0xEF8 = { 3938, 3}, - 0xEF9 = { 3941, 3}, - 0xEFA = { 3944, 3}, - 0xEFB = { 3947, 3}, - 0xEFC = { 3950, 3}, - 0xEFD = { 3953, 3}, - 0xEFE = { 3956, 3}, - 0xEFF = { 3959, 3}, - 0xF00 = { 3962, 12}, - 0xF01 = { 3974, 11}, - 0xF02 = { 3985, 8}, - 0xF03 = { 3993, 8}, - 0xF04 = { 4001, 9}, - 0xF05 = { 4010, 6}, - 0xF06 = { 4016, 5}, - 0xF07 = { 4021, 5}, - 0xF08 = { 4026, 6}, - 0xF09 = { 4032, 6}, - 0xF0A = { 4038, 4}, - 0xF0B = { 4042, 4}, - 0xF0C = { 4046, 4}, - 0xF0D = { 4050, 3}, - 0xF0E = { 4053, 4}, - 0xF0F = { 4057, 4}, - 0xF10 = { 4061, 7}, - 0xF11 = { 4068, 7}, - 0xF12 = { 4075, 6}, - 0xF13 = { 4081, 6}, - 0xF14 = { 4087, 5}, - 0xF15 = { 4092, 4}, - 0xF16 = { 4096, 5}, - 0xF17 = { 4101, 5}, - 0xF18 = { 4106, 5}, - 0xF19 = { 4111, 4}, - 0xF1A = { 4115, 4}, - 0xF1B = { 4119, 5}, - 0xF1C = { 4124, 5}, - 0xF1D = { 4129, 4}, - 0xF1E = { 4133, 4}, - 0xF1F = { 4137, 4}, - 0xF20 = { 4141, 5}, - 0xF21 = { 4146, 4}, - 0xF22 = { 4150, 4}, - 0xF23 = { 4154, 4}, - 0xF24 = { 4158, 5}, - 0xF25 = { 4163, 3}, - 0xF26 = { 4166, 4}, - 0xF27 = { 4170, 4}, - 0xF28 = { 4174, 5}, - 0xF29 = { 4179, 4}, - 0xF2A = { 4183, 4}, - 0xF2B = { 4187, 4}, - 0xF2C = { 4191, 5}, - 0xF2D = { 4196, 3}, - 0xF2E = { 4199, 4}, - 0xF2F = { 4203, 4}, - 0xF30 = { 4207, 6}, - 0xF31 = { 4213, 4}, - 0xF32 = { 4217, 6}, - 0xF33 = { 4223, 4}, - 0xF34 = { 4227, 5}, - 0xF35 = { 4232, 3}, - 0xF36 = { 4235, 6}, - 0xF37 = { 4241, 4}, - 0xF38 = { 4245, 7}, - 0xF39 = { 4252, 4}, - 0xF3A = { 4256, 19}, - 0xF3B = { 4275, 9}, - 0xF3C = { 4284, 5}, - 0xF3D = { 4289, 3}, - 0xF3E = { 4292, 5}, - 0xF3F = { 4297, 4}, - 0xF40 = { 4301, 7}, - 0xF41 = { 4308, 7}, - 0xF42 = { 4315, 5}, - 0xF43 = { 4320, 5}, - 0xF44 = { 4325, 7}, - 0xF45 = { 4332, 6}, - 0xF46 = { 4338, 5}, - 0xF47 = { 4343, 5}, - 0xF48 = { 4348, 6}, - 0xF49 = { 4354, 6}, - 0xF4A = { 4360, 4}, - 0xF4B = { 4364, 4}, - 0xF4C = { 4368, 4}, - 0xF4D = { 4372, 3}, - 0xF4E = { 4375, 4}, - 0xF4F = { 4379, 4}, - 0xF50 = { 4383, 5}, - 0xF51 = { 4388, 5}, - 0xF52 = { 4393, 4}, - 0xF53 = { 4397, 4}, - 0xF54 = { 4401, 5}, - 0xF55 = { 4406, 4}, - 0xF56 = { 4410, 5}, - 0xF57 = { 4415, 5}, - 0xF58 = { 4420, 5}, - 0xF59 = { 4425, 4}, - 0xF5A = { 4429, 4}, - 0xF5B = { 4433, 5}, - 0xF5C = { 4438, 5}, - 0xF5D = { 4443, 4}, - 0xF5E = { 4447, 4}, - 0xF5F = { 4451, 4}, - 0xF60 = { 4455, 5}, - 0xF61 = { 4460, 4}, - 0xF62 = { 4464, 4}, - 0xF63 = { 4468, 4}, - 0xF64 = { 4472, 5}, - 0xF65 = { 4477, 3}, - 0xF66 = { 4480, 4}, - 0xF67 = { 4484, 4}, - 0xF68 = { 4488, 5}, - 0xF69 = { 4493, 4}, - 0xF6A = { 4497, 4}, - 0xF6B = { 4501, 4}, - 0xF6C = { 4505, 5}, - 0xF6D = { 4510, 3}, - 0xF6E = { 4513, 4}, - 0xF6F = { 4517, 4}, - 0xF70 = { 4521, 5}, - 0xF71 = { 4526, 4}, - 0xF72 = { 4530, 4}, - 0xF73 = { 4534, 4}, - 0xF74 = { 4538, 4}, - 0xF75 = { 4542, 3}, - 0xF76 = { 4545, 4}, - 0xF77 = { 4549, 4}, - 0xF78 = { 4553, 8}, - 0xF79 = { 4561, 4}, - 0xF7A = { 4565, 4}, - 0xF7B = { 4569, 4}, - 0xF7C = { 4573, 4}, - 0xF7D = { 4577, 3}, - 0xF7E = { 4580, 4}, - 0xF7F = { 4584, 5}, - 0xF80 = { 4589, 1}, - 0xF81 = { 4590, 1}, - 0xF82 = { 4591, 1}, - 0xF83 = { 4592, 2}, - 0xF84 = { 4594, 1}, - 0xF85 = { 4595, 2}, - 0xF88 = { 4597, 1}, - 0xF89 = { 4598, 2}, - 0xF8A = { 4600, 1}, - 0xF8B = { 4601, 1}, - 0xF8C = { 4602, 1}, - 0xF8D = { 4603, 2}, - 0xF91 = { 4605, 1}, - 0xF93 = { 4606, 1}, - 0xF99 = { 4607, 2}, - 0xF9B = { 4609, 1}, - 0xFA0 = { 4610, 3}, - 0xFA1 = { 4613, 3}, - 0xFA2 = { 4616, 3}, - 0xFA3 = { 4619, 3}, - 0xFA4 = { 4622, 3}, - 0xFA5 = { 4625, 3}, - 0xFA6 = { 4628, 1}, - 0xFA7 = { 4629, 1}, - 0xFA8 = { 4630, 10}, - 0xFA9 = { 4640, 10}, - 0xFAA = { 4650, 6}, - 0xFAB = { 4656, 1}, - 0xFAC = { 4657, 6}, - 0xFAD = { 4663, 6}, - 0xFAE = { 4669, 6}, - 0xFB0 = { 4675, 3}, - 0xFB5 = { 4678, 1}, - 0xFB8 = { 4679, 1}, - 0xFB9 = { 4680, 1}, - 0xFBA = { 4681, 1}, - 0xFBB = { 4682, 1}, - 0xFBC = { 4683, 1}, - 0xFBE = { 4684, 1}, - 0xFC0 = { 4685, 1}, - 0xFC1 = { 4686, 1}, - 0xFC2 = { 4687, 3}, - 0xFC3 = { 4690, 3}, - 0xFC4 = { 4693, 1}, - 0xFC5 = { 4694, 1}, - 0xFC6 = { 4695, 2}, - 0xFC7 = { 4697, 2}, - 0xFC8 = { 4699, 7}, - 0xFC9 = { 4706, 11}, - 0xFCA = { 4717, 3}, - 0xFCB = { 4720, 3}, - 0xFCC = { 4723, 7}, - 0xFCD = { 4730, 7}, - 0xFCE = { 4737, 2}, - 0xFCF = { 4739, 2}, - 0xFD2 = { 4741, 1}, - 0xFD3 = { 4742, 1}, - 0xFD9 = { 4743, 4}, - 0xFDA = { 4747, 1}, - 0xFDB = { 4748, 1}, - 0xFE0 = { 4749, 28}, - 0xFE1 = { 4777, 26}, - 0xFE2 = { 4803, 26}, - 0xFE3 = { 4829, 32}, - 0xFE4 = { 4861, 29}, - 0xFE5 = { 4890, 27}, - 0xFE6 = { 4917, 27}, - 0xFE7 = { 4944, 33}, - 0xFE8 = { 4977, 32}, - 0xFE9 = { 5009, 17}, - 0xFEA = { 5026, 17}, - 0xFEB = { 5043, 29}, - 0xFEC = { 5072, 31}, - 0xFED = { 5103, 18}, - 0xFEE = { 5121, 26}, - 0xFEF = { 5147, 32}, - 0xFF0 = { 5179, 19}, - 0xFF1 = { 5198, 18}, - 0xFF2 = { 5216, 17}, - 0xFF3 = { 5233, 17}, - 0xFF4 = { 5250, 19}, - 0xFF5 = { 5269, 18}, - 0xFF6 = { 5287, 17}, - 0xFF7 = { 5304, 17}, - 0xFF8 = { 5321, 4}, - 0xFF9 = { 5325, 4}, - 0xFFA = { 5329, 4}, - 0xFFB = { 5333, 17}, - 0xFFC = { 5350, 4}, - 0xFFD = { 5354, 4}, - 0xFFE = { 5358, 4}, - 0xFFF = { 5362, 17}, + 0xE84 = { 3321, 6}, + 0xE85 = { 3327, 2}, + 0xE86 = { 3329, 1}, + 0xE87 = { 3330, 1}, + 0xE88 = { 3331, 1}, + 0xE89 = { 3332, 1}, + 0xE8A = { 3333, 1}, + 0xE8B = { 3334, 2}, + 0xE8C = { 3336, 4}, + 0xE8D = { 3340, 6}, + 0xE8E = { 3346, 1}, + 0xE8F = { 3347, 1}, + 0xE90 = { 3348, 1}, + 0xE91 = { 3349, 1}, + 0xE92 = { 3350, 2}, + 0xE93 = { 3352, 1}, + 0xE94 = { 3353, 1}, + 0xE95 = { 3354, 1}, + 0xE96 = { 3355, 1}, + 0xE97 = { 3356, 2}, + 0xE9C = { 3358, 1}, + 0xE9D = { 3359, 1}, + 0xE9E = { 3360, 1}, + 0xE9F = { 3361, 1}, + 0xEA0 = { 3362, 2}, + 0xEA1 = { 3364, 3}, + 0xEA2 = { 3367, 1}, + 0xEA3 = { 3368, 1}, + 0xEA4 = { 3369, 7}, + 0xEA5 = { 3376, 7}, + 0xEA6 = { 3383, 1}, + 0xEA7 = { 3384, 1}, + 0xEA8 = { 3385, 1}, + 0xEA9 = { 3386, 2}, + 0xEB1 = { 3388, 1}, + 0xEB4 = { 3389, 1}, + 0xEB5 = { 3390, 1}, + 0xEB6 = { 3391, 1}, + 0xEB7 = { 3392, 1}, + 0xEBB = { 3393, 1}, + 0xEBC = { 3394, 1}, + 0xEBD = { 3395, 1}, + 0xEC0 = { 3396, 2}, + 0xEC1 = { 3398, 1}, + 0xEC2 = { 3399, 3}, + 0xEC3 = { 3402, 2}, + 0xEC4 = { 3404, 2}, + 0xEC5 = { 3406, 1}, + 0xEC6 = { 3407, 7}, + 0xEC7 = { 3414, 2}, + 0xEC8 = { 3416, 1}, + 0xEC9 = { 3417, 1}, + 0xECA = { 3418, 2}, + 0xECB = { 3420, 2}, + 0xECC = { 3422, 1}, + 0xECD = { 3423, 1}, + 0xECE = { 3424, 2}, + 0xECF = { 3426, 2}, + 0xED6 = { 3428, 4}, + 0xED8 = { 3432, 4}, + 0xED9 = { 3436, 4}, + 0xEDC = { 3440, 4}, + 0xEDD = { 3444, 4}, + 0xEE0 = { 3448, 24}, + 0xEE1 = { 3472, 23}, + 0xEE2 = { 3495, 22}, + 0xEE3 = { 3517, 29}, + 0xEE4 = { 3546, 23}, + 0xEE5 = { 3569, 22}, + 0xEE6 = { 3591, 22}, + 0xEE7 = { 3613, 29}, + 0xEE8 = { 3642, 28}, + 0xEE9 = { 3670, 12}, + 0xEEA = { 3682, 13}, + 0xEEB = { 3695, 18}, + 0xEEC = { 3713, 27}, + 0xEED = { 3740, 13}, + 0xEEE = { 3753, 22}, + 0xEEF = { 3775, 23}, + 0xEF0 = { 3798, 15}, + 0xEF1 = { 3813, 15}, + 0xEF2 = { 3828, 15}, + 0xEF3 = { 3843, 15}, + 0xEF4 = { 3858, 15}, + 0xEF5 = { 3873, 15}, + 0xEF6 = { 3888, 15}, + 0xEF7 = { 3903, 15}, + 0xEF8 = { 3918, 3}, + 0xEF9 = { 3921, 3}, + 0xEFA = { 3924, 3}, + 0xEFB = { 3927, 3}, + 0xEFC = { 3930, 3}, + 0xEFD = { 3933, 3}, + 0xEFE = { 3936, 3}, + 0xEFF = { 3939, 3}, + 0xF00 = { 3942, 12}, + 0xF01 = { 3954, 11}, + 0xF02 = { 3965, 8}, + 0xF03 = { 3973, 8}, + 0xF04 = { 3981, 9}, + 0xF05 = { 3990, 6}, + 0xF06 = { 3996, 5}, + 0xF07 = { 4001, 5}, + 0xF08 = { 4006, 6}, + 0xF09 = { 4012, 6}, + 0xF0A = { 4018, 4}, + 0xF0B = { 4022, 4}, + 0xF0C = { 4026, 4}, + 0xF0D = { 4030, 3}, + 0xF0E = { 4033, 4}, + 0xF0F = { 4037, 4}, + 0xF10 = { 4041, 7}, + 0xF11 = { 4048, 7}, + 0xF12 = { 4055, 6}, + 0xF13 = { 4061, 6}, + 0xF14 = { 4067, 5}, + 0xF15 = { 4072, 4}, + 0xF16 = { 4076, 5}, + 0xF17 = { 4081, 5}, + 0xF18 = { 4086, 5}, + 0xF19 = { 4091, 4}, + 0xF1A = { 4095, 4}, + 0xF1B = { 4099, 5}, + 0xF1C = { 4104, 5}, + 0xF1D = { 4109, 4}, + 0xF1E = { 4113, 4}, + 0xF1F = { 4117, 4}, + 0xF20 = { 4121, 5}, + 0xF21 = { 4126, 4}, + 0xF22 = { 4130, 4}, + 0xF23 = { 4134, 4}, + 0xF24 = { 4138, 5}, + 0xF25 = { 4143, 3}, + 0xF26 = { 4146, 4}, + 0xF27 = { 4150, 4}, + 0xF28 = { 4154, 5}, + 0xF29 = { 4159, 4}, + 0xF2A = { 4163, 4}, + 0xF2B = { 4167, 4}, + 0xF2C = { 4171, 5}, + 0xF2D = { 4176, 3}, + 0xF2E = { 4179, 4}, + 0xF2F = { 4183, 4}, + 0xF30 = { 4187, 6}, + 0xF31 = { 4193, 4}, + 0xF32 = { 4197, 6}, + 0xF33 = { 4203, 4}, + 0xF34 = { 4207, 5}, + 0xF35 = { 4212, 3}, + 0xF36 = { 4215, 6}, + 0xF37 = { 4221, 4}, + 0xF38 = { 4225, 7}, + 0xF39 = { 4232, 4}, + 0xF3A = { 4236, 19}, + 0xF3B = { 4255, 9}, + 0xF3C = { 4264, 5}, + 0xF3D = { 4269, 3}, + 0xF3E = { 4272, 5}, + 0xF3F = { 4277, 4}, + 0xF40 = { 4281, 7}, + 0xF41 = { 4288, 7}, + 0xF42 = { 4295, 5}, + 0xF43 = { 4300, 5}, + 0xF44 = { 4305, 7}, + 0xF45 = { 4312, 6}, + 0xF46 = { 4318, 5}, + 0xF47 = { 4323, 5}, + 0xF48 = { 4328, 6}, + 0xF49 = { 4334, 6}, + 0xF4A = { 4340, 4}, + 0xF4B = { 4344, 4}, + 0xF4C = { 4348, 4}, + 0xF4D = { 4352, 3}, + 0xF4E = { 4355, 4}, + 0xF4F = { 4359, 4}, + 0xF50 = { 4363, 5}, + 0xF51 = { 4368, 5}, + 0xF52 = { 4373, 4}, + 0xF53 = { 4377, 4}, + 0xF54 = { 4381, 5}, + 0xF55 = { 4386, 4}, + 0xF56 = { 4390, 5}, + 0xF57 = { 4395, 5}, + 0xF58 = { 4400, 5}, + 0xF59 = { 4405, 4}, + 0xF5A = { 4409, 4}, + 0xF5B = { 4413, 5}, + 0xF5C = { 4418, 5}, + 0xF5D = { 4423, 4}, + 0xF5E = { 4427, 4}, + 0xF5F = { 4431, 4}, + 0xF60 = { 4435, 5}, + 0xF61 = { 4440, 4}, + 0xF62 = { 4444, 4}, + 0xF63 = { 4448, 4}, + 0xF64 = { 4452, 5}, + 0xF65 = { 4457, 3}, + 0xF66 = { 4460, 4}, + 0xF67 = { 4464, 4}, + 0xF68 = { 4468, 5}, + 0xF69 = { 4473, 4}, + 0xF6A = { 4477, 4}, + 0xF6B = { 4481, 4}, + 0xF6C = { 4485, 5}, + 0xF6D = { 4490, 3}, + 0xF6E = { 4493, 4}, + 0xF6F = { 4497, 4}, + 0xF70 = { 4501, 5}, + 0xF71 = { 4506, 4}, + 0xF72 = { 4510, 4}, + 0xF73 = { 4514, 4}, + 0xF74 = { 4518, 4}, + 0xF75 = { 4522, 3}, + 0xF76 = { 4525, 4}, + 0xF77 = { 4529, 4}, + 0xF78 = { 4533, 8}, + 0xF79 = { 4541, 4}, + 0xF7A = { 4545, 4}, + 0xF7B = { 4549, 4}, + 0xF7C = { 4553, 4}, + 0xF7D = { 4557, 3}, + 0xF7E = { 4560, 4}, + 0xF7F = { 4564, 5}, + 0xF80 = { 4569, 1}, + 0xF81 = { 4570, 1}, + 0xF82 = { 4571, 1}, + 0xF83 = { 4572, 2}, + 0xF84 = { 4574, 1}, + 0xF85 = { 4575, 2}, + 0xF88 = { 4577, 1}, + 0xF89 = { 4578, 2}, + 0xF8A = { 4580, 1}, + 0xF8B = { 4581, 1}, + 0xF8C = { 4582, 1}, + 0xF8D = { 4583, 2}, + 0xF91 = { 4585, 1}, + 0xF93 = { 4586, 1}, + 0xF99 = { 4587, 2}, + 0xF9B = { 4589, 1}, + 0xFA0 = { 4590, 3}, + 0xFA1 = { 4593, 3}, + 0xFA2 = { 4596, 3}, + 0xFA3 = { 4599, 3}, + 0xFA4 = { 4602, 3}, + 0xFA5 = { 4605, 3}, + 0xFA6 = { 4608, 1}, + 0xFA7 = { 4609, 1}, + 0xFA8 = { 4610, 10}, + 0xFA9 = { 4620, 10}, + 0xFAA = { 4630, 6}, + 0xFAB = { 4636, 1}, + 0xFAC = { 4637, 6}, + 0xFAD = { 4643, 6}, + 0xFAE = { 4649, 6}, + 0xFB0 = { 4655, 3}, + 0xFB5 = { 4658, 1}, + 0xFB8 = { 4659, 1}, + 0xFB9 = { 4660, 1}, + 0xFBA = { 4661, 1}, + 0xFBB = { 4662, 1}, + 0xFBC = { 4663, 1}, + 0xFBE = { 4664, 1}, + 0xFC0 = { 4665, 1}, + 0xFC1 = { 4666, 1}, + 0xFC2 = { 4667, 3}, + 0xFC3 = { 4670, 3}, + 0xFC4 = { 4673, 1}, + 0xFC5 = { 4674, 1}, + 0xFC6 = { 4675, 2}, + 0xFC7 = { 4677, 2}, + 0xFC8 = { 4679, 7}, + 0xFC9 = { 4686, 11}, + 0xFCA = { 4697, 3}, + 0xFCB = { 4700, 3}, + 0xFCC = { 4703, 7}, + 0xFCD = { 4710, 7}, + 0xFCE = { 4717, 2}, + 0xFCF = { 4719, 2}, + 0xFD2 = { 4721, 1}, + 0xFD3 = { 4722, 1}, + 0xFD9 = { 4723, 4}, + 0xFDA = { 4727, 1}, + 0xFDB = { 4728, 1}, + 0xFE0 = { 4729, 28}, + 0xFE1 = { 4757, 26}, + 0xFE2 = { 4783, 26}, + 0xFE3 = { 4809, 32}, + 0xFE4 = { 4841, 29}, + 0xFE5 = { 4870, 27}, + 0xFE6 = { 4897, 27}, + 0xFE7 = { 4924, 33}, + 0xFE8 = { 4957, 32}, + 0xFE9 = { 4989, 17}, + 0xFEA = { 5006, 17}, + 0xFEB = { 5023, 29}, + 0xFEC = { 5052, 31}, + 0xFED = { 5083, 18}, + 0xFEE = { 5101, 26}, + 0xFEF = { 5127, 32}, + 0xFF0 = { 5159, 19}, + 0xFF1 = { 5178, 18}, + 0xFF2 = { 5196, 17}, + 0xFF3 = { 5213, 17}, + 0xFF4 = { 5230, 19}, + 0xFF5 = { 5249, 18}, + 0xFF6 = { 5267, 17}, + 0xFF7 = { 5284, 17}, + 0xFF8 = { 5301, 4}, + 0xFF9 = { 5305, 4}, + 0xFFA = { 5309, 4}, + 0xFFB = { 5313, 17}, + 0xFFC = { 5330, 4}, + 0xFFD = { 5334, 4}, + 0xFFE = { 5338, 4}, + 0xFFF = { 5342, 17}, } diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index e6885c0dd..1fed899bc 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -ENCODE_FORMS := [1656]lib.Encoding{ +ENCODE_FORMS := [1649]lib.Encoding{ // .AND { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -1126,10 +1126,12 @@ ENCODE_FORMS := [1656]lib.Encoding{ { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.VN_D,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, { .VMOV, {.QPR_ELEM,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE000B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.GPR,.QPR_ELEM,.NONE,.NONE}, {.RT_T32,.VD_Q,.NONE,.NONE}, 0xEE100B10, 0xFF900F1F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, + { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, // .VMRS { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VMSR @@ -1780,47 +1782,61 @@ ENCODE_FORMS := [1656]lib.Encoding{ // .VSWP { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - // .VMOV_LANE - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, - { .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, // .VLD1 { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_ALL,.RN_A32,.NONE,.NONE}, 0xF4A00C0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8,.RN_A32,.NONE,.NONE}, 0xF4A0000F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16,.RN_A32,.NONE,.NONE}, 0xF4A0040F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32,.RN_A32,.NONE,.NONE}, 0xF4A0080F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD2 { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_2,.RN_A32,.NONE,.NONE}, 0xF4A0010F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_2,.RN_A32,.NONE,.NONE}, 0xF4A0050F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_2,.RN_A32,.NONE,.NONE}, 0xF4A0090F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD3 { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_3,.RN_A32,.NONE,.NONE}, 0xF4A0020F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_3,.RN_A32,.NONE,.NONE}, 0xF4A0060F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_3,.RN_A32,.NONE,.NONE}, 0xF4A00A0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VLD4 { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_4,.RN_A32,.NONE,.NONE}, 0xF4A0030F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF4A0070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4A00B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST1 { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {}, {.SZ32,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8,.RN_A32,.NONE,.NONE}, 0xF480000F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16,.RN_A32,.NONE,.NONE}, 0xF480040F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32,.RN_A32,.NONE,.NONE}, 0xF480080F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST2 { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_2,.RN_A32,.NONE,.NONE}, 0xF480010F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_2,.RN_A32,.NONE,.NONE}, 0xF480050F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_2,.RN_A32,.NONE,.NONE}, 0xF480090F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST3 { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_3,.RN_A32,.NONE,.NONE}, 0xF480020F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_3,.RN_A32,.NONE,.NONE}, 0xF480060F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_3,.RN_A32,.NONE,.NONE}, 0xF4800A0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .VST4 { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_8_4,.RN_A32,.NONE,.NONE}, 0xF480030F, 0xFFB00F1F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_16_4,.RN_A32,.NONE,.NONE}, 0xF480070F, 0xFFB00F3F, .NEON, .A32, {}, {.SZ16,.NONE} }, + { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_LANE_D_32_4,.RN_A32,.NONE,.NONE}, 0xF4800B0F, 0xFFB00F7F, .NEON, .A32, {}, {.SZ32,.NONE} }, // .AESE { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {}, {.NONE,.NONE} }, // .AESD @@ -1909,38 +1925,6 @@ ENCODE_FORMS := [1656]lib.Encoding{ { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, // .VLD4R { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - // .VLD1_LANE - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VLD2_LANE - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VLD3_LANE - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VLD4_LANE - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VST1_LANE - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VST2_LANE - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VST3_LANE - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, - // .VST4_LANE - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {}, {.SZ16,.NONE} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {}, {.SZ32,.NONE} }, // .IT { .IT, {.COND,.IMM4,.NONE,.NONE}, {.NONE,.IT_MASK,.NONE,.NONE}, 0x0000BF00, 0x0000FF00, .V6T2, .T32, {}, {.NONE,.NONE} }, // .TT @@ -2545,315 +2529,306 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .VCVTP = { 798, 2}, .VCVTM = { 800, 2}, .VCVTR = { 802, 4}, - .VMOV = { 806, 31}, - .VMRS = { 837, 1}, - .VMSR = { 838, 1}, - .VLDR = { 839, 2}, - .VSTR = { 841, 2}, - .VLDM = { 843, 2}, - .VSTM = { 845, 2}, - .VPUSH = { 847, 2}, - .VPOP = { 849, 2}, - .VSEL = { 851, 2}, - .VMAXNM = { 853, 2}, - .VMINNM = { 855, 2}, - .VRINTA = { 857, 3}, - .VRINTN = { 860, 3}, - .VRINTP = { 863, 3}, - .VRINTM = { 866, 3}, - .VRINTR = { 869, 2}, - .VRINTZ = { 871, 3}, - .VRINTX = { 874, 3}, - .VADDL = { 877, 6}, - .VADDW = { 883, 6}, - .VSUBL = { 889, 6}, - .VSUBW = { 895, 6}, - .VHADD = { 901, 9}, - .VHSUB = { 910, 9}, - .VRHADD = { 919, 3}, - .VQADD = { 922, 11}, - .VQSUB = { 933, 11}, - .VMULL = { 944, 11}, - .VMLAL = { 955, 10}, - .VMLSL = { 965, 10}, - .VQDMULL = { 975, 4}, - .VQDMLAL = { 979, 4}, - .VQDMLSL = { 983, 4}, - .VQDMULH = { 987, 8}, - .VQRDMULH = { 995, 8}, - .VQRDMLAH = { 1003, 8}, - .VQRDMLSH = { 1011, 8}, - .VABA = { 1019, 8}, - .VABAL = { 1027, 6}, - .VABD = { 1033, 10}, - .VABDL = { 1043, 6}, - .VAND = { 1049, 3}, - .VBIC = { 1052, 3}, - .VORR = { 1055, 3}, - .VORN = { 1058, 3}, - .VEOR = { 1061, 3}, - .VBSL = { 1064, 2}, - .VBIT = { 1066, 2}, - .VBIF = { 1068, 2}, - .VMVN = { 1070, 13}, - .VMOVN = { 1083, 3}, - .VQMOVN = { 1086, 6}, - .VQMOVUN = { 1092, 3}, - .VMOVL = { 1095, 6}, - .VTST = { 1101, 6}, - .VCEQ = { 1107, 14}, - .VCGE = { 1121, 16}, - .VCGT = { 1137, 16}, - .VCLE = { 1153, 18}, - .VCLT = { 1171, 18}, - .VACGE = { 1189, 2}, - .VACGT = { 1191, 2}, - .VACLE = { 1193, 2}, - .VACLT = { 1195, 2}, - .VMAX = { 1197, 13}, - .VMIN = { 1210, 13}, - .VPMAX = { 1223, 5}, - .VPMIN = { 1228, 5}, - .VPADD = { 1233, 5}, - .VPADDL = { 1238, 6}, - .VPADAL = { 1244, 4}, - .VRECPE = { 1248, 4}, - .VRECPS = { 1252, 2}, - .VRSQRTE = { 1254, 4}, - .VRSQRTS = { 1258, 2}, - .VSHL = { 1260, 9}, - .VSHR = { 1269, 3}, - .VSRA = { 1272, 3}, - .VRSHL = { 1275, 5}, - .VRSHR = { 1280, 3}, - .VRSRA = { 1283, 2}, - .VSLI = { 1285, 2}, - .VSRI = { 1287, 2}, - .VQSHL = { 1289, 7}, - .VQSHRN = { 1296, 1}, - .VQSHRUN = { 1297, 1}, - .VQRSHL = { 1298, 16}, - .VQRSHRN = { 1314, 1}, - .VQRSHRUN = { 1315, 1}, - .VSHRN = { 1316, 1}, - .VRSHRN = { 1317, 1}, - .VSHLL = { 1318, 4}, - .VCLS = { 1322, 6}, - .VCLZ = { 1328, 6}, - .VCNT = { 1334, 2}, - .VREV16 = { 1336, 2}, - .VREV32 = { 1338, 4}, - .VREV64 = { 1342, 6}, - .VEXT = { 1348, 2}, - .VTBL = { 1350, 4}, - .VTBX = { 1354, 4}, - .VTRN = { 1358, 6}, - .VUZP = { 1364, 5}, - .VZIP = { 1369, 5}, - .VDUP = { 1374, 5}, - .VSWP = { 1379, 2}, - .VMOV_LANE = { 1381, 3}, - .VLD1 = { 1384, 8}, - .VLD2 = { 1392, 3}, - .VLD3 = { 1395, 2}, - .VLD4 = { 1397, 2}, - .VST1 = { 1399, 7}, - .VST2 = { 1406, 3}, - .VST3 = { 1409, 2}, - .VST4 = { 1411, 2}, - .AESE = { 1413, 1}, - .AESD = { 1414, 1}, - .AESMC = { 1415, 1}, - .AESIMC = { 1416, 1}, - .SHA1H = { 1417, 1}, - .SHA1SU0 = { 1418, 1}, - .SHA1SU1 = { 1419, 1}, - .SHA1C = { 1420, 1}, - .SHA1M = { 1421, 1}, - .SHA1P = { 1422, 1}, - .SHA256H = { 1423, 1}, - .SHA256H2 = { 1424, 1}, - .SHA256SU0 = { 1425, 1}, - .SHA256SU1 = { 1426, 1}, - .VJCVT = { 1427, 1}, - .VSDOT = { 1428, 4}, - .VUDOT = { 1432, 4}, - .VDOT = { 1436, 2}, - .VMMLA = { 1438, 1}, - .VFMAL = { 1439, 2}, - .VFMSL = { 1441, 2}, - .VCMLA = { 1443, 5}, - .VCADD = { 1448, 2}, - .VSMMLA = { 1450, 1}, - .VUMMLA = { 1451, 1}, - .VUSMMLA = { 1452, 1}, - .VSUDOT = { 1453, 2}, - .VUSDOT = { 1455, 4}, - .VQABS = { 1459, 1}, - .VQNEG = { 1460, 1}, - .VMOVX = { 1461, 1}, - .VINS = { 1462, 1}, - .VLD2R = { 1463, 1}, - .VLD3R = { 1464, 1}, - .VLD4R = { 1465, 1}, - .VLD1_LANE = { 1466, 3}, - .VLD2_LANE = { 1469, 3}, - .VLD3_LANE = { 1472, 3}, - .VLD4_LANE = { 1475, 3}, - .VST1_LANE = { 1478, 3}, - .VST2_LANE = { 1481, 3}, - .VST3_LANE = { 1484, 3}, - .VST4_LANE = { 1487, 3}, - .IT = { 1490, 1}, - .TT = { 1491, 1}, - .TTT = { 1492, 1}, - .TTA = { 1493, 1}, - .TTAT = { 1494, 1}, - .SG = { 1495, 1}, - .BXNS = { 1496, 1}, - .BLXNS = { 1497, 1}, - .PAC = { 1498, 1}, - .PACBTI = { 1499, 1}, - .AUT = { 1500, 1}, - .AUTG = { 1501, 1}, - .BTI = { 1502, 1}, - .WLS = { 1503, 1}, - .WLSTP = { 1504, 1}, - .DLS = { 1505, 1}, - .DLSTP = { 1506, 1}, - .LE = { 1507, 1}, - .LETP = { 1508, 1}, - .LCTP = { 1509, 1}, - .BF = { 1510, 1}, - .BFX = { 1511, 1}, - .BFL = { 1512, 1}, - .BFLX = { 1513, 1}, - .BFCSEL = { 1514, 1}, - .CX1 = { 1515, 1}, - .CX1A = { 1516, 1}, - .CX1D = { 1517, 1}, - .CX1DA = { 1518, 1}, - .CX2 = { 1519, 1}, - .CX2A = { 1520, 1}, - .CX2D = { 1521, 1}, - .CX2DA = { 1522, 1}, - .CX3 = { 1523, 1}, - .CX3A = { 1524, 1}, - .CX3D = { 1525, 1}, - .CX3DA = { 1526, 1}, - .VCX1 = { 1527, 2}, - .VCX1A = { 1529, 2}, - .VCX2 = { 1531, 2}, - .VCX2A = { 1533, 2}, - .VCX3 = { 1535, 2}, - .VCX3A = { 1537, 2}, - .VPT = { 1539, 1}, - .VPST = { 1540, 1}, - .VPSEL = { 1541, 1}, - .VPNOT = { 1542, 1}, - .VCTP = { 1543, 1}, - .VADDV = { 1544, 1}, - .VADDVA = { 1545, 1}, - .VADDLV = { 1546, 1}, - .VADDLVA = { 1547, 1}, - .VMAXV = { 1548, 1}, - .VMAXAV = { 1549, 1}, - .VMINV = { 1550, 1}, - .VMINAV = { 1551, 1}, - .VMAXNMV = { 1552, 1}, - .VMAXNMAV = { 1553, 1}, - .VMINNMV = { 1554, 1}, - .VMINNMAV = { 1555, 1}, - .VABAV = { 1556, 1}, - .VMLADAV = { 1557, 1}, - .VMLADAVA = { 1558, 1}, - .VMLADAVX = { 1559, 1}, - .VMLADAVAX = { 1560, 1}, - .VMLALDAV = { 1561, 1}, - .VMLALDAVA = { 1562, 1}, - .VMLALDAVX = { 1563, 1}, - .VMLALDAVAX = { 1564, 1}, - .VMLSDAV = { 1565, 1}, - .VMLSDAVA = { 1566, 1}, - .VMLSDAVX = { 1567, 1}, - .VMLSDAVAX = { 1568, 1}, - .VMLSLDAV = { 1569, 1}, - .VMLSLDAVA = { 1570, 1}, - .VMLSLDAVX = { 1571, 1}, - .VMLSLDAVAX = { 1572, 1}, - .VRMLALDAVH = { 1573, 1}, - .VRMLALDAVHA = { 1574, 1}, - .VRMLALDAVHX = { 1575, 1}, - .VRMLALDAVHAX = { 1576, 1}, - .VRMLSLDAVH = { 1577, 1}, - .VRMLSLDAVHA = { 1578, 1}, - .VRMLSLDAVHX = { 1579, 1}, - .VRMLSLDAVHAX = { 1580, 1}, - .VMLAV = { 1581, 1}, - .VMLAVA = { 1582, 1}, - .VMLSV = { 1583, 1}, - .VMLSVA = { 1584, 1}, - .VCMUL = { 1585, 1}, - .VHCADD = { 1586, 2}, - .VBRSR = { 1588, 1}, - .VSHLC = { 1589, 1}, - .VDDUP = { 1590, 1}, - .VIDUP = { 1591, 1}, - .VDWDUP = { 1592, 1}, - .VIWDUP = { 1593, 1}, - .VMOVNB = { 1594, 1}, - .VMOVNT = { 1595, 1}, - .VQMOVNB = { 1596, 1}, - .VQMOVNT = { 1597, 1}, - .VQMOVUNB = { 1598, 1}, - .VQMOVUNT = { 1599, 1}, - .VSHLLB = { 1600, 1}, - .VSHLLT = { 1601, 1}, - .VMULLB = { 1602, 1}, - .VMULLT = { 1603, 1}, - .VMLALB = { 1604, 1}, - .VMLALT = { 1605, 1}, - .VMLSLB = { 1606, 1}, - .VMLSLT = { 1607, 1}, - .VSHRNB = { 1608, 1}, - .VSHRNT = { 1609, 1}, - .VRSHRNB = { 1610, 1}, - .VRSHRNT = { 1611, 1}, - .VQSHRNB = { 1612, 1}, - .VQSHRNT = { 1613, 1}, - .VQRSHRNB = { 1614, 1}, - .VQRSHRNT = { 1615, 1}, - .VQSHRUNB = { 1616, 1}, - .VQSHRUNT = { 1617, 1}, - .VQRSHRUNB = { 1618, 1}, - .VQRSHRUNT = { 1619, 1}, - .VQDMLADH = { 1620, 1}, - .VQDMLADHX = { 1621, 1}, - .VQDMLSDH = { 1622, 1}, - .VQDMLSDHX = { 1623, 1}, - .VQRDMLADH = { 1624, 1}, - .VQRDMLADHX = { 1625, 1}, - .VQRDMLSDH = { 1626, 1}, - .VQRDMLSDHX = { 1627, 1}, - .VLDRB = { 1628, 2}, - .VLDRH = { 1630, 2}, - .VLDRW = { 1632, 2}, - .VLDRD = { 1634, 2}, - .VSTRB = { 1636, 2}, - .VSTRH = { 1638, 2}, - .VSTRW = { 1640, 2}, - .VSTRD = { 1642, 2}, - .VLD20 = { 1644, 1}, - .VLD21 = { 1645, 1}, - .VLD40 = { 1646, 1}, - .VLD41 = { 1647, 1}, - .VLD42 = { 1648, 1}, - .VLD43 = { 1649, 1}, - .VST20 = { 1650, 1}, - .VST21 = { 1651, 1}, - .VST40 = { 1652, 1}, - .VST41 = { 1653, 1}, - .VST42 = { 1654, 1}, - .VST43 = { 1655, 1}, - ._COUNT = { 1656, 0}, + .VMOV = { 806, 33}, + .VMRS = { 839, 1}, + .VMSR = { 840, 1}, + .VLDR = { 841, 2}, + .VSTR = { 843, 2}, + .VLDM = { 845, 2}, + .VSTM = { 847, 2}, + .VPUSH = { 849, 2}, + .VPOP = { 851, 2}, + .VSEL = { 853, 2}, + .VMAXNM = { 855, 2}, + .VMINNM = { 857, 2}, + .VRINTA = { 859, 3}, + .VRINTN = { 862, 3}, + .VRINTP = { 865, 3}, + .VRINTM = { 868, 3}, + .VRINTR = { 871, 2}, + .VRINTZ = { 873, 3}, + .VRINTX = { 876, 3}, + .VADDL = { 879, 6}, + .VADDW = { 885, 6}, + .VSUBL = { 891, 6}, + .VSUBW = { 897, 6}, + .VHADD = { 903, 9}, + .VHSUB = { 912, 9}, + .VRHADD = { 921, 3}, + .VQADD = { 924, 11}, + .VQSUB = { 935, 11}, + .VMULL = { 946, 11}, + .VMLAL = { 957, 10}, + .VMLSL = { 967, 10}, + .VQDMULL = { 977, 4}, + .VQDMLAL = { 981, 4}, + .VQDMLSL = { 985, 4}, + .VQDMULH = { 989, 8}, + .VQRDMULH = { 997, 8}, + .VQRDMLAH = { 1005, 8}, + .VQRDMLSH = { 1013, 8}, + .VABA = { 1021, 8}, + .VABAL = { 1029, 6}, + .VABD = { 1035, 10}, + .VABDL = { 1045, 6}, + .VAND = { 1051, 3}, + .VBIC = { 1054, 3}, + .VORR = { 1057, 3}, + .VORN = { 1060, 3}, + .VEOR = { 1063, 3}, + .VBSL = { 1066, 2}, + .VBIT = { 1068, 2}, + .VBIF = { 1070, 2}, + .VMVN = { 1072, 13}, + .VMOVN = { 1085, 3}, + .VQMOVN = { 1088, 6}, + .VQMOVUN = { 1094, 3}, + .VMOVL = { 1097, 6}, + .VTST = { 1103, 6}, + .VCEQ = { 1109, 14}, + .VCGE = { 1123, 16}, + .VCGT = { 1139, 16}, + .VCLE = { 1155, 18}, + .VCLT = { 1173, 18}, + .VACGE = { 1191, 2}, + .VACGT = { 1193, 2}, + .VACLE = { 1195, 2}, + .VACLT = { 1197, 2}, + .VMAX = { 1199, 13}, + .VMIN = { 1212, 13}, + .VPMAX = { 1225, 5}, + .VPMIN = { 1230, 5}, + .VPADD = { 1235, 5}, + .VPADDL = { 1240, 6}, + .VPADAL = { 1246, 4}, + .VRECPE = { 1250, 4}, + .VRECPS = { 1254, 2}, + .VRSQRTE = { 1256, 4}, + .VRSQRTS = { 1260, 2}, + .VSHL = { 1262, 9}, + .VSHR = { 1271, 3}, + .VSRA = { 1274, 3}, + .VRSHL = { 1277, 5}, + .VRSHR = { 1282, 3}, + .VRSRA = { 1285, 2}, + .VSLI = { 1287, 2}, + .VSRI = { 1289, 2}, + .VQSHL = { 1291, 7}, + .VQSHRN = { 1298, 1}, + .VQSHRUN = { 1299, 1}, + .VQRSHL = { 1300, 16}, + .VQRSHRN = { 1316, 1}, + .VQRSHRUN = { 1317, 1}, + .VSHRN = { 1318, 1}, + .VRSHRN = { 1319, 1}, + .VSHLL = { 1320, 4}, + .VCLS = { 1324, 6}, + .VCLZ = { 1330, 6}, + .VCNT = { 1336, 2}, + .VREV16 = { 1338, 2}, + .VREV32 = { 1340, 4}, + .VREV64 = { 1344, 6}, + .VEXT = { 1350, 2}, + .VTBL = { 1352, 4}, + .VTBX = { 1356, 4}, + .VTRN = { 1360, 6}, + .VUZP = { 1366, 5}, + .VZIP = { 1371, 5}, + .VDUP = { 1376, 5}, + .VSWP = { 1381, 2}, + .VLD1 = { 1383, 8}, + .VLD2 = { 1391, 6}, + .VLD3 = { 1397, 5}, + .VLD4 = { 1402, 5}, + .VST1 = { 1407, 7}, + .VST2 = { 1414, 6}, + .VST3 = { 1420, 5}, + .VST4 = { 1425, 5}, + .AESE = { 1430, 1}, + .AESD = { 1431, 1}, + .AESMC = { 1432, 1}, + .AESIMC = { 1433, 1}, + .SHA1H = { 1434, 1}, + .SHA1SU0 = { 1435, 1}, + .SHA1SU1 = { 1436, 1}, + .SHA1C = { 1437, 1}, + .SHA1M = { 1438, 1}, + .SHA1P = { 1439, 1}, + .SHA256H = { 1440, 1}, + .SHA256H2 = { 1441, 1}, + .SHA256SU0 = { 1442, 1}, + .SHA256SU1 = { 1443, 1}, + .VJCVT = { 1444, 1}, + .VSDOT = { 1445, 4}, + .VUDOT = { 1449, 4}, + .VDOT = { 1453, 2}, + .VMMLA = { 1455, 1}, + .VFMAL = { 1456, 2}, + .VFMSL = { 1458, 2}, + .VCMLA = { 1460, 5}, + .VCADD = { 1465, 2}, + .VSMMLA = { 1467, 1}, + .VUMMLA = { 1468, 1}, + .VUSMMLA = { 1469, 1}, + .VSUDOT = { 1470, 2}, + .VUSDOT = { 1472, 4}, + .VQABS = { 1476, 1}, + .VQNEG = { 1477, 1}, + .VMOVX = { 1478, 1}, + .VINS = { 1479, 1}, + .VLD2R = { 1480, 1}, + .VLD3R = { 1481, 1}, + .VLD4R = { 1482, 1}, + .IT = { 1483, 1}, + .TT = { 1484, 1}, + .TTT = { 1485, 1}, + .TTA = { 1486, 1}, + .TTAT = { 1487, 1}, + .SG = { 1488, 1}, + .BXNS = { 1489, 1}, + .BLXNS = { 1490, 1}, + .PAC = { 1491, 1}, + .PACBTI = { 1492, 1}, + .AUT = { 1493, 1}, + .AUTG = { 1494, 1}, + .BTI = { 1495, 1}, + .WLS = { 1496, 1}, + .WLSTP = { 1497, 1}, + .DLS = { 1498, 1}, + .DLSTP = { 1499, 1}, + .LE = { 1500, 1}, + .LETP = { 1501, 1}, + .LCTP = { 1502, 1}, + .BF = { 1503, 1}, + .BFX = { 1504, 1}, + .BFL = { 1505, 1}, + .BFLX = { 1506, 1}, + .BFCSEL = { 1507, 1}, + .CX1 = { 1508, 1}, + .CX1A = { 1509, 1}, + .CX1D = { 1510, 1}, + .CX1DA = { 1511, 1}, + .CX2 = { 1512, 1}, + .CX2A = { 1513, 1}, + .CX2D = { 1514, 1}, + .CX2DA = { 1515, 1}, + .CX3 = { 1516, 1}, + .CX3A = { 1517, 1}, + .CX3D = { 1518, 1}, + .CX3DA = { 1519, 1}, + .VCX1 = { 1520, 2}, + .VCX1A = { 1522, 2}, + .VCX2 = { 1524, 2}, + .VCX2A = { 1526, 2}, + .VCX3 = { 1528, 2}, + .VCX3A = { 1530, 2}, + .VPT = { 1532, 1}, + .VPST = { 1533, 1}, + .VPSEL = { 1534, 1}, + .VPNOT = { 1535, 1}, + .VCTP = { 1536, 1}, + .VADDV = { 1537, 1}, + .VADDVA = { 1538, 1}, + .VADDLV = { 1539, 1}, + .VADDLVA = { 1540, 1}, + .VMAXV = { 1541, 1}, + .VMAXAV = { 1542, 1}, + .VMINV = { 1543, 1}, + .VMINAV = { 1544, 1}, + .VMAXNMV = { 1545, 1}, + .VMAXNMAV = { 1546, 1}, + .VMINNMV = { 1547, 1}, + .VMINNMAV = { 1548, 1}, + .VABAV = { 1549, 1}, + .VMLADAV = { 1550, 1}, + .VMLADAVA = { 1551, 1}, + .VMLADAVX = { 1552, 1}, + .VMLADAVAX = { 1553, 1}, + .VMLALDAV = { 1554, 1}, + .VMLALDAVA = { 1555, 1}, + .VMLALDAVX = { 1556, 1}, + .VMLALDAVAX = { 1557, 1}, + .VMLSDAV = { 1558, 1}, + .VMLSDAVA = { 1559, 1}, + .VMLSDAVX = { 1560, 1}, + .VMLSDAVAX = { 1561, 1}, + .VMLSLDAV = { 1562, 1}, + .VMLSLDAVA = { 1563, 1}, + .VMLSLDAVX = { 1564, 1}, + .VMLSLDAVAX = { 1565, 1}, + .VRMLALDAVH = { 1566, 1}, + .VRMLALDAVHA = { 1567, 1}, + .VRMLALDAVHX = { 1568, 1}, + .VRMLALDAVHAX = { 1569, 1}, + .VRMLSLDAVH = { 1570, 1}, + .VRMLSLDAVHA = { 1571, 1}, + .VRMLSLDAVHX = { 1572, 1}, + .VRMLSLDAVHAX = { 1573, 1}, + .VMLAV = { 1574, 1}, + .VMLAVA = { 1575, 1}, + .VMLSV = { 1576, 1}, + .VMLSVA = { 1577, 1}, + .VCMUL = { 1578, 1}, + .VHCADD = { 1579, 2}, + .VBRSR = { 1581, 1}, + .VSHLC = { 1582, 1}, + .VDDUP = { 1583, 1}, + .VIDUP = { 1584, 1}, + .VDWDUP = { 1585, 1}, + .VIWDUP = { 1586, 1}, + .VMOVNB = { 1587, 1}, + .VMOVNT = { 1588, 1}, + .VQMOVNB = { 1589, 1}, + .VQMOVNT = { 1590, 1}, + .VQMOVUNB = { 1591, 1}, + .VQMOVUNT = { 1592, 1}, + .VSHLLB = { 1593, 1}, + .VSHLLT = { 1594, 1}, + .VMULLB = { 1595, 1}, + .VMULLT = { 1596, 1}, + .VMLALB = { 1597, 1}, + .VMLALT = { 1598, 1}, + .VMLSLB = { 1599, 1}, + .VMLSLT = { 1600, 1}, + .VSHRNB = { 1601, 1}, + .VSHRNT = { 1602, 1}, + .VRSHRNB = { 1603, 1}, + .VRSHRNT = { 1604, 1}, + .VQSHRNB = { 1605, 1}, + .VQSHRNT = { 1606, 1}, + .VQRSHRNB = { 1607, 1}, + .VQRSHRNT = { 1608, 1}, + .VQSHRUNB = { 1609, 1}, + .VQSHRUNT = { 1610, 1}, + .VQRSHRUNB = { 1611, 1}, + .VQRSHRUNT = { 1612, 1}, + .VQDMLADH = { 1613, 1}, + .VQDMLADHX = { 1614, 1}, + .VQDMLSDH = { 1615, 1}, + .VQDMLSDHX = { 1616, 1}, + .VQRDMLADH = { 1617, 1}, + .VQRDMLADHX = { 1618, 1}, + .VQRDMLSDH = { 1619, 1}, + .VQRDMLSDHX = { 1620, 1}, + .VLDRB = { 1621, 2}, + .VLDRH = { 1623, 2}, + .VLDRW = { 1625, 2}, + .VLDRD = { 1627, 2}, + .VSTRB = { 1629, 2}, + .VSTRH = { 1631, 2}, + .VSTRW = { 1633, 2}, + .VSTRD = { 1635, 2}, + .VLD20 = { 1637, 1}, + .VLD21 = { 1638, 1}, + .VLD40 = { 1639, 1}, + .VLD41 = { 1640, 1}, + .VLD42 = { 1641, 1}, + .VLD43 = { 1642, 1}, + .VST20 = { 1643, 1}, + .VST21 = { 1644, 1}, + .VST40 = { 1645, 1}, + .VST41 = { 1646, 1}, + .VST42 = { 1647, 1}, + .VST43 = { 1648, 1}, + ._COUNT = { 1649, 0}, } diff --git a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin b/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin index 4745e8f6ad5321d098a1804cf41d4dba0e2d8b9c..1b4ef0d76fdf0f4fe94248d6e8eae01468d2e2a9 100644 GIT binary patch literal 10718 zcmZQzU}RuoU}j)oU}0cnU}a!pU}Ios;9%fnU}NB7U}xZF;9%fk;AP-r;AaqE5M&Ty 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j7KXDTEDRS#SQxH~2r@hqVPSYB!ou)QgoWXgh#&(1ZsV*4 diff --git a/core/rexcode/isa/arm32/tests/smoke.odin b/core/rexcode/isa/arm32/tests/smoke.odin index b7b38dd1c..0c5aa80aa 100644 --- a/core/rexcode/isa/arm32/tests/smoke.odin +++ b/core/rexcode/isa/arm32/tests/smoke.odin @@ -188,11 +188,11 @@ run_smoke :: proc() { check("VZIP.I8 D", .VZIP, 0, 0xF3B20180, 0xFFB30FD0) check("VTBL", .VTBL, 0, 0xF3B00800, 0xFFB00F70) check("VRECPE F32 D", .VRECPE, 2, 0xF3BB0500, 0xFFBF0FD0) - check("VLD1 1-reg", .VLD1, 0, 0xF4200700, 0xFFF00F00) - check("VST1 1-reg", .VST1, 0, 0xF4000700, 0xFFF00F00) - check("VLD2 2-reg", .VLD2, 0, 0xF4200800, 0xFFF00F00) - check("VLD3 3-reg", .VLD3, 0, 0xF4200400, 0xFFF00F00) - check("VLD4 4-reg", .VLD4, 0, 0xF4200000, 0xFFF00F00) + check("VLD1 1-reg", .VLD1, 0, 0xF420070F, 0xFFF00F0F) + check("VST1 1-reg", .VST1, 0, 0xF400070F, 0xFFF00F0F) + check("VLD2 2-reg", .VLD2, 0, 0xF420080F, 0xFFF00F0F) + check("VLD3 3-reg", .VLD3, 0, 0xF420040F, 0xFFF00F0F) + check("VLD4 4-reg", .VLD4, 0, 0xF420000F, 0xFFF00F0F) check("VMULL.S8", .VMULL, 0, 0xF2800C00, 0xFFB00F50) // ---- Thumb-2 ---- @@ -550,15 +550,15 @@ run_smoke :: proc() { check("VLD4R", .VLD4R, 0, 0xF4A00F0F, 0xFFB00F0F) // ---- NEON single-element lane loads/stores ---- - check("VLD1_LANE .8", .VLD1_LANE, 0, 0xF4A00000, 0xFFB00C00) - check("VLD1_LANE .16", .VLD1_LANE, 1, 0xF4A00400, 0xFFB00C00) - check("VLD1_LANE .32", .VLD1_LANE, 2, 0xF4A00800, 0xFFB00C00) - check("VLD2_LANE .8", .VLD2_LANE, 0, 0xF4A00100, 0xFFB00D00) - check("VLD3_LANE .16", .VLD3_LANE, 1, 0xF4A00600, 0xFFB00D00) - check("VLD4_LANE .32", .VLD4_LANE, 2, 0xF4A00B00, 0xFFB00D00) - check("VST1_LANE .8", .VST1_LANE, 0, 0xF4800000, 0xFFB00C00) - check("VST3_LANE .32", .VST3_LANE, 2, 0xF4800A00, 0xFFB00D00) - check("VST4_LANE .16", .VST4_LANE, 1, 0xF4800700, 0xFFB00D00) + check("VLD1 lane .8", .VLD1, 5, 0xF4A0000F, 0xFFB00F1F) + check("VLD1 lane .16", .VLD1, 6, 0xF4A0040F, 0xFFB00F3F) + check("VLD1 lane .32", .VLD1, 7, 0xF4A0080F, 0xFFB00F7F) + check("VLD2 lane .8", .VLD2, 3, 0xF4A0010F, 0xFFB00F1F) + check("VLD3 lane .16", .VLD3, 3, 0xF4A0060F, 0xFFB00F3F) + check("VLD4 lane .32", .VLD4, 4, 0xF4A00B0F, 0xFFB00F7F) + check("VST1 lane .8", .VST1, 4, 0xF480000F, 0xFFB00F1F) + check("VST3 lane .32", .VST3, 4, 0xF4800A0F, 0xFFB00F7F) + check("VST4 lane .16", .VST4, 3, 0xF480070F, 0xFFB00F3F) // ---- MVE rounding-to-int (VPADD/VPMAX/VPMIN MVE forms removed - don't exist) ---- check("VRINTA MVE", .VRINTA, 2, 0xFFBA0540, 0xFFBB0FD1)