From 307aa2a9dd31405555e6f9e5ef068e7acc9bcba1 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Thu, 18 Jun 2026 03:11:41 -0400 Subject: [PATCH] rexcode/mips: MSA 3RF/3R/2R/2RF/VEC encode forms (specgen) New mips specgen (llvm-mc --triple=mips --mattr=+msa as the bits oracle, big-endian words, empirical masks): vector FP arithmetic/compare FADD/ FSUB/FMUL/FDIV/FMAX/FMIN/FCEQ/FCLE/FCLT/FCNE (.W/.D), dot product DOTP_S/U (.H/.W/.D), count/popcount NLOC/NLZC/PCNT (.B/.H/.W/.D), one-source FP FSQRT/FRSQRT/FRCP/FRINT/FTRUNC_S/U/FFINT_S/U (.W/.D), and bit-select BMNZ/BMZ/BSEL.V. 57 forms reusing the existing WD/WS/WT slots. Spot- checked byte-exact vs llvm-mc and decode-clean; 281 tests green. --- core/rexcode/mips/mnemonic_builders.odin | 228 +++++ .../rexcode/mips/tablegen/encoding_table.odin | 60 ++ .../tablegen/generated/decode_tables.odin | 163 ++-- .../tablegen/generated/encode_tables.odin | 796 ++++++++++-------- core/rexcode/mips/tablegen/specgen.lua | 113 +++ .../rexcode/mips/tables/mips.encode_forms.bin | Bin 15660 -> 16800 bytes core/rexcode/mips/tables/mips.encode_runs.bin | Bin 8224 -> 8224 bytes core/rexcode/mips/tables/mips.entries.bin | Bin 15660 -> 16800 bytes core/rexcode/mips/tables/mips.idx_primary.bin | Bin 256 -> 256 bytes .../rexcode/mips/tables/mips.idx_special3.bin | Bin 256 -> 256 bytes 10 files changed, 966 insertions(+), 394 deletions(-) create mode 100644 core/rexcode/mips/tablegen/specgen.lua diff --git a/core/rexcode/mips/mnemonic_builders.odin b/core/rexcode/mips/mnemonic_builders.odin index d542aeca6..6d4054f07 100644 --- a/core/rexcode/mips/mnemonic_builders.odin +++ b/core/rexcode/mips/mnemonic_builders.odin @@ -1166,6 +1166,18 @@ inst_msubv_w_w_w_w :: #force_inline proc "contextless" (dst: Register, sr emit_msubv_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_msubv_w_w_w_w(dst, src, src2)) } inst_msubv_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MSUBV_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_msubv_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_msubv_d_w_w_w(dst, src, src2)) } +inst_dotp_s_h_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DOTP_S_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_dotp_s_h_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dotp_s_h_w_w_w(dst, src, src2)) } +inst_dotp_s_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DOTP_S_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_dotp_s_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dotp_s_w_w_w_w(dst, src, src2)) } +inst_dotp_s_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DOTP_S_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_dotp_s_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dotp_s_d_w_w_w(dst, src, src2)) } +inst_dotp_u_h_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DOTP_U_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_dotp_u_h_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dotp_u_h_w_w_w(dst, src, src2)) } +inst_dotp_u_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DOTP_U_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_dotp_u_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dotp_u_w_w_w_w(dst, src, src2)) } +inst_dotp_u_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .DOTP_U_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_dotp_u_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_dotp_u_d_w_w_w(dst, src, src2)) } inst_and_v_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND_V, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_and_v_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_v_w_w_w(dst, src, src2)) } inst_or_v_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .OR_V, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } @@ -1174,6 +1186,12 @@ inst_nor_v_w_w_w :: #force_inline proc "contextless" (dst: Register, sr emit_nor_v_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_nor_v_w_w_w(dst, src, src2)) } inst_xor_v_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .XOR_V, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_xor_v_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_xor_v_w_w_w(dst, src, src2)) } +inst_bsel_v_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSEL_V, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_bsel_v_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsel_v_w_w_w(dst, src, src2)) } +inst_bmnz_v_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BMNZ_V, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_bmnz_v_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bmnz_v_w_w_w(dst, src, src2)) } +inst_bmz_v_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BMZ_V, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_bmz_v_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bmz_v_w_w_w(dst, src, src2)) } inst_ceq_b_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CEQ_B, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_ceq_b_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ceq_b_w_w_w(dst, src, src2)) } inst_ceq_h_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CEQ_H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } @@ -1270,6 +1288,78 @@ inst_sra_w_w_w_w :: #force_inline proc "contextless" (dst: Register, sr emit_sra_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sra_w_w_w_w(dst, src, src2)) } inst_sra_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SRA_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_sra_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sra_d_w_w_w(dst, src, src2)) } +inst_fadd_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fadd_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_w_w_w_w(dst, src, src2)) } +inst_fadd_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fadd_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_d_w_w_w(dst, src, src2)) } +inst_fsub_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fsub_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_w_w_w_w(dst, src, src2)) } +inst_fsub_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fsub_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_d_w_w_w(dst, src, src2)) } +inst_fmul_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fmul_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_w_w_w_w(dst, src, src2)) } +inst_fmul_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fmul_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_d_w_w_w(dst, src, src2)) } +inst_fdiv_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fdiv_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_w_w_w_w(dst, src, src2)) } +inst_fdiv_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fdiv_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_d_w_w_w(dst, src, src2)) } +inst_fsqrt_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT_W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_fsqrt_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_w_w_w(dst, src)) } +inst_fsqrt_d_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FSQRT_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_fsqrt_d_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_d_w_w(dst, src)) } +inst_frsqrt_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRT_W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_frsqrt_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrt_w_w_w(dst, src)) } +inst_frsqrt_d_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRSQRT_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_frsqrt_d_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frsqrt_d_w_w(dst, src)) } +inst_frcp_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRCP_W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_frcp_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frcp_w_w_w(dst, src)) } +inst_frcp_d_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRCP_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_frcp_d_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frcp_d_w_w(dst, src)) } +inst_frint_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINT_W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_frint_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frint_w_w_w(dst, src)) } +inst_frint_d_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FRINT_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_frint_d_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_frint_d_w_w(dst, src)) } +inst_fmax_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fmax_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_w_w_w_w(dst, src, src2)) } +inst_fmax_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMAX_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fmax_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_d_w_w_w(dst, src, src2)) } +inst_fmin_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fmin_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_w_w_w_w(dst, src, src2)) } +inst_fmin_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMIN_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fmin_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_d_w_w_w(dst, src, src2)) } +inst_fceq_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCEQ_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fceq_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fceq_w_w_w_w(dst, src, src2)) } +inst_fceq_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCEQ_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fceq_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fceq_d_w_w_w(dst, src, src2)) } +inst_fcne_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCNE_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fcne_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcne_w_w_w_w(dst, src, src2)) } +inst_fcne_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCNE_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fcne_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcne_d_w_w_w(dst, src, src2)) } +inst_fclt_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCLT_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fclt_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fclt_w_w_w_w(dst, src, src2)) } +inst_fclt_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCLT_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fclt_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fclt_d_w_w_w(dst, src, src2)) } +inst_fcle_w_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCLE_W, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fcle_w_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcle_w_w_w_w(dst, src, src2)) } +inst_fcle_d_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FCLE_D, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_fcle_d_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fcle_d_w_w_w(dst, src, src2)) } +inst_ffint_s_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FFINT_S_W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ffint_s_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ffint_s_w_w_w(dst, src)) } +inst_ffint_s_d_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FFINT_S_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ffint_s_d_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ffint_s_d_w_w(dst, src)) } +inst_ffint_u_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FFINT_U_W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ffint_u_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ffint_u_w_w_w(dst, src)) } +inst_ffint_u_d_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FFINT_U_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ffint_u_d_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ffint_u_d_w_w(dst, src)) } +inst_ftrunc_s_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FTRUNC_S_W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ftrunc_s_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ftrunc_s_w_w_w(dst, src)) } +inst_ftrunc_s_d_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FTRUNC_S_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ftrunc_s_d_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ftrunc_s_d_w_w(dst, src)) } +inst_ftrunc_u_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FTRUNC_U_W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ftrunc_u_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ftrunc_u_w_w_w(dst, src)) } +inst_ftrunc_u_d_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .FTRUNC_U_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ftrunc_u_d_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ftrunc_u_d_w_w(dst, src)) } inst_ld_b_w_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD_B, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(mem, 4), {}, {}}} } emit_ld_b_w_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld_b_w_m(dst, mem)) } inst_ld_h_w_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD_H, operand_count = 2, length = 4, ops = {op_reg(dst), op_mem(mem, 4), {}, {}}} } @@ -1294,6 +1384,30 @@ inst_ldi_w_w_i5 :: #force_inline proc "contextless" (dst: Register, im emit_ldi_w_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_ldi_w_w_i5(dst, imm)) } inst_ldi_d_w_i5 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LDI_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_imm(imm, 1), {}, {}}} } emit_ldi_d_w_i5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_ldi_d_w_i5(dst, imm)) } +inst_nloc_b_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NLOC_B, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_nloc_b_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_nloc_b_w_w(dst, src)) } +inst_nloc_h_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NLOC_H, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_nloc_h_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_nloc_h_w_w(dst, src)) } +inst_nloc_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NLOC_W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_nloc_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_nloc_w_w_w(dst, src)) } +inst_nloc_d_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NLOC_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_nloc_d_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_nloc_d_w_w(dst, src)) } +inst_nlzc_b_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NLZC_B, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_nlzc_b_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_nlzc_b_w_w(dst, src)) } +inst_nlzc_h_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NLZC_H, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_nlzc_h_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_nlzc_h_w_w(dst, src)) } +inst_nlzc_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NLZC_W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_nlzc_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_nlzc_w_w_w(dst, src)) } +inst_nlzc_d_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NLZC_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_nlzc_d_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_nlzc_d_w_w(dst, src)) } +inst_pcnt_b_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PCNT_B, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_pcnt_b_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pcnt_b_w_w(dst, src)) } +inst_pcnt_h_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PCNT_H, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_pcnt_h_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pcnt_h_w_w(dst, src)) } +inst_pcnt_w_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PCNT_W, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_pcnt_w_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pcnt_w_w_w(dst, src)) } +inst_pcnt_d_w_w :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .PCNT_D, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_pcnt_d_w_w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pcnt_d_w_w(dst, src)) } inst_vmov_s_vs_vs :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_S, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } emit_vmov_s_vs_vs :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmov_s_vs_vs(dst, src)) } inst_vmov_p_vp_vp :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_P, operand_count = 2, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } @@ -2737,6 +2851,18 @@ inst_msubv_w :: inst_msubv_w_w_w_w emit_msubv_w :: emit_msubv_w_w_w_w inst_msubv_d :: inst_msubv_d_w_w_w emit_msubv_d :: emit_msubv_d_w_w_w +inst_dotp_s_h :: inst_dotp_s_h_w_w_w +emit_dotp_s_h :: emit_dotp_s_h_w_w_w +inst_dotp_s_w :: inst_dotp_s_w_w_w_w +emit_dotp_s_w :: emit_dotp_s_w_w_w_w +inst_dotp_s_d :: inst_dotp_s_d_w_w_w +emit_dotp_s_d :: emit_dotp_s_d_w_w_w +inst_dotp_u_h :: inst_dotp_u_h_w_w_w +emit_dotp_u_h :: emit_dotp_u_h_w_w_w +inst_dotp_u_w :: inst_dotp_u_w_w_w_w +emit_dotp_u_w :: emit_dotp_u_w_w_w_w +inst_dotp_u_d :: inst_dotp_u_d_w_w_w +emit_dotp_u_d :: emit_dotp_u_d_w_w_w inst_and_v :: inst_and_v_w_w_w emit_and_v :: emit_and_v_w_w_w inst_or_v :: inst_or_v_w_w_w @@ -2745,6 +2871,12 @@ inst_nor_v :: inst_nor_v_w_w_w emit_nor_v :: emit_nor_v_w_w_w inst_xor_v :: inst_xor_v_w_w_w emit_xor_v :: emit_xor_v_w_w_w +inst_bsel_v :: inst_bsel_v_w_w_w +emit_bsel_v :: emit_bsel_v_w_w_w +inst_bmnz_v :: inst_bmnz_v_w_w_w +emit_bmnz_v :: emit_bmnz_v_w_w_w +inst_bmz_v :: inst_bmz_v_w_w_w +emit_bmz_v :: emit_bmz_v_w_w_w inst_ceq_b :: inst_ceq_b_w_w_w emit_ceq_b :: emit_ceq_b_w_w_w inst_ceq_h :: inst_ceq_h_w_w_w @@ -2841,6 +2973,78 @@ inst_sra_w :: inst_sra_w_w_w_w emit_sra_w :: emit_sra_w_w_w_w inst_sra_d :: inst_sra_d_w_w_w emit_sra_d :: emit_sra_d_w_w_w +inst_fadd_w :: inst_fadd_w_w_w_w +emit_fadd_w :: emit_fadd_w_w_w_w +inst_fadd_d :: inst_fadd_d_w_w_w +emit_fadd_d :: emit_fadd_d_w_w_w +inst_fsub_w :: inst_fsub_w_w_w_w +emit_fsub_w :: emit_fsub_w_w_w_w +inst_fsub_d :: inst_fsub_d_w_w_w +emit_fsub_d :: emit_fsub_d_w_w_w +inst_fmul_w :: inst_fmul_w_w_w_w +emit_fmul_w :: emit_fmul_w_w_w_w +inst_fmul_d :: inst_fmul_d_w_w_w +emit_fmul_d :: emit_fmul_d_w_w_w +inst_fdiv_w :: inst_fdiv_w_w_w_w +emit_fdiv_w :: emit_fdiv_w_w_w_w +inst_fdiv_d :: inst_fdiv_d_w_w_w +emit_fdiv_d :: emit_fdiv_d_w_w_w +inst_fsqrt_w :: inst_fsqrt_w_w_w +emit_fsqrt_w :: emit_fsqrt_w_w_w +inst_fsqrt_d :: inst_fsqrt_d_w_w +emit_fsqrt_d :: emit_fsqrt_d_w_w +inst_frsqrt_w :: inst_frsqrt_w_w_w +emit_frsqrt_w :: emit_frsqrt_w_w_w +inst_frsqrt_d :: inst_frsqrt_d_w_w +emit_frsqrt_d :: emit_frsqrt_d_w_w +inst_frcp_w :: inst_frcp_w_w_w +emit_frcp_w :: emit_frcp_w_w_w +inst_frcp_d :: inst_frcp_d_w_w +emit_frcp_d :: emit_frcp_d_w_w +inst_frint_w :: inst_frint_w_w_w +emit_frint_w :: emit_frint_w_w_w +inst_frint_d :: inst_frint_d_w_w +emit_frint_d :: emit_frint_d_w_w +inst_fmax_w :: inst_fmax_w_w_w_w +emit_fmax_w :: emit_fmax_w_w_w_w +inst_fmax_d :: inst_fmax_d_w_w_w +emit_fmax_d :: emit_fmax_d_w_w_w +inst_fmin_w :: inst_fmin_w_w_w_w +emit_fmin_w :: emit_fmin_w_w_w_w +inst_fmin_d :: inst_fmin_d_w_w_w +emit_fmin_d :: emit_fmin_d_w_w_w +inst_fceq_w :: inst_fceq_w_w_w_w +emit_fceq_w :: emit_fceq_w_w_w_w +inst_fceq_d :: inst_fceq_d_w_w_w +emit_fceq_d :: emit_fceq_d_w_w_w +inst_fcne_w :: inst_fcne_w_w_w_w +emit_fcne_w :: emit_fcne_w_w_w_w +inst_fcne_d :: inst_fcne_d_w_w_w +emit_fcne_d :: emit_fcne_d_w_w_w +inst_fclt_w :: inst_fclt_w_w_w_w +emit_fclt_w :: emit_fclt_w_w_w_w +inst_fclt_d :: inst_fclt_d_w_w_w +emit_fclt_d :: emit_fclt_d_w_w_w +inst_fcle_w :: inst_fcle_w_w_w_w +emit_fcle_w :: emit_fcle_w_w_w_w +inst_fcle_d :: inst_fcle_d_w_w_w +emit_fcle_d :: emit_fcle_d_w_w_w +inst_ffint_s_w :: inst_ffint_s_w_w_w +emit_ffint_s_w :: emit_ffint_s_w_w_w +inst_ffint_s_d :: inst_ffint_s_d_w_w +emit_ffint_s_d :: emit_ffint_s_d_w_w +inst_ffint_u_w :: inst_ffint_u_w_w_w +emit_ffint_u_w :: emit_ffint_u_w_w_w +inst_ffint_u_d :: inst_ffint_u_d_w_w +emit_ffint_u_d :: emit_ffint_u_d_w_w +inst_ftrunc_s_w :: inst_ftrunc_s_w_w_w +emit_ftrunc_s_w :: emit_ftrunc_s_w_w_w +inst_ftrunc_s_d :: inst_ftrunc_s_d_w_w +emit_ftrunc_s_d :: emit_ftrunc_s_d_w_w +inst_ftrunc_u_w :: inst_ftrunc_u_w_w_w +emit_ftrunc_u_w :: emit_ftrunc_u_w_w_w +inst_ftrunc_u_d :: inst_ftrunc_u_d_w_w +emit_ftrunc_u_d :: emit_ftrunc_u_d_w_w inst_ld_b :: inst_ld_b_w_m emit_ld_b :: emit_ld_b_w_m inst_ld_h :: inst_ld_h_w_m @@ -2865,6 +3069,30 @@ inst_ldi_w :: inst_ldi_w_w_i5 emit_ldi_w :: emit_ldi_w_w_i5 inst_ldi_d :: inst_ldi_d_w_i5 emit_ldi_d :: emit_ldi_d_w_i5 +inst_nloc_b :: inst_nloc_b_w_w +emit_nloc_b :: emit_nloc_b_w_w +inst_nloc_h :: inst_nloc_h_w_w +emit_nloc_h :: emit_nloc_h_w_w +inst_nloc_w :: inst_nloc_w_w_w +emit_nloc_w :: emit_nloc_w_w_w +inst_nloc_d :: inst_nloc_d_w_w +emit_nloc_d :: emit_nloc_d_w_w +inst_nlzc_b :: inst_nlzc_b_w_w +emit_nlzc_b :: emit_nlzc_b_w_w +inst_nlzc_h :: inst_nlzc_h_w_w +emit_nlzc_h :: emit_nlzc_h_w_w +inst_nlzc_w :: inst_nlzc_w_w_w +emit_nlzc_w :: emit_nlzc_w_w_w +inst_nlzc_d :: inst_nlzc_d_w_w +emit_nlzc_d :: emit_nlzc_d_w_w +inst_pcnt_b :: inst_pcnt_b_w_w +emit_pcnt_b :: emit_pcnt_b_w_w +inst_pcnt_h :: inst_pcnt_h_w_w +emit_pcnt_h :: emit_pcnt_h_w_w +inst_pcnt_w :: inst_pcnt_w_w_w +emit_pcnt_w :: emit_pcnt_w_w_w +inst_pcnt_d :: inst_pcnt_d_w_w +emit_pcnt_d :: emit_pcnt_d_w_w inst_vmov_s :: inst_vmov_s_vs_vs emit_vmov_s :: emit_vmov_s_vs_vs inst_vmov_p :: inst_vmov_p_vp_vp diff --git a/core/rexcode/mips/tablegen/encoding_table.odin b/core/rexcode/mips/tablegen/encoding_table.odin index 1ae9c3dd0..943c4e52a 100644 --- a/core/rexcode/mips/tablegen/encoding_table.odin +++ b/core/rexcode/mips/tablegen/encoding_table.odin @@ -1450,4 +1450,64 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .VIIM_S = { {.VIIM_S, {.VFPU_S, .IMM16S, .NONE, .NONE}, {.RT, .IMM_16, .NONE, .NONE}, 0xDF000000, 0xFF800000, .VFPU_PSP, {}} }, .VFIM_S = { {.VFIM_S, {.VFPU_S, .IMM16S, .NONE, .NONE}, {.RT, .IMM_16, .NONE, .NONE}, 0xDF800000, 0xFF800000, .VFPU_PSP, {}} }, + + // SPECGEN:BEGIN + .FADD_W = { {.FADD_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800001B, 0xFFE0003F, .MSA, {}} }, + .FADD_D = { {.FADD_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7820001B, 0xFFE0003F, .MSA, {}} }, + .FSUB_W = { {.FSUB_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7840001B, 0xFFE0003F, .MSA, {}} }, + .FSUB_D = { {.FSUB_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7860001B, 0xFFE0003F, .MSA, {}} }, + .FMUL_W = { {.FMUL_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7880001B, 0xFFE0003F, .MSA, {}} }, + .FMUL_D = { {.FMUL_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0001B, 0xFFE0003F, .MSA, {}} }, + .FDIV_W = { {.FDIV_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0001B, 0xFFE0003F, .MSA, {}} }, + .FDIV_D = { {.FDIV_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E0001B, 0xFFE0003F, .MSA, {}} }, + .FMAX_W = { {.FMAX_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7B80001B, 0xFFE0003F, .MSA, {}} }, + .FMAX_D = { {.FMAX_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7BA0001B, 0xFFE0003F, .MSA, {}} }, + .FMIN_W = { {.FMIN_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7B00001B, 0xFFE0003F, .MSA, {}} }, + .FMIN_D = { {.FMIN_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7B20001B, 0xFFE0003F, .MSA, {}} }, + .FCEQ_W = { {.FCEQ_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7880001A, 0xFFE0003F, .MSA, {}} }, + .FCEQ_D = { {.FCEQ_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0001A, 0xFFE0003F, .MSA, {}} }, + .FCLE_W = { {.FCLE_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7980001A, 0xFFE0003F, .MSA, {}} }, + .FCLE_D = { {.FCLE_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x79A0001A, 0xFFE0003F, .MSA, {}} }, + .FCLT_W = { {.FCLT_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7900001A, 0xFFE0003F, .MSA, {}} }, + .FCLT_D = { {.FCLT_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7920001A, 0xFFE0003F, .MSA, {}} }, + .FCNE_W = { {.FCNE_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0001C, 0xFFE0003F, .MSA, {}} }, + .FCNE_D = { {.FCNE_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E0001C, 0xFFE0003F, .MSA, {}} }, + .DOTP_S_H = { {.DOTP_S_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78200013, 0xFFE0003F, .MSA, {}} }, + .DOTP_S_W = { {.DOTP_S_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78400013, 0xFFE0003F, .MSA, {}} }, + .DOTP_S_D = { {.DOTP_S_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78600013, 0xFFE0003F, .MSA, {}} }, + .DOTP_U_H = { {.DOTP_U_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A00013, 0xFFE0003F, .MSA, {}} }, + .DOTP_U_W = { {.DOTP_U_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C00013, 0xFFE0003F, .MSA, {}} }, + .DOTP_U_D = { {.DOTP_U_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E00013, 0xFFE0003F, .MSA, {}} }, + .BMNZ_V = { {.BMNZ_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7880001E, 0xFFE0003F, .MSA, {}} }, + .BMZ_V = { {.BMZ_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0001E, 0xFFE0003F, .MSA, {}} }, + .BSEL_V = { {.BSEL_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0001E, 0xFFE0003F, .MSA, {}} }, + .NLOC_B = { {.NLOC_B, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B08001E, 0xFFFF003F, .MSA, {}} }, + .NLOC_H = { {.NLOC_H, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B09001E, 0xFFFF003F, .MSA, {}} }, + .NLOC_W = { {.NLOC_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0A001E, 0xFFFF003F, .MSA, {}} }, + .NLOC_D = { {.NLOC_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0B001E, 0xFFFF003F, .MSA, {}} }, + .NLZC_B = { {.NLZC_B, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0C001E, 0xFFFF003F, .MSA, {}} }, + .NLZC_H = { {.NLZC_H, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0D001E, 0xFFFF003F, .MSA, {}} }, + .NLZC_W = { {.NLZC_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0E001E, 0xFFFF003F, .MSA, {}} }, + .NLZC_D = { {.NLZC_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0F001E, 0xFFFF003F, .MSA, {}} }, + .PCNT_B = { {.PCNT_B, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B04001E, 0xFFFF003F, .MSA, {}} }, + .PCNT_H = { {.PCNT_H, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B05001E, 0xFFFF003F, .MSA, {}} }, + .PCNT_W = { {.PCNT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B06001E, 0xFFFF003F, .MSA, {}} }, + .PCNT_D = { {.PCNT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B07001E, 0xFFFF003F, .MSA, {}} }, + .FSQRT_W = { {.FSQRT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B26001E, 0xFFFF003F, .MSA, {}} }, + .FSQRT_D = { {.FSQRT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B27001E, 0xFFFF003F, .MSA, {}} }, + .FRSQRT_W = { {.FRSQRT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B28001E, 0xFFFF003F, .MSA, {}} }, + .FRSQRT_D = { {.FRSQRT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B29001E, 0xFFFF003F, .MSA, {}} }, + .FRCP_W = { {.FRCP_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2A001E, 0xFFFF003F, .MSA, {}} }, + .FRCP_D = { {.FRCP_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2B001E, 0xFFFF003F, .MSA, {}} }, + .FRINT_W = { {.FRINT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2C001E, 0xFFFF003F, .MSA, {}} }, + .FRINT_D = { {.FRINT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2D001E, 0xFFFF003F, .MSA, {}} }, + .FTRUNC_S_W = { {.FTRUNC_S_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B22001E, 0xFFFF003F, .MSA, {}} }, + .FTRUNC_S_D = { {.FTRUNC_S_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B23001E, 0xFFFF003F, .MSA, {}} }, + .FTRUNC_U_W = { {.FTRUNC_U_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B24001E, 0xFFFF003F, .MSA, {}} }, + .FTRUNC_U_D = { {.FTRUNC_U_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B25001E, 0xFFFF003F, .MSA, {}} }, + .FFINT_S_W = { {.FFINT_S_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3C001E, 0xFFFF003F, .MSA, {}} }, + .FFINT_S_D = { {.FFINT_S_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3D001E, 0xFFFF003F, .MSA, {}} }, + .FFINT_U_W = { {.FFINT_U_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3E001E, 0xFFFF003F, .MSA, {}} }, + .FFINT_U_D = { {.FFINT_U_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3F001E, 0xFFFF003F, .MSA, {}} }, + // SPECGEN:END } diff --git a/core/rexcode/mips/tablegen/generated/decode_tables.odin b/core/rexcode/mips/tablegen/generated/decode_tables.odin index 1d74c94e0..0da1b98cd 100644 --- a/core/rexcode/mips/tablegen/generated/decode_tables.odin +++ b/core/rexcode/mips/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_mips_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [783]lib.Decode_Entry{ +DECODE_ENTRIES := [840]lib.Decode_Entry{ { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00000000, 0xFFFFFFFF, .MIPS_I, {} }, { .SSNOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00000040, 0xFFFFFFFF, .MIPS32_R1, {} }, { .EHB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x000000C0, 0xFFFFFFFF, .MIPS32_R2, {} }, @@ -452,6 +452,34 @@ DECODE_ENTRIES := [783]lib.Decode_Entry{ { .PSRAW, {.GPR,.GPR,.IMM5,.NONE}, {.RD,.RT,.IMM_5,.NONE}, 0x7000003F, 0xFFE0003F, .MMI_PS2, {} }, { .SDBBP, {.IMM20,.NONE,.NONE,.NONE}, {.IMM_20,.NONE,.NONE,.NONE}, 0x7000003F, 0xFC00003F, .MIPS32_R1, {} }, { .DAUI, {.GPR,.GPR,.IMM16U,.NONE}, {.RT,.RS,.IMM_16,.NONE}, 0x74000000, 0xFC000000, .MIPS64_R6, {only_64=true} }, + { .FSQRT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B26001E, 0xFFFF003F, .MSA, {} }, + { .FSQRT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B27001E, 0xFFFF003F, .MSA, {} }, + { .FRSQRT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B28001E, 0xFFFF003F, .MSA, {} }, + { .FRSQRT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B29001E, 0xFFFF003F, .MSA, {} }, + { .FRCP_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2A001E, 0xFFFF003F, .MSA, {} }, + { .FRCP_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2B001E, 0xFFFF003F, .MSA, {} }, + { .FRINT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2C001E, 0xFFFF003F, .MSA, {} }, + { .FRINT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2D001E, 0xFFFF003F, .MSA, {} }, + { .FFINT_S_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3C001E, 0xFFFF003F, .MSA, {} }, + { .FFINT_S_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3D001E, 0xFFFF003F, .MSA, {} }, + { .FFINT_U_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3E001E, 0xFFFF003F, .MSA, {} }, + { .FFINT_U_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3F001E, 0xFFFF003F, .MSA, {} }, + { .FTRUNC_S_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B22001E, 0xFFFF003F, .MSA, {} }, + { .FTRUNC_S_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B23001E, 0xFFFF003F, .MSA, {} }, + { .FTRUNC_U_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B24001E, 0xFFFF003F, .MSA, {} }, + { .FTRUNC_U_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B25001E, 0xFFFF003F, .MSA, {} }, + { .NLOC_B, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B08001E, 0xFFFF003F, .MSA, {} }, + { .NLOC_H, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B09001E, 0xFFFF003F, .MSA, {} }, + { .NLOC_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0A001E, 0xFFFF003F, .MSA, {} }, + { .NLOC_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0B001E, 0xFFFF003F, .MSA, {} }, + { .NLZC_B, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0C001E, 0xFFFF003F, .MSA, {} }, + { .NLZC_H, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0D001E, 0xFFFF003F, .MSA, {} }, + { .NLZC_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0E001E, 0xFFFF003F, .MSA, {} }, + { .NLZC_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0F001E, 0xFFFF003F, .MSA, {} }, + { .PCNT_B, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B04001E, 0xFFFF003F, .MSA, {} }, + { .PCNT_H, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B05001E, 0xFFFF003F, .MSA, {} }, + { .PCNT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B06001E, 0xFFFF003F, .MSA, {} }, + { .PCNT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B07001E, 0xFFFF003F, .MSA, {} }, { .ADDV_B, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800000E, 0xFFE0003F, .MSA, {} }, { .ADDV_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7820000E, 0xFFE0003F, .MSA, {} }, { .ADDV_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7840000E, 0xFFE0003F, .MSA, {} }, @@ -504,10 +532,19 @@ DECODE_ENTRIES := [783]lib.Decode_Entry{ { .MSUBV_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x79200012, 0xFFE0003F, .MSA, {} }, { .MSUBV_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x79400012, 0xFFE0003F, .MSA, {} }, { .MSUBV_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x79600012, 0xFFE0003F, .MSA, {} }, + { .DOTP_S_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78200013, 0xFFE0003F, .MSA, {} }, + { .DOTP_S_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78400013, 0xFFE0003F, .MSA, {} }, + { .DOTP_S_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78600013, 0xFFE0003F, .MSA, {} }, + { .DOTP_U_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A00013, 0xFFE0003F, .MSA, {} }, + { .DOTP_U_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C00013, 0xFFE0003F, .MSA, {} }, + { .DOTP_U_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E00013, 0xFFE0003F, .MSA, {} }, { .AND_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800001E, 0xFFE0003F, .MSA, {} }, { .OR_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7820001E, 0xFFE0003F, .MSA, {} }, { .NOR_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7840001E, 0xFFE0003F, .MSA, {} }, { .XOR_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7860001E, 0xFFE0003F, .MSA, {} }, + { .BSEL_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0001E, 0xFFE0003F, .MSA, {} }, + { .BMNZ_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7880001E, 0xFFE0003F, .MSA, {} }, + { .BMZ_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0001E, 0xFFE0003F, .MSA, {} }, { .CEQ_B, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800000F, 0xFFE0003F, .MSA, {} }, { .CEQ_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7820000F, 0xFFE0003F, .MSA, {} }, { .CEQ_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7840000F, 0xFFE0003F, .MSA, {} }, @@ -556,6 +593,26 @@ DECODE_ENTRIES := [783]lib.Decode_Entry{ { .SRA_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0000D, 0xFFE0003F, .MSA, {} }, { .SRA_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0000D, 0xFFE0003F, .MSA, {} }, { .SRA_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E0000D, 0xFFE0003F, .MSA, {} }, + { .FADD_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800001B, 0xFFE0003F, .MSA, {} }, + { .FADD_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7820001B, 0xFFE0003F, .MSA, {} }, + { .FSUB_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7840001B, 0xFFE0003F, .MSA, {} }, + { .FSUB_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7860001B, 0xFFE0003F, .MSA, {} }, + { .FMUL_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7880001B, 0xFFE0003F, .MSA, {} }, + { .FMUL_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0001B, 0xFFE0003F, .MSA, {} }, + { .FDIV_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0001B, 0xFFE0003F, .MSA, {} }, + { .FDIV_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E0001B, 0xFFE0003F, .MSA, {} }, + { .FMAX_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7B80001B, 0xFFE0003F, .MSA, {} }, + { .FMAX_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7BA0001B, 0xFFE0003F, .MSA, {} }, + { .FMIN_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7B00001B, 0xFFE0003F, .MSA, {} }, + { .FMIN_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7B20001B, 0xFFE0003F, .MSA, {} }, + { .FCEQ_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7880001A, 0xFFE0003F, .MSA, {} }, + { .FCEQ_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0001A, 0xFFE0003F, .MSA, {} }, + { .FCNE_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0001C, 0xFFE0003F, .MSA, {} }, + { .FCNE_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E0001C, 0xFFE0003F, .MSA, {} }, + { .FCLT_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7900001A, 0xFFE0003F, .MSA, {} }, + { .FCLT_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7920001A, 0xFFE0003F, .MSA, {} }, + { .FCLE_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7980001A, 0xFFE0003F, .MSA, {} }, + { .FCLE_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x79A0001A, 0xFFE0003F, .MSA, {} }, { .LDI_B, {.MSA_VEC,.IMM5,.NONE,.NONE}, {.WD,.MSA_I5,.NONE,.NONE}, 0x7B000007, 0xFFE0003F, .MSA, {} }, { .LDI_H, {.MSA_VEC,.IMM5,.NONE,.NONE}, {.WD,.MSA_I5,.NONE,.NONE}, 0x7B200007, 0xFFE0003F, .MSA, {} }, { .LDI_W, {.MSA_VEC,.IMM5,.NONE,.NONE}, {.WD,.MSA_I5,.NONE,.NONE}, 0x7B400007, 0xFFE0003F, .MSA, {} }, @@ -826,40 +883,40 @@ DECODE_INDEX_PRIMARY := [64]lib.Decode_Index{ 0x1B = { 320, 13}, 0x1C = { 333, 109}, 0x1D = { 442, 1}, - 0x1E = { 443, 117}, - 0x1F = { 560, 78}, - 0x20 = { 638, 1}, - 0x21 = { 639, 1}, - 0x22 = { 640, 1}, - 0x23 = { 641, 1}, - 0x24 = { 642, 1}, - 0x25 = { 643, 1}, - 0x26 = { 644, 1}, - 0x27 = { 645, 1}, - 0x28 = { 646, 1}, - 0x29 = { 647, 1}, - 0x2A = { 648, 1}, - 0x2B = { 649, 1}, - 0x2C = { 650, 1}, - 0x2D = { 651, 1}, - 0x2E = { 652, 1}, - 0x2F = { 653, 1}, - 0x30 = { 654, 1}, - 0x31 = { 655, 1}, - 0x32 = { 656, 3}, - 0x33 = { 659, 1}, - 0x34 = { 660, 63}, - 0x35 = { 723, 3}, - 0x36 = { 726, 5}, - 0x37 = { 731, 6}, - 0x38 = { 737, 1}, - 0x39 = { 738, 1}, - 0x3A = { 739, 3}, - 0x3B = { 742, 2}, - 0x3C = { 744, 27}, - 0x3D = { 771, 3}, - 0x3E = { 774, 5}, - 0x3F = { 779, 4}, + 0x1E = { 443, 174}, + 0x1F = { 617, 78}, + 0x20 = { 695, 1}, + 0x21 = { 696, 1}, + 0x22 = { 697, 1}, + 0x23 = { 698, 1}, + 0x24 = { 699, 1}, + 0x25 = { 700, 1}, + 0x26 = { 701, 1}, + 0x27 = { 702, 1}, + 0x28 = { 703, 1}, + 0x29 = { 704, 1}, + 0x2A = { 705, 1}, + 0x2B = { 706, 1}, + 0x2C = { 707, 1}, + 0x2D = { 708, 1}, + 0x2E = { 709, 1}, + 0x2F = { 710, 1}, + 0x30 = { 711, 1}, + 0x31 = { 712, 1}, + 0x32 = { 713, 3}, + 0x33 = { 716, 1}, + 0x34 = { 717, 63}, + 0x35 = { 780, 3}, + 0x36 = { 783, 5}, + 0x37 = { 788, 6}, + 0x38 = { 794, 1}, + 0x39 = { 795, 1}, + 0x3A = { 796, 3}, + 0x3B = { 799, 2}, + 0x3C = { 801, 27}, + 0x3D = { 828, 3}, + 0x3E = { 831, 5}, + 0x3F = { 836, 4}, } @(rodata) @@ -1006,23 +1063,23 @@ DECODE_INDEX_SPECIAL2 := [64]lib.Decode_Index{ @(rodata) DECODE_INDEX_SPECIAL3 := [64]lib.Decode_Index{ - 0x00 = { 560, 2}, - 0x01 = { 562, 1}, - 0x02 = { 563, 1}, - 0x03 = { 564, 1}, - 0x04 = { 565, 1}, - 0x05 = { 566, 1}, - 0x06 = { 567, 1}, - 0x07 = { 568, 1}, - 0x0A = { 569, 3}, - 0x0C = { 572, 1}, - 0x0F = { 573, 8}, - 0x10 = { 581, 12}, - 0x12 = { 593, 9}, - 0x13 = { 602, 9}, - 0x20 = { 611, 5}, - 0x24 = { 616, 4}, - 0x30 = { 620, 9}, - 0x38 = { 629, 9}, + 0x00 = { 617, 2}, + 0x01 = { 619, 1}, + 0x02 = { 620, 1}, + 0x03 = { 621, 1}, + 0x04 = { 622, 1}, + 0x05 = { 623, 1}, + 0x06 = { 624, 1}, + 0x07 = { 625, 1}, + 0x0A = { 626, 3}, + 0x0C = { 629, 1}, + 0x0F = { 630, 8}, + 0x10 = { 638, 12}, + 0x12 = { 650, 9}, + 0x13 = { 659, 9}, + 0x20 = { 668, 5}, + 0x24 = { 673, 4}, + 0x30 = { 677, 9}, + 0x38 = { 686, 9}, } diff --git a/core/rexcode/mips/tablegen/generated/encode_tables.odin b/core/rexcode/mips/tablegen/generated/encode_tables.odin index dc456ff06..059b7f015 100644 --- a/core/rexcode/mips/tablegen/generated/encode_tables.odin +++ b/core/rexcode/mips/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_mips_generated import lib "../.." @(rodata) -ENCODE_FORMS := [783]lib.Encoding{ +ENCODE_FORMS := [840]lib.Encoding{ // .ADD { .ADD, {.GPR,.GPR,.GPR,.NONE}, {.RD,.RS,.RT,.NONE}, 0x00000020, 0xFC0007FF, .MIPS_I, {} }, // .ADDU @@ -1147,6 +1147,18 @@ ENCODE_FORMS := [783]lib.Encoding{ { .MSUBV_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x79400012, 0xFFE0003F, .MSA, {} }, // .MSUBV_D { .MSUBV_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x79600012, 0xFFE0003F, .MSA, {} }, + // .DOTP_S_H + { .DOTP_S_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78200013, 0xFFE0003F, .MSA, {} }, + // .DOTP_S_W + { .DOTP_S_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78400013, 0xFFE0003F, .MSA, {} }, + // .DOTP_S_D + { .DOTP_S_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78600013, 0xFFE0003F, .MSA, {} }, + // .DOTP_U_H + { .DOTP_U_H, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A00013, 0xFFE0003F, .MSA, {} }, + // .DOTP_U_W + { .DOTP_U_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C00013, 0xFFE0003F, .MSA, {} }, + // .DOTP_U_D + { .DOTP_U_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E00013, 0xFFE0003F, .MSA, {} }, // .AND_V { .AND_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800001E, 0xFFE0003F, .MSA, {} }, // .OR_V @@ -1155,6 +1167,12 @@ ENCODE_FORMS := [783]lib.Encoding{ { .NOR_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7840001E, 0xFFE0003F, .MSA, {} }, // .XOR_V { .XOR_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7860001E, 0xFFE0003F, .MSA, {} }, + // .BSEL_V + { .BSEL_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0001E, 0xFFE0003F, .MSA, {} }, + // .BMNZ_V + { .BMNZ_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7880001E, 0xFFE0003F, .MSA, {} }, + // .BMZ_V + { .BMZ_V, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0001E, 0xFFE0003F, .MSA, {} }, // .CEQ_B { .CEQ_B, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800000F, 0xFFE0003F, .MSA, {} }, // .CEQ_H @@ -1251,6 +1269,78 @@ ENCODE_FORMS := [783]lib.Encoding{ { .SRA_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0000D, 0xFFE0003F, .MSA, {} }, // .SRA_D { .SRA_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E0000D, 0xFFE0003F, .MSA, {} }, + // .FADD_W + { .FADD_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7800001B, 0xFFE0003F, .MSA, {} }, + // .FADD_D + { .FADD_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7820001B, 0xFFE0003F, .MSA, {} }, + // .FSUB_W + { .FSUB_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7840001B, 0xFFE0003F, .MSA, {} }, + // .FSUB_D + { .FSUB_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7860001B, 0xFFE0003F, .MSA, {} }, + // .FMUL_W + { .FMUL_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7880001B, 0xFFE0003F, .MSA, {} }, + // .FMUL_D + { .FMUL_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0001B, 0xFFE0003F, .MSA, {} }, + // .FDIV_W + { .FDIV_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0001B, 0xFFE0003F, .MSA, {} }, + // .FDIV_D + { .FDIV_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E0001B, 0xFFE0003F, .MSA, {} }, + // .FSQRT_W + { .FSQRT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B26001E, 0xFFFF003F, .MSA, {} }, + // .FSQRT_D + { .FSQRT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B27001E, 0xFFFF003F, .MSA, {} }, + // .FRSQRT_W + { .FRSQRT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B28001E, 0xFFFF003F, .MSA, {} }, + // .FRSQRT_D + { .FRSQRT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B29001E, 0xFFFF003F, .MSA, {} }, + // .FRCP_W + { .FRCP_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2A001E, 0xFFFF003F, .MSA, {} }, + // .FRCP_D + { .FRCP_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2B001E, 0xFFFF003F, .MSA, {} }, + // .FRINT_W + { .FRINT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2C001E, 0xFFFF003F, .MSA, {} }, + // .FRINT_D + { .FRINT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B2D001E, 0xFFFF003F, .MSA, {} }, + // .FMAX_W + { .FMAX_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7B80001B, 0xFFE0003F, .MSA, {} }, + // .FMAX_D + { .FMAX_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7BA0001B, 0xFFE0003F, .MSA, {} }, + // .FMIN_W + { .FMIN_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7B00001B, 0xFFE0003F, .MSA, {} }, + // .FMIN_D + { .FMIN_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7B20001B, 0xFFE0003F, .MSA, {} }, + // .FCEQ_W + { .FCEQ_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7880001A, 0xFFE0003F, .MSA, {} }, + // .FCEQ_D + { .FCEQ_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78A0001A, 0xFFE0003F, .MSA, {} }, + // .FCNE_W + { .FCNE_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78C0001C, 0xFFE0003F, .MSA, {} }, + // .FCNE_D + { .FCNE_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x78E0001C, 0xFFE0003F, .MSA, {} }, + // .FCLT_W + { .FCLT_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7900001A, 0xFFE0003F, .MSA, {} }, + // .FCLT_D + { .FCLT_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7920001A, 0xFFE0003F, .MSA, {} }, + // .FCLE_W + { .FCLE_W, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x7980001A, 0xFFE0003F, .MSA, {} }, + // .FCLE_D + { .FCLE_D, {.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}, {.WD,.WS,.WT,.NONE}, 0x79A0001A, 0xFFE0003F, .MSA, {} }, + // .FFINT_S_W + { .FFINT_S_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3C001E, 0xFFFF003F, .MSA, {} }, + // .FFINT_S_D + { .FFINT_S_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3D001E, 0xFFFF003F, .MSA, {} }, + // .FFINT_U_W + { .FFINT_U_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3E001E, 0xFFFF003F, .MSA, {} }, + // .FFINT_U_D + { .FFINT_U_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B3F001E, 0xFFFF003F, .MSA, {} }, + // .FTRUNC_S_W + { .FTRUNC_S_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B22001E, 0xFFFF003F, .MSA, {} }, + // .FTRUNC_S_D + { .FTRUNC_S_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B23001E, 0xFFFF003F, .MSA, {} }, + // .FTRUNC_U_W + { .FTRUNC_U_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B24001E, 0xFFFF003F, .MSA, {} }, + // .FTRUNC_U_D + { .FTRUNC_U_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B25001E, 0xFFFF003F, .MSA, {} }, // .LD_B { .LD_B, {.MSA_VEC,.MEM,.NONE,.NONE}, {.WD,.MSA_OFFSET_BASE_B,.NONE,.NONE}, 0x78000020, 0xFC00003F, .MSA, {} }, // .LD_H @@ -1275,6 +1365,30 @@ ENCODE_FORMS := [783]lib.Encoding{ { .LDI_W, {.MSA_VEC,.IMM5,.NONE,.NONE}, {.WD,.MSA_I5,.NONE,.NONE}, 0x7B400007, 0xFFE0003F, .MSA, {} }, // .LDI_D { .LDI_D, {.MSA_VEC,.IMM5,.NONE,.NONE}, {.WD,.MSA_I5,.NONE,.NONE}, 0x7B600007, 0xFFE0003F, .MSA, {} }, + // .NLOC_B + { .NLOC_B, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B08001E, 0xFFFF003F, .MSA, {} }, + // .NLOC_H + { .NLOC_H, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B09001E, 0xFFFF003F, .MSA, {} }, + // .NLOC_W + { .NLOC_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0A001E, 0xFFFF003F, .MSA, {} }, + // .NLOC_D + { .NLOC_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0B001E, 0xFFFF003F, .MSA, {} }, + // .NLZC_B + { .NLZC_B, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0C001E, 0xFFFF003F, .MSA, {} }, + // .NLZC_H + { .NLZC_H, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0D001E, 0xFFFF003F, .MSA, {} }, + // .NLZC_W + { .NLZC_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0E001E, 0xFFFF003F, .MSA, {} }, + // .NLZC_D + { .NLZC_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B0F001E, 0xFFFF003F, .MSA, {} }, + // .PCNT_B + { .PCNT_B, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B04001E, 0xFFFF003F, .MSA, {} }, + // .PCNT_H + { .PCNT_H, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B05001E, 0xFFFF003F, .MSA, {} }, + // .PCNT_W + { .PCNT_W, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B06001E, 0xFFFF003F, .MSA, {} }, + // .PCNT_D + { .PCNT_D, {.MSA_VEC,.MSA_VEC,.NONE,.NONE}, {.WD,.WS,.NONE,.NONE}, 0x7B07001E, 0xFFFF003F, .MSA, {} }, // .VMOV_S { .VMOV_S, {.VFPU_S,.VFPU_S,.NONE,.NONE}, {.VFPU_VD,.VFPU_VS,.NONE,.NONE}, 0xD0000000, 0xFFFF8080, .VFPU_PSP, {} }, // .VMOV_P @@ -2267,344 +2381,344 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .MSUBV_H = { 566, 1}, .MSUBV_W = { 567, 1}, .MSUBV_D = { 568, 1}, - .DOTP_S_H = { 569, 0}, - .DOTP_S_W = { 569, 0}, - .DOTP_S_D = { 569, 0}, - .DOTP_U_H = { 569, 0}, - .DOTP_U_W = { 569, 0}, - .DOTP_U_D = { 569, 0}, - .AND_V = { 569, 1}, - .OR_V = { 570, 1}, - .NOR_V = { 571, 1}, - .XOR_V = { 572, 1}, - .ANDI_B = { 573, 0}, - .ORI_B = { 573, 0}, - .NORI_B = { 573, 0}, - .XORI_B = { 573, 0}, - .BSEL_V = { 573, 0}, - .BSELI_B = { 573, 0}, - .BMNZ_V = { 573, 0}, - .BMNZI_B = { 573, 0}, - .BMZ_V = { 573, 0}, - .BMZI_B = { 573, 0}, - .CEQ_B = { 573, 1}, - .CEQ_H = { 574, 1}, - .CEQ_W = { 575, 1}, - .CEQ_D = { 576, 1}, - .CLT_S_B = { 577, 1}, - .CLT_S_H = { 578, 1}, - .CLT_S_W = { 579, 1}, - .CLT_S_D = { 580, 1}, - .CLT_U_B = { 581, 1}, - .CLT_U_H = { 582, 1}, - .CLT_U_W = { 583, 1}, - .CLT_U_D = { 584, 1}, - .CLE_S_B = { 585, 1}, - .CLE_S_H = { 586, 1}, - .CLE_S_W = { 587, 1}, - .CLE_S_D = { 588, 1}, - .CLE_U_B = { 589, 1}, - .CLE_U_H = { 590, 1}, - .CLE_U_W = { 591, 1}, - .CLE_U_D = { 592, 1}, - .MIN_S_B = { 593, 1}, - .MIN_S_H = { 594, 1}, - .MIN_S_W = { 595, 1}, - .MIN_S_D = { 596, 1}, - .MIN_U_B = { 597, 1}, - .MIN_U_H = { 598, 1}, - .MIN_U_W = { 599, 1}, - .MIN_U_D = { 600, 1}, - .MAX_S_B = { 601, 1}, - .MAX_S_H = { 602, 1}, - .MAX_S_W = { 603, 1}, - .MAX_S_D = { 604, 1}, - .MAX_U_B = { 605, 1}, - .MAX_U_H = { 606, 1}, - .MAX_U_W = { 607, 1}, - .MAX_U_D = { 608, 1}, - .SLL_B = { 609, 1}, - .SLL_H = { 610, 1}, - .SLL_W = { 611, 1}, - .SLL_D = { 612, 1}, - .SRL_B = { 613, 1}, - .SRL_H = { 614, 1}, - .SRL_W = { 615, 1}, - .SRL_D = { 616, 1}, - .SRA_B = { 617, 1}, - .SRA_H = { 618, 1}, - .SRA_W = { 619, 1}, - .SRA_D = { 620, 1}, - .SLLI_B = { 621, 0}, - .SLLI_H = { 621, 0}, - .SLLI_W = { 621, 0}, - .SLLI_D = { 621, 0}, - .SRLI_B = { 621, 0}, - .SRLI_H = { 621, 0}, - .SRLI_W = { 621, 0}, - .SRLI_D = { 621, 0}, - .SRAI_B = { 621, 0}, - .SRAI_H = { 621, 0}, - .SRAI_W = { 621, 0}, - .SRAI_D = { 621, 0}, - .FADD_W = { 621, 0}, - .FADD_D = { 621, 0}, - .FSUB_W = { 621, 0}, - .FSUB_D = { 621, 0}, - .FMUL_W = { 621, 0}, - .FMUL_D = { 621, 0}, - .FDIV_W = { 621, 0}, - .FDIV_D = { 621, 0}, - .FSQRT_W = { 621, 0}, - .FSQRT_D = { 621, 0}, - .FRSQRT_W = { 621, 0}, - .FRSQRT_D = { 621, 0}, - .FRCP_W = { 621, 0}, - .FRCP_D = { 621, 0}, - .FRINT_W = { 621, 0}, - .FRINT_D = { 621, 0}, - .FMAX_W = { 621, 0}, - .FMAX_D = { 621, 0}, - .FMIN_W = { 621, 0}, - .FMIN_D = { 621, 0}, - .FCEQ_W = { 621, 0}, - .FCEQ_D = { 621, 0}, - .FCNE_W = { 621, 0}, - .FCNE_D = { 621, 0}, - .FCLT_W = { 621, 0}, - .FCLT_D = { 621, 0}, - .FCLE_W = { 621, 0}, - .FCLE_D = { 621, 0}, - .FFINT_S_W = { 621, 0}, - .FFINT_S_D = { 621, 0}, - .FFINT_U_W = { 621, 0}, - .FFINT_U_D = { 621, 0}, - .FTRUNC_S_W = { 621, 0}, - .FTRUNC_S_D = { 621, 0}, - .FTRUNC_U_W = { 621, 0}, - .FTRUNC_U_D = { 621, 0}, - .FCVT_S_W = { 621, 0}, - .FCVT_S_D = { 621, 0}, - .FCVT_D_W = { 621, 0}, - .LD_B = { 621, 1}, - .LD_H = { 622, 1}, - .LD_W = { 623, 1}, - .LD_D = { 624, 1}, - .ST_B = { 625, 1}, - .ST_H = { 626, 1}, - .ST_W = { 627, 1}, - .ST_D = { 628, 1}, - .LDI_B = { 629, 1}, - .LDI_H = { 630, 1}, - .LDI_W = { 631, 1}, - .LDI_D = { 632, 1}, - .COPY_S_B = { 633, 0}, - .COPY_S_H = { 633, 0}, - .COPY_S_W = { 633, 0}, - .COPY_U_B = { 633, 0}, - .COPY_U_H = { 633, 0}, - .COPY_U_W = { 633, 0}, - .INSERT_B = { 633, 0}, - .INSERT_H = { 633, 0}, - .INSERT_W = { 633, 0}, - .INSERT_D = { 633, 0}, - .INSVE_B = { 633, 0}, - .INSVE_H = { 633, 0}, - .INSVE_W = { 633, 0}, - .INSVE_D = { 633, 0}, - .SHF_B = { 633, 0}, - .SHF_H = { 633, 0}, - .SHF_W = { 633, 0}, - .VSHF_B = { 633, 0}, - .VSHF_H = { 633, 0}, - .VSHF_W = { 633, 0}, - .VSHF_D = { 633, 0}, - .SLD_B = { 633, 0}, - .SLD_H = { 633, 0}, - .SLD_W = { 633, 0}, - .SLD_D = { 633, 0}, - .SLDI_B = { 633, 0}, - .SLDI_H = { 633, 0}, - .SLDI_W = { 633, 0}, - .SLDI_D = { 633, 0}, - .SPLAT_B = { 633, 0}, - .SPLAT_H = { 633, 0}, - .SPLAT_W = { 633, 0}, - .SPLAT_D = { 633, 0}, - .SPLATI_B = { 633, 0}, - .SPLATI_H = { 633, 0}, - .SPLATI_W = { 633, 0}, - .SPLATI_D = { 633, 0}, - .BZ_V = { 633, 0}, - .BNZ_V = { 633, 0}, - .BZ_B = { 633, 0}, - .BZ_H = { 633, 0}, - .BZ_W = { 633, 0}, - .BZ_D = { 633, 0}, - .BNZ_B = { 633, 0}, - .BNZ_H = { 633, 0}, - .BNZ_W = { 633, 0}, - .BNZ_D = { 633, 0}, - .NLOC_B = { 633, 0}, - .NLOC_H = { 633, 0}, - .NLOC_W = { 633, 0}, - .NLOC_D = { 633, 0}, - .NLZC_B = { 633, 0}, - .NLZC_H = { 633, 0}, - .NLZC_W = { 633, 0}, - .NLZC_D = { 633, 0}, - .PCNT_B = { 633, 0}, - .PCNT_H = { 633, 0}, - .PCNT_W = { 633, 0}, - .PCNT_D = { 633, 0}, - .VMOV_S = { 633, 1}, - .VMOV_P = { 634, 1}, - .VMOV_T = { 635, 1}, - .VMOV_Q = { 636, 1}, - .LV_S = { 637, 1}, - .LV_Q = { 638, 1}, - .SV_S = { 639, 1}, - .SV_Q = { 640, 1}, - .LVL_Q = { 641, 1}, - .LVR_Q = { 642, 1}, - .SVL_Q = { 643, 1}, - .SVR_Q = { 644, 1}, - .VIIM_S = { 645, 1}, - .VFIM_S = { 646, 1}, - .VADD_S = { 647, 1}, - .VADD_P = { 648, 1}, - .VADD_T = { 649, 1}, - .VADD_Q = { 650, 1}, - .VSUB_S = { 651, 1}, - .VSUB_P = { 652, 1}, - .VSUB_T = { 653, 1}, - .VSUB_Q = { 654, 1}, - .VMUL_S = { 655, 1}, - .VMUL_P = { 656, 1}, - .VMUL_T = { 657, 1}, - .VMUL_Q = { 658, 1}, - .VDIV_S = { 659, 1}, - .VDIV_P = { 660, 1}, - .VDIV_T = { 661, 1}, - .VDIV_Q = { 662, 1}, - .VABS_S = { 663, 1}, - .VABS_P = { 664, 1}, - .VABS_T = { 665, 1}, - .VABS_Q = { 666, 1}, - .VNEG_S = { 667, 1}, - .VNEG_P = { 668, 1}, - .VNEG_T = { 669, 1}, - .VNEG_Q = { 670, 1}, - .VSQRT_S = { 671, 1}, - .VRCP_S = { 672, 1}, - .VRCP_P = { 673, 1}, - .VRCP_T = { 674, 1}, - .VRCP_Q = { 675, 1}, - .VRSQ_S = { 676, 1}, - .VRSQ_P = { 677, 1}, - .VRSQ_T = { 678, 1}, - .VRSQ_Q = { 679, 1}, - .VDOT_P = { 680, 1}, - .VDOT_T = { 681, 1}, - .VDOT_Q = { 682, 1}, - .VSCL_P = { 683, 1}, - .VSCL_T = { 684, 1}, - .VSCL_Q = { 685, 1}, - .VHDP_P = { 686, 1}, - .VHDP_T = { 687, 1}, - .VHDP_Q = { 688, 1}, - .VAVG_P = { 689, 1}, - .VAVG_T = { 690, 1}, - .VAVG_Q = { 691, 1}, - .VFAD_P = { 692, 1}, - .VFAD_T = { 693, 1}, - .VFAD_Q = { 694, 1}, - .VMMUL_P = { 695, 1}, - .VMMUL_T = { 696, 1}, - .VMMUL_Q = { 697, 1}, - .VTFM2_P = { 698, 1}, - .VTFM3_T = { 699, 1}, - .VTFM4_Q = { 700, 1}, - .VHTFM2_P = { 701, 1}, - .VHTFM3_T = { 702, 1}, - .VHTFM4_Q = { 703, 1}, - .VMSCL_P = { 704, 1}, - .VMSCL_T = { 705, 1}, - .VMSCL_Q = { 706, 1}, - .VMMOV_P = { 707, 1}, - .VMMOV_T = { 708, 1}, - .VMMOV_Q = { 709, 1}, - .VMIDT_P = { 710, 1}, - .VMIDT_T = { 711, 1}, - .VMIDT_Q = { 712, 1}, - .VMZERO_P = { 713, 1}, - .VMZERO_T = { 714, 1}, - .VMZERO_Q = { 715, 1}, - .VMONE_P = { 716, 1}, - .VMONE_T = { 717, 1}, - .VMONE_Q = { 718, 1}, - .VCRS_T = { 719, 1}, - .VCRSP_T = { 720, 1}, - .VQMUL_Q = { 721, 1}, - .VCMP_S = { 722, 1}, - .VCMP_P = { 723, 1}, - .VCMP_T = { 724, 1}, - .VCMP_Q = { 725, 1}, - .VMIN_S = { 726, 1}, - .VMIN_P = { 727, 1}, - .VMIN_T = { 728, 1}, - .VMIN_Q = { 729, 1}, - .VMAX_S = { 730, 1}, - .VMAX_P = { 731, 1}, - .VMAX_T = { 732, 1}, - .VMAX_Q = { 733, 1}, - .VSIN_S = { 734, 1}, - .VCOS_S = { 735, 1}, - .VEXP2_S = { 736, 1}, - .VLOG2_S = { 737, 1}, - .VASIN_S = { 738, 1}, - .VNRCP_S = { 739, 1}, - .VNSIN_S = { 740, 1}, - .VREXP2_S = { 741, 1}, - .VSGN_S = { 742, 1}, - .VI2F_S = { 743, 1}, - .VI2F_P = { 744, 1}, - .VI2F_T = { 745, 1}, - .VI2F_Q = { 746, 1}, - .VF2IN_S = { 747, 1}, - .VF2IN_P = { 748, 1}, - .VF2IN_T = { 749, 1}, - .VF2IN_Q = { 750, 1}, - .VF2IZ_S = { 751, 1}, - .VF2IZ_P = { 752, 1}, - .VF2IZ_T = { 753, 1}, - .VF2IZ_Q = { 754, 1}, - .VF2IU_S = { 755, 1}, - .VF2IU_P = { 756, 1}, - .VF2IU_T = { 757, 1}, - .VF2IU_Q = { 758, 1}, - .VF2ID_S = { 759, 1}, - .VF2ID_P = { 760, 1}, - .VF2ID_T = { 761, 1}, - .VF2ID_Q = { 762, 1}, - .VF2H_P = { 763, 1}, - .VH2F_S = { 764, 1}, - .VFLUSH = { 765, 1}, - .VSYNC = { 766, 1}, - .VNOP = { 767, 1}, - .VPFXS = { 768, 1}, - .VPFXT = { 769, 1}, - .VPFXD = { 770, 1}, - .VCST_S = { 771, 1}, - .VCST_P = { 772, 1}, - .VCST_T = { 773, 1}, - .VCST_Q = { 774, 1}, - .MFV = { 775, 1}, - .MTV = { 776, 1}, - .MFVC = { 777, 1}, - .MTVC = { 778, 1}, - .BVF = { 779, 1}, - .BVT = { 780, 1}, - .BVFL = { 781, 1}, - .BVTL = { 782, 1}, + .DOTP_S_H = { 569, 1}, + .DOTP_S_W = { 570, 1}, + .DOTP_S_D = { 571, 1}, + .DOTP_U_H = { 572, 1}, + .DOTP_U_W = { 573, 1}, + .DOTP_U_D = { 574, 1}, + .AND_V = { 575, 1}, + .OR_V = { 576, 1}, + .NOR_V = { 577, 1}, + .XOR_V = { 578, 1}, + .ANDI_B = { 579, 0}, + .ORI_B = { 579, 0}, + .NORI_B = { 579, 0}, + .XORI_B = { 579, 0}, + .BSEL_V = { 579, 1}, + .BSELI_B = { 580, 0}, + .BMNZ_V = { 580, 1}, + .BMNZI_B = { 581, 0}, + .BMZ_V = { 581, 1}, + .BMZI_B = { 582, 0}, + .CEQ_B = { 582, 1}, + .CEQ_H = { 583, 1}, + .CEQ_W = { 584, 1}, + .CEQ_D = { 585, 1}, + .CLT_S_B = { 586, 1}, + .CLT_S_H = { 587, 1}, + .CLT_S_W = { 588, 1}, + .CLT_S_D = { 589, 1}, + .CLT_U_B = { 590, 1}, + .CLT_U_H = { 591, 1}, + .CLT_U_W = { 592, 1}, + .CLT_U_D = { 593, 1}, + .CLE_S_B = { 594, 1}, + .CLE_S_H = { 595, 1}, + .CLE_S_W = { 596, 1}, + .CLE_S_D = { 597, 1}, + .CLE_U_B = { 598, 1}, + .CLE_U_H = { 599, 1}, + .CLE_U_W = { 600, 1}, + .CLE_U_D = { 601, 1}, + .MIN_S_B = { 602, 1}, + .MIN_S_H = { 603, 1}, + .MIN_S_W = { 604, 1}, + .MIN_S_D = { 605, 1}, + .MIN_U_B = { 606, 1}, + .MIN_U_H = { 607, 1}, + .MIN_U_W = { 608, 1}, + .MIN_U_D = { 609, 1}, + .MAX_S_B = { 610, 1}, + .MAX_S_H = { 611, 1}, + .MAX_S_W = { 612, 1}, + .MAX_S_D = { 613, 1}, + .MAX_U_B = { 614, 1}, + .MAX_U_H = { 615, 1}, + .MAX_U_W = { 616, 1}, + .MAX_U_D = { 617, 1}, + .SLL_B = { 618, 1}, + .SLL_H = { 619, 1}, + .SLL_W = { 620, 1}, + .SLL_D = { 621, 1}, + .SRL_B = { 622, 1}, + .SRL_H = { 623, 1}, + .SRL_W = { 624, 1}, + .SRL_D = { 625, 1}, + .SRA_B = { 626, 1}, + .SRA_H = { 627, 1}, + .SRA_W = { 628, 1}, + .SRA_D = { 629, 1}, + .SLLI_B = { 630, 0}, + .SLLI_H = { 630, 0}, + .SLLI_W = { 630, 0}, + .SLLI_D = { 630, 0}, + .SRLI_B = { 630, 0}, + .SRLI_H = { 630, 0}, + .SRLI_W = { 630, 0}, + .SRLI_D = { 630, 0}, + .SRAI_B = { 630, 0}, + .SRAI_H = { 630, 0}, + .SRAI_W = { 630, 0}, + .SRAI_D = { 630, 0}, + .FADD_W = { 630, 1}, + .FADD_D = { 631, 1}, + .FSUB_W = { 632, 1}, + .FSUB_D = { 633, 1}, + .FMUL_W = { 634, 1}, + .FMUL_D = { 635, 1}, + .FDIV_W = { 636, 1}, + .FDIV_D = { 637, 1}, + .FSQRT_W = { 638, 1}, + .FSQRT_D = { 639, 1}, + .FRSQRT_W = { 640, 1}, + .FRSQRT_D = { 641, 1}, + .FRCP_W = { 642, 1}, + .FRCP_D = { 643, 1}, + .FRINT_W = { 644, 1}, + .FRINT_D = { 645, 1}, + .FMAX_W = { 646, 1}, + .FMAX_D = { 647, 1}, + .FMIN_W = { 648, 1}, + .FMIN_D = { 649, 1}, + .FCEQ_W = { 650, 1}, + .FCEQ_D = { 651, 1}, + .FCNE_W = { 652, 1}, + .FCNE_D = { 653, 1}, + .FCLT_W = { 654, 1}, + .FCLT_D = { 655, 1}, + .FCLE_W = { 656, 1}, + .FCLE_D = { 657, 1}, + .FFINT_S_W = { 658, 1}, + .FFINT_S_D = { 659, 1}, + .FFINT_U_W = { 660, 1}, + .FFINT_U_D = { 661, 1}, + .FTRUNC_S_W = { 662, 1}, + .FTRUNC_S_D = { 663, 1}, + .FTRUNC_U_W = { 664, 1}, + .FTRUNC_U_D = { 665, 1}, + .FCVT_S_W = { 666, 0}, + .FCVT_S_D = { 666, 0}, + .FCVT_D_W = { 666, 0}, + .LD_B = { 666, 1}, + .LD_H = { 667, 1}, + .LD_W = { 668, 1}, + .LD_D = { 669, 1}, + .ST_B = { 670, 1}, + .ST_H = { 671, 1}, + .ST_W = { 672, 1}, + .ST_D = { 673, 1}, + .LDI_B = { 674, 1}, + .LDI_H = { 675, 1}, + .LDI_W = { 676, 1}, + .LDI_D = { 677, 1}, + .COPY_S_B = { 678, 0}, + .COPY_S_H = { 678, 0}, + .COPY_S_W = { 678, 0}, + .COPY_U_B = { 678, 0}, + .COPY_U_H = { 678, 0}, + .COPY_U_W = { 678, 0}, + .INSERT_B = { 678, 0}, + .INSERT_H = { 678, 0}, + .INSERT_W = { 678, 0}, + .INSERT_D = { 678, 0}, + .INSVE_B = { 678, 0}, + .INSVE_H = { 678, 0}, + .INSVE_W = { 678, 0}, + .INSVE_D = { 678, 0}, + .SHF_B = { 678, 0}, + .SHF_H = { 678, 0}, + .SHF_W = { 678, 0}, + .VSHF_B = { 678, 0}, + .VSHF_H = { 678, 0}, + .VSHF_W = { 678, 0}, + .VSHF_D = { 678, 0}, + .SLD_B = { 678, 0}, + .SLD_H = { 678, 0}, + .SLD_W = { 678, 0}, + .SLD_D = { 678, 0}, + .SLDI_B = { 678, 0}, + .SLDI_H = { 678, 0}, + .SLDI_W = { 678, 0}, + .SLDI_D = { 678, 0}, + .SPLAT_B = { 678, 0}, + .SPLAT_H = { 678, 0}, + .SPLAT_W = { 678, 0}, + .SPLAT_D = { 678, 0}, + .SPLATI_B = { 678, 0}, + .SPLATI_H = { 678, 0}, + .SPLATI_W = { 678, 0}, + .SPLATI_D = { 678, 0}, + .BZ_V = { 678, 0}, + .BNZ_V = { 678, 0}, + .BZ_B = { 678, 0}, + .BZ_H = { 678, 0}, + .BZ_W = { 678, 0}, + .BZ_D = { 678, 0}, + .BNZ_B = { 678, 0}, + .BNZ_H = { 678, 0}, + .BNZ_W = { 678, 0}, + .BNZ_D = { 678, 0}, + .NLOC_B = { 678, 1}, + .NLOC_H = { 679, 1}, + .NLOC_W = { 680, 1}, + .NLOC_D = { 681, 1}, + .NLZC_B = { 682, 1}, + .NLZC_H = { 683, 1}, + .NLZC_W = { 684, 1}, + .NLZC_D = { 685, 1}, + .PCNT_B = { 686, 1}, + .PCNT_H = { 687, 1}, + .PCNT_W = { 688, 1}, + .PCNT_D = { 689, 1}, + .VMOV_S = { 690, 1}, + .VMOV_P = { 691, 1}, + .VMOV_T = { 692, 1}, + .VMOV_Q = { 693, 1}, + .LV_S = { 694, 1}, + .LV_Q = { 695, 1}, + .SV_S = { 696, 1}, + .SV_Q = { 697, 1}, + .LVL_Q = { 698, 1}, + .LVR_Q = { 699, 1}, + .SVL_Q = { 700, 1}, + .SVR_Q = { 701, 1}, + .VIIM_S = { 702, 1}, + .VFIM_S = { 703, 1}, + .VADD_S = { 704, 1}, + .VADD_P = { 705, 1}, + .VADD_T = { 706, 1}, + .VADD_Q = { 707, 1}, + .VSUB_S = { 708, 1}, + .VSUB_P = { 709, 1}, + .VSUB_T = { 710, 1}, + .VSUB_Q = { 711, 1}, + .VMUL_S = { 712, 1}, + .VMUL_P = { 713, 1}, + .VMUL_T = { 714, 1}, + .VMUL_Q = { 715, 1}, + .VDIV_S = { 716, 1}, + .VDIV_P = { 717, 1}, + .VDIV_T = { 718, 1}, + .VDIV_Q = { 719, 1}, + .VABS_S = { 720, 1}, + .VABS_P = { 721, 1}, + .VABS_T = { 722, 1}, + .VABS_Q = { 723, 1}, + .VNEG_S = { 724, 1}, + .VNEG_P = { 725, 1}, + .VNEG_T = { 726, 1}, + .VNEG_Q = { 727, 1}, + .VSQRT_S = { 728, 1}, + .VRCP_S = { 729, 1}, + .VRCP_P = { 730, 1}, + .VRCP_T = { 731, 1}, + .VRCP_Q = { 732, 1}, + .VRSQ_S = { 733, 1}, + .VRSQ_P = { 734, 1}, + .VRSQ_T = { 735, 1}, + .VRSQ_Q = { 736, 1}, + .VDOT_P = { 737, 1}, + .VDOT_T = { 738, 1}, + .VDOT_Q = { 739, 1}, + .VSCL_P = { 740, 1}, + .VSCL_T = { 741, 1}, + .VSCL_Q = { 742, 1}, + .VHDP_P = { 743, 1}, + .VHDP_T = { 744, 1}, + .VHDP_Q = { 745, 1}, + .VAVG_P = { 746, 1}, + .VAVG_T = { 747, 1}, + .VAVG_Q = { 748, 1}, + .VFAD_P = { 749, 1}, + .VFAD_T = { 750, 1}, + .VFAD_Q = { 751, 1}, + .VMMUL_P = { 752, 1}, + .VMMUL_T = { 753, 1}, + .VMMUL_Q = { 754, 1}, + .VTFM2_P = { 755, 1}, + .VTFM3_T = { 756, 1}, + .VTFM4_Q = { 757, 1}, + .VHTFM2_P = { 758, 1}, + .VHTFM3_T = { 759, 1}, + .VHTFM4_Q = { 760, 1}, + .VMSCL_P = { 761, 1}, + .VMSCL_T = { 762, 1}, + .VMSCL_Q = { 763, 1}, + .VMMOV_P = { 764, 1}, + .VMMOV_T = { 765, 1}, + .VMMOV_Q = { 766, 1}, + .VMIDT_P = { 767, 1}, + .VMIDT_T = { 768, 1}, + .VMIDT_Q = { 769, 1}, + .VMZERO_P = { 770, 1}, + .VMZERO_T = { 771, 1}, + .VMZERO_Q = { 772, 1}, + .VMONE_P = { 773, 1}, + .VMONE_T = { 774, 1}, + .VMONE_Q = { 775, 1}, + .VCRS_T = { 776, 1}, + .VCRSP_T = { 777, 1}, + .VQMUL_Q = { 778, 1}, + .VCMP_S = { 779, 1}, + .VCMP_P = { 780, 1}, + .VCMP_T = { 781, 1}, + .VCMP_Q = { 782, 1}, + .VMIN_S = { 783, 1}, + .VMIN_P = { 784, 1}, + .VMIN_T = { 785, 1}, + .VMIN_Q = { 786, 1}, + .VMAX_S = { 787, 1}, + .VMAX_P = { 788, 1}, + .VMAX_T = { 789, 1}, + .VMAX_Q = { 790, 1}, + .VSIN_S = { 791, 1}, + .VCOS_S = { 792, 1}, + .VEXP2_S = { 793, 1}, + .VLOG2_S = { 794, 1}, + .VASIN_S = { 795, 1}, + .VNRCP_S = { 796, 1}, + .VNSIN_S = { 797, 1}, + .VREXP2_S = { 798, 1}, + .VSGN_S = { 799, 1}, + .VI2F_S = { 800, 1}, + .VI2F_P = { 801, 1}, + .VI2F_T = { 802, 1}, + .VI2F_Q = { 803, 1}, + .VF2IN_S = { 804, 1}, + .VF2IN_P = { 805, 1}, + .VF2IN_T = { 806, 1}, + .VF2IN_Q = { 807, 1}, + .VF2IZ_S = { 808, 1}, + .VF2IZ_P = { 809, 1}, + .VF2IZ_T = { 810, 1}, + .VF2IZ_Q = { 811, 1}, + .VF2IU_S = { 812, 1}, + .VF2IU_P = { 813, 1}, + .VF2IU_T = { 814, 1}, + .VF2IU_Q = { 815, 1}, + .VF2ID_S = { 816, 1}, + .VF2ID_P = { 817, 1}, + .VF2ID_T = { 818, 1}, + .VF2ID_Q = { 819, 1}, + .VF2H_P = { 820, 1}, + .VH2F_S = { 821, 1}, + .VFLUSH = { 822, 1}, + .VSYNC = { 823, 1}, + .VNOP = { 824, 1}, + .VPFXS = { 825, 1}, + .VPFXT = { 826, 1}, + .VPFXD = { 827, 1}, + .VCST_S = { 828, 1}, + .VCST_P = { 829, 1}, + .VCST_T = { 830, 1}, + .VCST_Q = { 831, 1}, + .MFV = { 832, 1}, + .MTV = { 833, 1}, + .MFVC = { 834, 1}, + .MTVC = { 835, 1}, + .BVF = { 836, 1}, + .BVT = { 837, 1}, + .BVFL = { 838, 1}, + .BVTL = { 839, 1}, } diff --git a/core/rexcode/mips/tablegen/specgen.lua b/core/rexcode/mips/tablegen/specgen.lua new file mode 100644 index 000000000..d18e5be20 --- /dev/null +++ b/core/rexcode/mips/tablegen/specgen.lua @@ -0,0 +1,113 @@ +#!/usr/bin/env luajit +-- rexcode ยท Brendan Punsky (dotbmp@github), original author +-- +-- Encode-form spec generator (MIPS / MSA). Expands compact per-family specs +-- into ENCODING_TABLE entries, deriving `bits` from llvm-mc (the oracle) and +-- `mask` empirically: assemble each form all-zero, then one variant per operand +-- field at its max register, and mask = ~(union of the deltas). MIPS words are +-- big-endian. Each MSA element format (.B/.H/.W/.D) is a distinct mnemonic +-- (e.g. FADD_W / FADD_D), so the data-format suffix is part of the name. +-- +-- Output replaces the SPECGEN:BEGIN..SPECGEN:END region of encoding_table.odin. +-- +-- Run: luajit tablegen/specgen.lua (from mips/, or with a full path) + +local bit = require("bit") +local LLVM = "llvm-mc --assemble --triple=mips --mattr=+msa --show-encoding" +local DIR = (arg[0]:match("^(.*)/[^/]*$")) or "." +local TABLE = DIR .. "/encoding_table.odin" + +local function word(line) + local p = io.popen(string.format("printf '%%s\\n' '%s' | %s 2>/dev/null", line, LLVM)) + local out = p:read("*a"); p:close() + local b1,b2,b3,b4 = out:match("0x(%x%x),0x(%x%x),0x(%x%x),0x(%x%x)") + if not b1 then return nil end + return tonumber(b1..b2..b3..b4, 16) -- big-endian: first byte is MSB +end +local function mask_of(base, variants) + local x = 0 + for _, w in ipairs(variants) do x = bit.bor(x, bit.bxor(base, w)) end + return bit.band(bit.bnot(x), 0xFFFFFFFF) +end + +local sections, skips, n_forms = {}, {}, 0 + +-- Emit one mnemonic's single-form entry from an asm builder + per-field maxes. +-- ops/enc are the prebuilt "{.A,.B,.C,.NONE}" text. asm(vals) returns the asm +-- (vals[i] = register number for field i); maxes[i] = max register for field i. +local function entry(mnem, ops, enc, feat, asm, maxes) + local zero = {}; for i=1,#maxes do zero[i]=0 end + local b0 = word(asm(zero)) + if not b0 then skips[#skips+1]=mnem; return nil end + local vs = {} + for i=1,#maxes do + local v={}; for j=1,#maxes do v[j]=0 end; v[i]=maxes[i] + local w=word(asm(v)); if not w then skips[#skips+1]=mnem; return nil end; vs[#vs+1]=w + end + n_forms = n_forms + 1 + return string.format(" .%s = { {.%s, %s, %s, 0x%s, 0x%s, .%s, {}} },", + mnem, mnem, ops, enc, bit.tohex(b0):upper(), bit.tohex(mask_of(b0,vs)):upper(), feat) +end + +-- A vector 3-register family: Wd, Ws, Wt (each a .B/.H/.W/.D variant). +local OPS3 = "{.MSA_VEC,.MSA_VEC,.MSA_VEC,.NONE}" +local ENC3 = "{.WD,.WS,.WT,.NONE}" +local OPS2 = "{.MSA_VEC,.MSA_VEC,.NONE,.NONE}" +local ENC2 = "{.WD,.WS,.NONE,.NONE}" + +-- emit a family across data-format suffixes. +-- base = uppercase stem (FADD); low = lowercase asm stem (fadd) +-- dfs = list of {SUFFIX, asm_token} (e.g. {"W","w"}) +-- three = 3-register (else 2-register) +local function family(base, low, dfs, three) + local rows = {} + local ops = three and OPS3 or ENC3 and (three and OPS3 or OPS2) + for _, d in ipairs(dfs) do + local mnem = base .. "_" .. d[1] + local function asm(v) + if three then return string.format("%s.%s $w%d,$w%d,$w%d", low, d[2], v[1], v[2], v[3]) end + return string.format("%s.%s $w%d,$w%d", low, d[2], v[1], v[2]) + end + local r = entry(mnem, three and OPS3 or OPS2, three and ENC3 or ENC2, "MSA", asm, three and {31,31,31} or {31,31}) + if r then rows[#rows+1] = r end + end + for _, r in ipairs(rows) do sections[#sections+1] = r end +end + +local WD = {{"W","w"},{"D","d"}} -- 3RF / 2RF data formats +local HWD = {{"H","h"},{"W","w"},{"D","d"}} -- 3R (no byte) data formats +local BHWD = {{"B","b"},{"H","h"},{"W","w"},{"D","d"}} + +-- ---- 3RF: vector floating-point arithmetic / compare (Wd, Ws, Wt; .W/.D) ---- +for _, b in ipairs({ + {"FADD","fadd"},{"FSUB","fsub"},{"FMUL","fmul"},{"FDIV","fdiv"}, + {"FMAX","fmax"},{"FMIN","fmin"}, + {"FCEQ","fceq"},{"FCLE","fcle"},{"FCLT","fclt"},{"FCNE","fcne"}, +}) do family(b[1], b[2], WD, true) end + +-- ---- 3R: signed/unsigned dot product (Wd, Ws, Wt; .H/.W/.D) ----------------- +for _, b in ipairs({{"DOTP_S","dotp_s"},{"DOTP_U","dotp_u"}}) do family(b[1], b[2], HWD, true) end + +-- ---- VEC: bit-select (no data format) -------------------------------------- +for _, b in ipairs({{"BMNZ_V","bmnz.v"},{"BMZ_V","bmz.v"},{"BSEL_V","bsel.v"}}) do + local r = entry(b[1], OPS3, ENC3, "MSA", function(v) return string.format("%s $w%d,$w%d,$w%d", b[2], v[1], v[2], v[3]) end, {31,31,31}) + if r then sections[#sections+1] = r end +end + +-- ---- 2R: count leading ones/zeros, popcount (Wd, Ws; .B/.H/.W/.D) ----------- +for _, b in ipairs({{"NLOC","nloc"},{"NLZC","nlzc"},{"PCNT","pcnt"}}) do family(b[1], b[2], BHWD, false) end + +-- ---- 2RF: vector floating-point one-source (Wd, Ws; .W/.D) ------------------ +for _, b in ipairs({ + {"FSQRT","fsqrt"},{"FRSQRT","frsqrt"},{"FRCP","frcp"},{"FRINT","frint"}, + {"FTRUNC_S","ftrunc_s"},{"FTRUNC_U","ftrunc_u"},{"FFINT_S","ffint_s"},{"FFINT_U","ffint_u"}, +}) do family(b[1], b[2], WD, false) end + +-- ---- splice into the SoT --------------------------------------------------- +local region = " // SPECGEN:BEGIN\n" .. table.concat(sections, "\n") .. "\n // SPECGEN:END" +local fh = assert(io.open(TABLE, "r")); local src = fh:read("*a"); fh:close() +local new, n = src:gsub(" // SPECGEN:BEGIN.- // SPECGEN:END", (region:gsub("%%", "%%%%"))) +if n ~= 1 then io.stderr:write("FATAL: expected one SPECGEN region, found "..n.."\n"); os.exit(1) end +local wh = assert(io.open(TABLE, "w")); wh:write(new); wh:close() +io.write(string.format("specgen(mips): wrote %d forms\n", n_forms)) +if #skips > 0 then io.write(" skipped "..#skips.." form(s): "..table.concat(skips, " ").."\n") end diff --git a/core/rexcode/mips/tables/mips.encode_forms.bin b/core/rexcode/mips/tables/mips.encode_forms.bin index b60d2002a1d345f409128642d065e04b81e9f7c6..e26df6cac6b85e18f73f3bfe5990ab3ac8d094c4 100644 GIT binary patch delta 1170 zcmZ2ewV;`CLy1oP1}0%)VFo2-6$W7jg$jFy2mb{bHX?~RK*cs8i6ubAHY15GfQoHF z5<37D+lnOi04lZ(A~v~N$J2BlgsrT?AjbgHa{x)K0jlQ^lGuXHdv%U8*E2A~oG;D5 z09D3_BnI;m6OtIrOUy`OFfXwniNUO8MG}K~lMNzPudKo#4R9D`c5J;VS1f()EUV(L&aE+jDxs2Derm?l(=2T4q;x*lR6FOr}(R3RUdm=08o zA4yCXDkgyB=!R-Y0uV$JTL2XkLK0(uiV4>v2`WGZMc`sm46q;+MG}Jrp%`3D1|EXq zNMf)Mlz@v#F)&m@94HADt5;!=Vo-nzNqC49+4o!%0NO43=CAIC)Y~KZ!VGMU=##dF$-!1n4VlJlU@%JT?Q2$02*vR!vI(e z@;AdWCW!q5;s8)8Sibq8j6HKbKQjXZh${f41);PMlop24B2ZcsN{c~haVRYTr6r-X z6qJ^R(lSt57D~%O=z0cu2!lZZN-IKXB`B>7rB$G`DwI}((&|uJ14?T`X)P$N4W)IU zv@Vp^1Jm^k4EkUO1A_sSHiXhfP}&$un?Pw(C~XF%&7rgfl(vM@R#4g+O4~qbTPSS@ kqP-ay80M|80|SF46Nn^0Pp%bJ_XMf4g{r2Ao;+97T#%80fx(4|fdNFjg6Pe% zV)l&nAWL$gmJ9$5wx3}DEC%_TA(sha|G+sw1Y6Kg4i)#G%pxHHc3dS?#Q@M?`xyqn gVsPYC!XjtD91uc_px-Pi!Ou9^MlxZuh_nkc0E=!#%>V!Z diff --git a/core/rexcode/mips/tables/mips.entries.bin b/core/rexcode/mips/tables/mips.entries.bin index f3f41136b2a885a8cbb1236008f9a058e0c9ba59..91bc2ee48babbe06514f7f4e0d20b346dd2576a1 100644 GIT binary patch delta 1172 zcmZ2ewV;`C!yKi04rXCt1_mW%1_n6>wQ75Y|NjLUIFZEEp<-M}Vj55}ZX_{Hs2C5D zm=;uw7fDPTD#iy9s|Q=G0~O?l2!h3Qp<*&fVm44QStK!AsF)m*m>pD19!bm|DyD!W zrc_-I@v$P3pfXgU5|Wq-R7@F3Ocg4Yge1lR6-!1EB#Mq%?o98GA zu+(p05*8L_P*PT55N1%QuxEJiUyxxVl9&TjY!i}L0#s}>lGp;M*cK$Q15mN8NMaA5 zV%s2MlQ*k*n(l+Jl~owz7+`u1Ac-|V^&CPHTd?`7+HvN324cs#6 delta 27 jcmZ3`%($j%!yKi}XH*1OCWmMSY<{45fO)flet{4Gq%8{L diff --git a/core/rexcode/mips/tables/mips.idx_primary.bin b/core/rexcode/mips/tables/mips.idx_primary.bin index 9978f027ce193fd8a4b795cefd5c10dbc5a64404..46474339bc8b58ad440444c78cf7d29ee895ce66 100644 GIT binary patch delta 142 zcmZo*YG9gBRlklQlgW=^I};|tVL*vrJou#bt6VLuZi z!vQ8nhJ#Fu42PH)84fcsG8|!IWH`#i$Z(8_k>NNKBf|+MMuwA2%nWCk7#Yqo*)#Ak wGc)irvoeSB|b z&cw*j!NkbW$;8Oe#l*_Vq_>}Vq}1UA|_@qvlL0JjERGxj)?~> j-o?bpFqw%H%qE4H!^DcBd?6DH3ZD>XDFHjz5s(J}n}P{u literal 256 zcmXqDVq!32Vq`F8Vq`F3Vq`F7Vq`F5Vq`F9Vq~yjVq|~;OD1M8(*{Y*mWhMGm5B!| i9>~PW5XHm^W|KlBGqIv5&tPIf;S=KI5U{h9fII-3odsk7