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Implement a CFG for the assembler to improve the soundness of the checks

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gingerBill
2026-08-24 21:49:32 +01:00
parent b69e61983a
commit 322f59dae0
7 changed files with 681 additions and 224 deletions
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15
core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin
View File

@@ -821,6 +821,21 @@ main :: proc() {
}
""")
strings.write_string(&sb, """
bool is_self_zeroing_idiom(u16 m) const {
switch (m) {
case M_XOR:
case M_SUB:
case M_SUBW:
case M_SLT:
case M_SLTU:
case M_ANDN:
return true;
}
return false;
}
""")
strings.write_string(&sb, "\n};\n")
strings.write_string(&sb, "\n\n\n")

39
core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin
View File

@@ -824,6 +824,45 @@ main :: proc() {
}
""")
strings.write_string(&sb, """
bool is_self_zeroing_idiom(u16 m) const {
switch (m) {
// integer xor / sub: x ^ x == 0, x - x == 0
case M_XOR:
case M_SUB:
// SSE/AVX bitwise xor of a register with itself
case M_PXOR:
case M_XORPS:
case M_XORPD:
case M_VPXOR:
case M_VXORPS:
case M_VXORPD:
// packed integer subtract: psub x, x == 0
case M_PSUBB:
case M_PSUBW:
case M_PSUBD:
case M_PSUBQ:
case M_VPSUBB:
case M_VPSUBW:
case M_VPSUBD:
case M_VPSUBQ:
// andnot of a value with itself: (~x) & x == 0
case M_ANDN: // BMI1 GPR: andn dst, a, a
case M_ANDNPS:
case M_ANDNPD:
case M_PANDN:
case M_VANDNPS:
case M_VANDNPD:
case M_VPANDN:
return true;
}
return false;
}
""")
strings.write_string(&sb, "\n};\n")
strings.write_string(&sb, "\n\n\n")