diff --git a/core/rexcode/isa/x86/clobber_types.odin b/core/rexcode/isa/x86/clobber_types.odin index 164003cd2..2e2d2eb64 100644 --- a/core/rexcode/isa/x86/clobber_types.odin +++ b/core/rexcode/isa/x86/clobber_types.odin @@ -29,12 +29,13 @@ Side_Effects :: distinct bit_set[Side_Effect; u16] Clobber_Regs :: distinct bit_set[Clobber_Reg; u16] Clobber_Reg :: enum u8 { - RAX, RBX, RCX, RDX, RSI, RDI, RSP, RBP, R11, - XMM0, VECTOR, MXCSR, FPU_ST, FPU_SW, + RAX, RBX, RCX, RDX, + RSI, RDI, RSP, RBP, + R11, XMM0, VECTOR, MXCSR, + FPU_ST, FPU_SW, } -Operand_Set :: distinct bit_set[Operand_Slot; u8] -Operand_Slot :: enum u8 { OP0, OP1, OP2, OP3 } +Operand_Set :: distinct bit_set[0..<4; u8] Clobber :: struct { written: Operand_Set, diff --git a/core/rexcode/isa/x86/tablegen/clobber_table.odin b/core/rexcode/isa/x86/tablegen/clobber_table.odin index 3bc0a9b19..2d59cce41 100644 --- a/core/rexcode/isa/x86/tablegen/clobber_table.odin +++ b/core/rexcode/isa/x86/tablegen/clobber_table.odin @@ -6,7 +6,7 @@ // 1. Implicit-operand normalisation. An operand that is an implicit register // (AL/AX/EAX/RAX_IMPL -> RAX, CL_IMPL -> RCX, XMM0_IMPL -> XMM0, // ST0_IMPL -> FPU_ST) or an implicit constant (ONE_IMPL) is removed from the -// OP0..OP3 slot set and, if that slot was written/read, folded into +// OP0.3 slot set and, if that slot was written/read, folded into // implicit_wr/implicit_rd. Registers that are implicit but NOT tied to an // operand (RSP for the stack, RSI/RDI/RCX for strings, RDX for MULX, ...) // are inherent and kept on every form. @@ -44,531 +44,531 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ // 8.1 Data Transfer Encodings .MOV = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .MOVABS = { - {written={.OP0}, read={.OP1}}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, }, .MOVZX = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .MOVSX = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .MOVSXD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .XCHG = { // asserts LOCK when a mem operand is used - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, }, .PUSH = { - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, }, .POP = { - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, }, .LEA = { // no memory access: computes effective address only - {written={.OP0}}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}}, + {written={0}}, + {written={0}}, }, // 8.2 Arithmetic Encodings .ADD = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .ADC = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, }, .SUB = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .SBB = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, }, .MUL = { // RAX/RDX widths follow operand size (r/m8 -> AX only) - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, }, .IMUL = { // union of forms: 1-op writes RDX:RAX (implicit); 2/3-op writes OP0, no implicit - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-op r/m8: AX <- AL*r/m8 - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-op r/m8: AX <- AL*r/m8 + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) }, .DIV = { // RDX:RAX = quotient/remainder; r/m8 uses AX only - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, .IDIV = { // RDX:RAX = quotient/remainder; r/m8 uses AX only - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, .INC = { // CF deliberately NOT affected - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .DEC = { // CF deliberately NOT affected - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .NEG = { - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .CMP = { // no operand written; flags only - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, // 8.3 Logical Encodings .AND = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .OR = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .XOR = { - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .NOT = { - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, }, .TEST = { // no operand written; flags only - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, }, // 8.4 Shift/Rotate Encodings .SHL = { // OF defined only for 1-bit count; count==0 leaves flags unchanged - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .SHR = { // OF defined only for 1-bit count; count==0 leaves flags unchanged - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .SAR = { // OF defined only for 1-bit count; count==0 leaves flags unchanged - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, }, .ROL = { // only CF/OF affected; count==0 leaves flags unchanged - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, }, .ROR = { // only CF/OF affected; count==0 leaves flags unchanged - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, }, .RCL = { - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, }, .RCR = { - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, }, .SHLD = { - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, }, .SHRD = { - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, }, // 8.5 Bit Operation Encodings .BT = { // ZF unaffected - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .BTS = { // ZF unaffected - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .BTR = { // ZF unaffected - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .BTC = { // ZF unaffected - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .BSF = { // destination undefined when source == 0 - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, }, .BSR = { // destination undefined when source == 0 - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, }, .POPCNT = { // ZF per source; CF/OF/SF/AF/PF cleared - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, .LZCNT = { - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .TZCNT = { - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, // 8.6 Control Flow Encodings .JMP = { // indirect forms read reg/mem; writes RIP - {read={.OP0}, side_effects={.CONTROL}}, - {read={.OP0}, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, side_effects={.CONTROL}}, + {read={0}, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, }, .JA = { // reads flags; writes RIP on taken branch {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, @@ -709,11 +709,11 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, }, .CALL = { // pushes return address - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, }, .RET = { // pops return address (+imm16 form adjusts RSP) {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, @@ -729,7 +729,7 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, }, .INT = { // pushes RFLAGS/CS/RIP; clears TF/IF via gate - {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + {read={0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, }, .INT3 = { // pushes RFLAGS/CS/RIP; clears TF/IF via gate {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, @@ -752,244 +752,244 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ // 8.7 Conditional Set/Move Encodings .SETA = { - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, }, .SETAE = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETB = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETBE = { - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, }, .SETC = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETE = { - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, }, .SETG = { - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, }, .SETGE = { - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, }, .SETL = { - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, }, .SETLE = { - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, }, .SETNA = { - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, }, .SETNAE = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETNB = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETNBE = { - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, }, .SETNC = { - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, }, .SETNE = { - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, }, .SETNG = { - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, }, .SETNGE = { - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, }, .SETNL = { - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, }, .SETNLE = { - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, }, .SETNO = { - {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + {written={0}, flags_rd={.OF}, writes_mem=true}, }, .SETNP = { - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, }, .SETNS = { - {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + {written={0}, flags_rd={.SF}, writes_mem=true}, }, .SETNZ = { - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, }, .SETO = { - {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + {written={0}, flags_rd={.OF}, writes_mem=true}, }, .SETP = { - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, }, .SETPE = { - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, }, .SETPO = { - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, }, .SETS = { - {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + {written={0}, flags_rd={.SF}, writes_mem=true}, }, .SETZ = { - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, }, .CMOVA = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, }, .CMOVAE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVB = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVBE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, }, .CMOVC = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, }, .CMOVG = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, }, .CMOVGE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, }, .CMOVL = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, }, .CMOVLE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, }, .CMOVNA = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, }, .CMOVNAE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVNB = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVNBE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, }, .CMOVNC = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, }, .CMOVNE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, }, .CMOVNG = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, }, .CMOVNGE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, }, .CMOVNL = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, }, .CMOVNLE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, }, .CMOVNO = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, }, .CMOVNP = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, }, .CMOVNS = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, }, .CMOVNZ = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, }, .CMOVO = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, }, .CMOVP = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, }, .CMOVPE = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, }, .CMOVPO = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, }, .CMOVS = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, }, .CMOVZ = { // conditional write of OP0 - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, }, // 8.8 String Operation Encodings @@ -1005,8 +1005,8 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ .MOVSD = { // REP/REPZ/REPNZ forms read+write RCX {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // SSE variants - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVSQ = { // REP/REPZ/REPNZ forms read+write RCX {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, @@ -1023,7 +1023,7 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ .CMPSD = { // REP/REPZ/REPNZ forms read+write RCX {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CMPSQ = { // REP/REPZ/REPNZ forms read+write RCX {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, @@ -1185,569 +1185,569 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ // 8.11 BMI/ADX Encodings .ANDN = { - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, }, .BEXTR = { - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, }, .BLSI = { - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, }, .BLSMSK = { - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, }, .BLSR = { - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, }, .BZHI = { - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, }, .PDEP = { // no flags affected - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PEXT = { // no flags affected - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .RORX = { // no flags affected - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SARX = { // no flags affected (unlike SAR/SHL/SHR) - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .SHLX = { // no flags affected (unlike SAR/SHL/SHR) - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .SHRX = { // no flags affected (unlike SAR/SHL/SHR) - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .MULX = { // no flags affected; implicit multiplicand in rDX - {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}, + {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}, }, .ADCX = { // only CF (chains with ADCX) - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, }, .ADOX = { // only OF (chains with ADOX) - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, }, // 8.12 SSE Encodings .MOVAPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVUPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVAPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVUPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVSS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVDQA = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVDQU = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVQ = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .MOVD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVLPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVHPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVLPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVHPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVLHPS = { - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .MOVHLPS = { - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .MOVMSKPS = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .MOVMSKPD = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .MOVNTPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVNTPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVNTDQ = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .MOVNTDQA = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ADDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ADDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ADDSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ADDSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SUBSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SUBSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MULPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MULPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MULSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MULSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .DIVPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .DIVPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .DIVSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .DIVSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SQRTPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SQRTPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SQRTSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .SQRTSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .RCPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .RCPSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .RSQRTPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .RSQRTSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MAXPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MAXPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MAXSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MAXSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MINPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MINPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MINSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MINSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ANDPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ANDPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ANDNPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ANDNPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ORPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .ORPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .XORPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .XORPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .CMPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CMPPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CMPSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .COMISS = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .COMISD = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .UCOMISS = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .UCOMISD = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .SHUFPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .SHUFPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .UNPCKLPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .UNPCKHPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .UNPCKLPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .UNPCKHPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .CVTPS2PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTPD2PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSS2SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSD2SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTPS2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTPD2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTDQ2PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTDQ2PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSS2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSD2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSI2SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTSI2SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTTPS2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTTPD2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTTSS2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .CVTTSD2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .PADDB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDUSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PADDUSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBUSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSUBUSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULLW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULHW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULHUW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULUDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMADDWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PAND = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PANDN = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .POR = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PXOR = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSLLW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSLLD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSLLQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSRLW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSRLD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSRLQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSRAW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PSRAD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .PCMPEQB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCMPEQW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCMPEQD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCMPGTB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCMPGTW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCMPGTD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PACKSSWB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PACKSSDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PACKUSWB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKLBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKLWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKLDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKLQDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKHBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKHWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKHDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PUNPCKHQDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSHUFD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PSHUFHW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PSHUFLW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PSHUFW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PEXTRW = { // destination may be memory - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .PINSRW = { - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PMOVMSKB = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .PAVGB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PAVGW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMAXUB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMAXSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINUB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSADBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .MASKMOVDQU = { // byte-masked store to DS:[rDI] - {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, }, .LFENCE = { // ordering/hint; no clobber {side_effects={.FENCE, .SERIALIZING}}, @@ -1762,233 +1762,233 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {side_effects={.HINT}}, }, .CLFLUSH = { // flushes cache line for the addressed byte - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, }, .ADDSUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ADDSUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .HADDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .HADDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .HSUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .HSUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .MOVDDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .MOVSLDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .MOVSHDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .LDDQU = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSHUFB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHADDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHADDD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHADDSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHSUBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHSUBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PHSUBSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMADDUBSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULHRSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSIGNB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSIGNW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PSIGND = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PABSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PABSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PABSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PALIGNR = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .BLENDPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .BLENDPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .BLENDVPS = { - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, }, .BLENDVPD = { - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, }, .PBLENDW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PBLENDVB = { - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, }, .DPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .DPPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .EXTRACTPS = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .INSERTPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .MPSADBW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PACKUSDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PEXTRB = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .PEXTRD = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .PEXTRQ = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .PHMINPOSUW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PINSRB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PINSRD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PINSRQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .PMAXSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMAXSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMAXUW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMAXUD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINUW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMINUD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXBQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXWQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVSXDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXBQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXWQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMOVZXDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PMULLD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PTEST = { // ZF from AND, CF from ANDN; others cleared - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .ROUNDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ROUNDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ROUNDSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .ROUNDSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .PCMPEQQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .CRC32 = { // accumulates CRC into OP0; no flags - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, }, .PCMPESTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, @@ -2003,430 +2003,430 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, .PCMPGTQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .PCLMULQDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .AESDEC = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .AESDECLAST = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .AESENC = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .AESENCLAST = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .AESIMC = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .AESKEYGENASSIST = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .SHA1MSG1 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SHA1MSG2 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SHA1NEXTE = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SHA1RNDS4 = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .SHA256MSG1 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SHA256MSG2 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .SHA256RNDS2 = { - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, }, // 8.13 AVX/AVX2 Encodings .VADDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VADDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VADDSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VADDSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSUBSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSUBSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMULPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMULPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMULSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMULSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VDIVPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VDIVPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VDIVSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VDIVSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSQRTPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSQRTPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSQRTSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSQRTSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCPSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRTPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRTSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMAXPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMAXPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMAXSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMAXSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMINPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMINPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMINSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VMINSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VANDPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VANDPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VANDNPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VANDNPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VORPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VORPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VXORPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VXORPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VCMPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCMPPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCMPSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCMPSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCOMISS = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .VCOMISD = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .VUCOMISS = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .VUCOMISD = { // OF/SF/AF cleared - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, }, .VSHUFPS = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VSHUFPD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VUNPCKLPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VUNPCKHPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VUNPCKLPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VUNPCKHPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VBLENDPS = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VBLENDPD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VBLENDVPS = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VBLENDVPD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VDPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VDPPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VROUNDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VROUNDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VROUNDSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VROUNDSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VEXTRACTPS = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .VINSERTPS = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VMOVAPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVUPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVAPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVUPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVSS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VMOVSD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VMOVDQA = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVDQU = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVQ = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VMOVD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVLPS = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVHPS = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVLPD = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVHPD = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVLHPS = { - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .VMOVHLPS = { - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .VMOVMSKPS = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VMOVMSKPD = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VMOVNTPS = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVNTPD = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVNTDQ = { - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .VMOVNTDQA = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VADDSUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VADDSUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VHADDPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VHADDPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VHSUBPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VHSUBPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VLDDQU = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVSLDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVSHDUP = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPCMPESTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, @@ -2441,565 +2441,565 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, }, .VPBROADCASTB = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPBROADCASTW = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPBROADCASTD = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPBROADCASTQ = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VCVTPS2PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTPD2PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSS2SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSD2SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTPS2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTPD2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTDQ2PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTDQ2PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSS2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSD2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSI2SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTSI2SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTTPS2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTTPD2DQ = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTTSS2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTTSD2SI = { // destination is a GPR - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VPADDB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPADDW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPADDD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPADDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSUBB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSUBW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSUBD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSUBQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULLW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULHW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULHUW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULUDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMADDWD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPAND = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPANDN = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPOR = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPXOR = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSLLW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSLLD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSLLQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSRLW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSRLD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSRLQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSRAW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPSRAD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, }, .VPCMPEQB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPEQW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPEQD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPEQQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPGTB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPGTW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPGTD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPGTQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPACKSSWB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPACKSSDW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPACKUSWB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPACKUSDW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKLBW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKLWD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKLDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKLQDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKHBW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKHWD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKHDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPUNPCKHQDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSHUFD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSHUFHW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSHUFLW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPEXTRB = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .VPEXTRW = { // destination may be memory - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, writes_mem=true}, }, .VPEXTRD = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .VPEXTRQ = { // destination may be memory - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, }, .VPINSRB = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPINSRW = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPINSRD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPINSRQ = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPMOVMSKB = { // destination is a GPR - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPTEST = { // ZF from AND, CF from ANDN; others cleared - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .VPSHUFB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHADDW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHADDD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHADDSW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHSUBW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHSUBD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPHSUBSW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMADDUBSW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULHRSW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSIGNB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSIGNW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSIGND = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPABSB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPABSW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPABSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPALIGNR = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPBLENDW = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPBLENDVB = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VMPSADBW = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPHMINPOSUW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMAXSB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMAXSD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMAXUW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMAXUD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMINSB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMINSD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMINUW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMINUD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMOVSXBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSXBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSXBQ = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSXWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSXWQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSXDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXBW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXBD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXBQ = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXWD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXWQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVZXDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMULDQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMULLD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VMASKMOVDQU = { // byte-masked store to DS:[rDI] - {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, }, .VPCLMULQDQ = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VAESDEC = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VAESDECLAST = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VAESENC = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VAESENCLAST = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VAESIMC = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VAESKEYGENASSIST = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VBROADCASTSS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VBROADCASTSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, }, .VBROADCASTF128 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VEXTRACTF128 = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VINSERTF128 = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPERM2F128 = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VMASKMOVPS = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VMASKMOVPD = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VTESTPS = { // ZF from AND, CF from ANDN; others cleared - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .VTESTPD = { // ZF from AND, CF from ANDN; others cleared - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, }, .VZEROALL = { // zeroes the entire vector register file (YMM/ZMM) {implicit_wr={.VECTOR}}, @@ -3008,1199 +3008,1199 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.VECTOR}}, }, .VBROADCASTI128 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VEXTRACTI128 = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VINSERTI128 = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPERM2I128 = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPERMD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPBLENDD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPSLLVD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSLLVQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSRLVD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSRLVQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSRAVD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMASKMOVD = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VPMASKMOVQ = { - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, }, .VGATHERDPS = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VGATHERDPD = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VGATHERQPS = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VGATHERQPD = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VPGATHERDD = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VPGATHERDQ = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VPGATHERQD = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, .VPGATHERQQ = { // mask operand (OP2) is zeroed as elements are gathered - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, }, // 8.14 FMA Encodings .VFMADD132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD132SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD213SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD231SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD132SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD213SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADD231SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB132SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB213SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB231SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB132SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB213SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUB231SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD132SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD213SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD231SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD132SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD213SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMADD231SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB132SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB213SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB231SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB132SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB213SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFNMSUB231SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMADDSUB231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD132PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD213PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD231PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD132PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD213PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFMSUBADD231PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTPH2PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VCVTPS2PH = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, }, // 8.15 AVX-512 Encodings .VMOVDQA32 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDQA64 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDQU8 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDQU16 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDQU32 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VMOVDQU64 = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPBLENDMB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPBLENDMW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPBLENDMD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPBLENDMQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VBLENDMPS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VBLENDMPD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPB = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPUB = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPW = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPUW = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPD = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPUD = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPQ = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCMPUQ = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTMB = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTMW = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTMD = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTMQ = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTNMB = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTNMW = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTNMD = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPTESTNMQ = { // result written to an opmask register (k1), not EFLAGS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPCOMPRESSD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPCOMPRESSQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VCOMPRESSPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VCOMPRESSPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPEXPANDD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPEXPANDQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VEXPANDPS = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VEXPANDPD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPCONFLICTD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPCONFLICTQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPLZCNTD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPLZCNTQ = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPERMI2B = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMI2W = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMI2D = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMI2Q = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMI2PS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMI2PD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2B = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2W = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2D = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2Q = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2PS = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMT2PD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPERMW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPMOVB2M = { // sign bits -> opmask register - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVW2M = { // sign bits -> opmask register - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVD2M = { // sign bits -> opmask register - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVQ2M = { // sign bits -> opmask register - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVM2B = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVM2W = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVM2D = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVM2Q = { - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .VPMOVQB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSQB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSQB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVQW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSQW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSQW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVQD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSQD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSQD = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVDB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSDB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSDB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSDW = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVWB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVSWB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPMOVUSWB = { - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VPROLD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPROLQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPROLVD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPROLVQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPRORD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPRORQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPRORVD = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPRORVQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSCATTERDD = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VPSCATTERDQ = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VPSCATTERQD = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VPSCATTERQQ = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VSCATTERDPS = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VSCATTERDPD = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VSCATTERQPS = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VSCATTERQPD = { // opmask k1 is consumed and cleared per element - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, }, .VPSRAVQ = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSRAVW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSLLVW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VPSRLVW = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .VRANGEPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRANGEPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRANGESS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRANGESD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VREDUCEPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VREDUCEPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VREDUCESS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VREDUCESD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRNDSCALEPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRNDSCALEPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRNDSCALESS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRNDSCALESD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRT14PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRT14PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRT14SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRSQRT14SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCP14PS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCP14PD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCP14SS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VRCP14SD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSCALEFPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSCALEFPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSCALEFSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VSCALEFSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETEXPPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETEXPPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETEXPSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETEXPSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETMANTPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETMANTPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETMANTSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VGETMANTSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFIXUPIMMPS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFIXUPIMMPD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFIXUPIMMSS = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFIXUPIMMSD = { // may set MXCSR exception/status bits - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, }, .VFPCLASSPS = { // class predicate written to an opmask register - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VFPCLASSPD = { // class predicate written to an opmask register - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VFPCLASSSS = { // class predicate written to an opmask register - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VFPCLASSSD = { // class predicate written to an opmask register - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, }, .VALIGNQ = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VALIGND = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VDBPSADBW = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPTERNLOGD = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPTERNLOGQ = { - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, }, .VPMULTISHIFTQB = { - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, }, .KADDW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KADDB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KADDQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KADDD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDNW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDNB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDNQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KANDND = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KMOVW = { // opmask <-> GPR/mem/opmask - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .KMOVB = { // opmask <-> GPR/mem/opmask - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .KMOVQ = { // opmask <-> GPR/mem/opmask - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .KMOVD = { // opmask <-> GPR/mem/opmask - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, }, .KNOTW = { // opmask register operation - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .KNOTB = { // opmask register operation - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .KNOTQ = { // opmask register operation - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .KNOTD = { // opmask register operation - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, }, .KORW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KORB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KORQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KORD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KORTESTW = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KORTESTB = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KORTESTQ = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KORTESTD = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KSHIFTLW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTLB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTLQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTLD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTRW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTRB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTRQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KSHIFTRD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KTESTW = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KTESTB = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KTESTQ = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KTESTD = { // sets ZF/CF from mask test - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .KUNPCKBW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KUNPCKWD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KUNPCKDQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXNORW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXNORB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXNORQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXNORD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXORW = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXORB = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXORQ = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, .KXORD = { // opmask register operation - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, }, // 8.16 x87 FPU Encodings @@ -4559,66 +4559,66 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ // 8.17 System Instruction Encodings .LGDT = { // privileged load - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .SGDT = { // stores descriptor/register to r/m (privileged for some) - {written={.OP0}, writes_mem=true}, - {written={.OP0}, writes_mem=true}, + {written={0}, writes_mem=true}, + {written={0}, writes_mem=true}, }, .LIDT = { // privileged load - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .SIDT = { // stores descriptor/register to r/m (privileged for some) - {written={.OP0}, writes_mem=true}, - {written={.OP0}, writes_mem=true}, + {written={0}, writes_mem=true}, + {written={0}, writes_mem=true}, }, .LLDT = { // privileged load - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .SLDT = { // stores descriptor/register to r/m (privileged for some) - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, }, .LTR = { // privileged load - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .STR = { // stores descriptor/register to r/m (privileged for some) - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, }, .LMSW = { // privileged load - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .SMSW = { // stores descriptor/register to r/m (privileged for some) - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, }, .CLTS = { // privileged; no GPR/EFLAGS clobber modeled {side_effects={.PRIVILEGED}}, }, .ARPL = { // legacy; adjusts RPL, sets ZF - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, }, .LAR = { // ZF=1 on success; OP0 undefined on failure - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, }, .LSL = { // ZF=1 on success; OP0 undefined on failure - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, }, .VERR = { // ZF=1 if segment is readable/writable - {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + {read={0}, flags_wr={.ZF}, reads_mem=true}, }, .VERW = { // ZF=1 if segment is readable/writable - {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + {read={0}, flags_wr={.ZF}, reads_mem=true}, }, .INVD = { // privileged; no GPR/EFLAGS clobber modeled {side_effects={.SERIALIZING, .PRIVILEGED}}, @@ -4627,11 +4627,11 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {side_effects={.SERIALIZING, .PRIVILEGED}}, }, .INVLPG = { // privileged; no GPR/EFLAGS clobber modeled - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, }, .INVPCID = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .RSM = { // privileged; no GPR/EFLAGS clobber modeled {side_effects={.SERIALIZING, .PRIVILEGED}}, @@ -4655,31 +4655,31 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {side_effects={.PRIVILEGED}}, }, .VMXON = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMCLEAR = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMPTRLD = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMPTRST = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMREAD = { // VMX status in ZF/CF - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMWRITE = { // VMX status in ZF/CF - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .VMFUNC = { // privileged; no GPR/EFLAGS clobber modeled {side_effects={.PRIVILEGED}}, }, .INVEPT = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, .INVVPID = { // VMX/INVx status reported in ZF/CF - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, }, // 8.18 Security and Memory Protection Encodings @@ -4699,16 +4699,16 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_rd={.RAX, .RCX, .RDX}}, }, .INCSSPD = { // advances SSP - {read={.OP0}, side_effects={.CET}}, + {read={0}, side_effects={.CET}}, }, .INCSSPQ = { // advances SSP - {read={.OP0}, side_effects={.CET}}, + {read={0}, side_effects={.CET}}, }, .RDSSPD = { // reads shadow-stack pointer into OP0 - {written={.OP0}, side_effects={.CET}}, + {written={0}, side_effects={.CET}}, }, .RDSSPQ = { // reads shadow-stack pointer into OP0 - {written={.OP0}, side_effects={.CET}}, + {written={0}, side_effects={.CET}}, }, .SAVEPREVSSP = { // CET shadow-stack management {side_effects={.CET}}, @@ -4717,16 +4717,16 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {side_effects={.CET}}, }, .WRSSD = { // writes to shadow stack - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, }, .WRSSQ = { // writes to shadow stack - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, }, .WRUSSD = { // writes to shadow stack - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, }, .WRUSSQ = { // writes to shadow stack - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, }, .SETSSBSY = { // CET shadow-stack management {side_effects={.CET}}, @@ -4781,58 +4781,58 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ // 8.20 Cache and Prefetch Encodings .PREFETCHT0 = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, .PREFETCHT1 = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, .PREFETCHT2 = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, .PREFETCHNTA = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, .PREFETCHW = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, .CLFLUSHOPT = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, }, .CLWB = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, }, .CLDEMOTE = { // cache hint/maintenance; no register or flag clobber - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, }, // 8.21 Atomic and Byte Swap Encodings .BSWAP = { - {written={.OP0}, read={.OP0}}, - {written={.OP0}, read={.OP0}}, + {written={0}, read={0}}, + {written={0}, read={0}}, }, .CMPXCHG = { // ZF set on match; on mismatch RAX <- dest - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, .CMPXCHG8B = { // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, }, .CMPXCHG16B = { // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, }, .XADD = { - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, }, // 8.22 Miscellaneous Encodings .BOUND = { // #BR if out of bounds - {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, - {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + {read={0, 1}, reads_mem=true, side_effects={.TRAP}}, + {read={0, 1}, reads_mem=true, side_effects={.TRAP}}, }, .ENTER = { // builds stack frame {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, @@ -4847,21 +4847,21 @@ CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, }, .MOVBE = { // byte-swapping load/store - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, }, .RDRAND = { // CF=1 if value valid; OF/SF/ZF/AF/PF cleared - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, .RDSEED = { // CF=1 if value valid; OF/SF/ZF/AF/PF cleared - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, }, } diff --git a/core/rexcode/isa/x86/tablegen/gen.odin b/core/rexcode/isa/x86/tablegen/gen.odin index 10225cd7d..54da4475d 100644 --- a/core/rexcode/isa/x86/tablegen/gen.odin +++ b/core/rexcode/isa/x86/tablegen/gen.odin @@ -23,6 +23,7 @@ package rexcode_x86_tablegen // before Stage B dumps it to raw bytes, so the blobs can never drift from a // well-typed table. +import "base:intrinsics" import "core:fmt" import "core:os" import "core:strings" @@ -177,7 +178,11 @@ write_clobber :: proc(sb: ^strings.Builder, c: lib.Clobber, max_name: int) { i := 0 for flag in flags { if i > 0 { strings.write_string(sb, ", ") } - fmt.sbprintf(sb, ".%s", flag) + when intrinsics.type_is_enum(type_of(flag)) { + fmt.sbprintf(sb, ".%s", flag) + } else { + fmt.sbprintf(sb, "%v", flag) + } i += 1 } strings.write_string(sb, "}") diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index 74eda1187..041487e87 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -3600,477 +3600,477 @@ ENCODE_FORMS := [2395]lib.Encoding{ @(rodata) CLOBBER_FORMS := [2395]lib.Clobber{ // .MOV - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .MOVABS - {written={.OP0}, read={.OP1}}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, // .MOVZX - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .MOVSX - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .MOVSXD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .XCHG - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP1}, read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, writes_mem=true, reads_mem=true}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, // .PUSH - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, // .POP - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, + {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, // .LEA - {written={.OP0}}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}}, + {written={0}}, + {written={0}}, // .ADD - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .ADC - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, // .SUB - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .SBB - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, // .MUL - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // .IMUL - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // .DIV - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .IDIV - {read={.OP0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .INC - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .DEC - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .NEG - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .CMP - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .AND - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .OR - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .XOR - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .NOT - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, writes_mem=true, reads_mem=true}, // .TEST - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, // .SHL - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .SHR - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .SAR - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, // .ROL - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, // .ROR - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, // .RCL - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, // .RCR - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, // .SHLD - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, // .SHRD - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1, .OP2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, // .BT - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .BTS - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .BTR - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .BTC - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .BSF - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, // .BSR - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, // .POPCNT - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .LZCNT - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .TZCNT - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .JMP - {read={.OP0}, side_effects={.CONTROL}}, - {read={.OP0}, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, side_effects={.CONTROL}}, + {read={0}, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, reads_mem=true, side_effects={.CONTROL}}, // .JA {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, @@ -4174,11 +4174,11 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .LOOPNE {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, // .CALL - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={.OP0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, + {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, // .RET {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, @@ -4189,7 +4189,7 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .IRETQ {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, // .INT - {read={.OP0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, + {read={0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // .INT3 {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, // .INTO @@ -4203,185 +4203,185 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .SYSEXIT {implicit_wr={.RSP}, implicit_rd={.RCX, .RDX}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, // .SETA - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, // .SETAE - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETB - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETBE - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, // .SETC - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETE - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, // .SETG - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, // .SETGE - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, // .SETL - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, // .SETLE - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, // .SETNA - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, // .SETNAE - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETNB - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETNBE - {written={.OP0}, flags_rd={.CF, .ZF}, writes_mem=true}, + {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, // .SETNC - {written={.OP0}, flags_rd={.CF}, writes_mem=true}, + {written={0}, flags_rd={.CF}, writes_mem=true}, // .SETNE - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, // .SETNG - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, // .SETNGE - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, // .SETNL - {written={.OP0}, flags_rd={.SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, // .SETNLE - {written={.OP0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, + {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, // .SETNO - {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + {written={0}, flags_rd={.OF}, writes_mem=true}, // .SETNP - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, // .SETNS - {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + {written={0}, flags_rd={.SF}, writes_mem=true}, // .SETNZ - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, // .SETO - {written={.OP0}, flags_rd={.OF}, writes_mem=true}, + {written={0}, flags_rd={.OF}, writes_mem=true}, // .SETP - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, // .SETPE - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, // .SETPO - {written={.OP0}, flags_rd={.PF}, writes_mem=true}, + {written={0}, flags_rd={.PF}, writes_mem=true}, // .SETS - {written={.OP0}, flags_rd={.SF}, writes_mem=true}, + {written={0}, flags_rd={.SF}, writes_mem=true}, // .SETZ - {written={.OP0}, flags_rd={.ZF}, writes_mem=true}, + {written={0}, flags_rd={.ZF}, writes_mem=true}, // .CMOVA - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, // .CMOVAE - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVB - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVBE - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, // .CMOVC - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVE - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, // .CMOVG - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // .CMOVGE - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, // .CMOVL - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, // .CMOVLE - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // .CMOVNA - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, // .CMOVNAE - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVNB - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVNBE - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, // .CMOVNC - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, // .CMOVNE - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, // .CMOVNG - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // .CMOVNGE - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, // .CMOVNL - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, // .CMOVNLE - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, // .CMOVNO - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, // .CMOVNP - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, // .CMOVNS - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, // .CMOVNZ - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, // .CMOVO - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, // .CMOVP - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, // .CMOVPE - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, // .CMOVPO - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, // .CMOVS - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, // .CMOVZ - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, // .MOVS {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // .MOVSB @@ -4390,8 +4390,8 @@ CLOBBER_FORMS := [2395]lib.Clobber{ {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // .MOVSD {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVSQ {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, // .CMPS @@ -4402,7 +4402,7 @@ CLOBBER_FORMS := [2395]lib.Clobber{ {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // .CMPSD {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .CMPSQ {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, // .SCAS @@ -4507,398 +4507,398 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .CQO {implicit_wr={.RDX}, implicit_rd={.RAX}}, // .ANDN - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, // .BEXTR - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, // .BLSI - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, // .BLSMSK - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, // .BLSR - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, // .BZHI - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, + {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, // .PDEP - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PEXT - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .RORX - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SARX - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .SHLX - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .SHRX - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .MULX - {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP2}, implicit_rd={.RDX}, reads_mem=true}, + {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}, + {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}, // .ADCX - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, // .ADOX - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, + {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, // .MOVAPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVUPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVAPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVUPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVSS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVDQA - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVDQU - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVQ - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .MOVD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVLPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVHPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVLPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVHPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVLHPS - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .MOVHLPS - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .MOVMSKPS - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .MOVMSKPD - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .MOVNTPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVNTPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVNTDQ - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .MOVNTDQA - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ADDPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .ADDPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .ADDSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .ADDSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SUBPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SUBPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SUBSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SUBSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MULPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MULPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MULSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MULSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .DIVPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .DIVPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .DIVSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .DIVSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SQRTPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SQRTPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SQRTSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .SQRTSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .RCPPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .RCPSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .RSQRTPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .RSQRTSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MAXPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MAXPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MAXSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MAXSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MINPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MINPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MINSS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MINSD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .ANDPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ANDPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ANDNPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ANDNPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ORPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .ORPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .XORPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .XORPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .CMPPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .CMPPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .CMPSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .COMISS - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .COMISD - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .UCOMISS - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .UCOMISD - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .SHUFPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .SHUFPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .UNPCKLPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .UNPCKHPS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .UNPCKLPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .UNPCKHPD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .CVTPS2PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTPD2PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSS2SD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSD2SS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTPS2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTPD2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTDQ2PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTDQ2PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSS2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSD2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSI2SS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTSI2SD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTTPS2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTTPD2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTTSS2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .CVTTSD2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .PADDB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDUSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PADDUSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBUSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSUBUSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULLW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULHW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULHUW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULUDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMADDWD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PAND - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PANDN - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .POR - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PXOR - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSLLW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSLLD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSLLQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSRLW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSRLD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSRLQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSRAW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PSRAD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .PCMPEQB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCMPEQW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCMPEQD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCMPGTB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCMPGTW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCMPGTD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PACKSSWB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PACKSSDW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PACKUSWB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKLBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKLWD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKLDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKLQDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKHBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKHWD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKHDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PUNPCKHQDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSHUFD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PSHUFHW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PSHUFLW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PSHUFW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PEXTRW - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .PINSRW - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, // .PMOVMSKB - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .PAVGB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PAVGW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMAXUB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMAXSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINUB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSADBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .MASKMOVDQU - {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, // .LFENCE {side_effects={.FENCE, .SERIALIZING}}, // .SFENCE @@ -4908,159 +4908,159 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .PAUSE {side_effects={.HINT}}, // .CLFLUSH - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, // .ADDSUBPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .ADDSUBPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .HADDPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .HADDPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .HSUBPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .HSUBPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .MOVDDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .MOVSLDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .MOVSHDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .LDDQU - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSHUFB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHADDW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHADDD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHADDSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHSUBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHSUBD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PHSUBSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMADDUBSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULHRSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSIGNB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSIGNW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PSIGND - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PABSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PABSW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PABSD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PALIGNR - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .BLENDPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .BLENDPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .BLENDVPS - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, // .BLENDVPD - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, // .PBLENDW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PBLENDVB - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, // .DPPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .DPPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .EXTRACTPS - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .INSERTPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .MPSADBW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PACKUSDW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PEXTRB - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .PEXTRD - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .PEXTRQ - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .PHMINPOSUW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PINSRB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PINSRD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PINSRQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .PMAXSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMAXSD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMAXUW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMAXUD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINSB - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINSD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINUW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMINUD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXBD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXBQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXWD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXWQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVSXDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXBW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXBD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXBQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXWD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXWQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMOVZXDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PMULLD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PTEST - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .ROUNDPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .ROUNDPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .ROUNDSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .ROUNDSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .PCMPEQQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .CRC32 - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, + {written={0}, read={0, 1}, reads_mem=true}, // .PCMPESTRI {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .PCMPESTRM @@ -5070,316 +5070,316 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .PCMPISTRM {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .PCMPGTQ - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .PCLMULQDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .AESDEC - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .AESDECLAST - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .AESENC - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .AESENCLAST - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .AESIMC - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .AESKEYGENASSIST - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .SHA1MSG1 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SHA1MSG2 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SHA1NEXTE - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SHA1RNDS4 - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .SHA256MSG1 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SHA256MSG2 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .SHA256RNDS2 - {written={.OP0}, read={.OP1}, implicit_rd={.XMM0}, reads_mem=true}, + {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, // .VADDPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VADDPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VADDSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VADDSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSUBPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSUBPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSUBSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSUBSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMULPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMULPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMULSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMULSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VDIVPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VDIVPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VDIVSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VDIVSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSQRTPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSQRTPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSQRTSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSQRTSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCPPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCPSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRTPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRTSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMAXPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMAXPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMAXSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMAXSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMINPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMINPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMINSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VMINSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VANDPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VANDPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VANDNPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VANDNPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VORPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VORPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VXORPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VXORPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VCMPPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCMPPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCMPSS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCMPSD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCOMISS - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .VCOMISD - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .VUCOMISS - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .VUCOMISD - {read={.OP0, .OP1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, // .VSHUFPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VSHUFPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VUNPCKLPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VUNPCKHPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VUNPCKLPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VUNPCKHPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VBLENDPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VBLENDPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VBLENDVPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VBLENDVPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VDPPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VDPPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VROUNDPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VROUNDPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VROUNDSS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VROUNDSD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VEXTRACTPS - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .VINSERTPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VMOVAPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVUPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVAPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVUPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVSS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}}, // .VMOVSD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}}, // .VMOVDQA - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVDQU - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVQ - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VMOVD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVLPS - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVHPS - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVLPD - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVHPD - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVLHPS - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .VMOVHLPS - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .VMOVMSKPS - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VMOVMSKPD - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VMOVNTPS - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVNTPD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVNTDQ - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .VMOVNTDQA - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VADDSUBPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VADDSUBPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VHADDPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VHADDPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VHSUBPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VHSUBPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VLDDQU - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVSLDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVSHDUP - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPCMPESTRI {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .VPCMPESTRM @@ -5389,1340 +5389,1340 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .VPCMPISTRM {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // .VPBROADCASTB - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPBROADCASTW - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPBROADCASTD - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPBROADCASTQ - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VCVTPS2PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTPD2PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSS2SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSD2SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTPS2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTPD2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTDQ2PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTDQ2PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSS2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSD2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSI2SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTSI2SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTTPS2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTTPD2DQ - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTTSS2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTTSD2SI - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VPADDB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPADDW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPADDD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPADDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSUBB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSUBW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSUBD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSUBQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULLW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULHW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULHUW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULUDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMADDWD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPAND - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPANDN - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPOR - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPXOR - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSLLW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSLLD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSLLQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSRLW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSRLD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSRLQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSRAW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPSRAD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}}, // .VPCMPEQB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPEQW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPEQD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPEQQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPGTB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPGTW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPGTD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPGTQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPACKSSWB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPACKSSDW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPACKUSWB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPACKUSDW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKLBW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKLWD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKLDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKLQDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKHBW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKHWD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKHDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPUNPCKHQDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSHUFD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSHUFHW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSHUFLW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPEXTRB - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .VPEXTRW - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, writes_mem=true}, // .VPEXTRD - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .VPEXTRQ - {written={.OP0}, read={.OP1}, writes_mem=true}, + {written={0}, read={1}, writes_mem=true}, // .VPINSRB - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPINSRW - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPINSRD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPINSRQ - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPMOVMSKB - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPTEST - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .VPSHUFB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHADDW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHADDD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHADDSW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHSUBW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHSUBD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPHSUBSW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMADDUBSW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULHRSW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSIGNB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSIGNW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSIGND - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPABSB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPABSW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPABSD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPALIGNR - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPBLENDW - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPBLENDVB - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VMPSADBW - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPHMINPOSUW - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMAXSB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMAXSD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMAXUW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMAXUD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMINSB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMINSD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMINUW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMINUD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMOVSXBW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSXBD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSXBQ - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSXWD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSXWQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSXDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXBW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXBD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXBQ - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXWD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXWQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVZXDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMULDQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMULLD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VMASKMOVDQU - {read={.OP0, .OP1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, + {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, // .VPCLMULQDQ - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VAESDEC - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VAESDECLAST - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VAESENC - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VAESENCLAST - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VAESIMC - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VAESKEYGENASSIST - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VBROADCASTSS - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VBROADCASTSD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}}, // .VBROADCASTF128 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VEXTRACTF128 - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VINSERTF128 - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPERM2F128 - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VMASKMOVPS - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VMASKMOVPD - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VTESTPS - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .VTESTPD - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={.OP0, .OP1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, + {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, // .VZEROALL {implicit_wr={.VECTOR}}, // .VZEROUPPER {implicit_wr={.VECTOR}}, // .VBROADCASTI128 - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VEXTRACTI128 - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VINSERTI128 - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPERM2I128 - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPERMD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPBLENDD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPSLLVD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSLLVQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSRLVD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSRLVQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSRAVD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMASKMOVD - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VPMASKMOVQ - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, // .VGATHERDPS - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VGATHERDPD - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VGATHERQPS - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VGATHERQPD - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VPGATHERDD - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VPGATHERDQ - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VPGATHERQD - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VPGATHERQQ - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, - {written={.OP0, .OP2}, read={.OP0, .OP1, .OP2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, + {written={0, 2}, read={0, 1, 2}, reads_mem=true}, // .VFMADD132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD132SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD213SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD231SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD132SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD213SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADD231SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB132SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB213SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB231SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB132SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB213SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUB231SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD132SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD213SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD231SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD132SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD213SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMADD231SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB132SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB213SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB231SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB132SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB213SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFNMSUB231SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMADDSUB231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD132PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD213PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD231PS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD132PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD213PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFMSUBADD231PD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTPH2PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VCVTPS2PH - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, // .VMOVDQA32 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDQA64 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDQU8 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDQU16 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDQU32 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VMOVDQU64 - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPBLENDMB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPBLENDMW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPBLENDMD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPBLENDMQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VBLENDMPS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VBLENDMPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPUB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPUW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPUD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCMPUQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTMB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTMW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTMD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTMQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTNMB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTNMW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTNMD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPTESTNMQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPCOMPRESSD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPCOMPRESSQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VCOMPRESSPS - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VCOMPRESSPD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPEXPANDD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPEXPANDQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VEXPANDPS - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VEXPANDPD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPCONFLICTD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPCONFLICTQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPLZCNTD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPLZCNTQ - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPERMI2B - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMI2W - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMI2D - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMI2Q - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMI2PS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMI2PD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2B - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2W - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2D - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2Q - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2PS - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMT2PD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPERMW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPMOVB2M - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVW2M - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVD2M - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVQ2M - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVM2B - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVM2W - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVM2D - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVM2Q - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .VPMOVQB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSQB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSQB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVQW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSQW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSQW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVQD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSQD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSQD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVDB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSDB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSDB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVDW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSDW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSDW - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVWB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVSWB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPMOVUSWB - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VPROLD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPROLQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPROLVD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPROLVQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPRORD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPRORQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPRORVD - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPRORVQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSCATTERDD - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VPSCATTERDQ - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VPSCATTERQD - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VPSCATTERQQ - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VSCATTERDPS - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VSCATTERDPD - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VSCATTERQPS - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VSCATTERQPD - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, - {read={.OP0, .OP1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, + {read={0, 1}, writes_mem=true}, // .VPSRAVQ - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSRAVW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSLLVW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VPSRLVW - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .VRANGEPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRANGEPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRANGESS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRANGESD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VREDUCEPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VREDUCEPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VREDUCESS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VREDUCESD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRNDSCALEPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRNDSCALEPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRNDSCALESS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRNDSCALESD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRT14PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRT14PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRT14SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRSQRT14SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCP14PS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCP14PD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCP14SS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VRCP14SD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSCALEFPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSCALEFPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSCALEFSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VSCALEFSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETEXPPS - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETEXPPD - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETEXPSS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETEXPSD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETMANTPS - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETMANTPD - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETMANTSS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VGETMANTSD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFIXUPIMMPS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFIXUPIMMPD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFIXUPIMMSS - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFIXUPIMMSD - {written={.OP0}, read={.OP1, .OP2, .OP3}, implicit_wr={.MXCSR}, reads_mem=true}, + {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, // .VFPCLASSPS - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VFPCLASSPD - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VFPCLASSSS - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VFPCLASSSD - {written={.OP0}, read={.OP1}, reads_mem=true}, + {written={0}, read={1}, reads_mem=true}, // .VALIGNQ - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VALIGND - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VDBPSADBW - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPTERNLOGD - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPTERNLOGQ - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2, .OP3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, + {written={0}, read={1, 2, 3}, reads_mem=true}, // .VPMULTISHIFTQB - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, - {written={.OP0}, read={.OP1, .OP2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, + {written={0}, read={1, 2}, reads_mem=true}, // .KADDW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KADDB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KADDQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KADDD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDNW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDNB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDNQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KANDND - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KMOVW - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .KMOVB - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .KMOVQ - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .KMOVD - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}}, - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}}, + {written={0}, read={1}}, // .KNOTW - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .KNOTB - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .KNOTQ - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .KNOTD - {written={.OP0}, read={.OP1}}, + {written={0}, read={1}}, // .KORW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KORB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KORQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KORD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KORTESTW - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KORTESTB - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KORTESTQ - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KORTESTD - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KSHIFTLW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTLB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTLQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTLD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTRW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTRB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTRQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KSHIFTRD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KTESTW - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KTESTB - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KTESTQ - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KTESTD - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .KUNPCKBW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KUNPCKWD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KUNPCKDQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXNORW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXNORB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXNORQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXNORD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXORW - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXORB - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXORQ - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .KXORD - {written={.OP0}, read={.OP1, .OP2}}, + {written={0}, read={1, 2}}, // .FADD {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, @@ -6978,60 +6978,60 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .FXRSTOR64 {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, // .LGDT - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .SGDT - {written={.OP0}, writes_mem=true}, - {written={.OP0}, writes_mem=true}, + {written={0}, writes_mem=true}, + {written={0}, writes_mem=true}, // .LIDT - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .SIDT - {written={.OP0}, writes_mem=true}, - {written={.OP0}, writes_mem=true}, + {written={0}, writes_mem=true}, + {written={0}, writes_mem=true}, // .LLDT - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .SLDT - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, // .LTR - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .STR - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, // .LMSW - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .SMSW - {written={.OP0}, writes_mem=true}, - {written={.OP0}}, - {written={.OP0}}, + {written={0}, writes_mem=true}, + {written={0}}, + {written={0}}, // .CLTS {side_effects={.PRIVILEGED}}, // .ARPL - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // .LAR - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, // .LSL - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, - {written={.OP0}, read={.OP1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, + {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, // .VERR - {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + {read={0}, flags_wr={.ZF}, reads_mem=true}, // .VERW - {read={.OP0}, flags_wr={.ZF}, reads_mem=true}, + {read={0}, flags_wr={.ZF}, reads_mem=true}, // .INVD {side_effects={.SERIALIZING, .PRIVILEGED}}, // .WBINVD {side_effects={.SERIALIZING, .PRIVILEGED}}, // .INVLPG - {read={.OP0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, + {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, // .INVPCID - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .RSM {side_effects={.SERIALIZING, .PRIVILEGED}}, // .RDMSR @@ -7047,23 +7047,23 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .VMXOFF {side_effects={.PRIVILEGED}}, // .VMXON - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMCLEAR - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMPTRLD - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMPTRST - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMREAD - {written={.OP0}, read={.OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, + {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMWRITE - {read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .VMFUNC {side_effects={.PRIVILEGED}}, // .INVEPT - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .INVVPID - {read={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, + {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, // .ENCLS {side_effects={.PRIVILEGED}}, // .ENCLU @@ -7075,25 +7075,25 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .WRPKRU {implicit_rd={.RAX, .RCX, .RDX}}, // .INCSSPD - {read={.OP0}, side_effects={.CET}}, + {read={0}, side_effects={.CET}}, // .INCSSPQ - {read={.OP0}, side_effects={.CET}}, + {read={0}, side_effects={.CET}}, // .RDSSPD - {written={.OP0}, side_effects={.CET}}, + {written={0}, side_effects={.CET}}, // .RDSSPQ - {written={.OP0}, side_effects={.CET}}, + {written={0}, side_effects={.CET}}, // .SAVEPREVSSP {side_effects={.CET}}, // .RSTORSSP {side_effects={.CET}}, // .WRSSD - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, // .WRSSQ - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, // .WRUSSD - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, // .WRUSSQ - {read={.OP0, .OP1}, writes_mem=true, side_effects={.CET}}, + {read={0, 1}, writes_mem=true, side_effects={.CET}}, // .SETSSBSY {side_effects={.CET}}, // .CLRSSBSY @@ -7127,41 +7127,41 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .XRSTORS64 {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, // .PREFETCHT0 - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .PREFETCHT1 - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .PREFETCHT2 - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .PREFETCHNTA - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .PREFETCHW - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .CLFLUSHOPT - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, // .CLWB - {read={.OP0}, reads_mem=true, side_effects={.CACHE}}, + {read={0}, reads_mem=true, side_effects={.CACHE}}, // .CLDEMOTE - {read={.OP0}, reads_mem=true, side_effects={.HINT}}, + {read={0}, reads_mem=true, side_effects={.HINT}}, // .BSWAP - {written={.OP0}, read={.OP0}}, - {written={.OP0}, read={.OP0}}, + {written={0}, read={0}}, + {written={0}, read={0}}, // .CMPXCHG - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP0, .OP1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .CMPXCHG8B - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // .CMPXCHG16B - {read={.OP0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, + {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, // .XADD - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={.OP0, .OP1}, read={.OP0, .OP1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, + {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, // .BOUND - {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, - {read={.OP0, .OP1}, reads_mem=true, side_effects={.TRAP}}, + {read={0, 1}, reads_mem=true, side_effects={.TRAP}}, + {read={0, 1}, reads_mem=true, side_effects={.TRAP}}, // .ENTER {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, // .LEAVE @@ -7171,20 +7171,20 @@ CLOBBER_FORMS := [2395]lib.Clobber{ // .XLATB {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, // .MOVBE - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, - {written={.OP0}, read={.OP1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, + {written={0}, read={1}, writes_mem=true, reads_mem=true}, // .RDRAND - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, // .RDSEED - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={.OP0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, + {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, } @(rodata)