From 421262e84ea73b779d1cd3c830f4b585dbc0c5ba Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Sat, 29 Aug 2026 00:37:11 -0400 Subject: [PATCH] rexcode/arm32: the NEON by-scalar forms dropped the lane they multiply by VMLA, VMUL, VMLAL, VQDMULL, VSDOT, VCMLA and the rest of the by-scalar family take one lane of a low D register as the multiplier -- `d0[2]`, not `d0`. Every one of them printed the bare register, which is not only missing information but assembles to a different instruction: the by-vector form. The forms already declared the operand type as DPR_ELEM; what they lacked was an encoding that knows the register number and the lane number share a single four-bit field. How they share it depends on the element size, and the two splits are different enough to be separate encodings: 16-bit takes Vm from bits 2:0, so D0..D7, and the lane from M:bit3, giving four lanes; 32-bit takes Vm from bits 3:0, so D0..D15, and the lane from M alone, giving two. The dot-product and complex forms share the 32-bit split despite being 8- and 16-bit operations. Those reaches are now checked when selecting a form, so `d8[0]` on a 16-bit form matches nothing rather than quietly encoding as `d0[0]`, and a lane-less operand no longer matches a by-scalar form at all. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_018UmHLRF11EoWwNWCJ7JGaA --- core/rexcode/isa/arm32/decoder.odin | 5 + core/rexcode/isa/arm32/encoder.odin | 16 ++- core/rexcode/isa/arm32/encoding_types.odin | 7 ++ .../isa/arm32/tablegen/encoding_table.odin | 98 +++++++++--------- .../tablegen/generated/decode_tables.odin | 98 +++++++++--------- .../tablegen/generated/encode_tables.odin | 98 +++++++++--------- .../isa/arm32/tables/arm32.encode_forms.bin | Bin 37927 -> 37927 bytes .../isa/arm32/tables/arm32.entries.bin | Bin 37927 -> 37927 bytes 8 files changed, 174 insertions(+), 148 deletions(-) diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index c7d453b38..594021caf 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -463,6 +463,11 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op op := op_dpr_lane(Register(REG_DPR | u16(n)), u8((word >> shift) & mask)) op.list = {count = count, stride = 1} return op + case .NEON_VM_SCALAR_16: + return op_dpr_lane(Register(REG_DPR | u16(word & 0x7)), + u8(((word >> 5) & 1) << 1 | ((word >> 3) & 1))) + case .NEON_VM_SCALAR_32: + return op_dpr_lane(Register(REG_DPR | u16(word & 0xF)), u8((word >> 5) & 1)) case .NEON_VN_TABLE_1, .NEON_VN_TABLE_2, .NEON_VN_TABLE_3, .NEON_VN_TABLE_4: n := ((word >> 7) & 1) << 4 | ((word >> 16) & 0xF) return op_reg_run(Register(REG_DPR | u16(n)), table_run_length(enc)) diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index 9b675919e..036d97567 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -286,7 +286,15 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op case .SPR: return op.kind == .REGISTER && is_spr(op.reg) case .DPR: return op.kind == .REGISTER && is_dpr(op.reg) case .QPR: return op.kind == .REGISTER && is_qpr(op.reg) - case .DPR_ELEM: return op.kind == .REGISTER && is_dpr(op.reg) + case .DPR_ELEM: + if op.kind != .REGISTER || !is_dpr(op.reg) { return false } + // A by-scalar multiplier names a lane, and how far the register and + // lane numbers reach depends on how they share the field. + #partial switch enc { + case .NEON_VM_SCALAR_16: return op.has_lane && reg_hw(op.reg) < 8 && op.lane < 4 + case .NEON_VM_SCALAR_32: return op.has_lane && reg_hw(op.reg) < 16 && op.lane < 2 + } + return true case .QPR_ELEM: return op.kind == .REGISTER && is_qpr(op.reg) case .SPR_ELEM: return op.kind == .REGISTER && is_spr(op.reg) case .SPR_LIST: @@ -518,6 +526,12 @@ pack_operand_inline :: #force_inline proc( n := u32(reg_hw(op.reg)) & 0x1F shift, mask, _ := neon_lane_shape(enc) return ((n >> 4) & 1) << 22 | (n & 0xF) << 12 | (u32(op.lane) & mask) << shift + case .NEON_VM_SCALAR_16: + n := u32(reg_hw(op.reg)) & 0x7 + idx := u32(op.lane) & 0x3 + return n | ((idx >> 1) & 1) << 5 | (idx & 1) << 3 + case .NEON_VM_SCALAR_32: + return (u32(reg_hw(op.reg)) & 0xF) | (u32(op.lane) & 1) << 5 case .NEON_VN_TABLE_1, .NEON_VN_TABLE_2, .NEON_VN_TABLE_3, .NEON_VN_TABLE_4: // The run length is already a fixed bit of the form; only Vn is ours. n := u32(reg_hw(op.reg)) & 0x1F diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index 4ac261bbd..4d423bc8d 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -336,6 +336,13 @@ Operand_Encoding :: enum u8 { // encodes -- so the length rides in the encoding, the way the NEON // structure-list lengths already do, and the encoder emits only Vn. NEON_VN_TABLE_1, NEON_VN_TABLE_2, NEON_VN_TABLE_3, NEON_VN_TABLE_4, + + // NEON "by scalar": the multiplier is one lane of a low D register, and + // the register number and the lane number share one four-bit field. How + // they share it depends on the element size -- 16-bit takes Vm from bits + // 2:0, so D0..D7, and the lane from M:bit3; 32-bit takes Vm from bits + // 3:0, so D0..D15, and the lane from M alone. + NEON_VM_SCALAR_16, NEON_VM_SCALAR_32, // NEON structure load/store lists (VLD1-4 / VST1-4). Unlike VLDM's list, // the register count is part of the form's type field at bits 11:8, so the // encoding writes only Vd; how many registers -- and whether the run steps diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index 562003868..5266b6b11 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -1736,11 +1736,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VMUL MVE scalar: per LLVM 0xEE05_3E63 -> base 0xEE011E60 {.VMUL, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, // Integer D-form .I16/.I32 - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, // Integer Q-form .I16/.I32 (bit 24 = 1) - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_16, .NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMUL, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VMLA / VMLS (integer + F32) ---- .VMLA = { @@ -1760,10 +1760,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLA, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, // MVE VMLA Qda, Qn, Rm (scalar) {.VMLA, {.QPR, .QPR, .GPR, .NONE}, {.VD_Q, .VN_Q, .RM_T32, .NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.I8, .NONE}}, - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_16, .NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLA, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, .VMLS = { {.VMLS, {.SPR, .SPR, .SPR, .NONE}, {.VD_S, .VN_S, .VM_S, .NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32, .NONE}}, @@ -1780,10 +1780,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // NEON F32 (bit 21 = 1 distinguishes FMLS from FMLA) {.VMLS, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, {.VMLS, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.F32, .NONE}}, - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, - {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_16, .NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VMLS, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, }, // ---- VAND / VBIC / VORR / VORN / VEOR (bitwise, no size variants) ---- .VAND = { @@ -2226,8 +2226,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VDUP, {.DPR, .GPR, .NONE, .NONE}, {.VD_D, .RT_A32, .NONE, .NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_A32, .NONE, .NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8, .NONE}}, // VDUP from vector lane (.D form): 1111 0011 1011 imm4 Vd 1100 0 Q M 0 Vm - {.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .VM_D, .NONE, .NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, - {.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .VM_D, .NONE, .NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, + {.VDUP, {.DPR, .DPR_ELEM, .NONE, .NONE}, {.VD_D, .NEON_VM_SCALAR_32, .NONE, .NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, + {.VDUP, {.QPR, .DPR_ELEM, .NONE, .NONE}, {.VD_Q, .NEON_VM_SCALAR_32, .NONE, .NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {cond_in_28=false}, {}}, // MVE VDUP Qd, Rt {.VDUP, {.QPR, .GPR, .NONE, .NONE}, {.VD_Q, .RT_T32, .NONE, .NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {.SZ32, .NONE}}, }, @@ -2394,11 +2394,11 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // polynomial: U=0, op=10 {.VMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.P8, .NONE}}, // signed .S16/.S32 - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, // unsigned .U16/.U32 (top byte 0xF3) - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, - {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, // VMLAL / VMLSL (widening multiply-accumulate) // VMLAL: signed F2800800 / unsigned F3800800; op=1000 (no minus); minus bit at 21 @@ -2409,10 +2409,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, {.VMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, - {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, .VMLSL = { // VMLSL: op=1010 (bit 9 = 1) @@ -2422,10 +2422,10 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U8, .NONE}}, {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, {.VMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, - {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U16, .NONE}}, + {.VMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.U32, .NONE}}, }, // ---- VQDMULH / VQRDMULH (saturating doubling multiply, high half) ---- @@ -2459,42 +2459,42 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VQRDMLAH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQRDMLAH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_16, .NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLAH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, .VQRDMLSH = { {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQRDMLSH, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQRDMLSH, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_16, .NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQRDMLSH, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // VQDMULL: 1111 0010 1 D size Vn Vd 1101 N 0 M 0 Vm .VQDMULL = { {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQDMULL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMULL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // VQDMLAL / VQDMLSL (saturating doubling multiply-accumulate long) .VQDMLAL = { // signed: 1111 0010 1 D size Vn Vd 1001 N 0 M 0 Vm {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQDMLAL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLAL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, .VQDMLSL = { // signed: 1111 0010 1 D size Vn Vd 1011 N 0 M 0 Vm {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, {.VQDMLSL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, - {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, - {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, + {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_16, .NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S16, .NONE}}, + {.VQDMLSL, {.QPR, .DPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {.S32, .NONE}}, }, // ---- VMOVL / VMOVN / VQMOVN / VQMOVUN (widening/narrowing moves) ---- @@ -2725,8 +2725,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VSDOT.S8 D: 0xFC200D00 {.VSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, {.VSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, // VUDOT (unsigned): bit 4 = 1 distinguishes from VSDOT (bit 4 = 0). // vudot.u8 d0,d1,d2 = 0xFC21_0D12 -> base 0xFC200D10 @@ -2734,8 +2734,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VUDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, {.VUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, // vudot.u8 d0,d1,d2[0] = 0xFE21_0D12 -> base 0xFE200D10 (bit 4 = 1 for U) - {.VUDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, - {.VUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VUDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, // FEAT_FCMA (ARMv8.3): VCMLA / VCADD (complex multiply-add + add) @@ -2745,8 +2745,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // Mask 0xFC800F10 leaves bits 24:23 variable for rotation operand {.VCMLA, {.DPR, .DPR, .DPR, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, - {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.DPR, .DPR, .DPR_ELEM, .IMM}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, + {.VCMLA, {.QPR, .QPR, .DPR_ELEM, .IMM}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {cond_in_28=false}, {.F16, .NONE}}, {.VCMLA, {.QPR, .QPR, .QPR, .IMM}, {.VD_Q, .VN_Q, .VM_Q, .MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true, cond_in_28=false}, {.F16, .NONE}}, }, .VCADD = { @@ -2797,13 +2797,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // vsudot.u8 q0,q1,d2[0] = 0xFE82_0D52 -> base 0xFE800D50 (lane only) .VSUDOT = { {.VSUDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {}}, - {.VSUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.U8, .NONE}}, + {.VSUDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.U8, .NONE}}, }, .VUSDOT = { {.VUSDOT, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, {.VUSDOT, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VUSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, - {.VUSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .VM_D, .NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VUSDOT, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR_32, .NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, + {.VUSDOT, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR_32, .NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {cond_in_28=false}, {.S8, .NONE}}, }, // ========================================================================= diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index cf783d63c..986c3ebe8 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -431,25 +431,25 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900200, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900500, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900700, 0xFFB01F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .ADD, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00100, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2A00300, 0xFFB11F50, .NEON, .A32, {}, {.S32,.NONE} }, @@ -458,25 +458,25 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00200, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00500, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00700, 0xFFB01F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .ADC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02A00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VEXT, {.QPR,.QPR,.QPR,.IMM4}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2B00040, 0xFFB00050, .NEON, .A32, {}, {.SZ64,.NONE} }, { .VEXT, {.DPR,.DPR,.DPR,.IMM4}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2B00000, 0xFFB00010, .NEON, .A32, {}, {.SZ32,.NONE} }, @@ -649,17 +649,17 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900200, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900500, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900700, 0xFFB01F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00100, 0xFFB11F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00300, 0xFFB11F50, .NEON, .A32, {}, {.U32,.NONE} }, @@ -670,17 +670,17 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00200, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00500, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00700, 0xFFB01F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, @@ -813,8 +813,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -1050,8 +1050,8 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, - { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VSEL, {.DPR,.DPR,.DPR,.COND}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000B00, 0xFF800F50, .V8, .A32, {}, {.F64,.NONE} }, { .VSEL, {.SPR,.SPR,.SPR,.COND}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {}, {.F32,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, @@ -1072,10 +1072,10 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VNMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .MRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {}, {.NONE,.NONE} }, { .MRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, - { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, - { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, - { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, + { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, + { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, + { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, + { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -1088,13 +1088,13 @@ DECODE_ENTRIES := [1649]lib.Decode_Entry{ { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, - { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, - { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, + { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, + { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, - { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index f7b48caaa..b6f98c6fc 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -935,10 +935,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000950, 0xEF810F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFF000D50, 0xFFA10F51, .MVE_FP, .T32, {thumb32=true}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE011E60, 0xEF811FF0, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VDIV { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VDIV, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E800B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -956,10 +956,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLA, {.QPR,.QPR,.GPR,.NONE}, {.VD_Q,.VN_Q,.RM_T32,.NONE}, 0xEE010E40, 0xEF811F51, .MVE_INT, .T32, {thumb32=true}, {.I8,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VMLS { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -972,10 +972,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200940, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMLS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, // .VNMUL { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, @@ -1274,10 +1274,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900A40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VMLAL { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1285,10 +1285,10 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800800, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VMLSL { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1296,25 +1296,25 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3800A00, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, // .VQDMULL { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMLAL { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900900, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMLSL { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900B00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900740, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, // .VQDMULH { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100B00, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, @@ -1338,19 +1338,19 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {}, {.S32,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B50, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B50, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, // .VQRDMLSH { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100C10, 0xFFB00F10, .V8, .A32, {}, {.S16,.NONE} }, { .VQRDMLSH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200C10, 0xFFB00F10, .V8, .A32, {}, {.S32,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100C50, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200C50, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, - { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, + { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, // .VABA { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000710, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VABA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100710, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -1776,8 +1776,8 @@ ENCODE_FORMS := [1649]lib.Encoding{ // .VDUP { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VD_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, - { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, + { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VD_Q,.RT_T32,.NONE,.NONE}, 0xEE800B10, 0xFF900F5F, .MVE_INT, .T32, {thumb32=true}, {.SZ32,.NONE} }, // .VSWP { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, @@ -1870,13 +1870,13 @@ ENCODE_FORMS := [1649]lib.Encoding{ // .VSDOT { .VSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, { .VSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, - { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, - { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, + { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, + { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, // .VUDOT { .VUDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, { .VUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, - { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, - { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, + { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, + { .VUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D50, 0xFFB00F50, .DOT, .A32, {}, {.U8,.NONE} }, // .VDOT { .VDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC000D00, 0xFFB00F10, .BF16, .A32, {}, {.BF16,.NONE} }, { .VDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC000D40, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, @@ -1891,8 +1891,8 @@ ENCODE_FORMS := [1649]lib.Encoding{ // .VCMLA { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.DPR,.DPR,.DPR_ELEM,.IMM}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE000800, 0xFFB00F10, .FCMA, .A32, {}, {.F16,.NONE} }, + { .VCMLA, {.QPR,.QPR,.DPR_ELEM,.IMM}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE000840, 0xFFB00F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.MVE_ROT_CMLA}, 0xFC200840, 0xFE611FF1, .MVE_FP, .T32, {thumb32=true}, {.F16,.NONE} }, // .VCADD { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, @@ -1905,12 +1905,12 @@ ENCODE_FORMS := [1649]lib.Encoding{ { .VUSMMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00C40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, // .VSUDOT { .VSUDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D50, 0xFFB00F50, .V8, .A32, {}, {.NONE,.NONE} }, - { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, + { .VSUDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D50, 0xFFB00F50, .V8, .A32, {}, {.U8,.NONE} }, // .VUSDOT { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, - { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, - { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, + { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, // .VQABS { .VQABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFB00740, 0xFFB30FD1, .MVE_INT, .T32, {thumb32=true}, {.S8,.NONE} }, // .VQNEG diff --git a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin index 76d1bda3b96e7ff2e1abfa5562664ef71155b3f8..f92d9332841f8601dc7d105b881c54b820c97c1e 100644 GIT binary patch delta 5847 zcmZ3!f@%2*rVaA^OjVVW75PP_sw){781g?eH2nY1&Zxk^AkDzYC@RLpQdK!QfL}BY zB%Sb?q2U8WRt6?p5x}s3y@25XKRW{h0|P{uo2R;hfx!WxS{6z51B7abFi7?0!~A9} z5@jq50t^e-3>Y5pvw}=BVPKSCW#BHKEGQxdk$ixVG=)jpi-@_Eu`n3$FJSw?{{f=Y zjDb;tk%7CMhk=1X;q!+NP*9j4})iJq+p$3=Ekd;Rg&13_n1^A|PQkZ3c!6kZ=RT2Zjp_ zKiC;TgjC%dvc+Y7-RP24kc&(0x^)S z3d{^2Ht>UtWthsK&&a?~zycO#{O})Dc=9hL7sis!_R4b^>q|jOJ}5AM`2U}u1EhBW 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