diff --git a/core/rexcode/arm32/mnemonic_builders.odin b/core/rexcode/arm32/mnemonic_builders.odin index 56b77aa86..1901ab5c8 100644 --- a/core/rexcode/arm32/mnemonic_builders.odin +++ b/core/rexcode/arm32/mnemonic_builders.odin @@ -9,1994 +9,2551 @@ package rexcode_arm32 // Generated by tools/gen_mnemonic_builders.odin from ENCODE_FORMS / ENCODE_RUNS. // Regenerate with: odin run arm32/tools/gen_mnemonic_builders.odin -file // -// Typed mnemonic builder procedures with overloading. Each mnemonic exposes an -// inst_ overload set (returns Instruction) and an emit_ overload -// set (appends to a ^[dynamic]Instruction). Only forms whose every operand is -// cleanly constructible from a single typed parameter are generated; shifted / -// register-shifted registers, register lists, NEON lane/vector forms, modified -// immediates, condition-code operands, coprocessor / PSR / MVE / CDE selectors -// and special encoded immediates are intentionally omitted. +// Typed mnemonic builder procedures with overloading. Each mnemonic with at +// least one encode form exposes an inst_ overload set (returns +// Instruction) and an emit_ overload set (appends to a +// ^[dynamic]Instruction). EVERY operand type is mapped to typed parameters: +// shifted / register-shifted registers (Register, Shift_Type, u8/Register), +// register lists (u16 mask), NEON D/Q lane elems (Register, u8), and every +// immediate subclass (modified-imm / barrier / endian / iflags / sysm / coproc +// / saturating / PSR field / hint / condition-operand / MVE / CDE) as i64 — the +// encoder performs the field packing. Forms whose ordered Odin parameter-type +// tuple duplicates an earlier form of the same mnemonic are folded out to keep +// each overload set unambiguous (all arm32 register classes share one Register +// type). // ============================================================================= // Individual Typed Builder Procedures // ============================================================================= -inst_and_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_and_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_and_rlo_rlo(dst, src)) } -inst_eor_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_eor_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_eor_rlo_rlo(dst, src)) } -inst_sub_rlo_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_sub_rlo_rlo_imm3 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_sub_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -emit_sub_rlo_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_rlo_rlo_rlo(dst, src, src2)) } -emit_sub_rlo_rlo_imm3 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_rlo_rlo_imm3(dst, src, imm)) } -emit_sub_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_sub_rlo_imm8(dst, imm)) } -inst_add_rlo_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_add_rlo_rlo_imm3 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_add_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_add_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_add_rlo_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_rlo_rlo_rlo(dst, src, src2)) } -emit_add_rlo_rlo_imm3 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_rlo_rlo_imm3(dst, src, imm)) } -emit_add_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_add_rlo_imm8(dst, imm)) } -emit_add_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_add_r_r(dst, src)) } -inst_adc_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_adc_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_adc_rlo_rlo(dst, src)) } -inst_sbc_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sbc_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sbc_rlo_rlo(dst, src)) } -inst_tst_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_tst_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tst_rlo_rlo(dst, src)) } -inst_cmp_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_cmp_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_cmp_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_rlo_imm8(dst, imm)) } -emit_cmp_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmp_rlo_rlo(dst, src)) } -inst_cmn_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_cmn_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmn_rlo_rlo(dst, src)) } -inst_orr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_orr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_orr_rlo_rlo(dst, src)) } -inst_mov_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_mov_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_rlo_imm8(dst, imm)) } -emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) } -inst_bic_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_bic_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bic_rlo_rlo(dst, src)) } -inst_mvn_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_mvn_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_rlo_rlo(dst, src)) } -inst_lsl_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_lsl_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_lsl_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_r_r_imm5(dst, src, imm)) } -emit_lsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsl_r_r_r(dst, src, src2)) } -emit_lsl_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_lsl_rlo_rlo(dst, src)) } -inst_lsr_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_lsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_lsr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_lsr_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_r_r_imm5(dst, src, imm)) } -emit_lsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsr_r_r_r(dst, src, src2)) } -emit_lsr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_lsr_rlo_rlo(dst, src)) } -inst_asr_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_asr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_asr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_asr_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_r_r_imm5(dst, src, imm)) } -emit_asr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asr_r_r_r(dst, src, src2)) } -emit_asr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_asr_rlo_rlo(dst, src)) } -inst_ror_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_ror_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_ror_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_ror_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_r_r_imm5(dst, src, imm)) } -emit_ror_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ror_r_r_r(dst, src, src2)) } -emit_ror_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ror_rlo_rlo(dst, src)) } -inst_rrx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RRX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_rrx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rrx_r_r(dst, src)) } -inst_adr_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } -emit_adr_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_adr_rlo_rel(dst, offset)) } -inst_neg_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_neg_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_rlo_rlo(dst, src)) } -inst_movw_r_imm16 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVW, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -emit_movw_r_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movw_r_imm16(dst, imm)) } -inst_movt_r_imm16 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -emit_movt_r_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movt_r_imm16(dst, imm)) } -inst_bfc_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .BFC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_imm(imm2), {}}} } -emit_bfc_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_bfc_r_imm5_imm5w(dst, imm, imm2)) } -inst_bfi_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .BFI, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } -emit_bfi_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_bfi_r_r_imm5_imm5w(dst, src, imm, imm2)) } -inst_sbfx_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SBFX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } -emit_sbfx_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sbfx_r_r_imm5_imm5w(dst, src, imm, imm2)) } -inst_ubfx_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UBFX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } -emit_ubfx_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_ubfx_r_r_imm5_imm5w(dst, src, imm, imm2)) } -inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) } -inst_sxtb16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTB16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sxtb16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb16_r_r(dst, src)) } -inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) } -inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) } -inst_uxtb16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTB16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_uxtb16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb16_r_r(dst, src)) } -inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) } -inst_sxtab_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sxtab_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtab_r_r_r(dst, src, src2)) } -inst_sxtab16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sxtab16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtab16_r_r_r(dst, src, src2)) } -inst_sxtah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sxtah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtah_r_r_r(dst, src, src2)) } -inst_uxtab_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uxtab_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtab_r_r_r(dst, src, src2)) } -inst_uxtab16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uxtab16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtab16_r_r_r(dst, src, src2)) } -inst_uxtah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uxtah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtah_r_r_r(dst, src, src2)) } -inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } -inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } -inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } -inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } -inst_revsh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REVSH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_revsh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_revsh_r_r(dst, src)) } -inst_sel_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sel_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sel_r_r_r(dst, src, src2)) } -inst_usad8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USAD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_usad8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usad8_r_r_r(dst, src, src2)) } -inst_usada8_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .USADA8, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_usada8_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_usada8_r_r_r_r(dst, src, src2, src3)) } -inst_ssat16_r_imm4s_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .SSAT16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), {}}} } -emit_ssat16_r_imm4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ssat16_r_imm4s_r(dst, imm, src)) } -inst_usat16_r_imm4s_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .USAT16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), {}}} } -emit_usat16_r_imm4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_usat16_r_imm4s_r(dst, imm, src)) } -inst_qadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd_r_r_r(dst, src, src2)) } -inst_qsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub_r_r_r(dst, src, src2)) } -inst_qdadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QDADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qdadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qdadd_r_r_r(dst, src, src2)) } -inst_qdsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QDSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qdsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qdsub_r_r_r(dst, src, src2)) } -inst_sadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sadd8_r_r_r(dst, src, src2)) } -inst_sadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sadd16_r_r_r(dst, src, src2)) } -inst_sasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sasx_r_r_r(dst, src, src2)) } -inst_ssax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_ssax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssax_r_r_r(dst, src, src2)) } -inst_ssub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_ssub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssub8_r_r_r(dst, src, src2)) } -inst_ssub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_ssub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssub16_r_r_r(dst, src, src2)) } -inst_uadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uadd8_r_r_r(dst, src, src2)) } -inst_uadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uadd16_r_r_r(dst, src, src2)) } -inst_uasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uasx_r_r_r(dst, src, src2)) } -inst_usax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_usax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usax_r_r_r(dst, src, src2)) } -inst_usub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_usub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usub8_r_r_r(dst, src, src2)) } -inst_usub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_usub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usub16_r_r_r(dst, src, src2)) } -inst_qadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd8_r_r_r(dst, src, src2)) } -inst_qadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd16_r_r_r(dst, src, src2)) } -inst_qasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qasx_r_r_r(dst, src, src2)) } -inst_qsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsax_r_r_r(dst, src, src2)) } -inst_qsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub8_r_r_r(dst, src, src2)) } -inst_qsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_qsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub16_r_r_r(dst, src, src2)) } -inst_uqadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd8_r_r_r(dst, src, src2)) } -inst_uqadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd16_r_r_r(dst, src, src2)) } -inst_uqasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqasx_r_r_r(dst, src, src2)) } -inst_uqsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsax_r_r_r(dst, src, src2)) } -inst_uqsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub8_r_r_r(dst, src, src2)) } -inst_uqsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uqsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub16_r_r_r(dst, src, src2)) } -inst_shadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd8_r_r_r(dst, src, src2)) } -inst_shadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd16_r_r_r(dst, src, src2)) } -inst_shasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shasx_r_r_r(dst, src, src2)) } -inst_shsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsax_r_r_r(dst, src, src2)) } -inst_shsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub8_r_r_r(dst, src, src2)) } -inst_shsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_shsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub16_r_r_r(dst, src, src2)) } -inst_uhadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd8_r_r_r(dst, src, src2)) } -inst_uhadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd16_r_r_r(dst, src, src2)) } -inst_uhasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhasx_r_r_r(dst, src, src2)) } -inst_uhsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsax_r_r_r(dst, src, src2)) } -inst_uhsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub8_r_r_r(dst, src, src2)) } -inst_uhsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_uhsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub16_r_r_r(dst, src, src2)) } -inst_smuad_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUAD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smuad_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smuad_r_r_r(dst, src, src2)) } -inst_smuadx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUADX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smuadx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smuadx_r_r_r(dst, src, src2)) } -inst_smusd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUSD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smusd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smusd_r_r_r(dst, src, src2)) } -inst_smusdx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUSDX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smusdx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smusdx_r_r_r(dst, src, src2)) } -inst_smlad_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlad_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlad_r_r_r_r(dst, src, src2, src3)) } -inst_smladx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLADX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smladx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smladx_r_r_r_r(dst, src, src2, src3)) } -inst_smlsd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlsd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsd_r_r_r_r(dst, src, src2, src3)) } -inst_smlsdx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlsdx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsdx_r_r_r_r(dst, src, src2, src3)) } -inst_smlald_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlald_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlald_r_r_r_r(dst, src, src2, src3)) } -inst_smlaldx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlaldx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaldx_r_r_r_r(dst, src, src2, src3)) } -inst_smlsld_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSLD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlsld_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsld_r_r_r_r(dst, src, src2, src3)) } -inst_smlsldx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSLDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlsldx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsldx_r_r_r_r(dst, src, src2, src3)) } -inst_smmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smmul_r_r_r(dst, src, src2)) } -inst_smmulr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMMULR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smmulr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smmulr_r_r_r(dst, src, src2)) } -inst_smmla_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smmla_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmla_r_r_r_r(dst, src, src2, src3)) } -inst_smmlar_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLAR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smmlar_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmlar_r_r_r_r(dst, src, src2, src3)) } -inst_smmls_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLS, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smmls_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmls_r_r_r_r(dst, src, src2, src3)) } -inst_smmlsr_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLSR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smmlsr_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmlsr_r_r_r_r(dst, src, src2, src3)) } -inst_mul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_mul_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_mul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_r_r_r(dst, src, src2)) } -emit_mul_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mul_rlo_rlo(dst, src)) } -inst_mla_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_mla_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_mla_r_r_r_r(dst, src, src2, src3)) } -inst_mls_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_mls_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_mls_r_r_r_r(dst, src, src2, src3)) } -inst_umull_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_umull_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umull_r_r_r_r(dst, src, src2, src3)) } -inst_umlal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_umlal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umlal_r_r_r_r(dst, src, src2, src3)) } -inst_smull_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smull_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smull_r_r_r_r(dst, src, src2, src3)) } -inst_smlal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlal_r_r_r_r(dst, src, src2, src3)) } -inst_umaal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMAAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_umaal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaal_r_r_r_r(dst, src, src2, src3)) } -inst_smlabb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLABB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlabb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlabb_r_r_r_r(dst, src, src2, src3)) } -inst_smlabt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLABT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlabt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlabt_r_r_r_r(dst, src, src2, src3)) } -inst_smlatb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLATB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlatb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlatb_r_r_r_r(dst, src, src2, src3)) } -inst_smlatt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLATT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlatt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlatt_r_r_r_r(dst, src, src2, src3)) } -inst_smlawb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAWB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlawb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlawb_r_r_r_r(dst, src, src2, src3)) } -inst_smlawt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAWT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlawt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlawt_r_r_r_r(dst, src, src2, src3)) } -inst_smulbb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULBB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smulbb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulbb_r_r_r(dst, src, src2)) } -inst_smulbt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULBT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smulbt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulbt_r_r_r(dst, src, src2)) } -inst_smultb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULTB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smultb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smultb_r_r_r(dst, src, src2)) } -inst_smultt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULTT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smultt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smultt_r_r_r(dst, src, src2)) } -inst_smulwb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULWB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smulwb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulwb_r_r_r(dst, src, src2)) } -inst_smulwt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULWT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_smulwt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulwt_r_r_r(dst, src, src2)) } -inst_smlalbb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALBB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlalbb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlalbb_r_r_r_r(dst, src, src2, src3)) } -inst_smlalbt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALBT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlalbt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlalbt_r_r_r_r(dst, src, src2, src3)) } -inst_smlaltb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALTB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlaltb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaltb_r_r_r_r(dst, src, src2, src3)) } -inst_smlaltt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALTT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_smlaltt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaltt_r_r_r_r(dst, src, src2, src3)) } -inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } -inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } -inst_b_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .B, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } -emit_b_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_b_rel(offset)) } -inst_bl_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .BL, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } -emit_bl_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_bl_rel(offset)) } -inst_bx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_bx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bx_r(dst)) } -inst_blx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BLX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -inst_blx_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .BLX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } -emit_blx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blx_r(dst)) } -emit_blx_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_blx_rel(offset)) } -inst_bxj_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BXJ, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_bxj_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bxj_r(dst)) } -inst_cbz_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } -emit_cbz_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_cbz_rlo_rel(dst, offset)) } -inst_cbnz_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } -emit_cbnz_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_cbnz_rlo_rel(dst, offset)) } -inst_tbb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TBB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_tbb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tbb_r_r(dst, src)) } -inst_tbh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TBH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_tbh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tbh_r_r(dst, src)) } -inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .NOP, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) } -inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .YIELD, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) } -inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .WFE, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) } -inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .WFI, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) } -inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SEV, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } -inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SEVL, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } -inst_clrex_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .CLREX, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_clrex_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_clrex_none()) } -inst_pld_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLD, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } -emit_pld_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pld_mem(dst)) } -inst_pldw_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLDW, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } -emit_pldw_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pldw_mem(dst)) } -inst_pli_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLI, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } -emit_pli_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pli_mem(dst)) } -inst_hlt_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_hlt_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_imm(imm)) } -inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ERET, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } -inst_esb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ESB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_esb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_esb_none()) } -inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PSB_CSYNC, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) } -inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TSB_CSYNC, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) } -inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .CSDB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) } -inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } -inst_svc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_svc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_imm(imm)) } -inst_bkpt_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BKPT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_bkpt_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bkpt_imm(imm)) } -inst_hvc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_hvc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_imm(imm)) } -inst_smc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_smc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_imm(imm)) } -inst_udf_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .UDF, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_udf_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_udf_imm(imm)) } -inst_ldr_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldr_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldr_r_mem(dst, src)) } -inst_str_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_str_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_str_r_mem(dst, src)) } -inst_ldrb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrb_r_mem(dst, src)) } -inst_strb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_strb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strb_r_mem(dst, src)) } -inst_ldrh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrh_r_mem(dst, src)) } -inst_strh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_strh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strh_r_mem(dst, src)) } -inst_ldrsb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrsb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsb_r_mem(dst, src)) } -inst_ldrsh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrsh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsh_r_mem(dst, src)) } -inst_ldrd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -inst_ldrd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_ldrd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrd_r_mem(dst, src)) } -emit_ldrd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldrd_r_r_mem(dst, src, src2)) } -inst_strd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -inst_strd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_strd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strd_r_mem(dst, src)) } -emit_strd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strd_r_r_mem(dst, src, src2)) } -inst_lda_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_lda_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_lda_r_mem(dst, src)) } -inst_stl_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_stl_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stl_r_mem(dst, src)) } -inst_ldab_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldab_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldab_r_mem(dst, src)) } -inst_stlb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STLB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_stlb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stlb_r_mem(dst, src)) } -inst_ldah_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldah_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldah_r_mem(dst, src)) } -inst_stlh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STLH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_stlh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stlh_r_mem(dst, src)) } -inst_ldrex_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrex_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrex_r_mem(dst, src)) } -inst_strex_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_strex_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strex_r_r_mem(dst, src, src2)) } -inst_ldrexb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrexb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexb_r_mem(dst, src)) } -inst_strexb_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_strexb_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexb_r_r_mem(dst, src, src2)) } -inst_ldrexh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldrexh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexh_r_mem(dst, src)) } -inst_strexh_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_strexh_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexh_r_r_mem(dst, src, src2)) } -inst_ldrexd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -inst_ldrexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDREXD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_ldrexd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexd_r_mem(dst, src)) } -emit_ldrexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldrexd_r_r_mem(dst, src, src2)) } -inst_strexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -inst_strexd_r_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Memory) -> Instruction { return Instruction{mnemonic = .STREXD, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(src3)}} } -emit_strexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexd_r_r_mem(dst, src, src2)) } -emit_strexd_r_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Memory) { append(instructions, inst_strexd_r_r_r_mem(dst, src, src2, src3)) } -inst_ldaex_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldaex_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaex_r_mem(dst, src)) } -inst_stlex_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_stlex_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlex_r_r_mem(dst, src, src2)) } -inst_ldaexb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldaexb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexb_r_mem(dst, src)) } -inst_stlexb_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_stlexb_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexb_r_r_mem(dst, src, src2)) } -inst_ldaexh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldaexh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexh_r_mem(dst, src)) } -inst_stlexh_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_stlexh_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexh_r_r_mem(dst, src, src2)) } -inst_ldaexd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_ldaexd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexd_r_mem(dst, src)) } -inst_stlexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } -emit_stlexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexd_r_r_mem(dst, src, src2)) } -inst_swp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWP, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_swp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swp_r_r_r(dst, src, src2)) } -inst_swpb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWPB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_swpb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swpb_r_r_r(dst, src, src2)) } -inst_rfe_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_rfe_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfe_r(dst)) } -inst_srs_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_srs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_srs_imm(imm)) } -inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32B, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) } -inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32H, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) } -inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32W, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) } -inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) } -inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) } -inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CW, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } -inst_vadd_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vadd_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vadd_s_s_s(dst, src, src2)) } -inst_vsub_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vsub_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsub_s_s_s(dst, src, src2)) } -inst_vmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmul_s_s_s(dst, src, src2)) } -inst_vdiv_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vdiv_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdiv_s_s_s(dst, src, src2)) } -inst_vmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmla_s_s_s(dst, src, src2)) } -inst_vmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmls_s_s_s(dst, src, src2)) } -inst_vnmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vnmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmul_s_s_s(dst, src, src2)) } -inst_vnmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vnmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmla_s_s_s(dst, src, src2)) } -inst_vnmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vnmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmls_s_s_s(dst, src, src2)) } -inst_vfma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_s_s_s(dst, src, src2)) } -inst_vfms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfms_s_s_s(dst, src, src2)) } -inst_vfnma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfnma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnma_s_s_s(dst, src, src2)) } -inst_vfnms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfnms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnms_s_s_s(dst, src, src2)) } -inst_vabs_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VABS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vabs_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vabs_s_s(dst, src)) } -inst_vneg_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VNEG, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vneg_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vneg_s_s(dst, src)) } -inst_vsqrt_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSQRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vsqrt_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vsqrt_s_s(dst, src)) } -inst_vcmp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -inst_vcmp_s :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCMP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vcmp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcmp_s_s(dst, src)) } -emit_vcmp_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vcmp_s(dst)) } -inst_vcmpe_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCMPE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -inst_vcmpe_s :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCMPE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vcmpe_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcmpe_s_s(dst, src)) } -emit_vcmpe_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vcmpe_s(dst)) } -inst_vcvt_d_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvt_d_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvt_d_s(dst, src)) } -inst_vcvtb_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvtb_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtb_s_s(dst, src)) } -inst_vcvtt_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvtt_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtt_s_s(dst, src)) } -inst_vcvta_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvta_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvta_s_s(dst, src)) } -inst_vcvtn_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvtn_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtn_s_s(dst, src)) } -inst_vcvtp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvtp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtp_s_s(dst, src)) } -inst_vcvtm_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvtm_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtm_s_s(dst, src)) } -inst_vmov_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -inst_vmov_s_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -inst_vmov_r_r_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vmov_r_r_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmov_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmov_s_s(dst, src)) } -emit_vmov_s_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmov_s_imm8(dst, imm)) } -emit_vmov_r_r_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmov_r_r_d(dst, src, src2)) } -emit_vmov_r_r_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmov_r_r_s_s(dst, src, src2, src3)) } -inst_vmrs_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vmrs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmrs_r(dst)) } -inst_vmsr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMSR, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vmsr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmsr_r(dst)) } -inst_vldr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vldr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldr_s_mem(dst, src)) } -inst_vstr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vstr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstr_s_mem(dst, src)) } -inst_vmaxnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmaxnm_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxnm_s_s_s(dst, src, src2)) } -inst_vminnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vminnm_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminnm_s_s_s(dst, src, src2)) } -inst_vrinta_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrinta_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrinta_s_s(dst, src)) } -inst_vrintn_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintn_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintn_s_s(dst, src)) } -inst_vrintp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintp_s_s(dst, src)) } -inst_vrintm_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintm_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintm_s_s(dst, src)) } -inst_vrintr_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintr_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintr_s_s(dst, src)) } -inst_vrintz_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintz_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintz_s_s(dst, src)) } -inst_vrintx_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrintx_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintx_s_s(dst, src)) } -inst_vhadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vhadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhadd_d_d_d(dst, src, src2)) } -inst_vhsub_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vhsub_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhsub_d_d_d(dst, src, src2)) } -inst_vrhadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRHADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vrhadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrhadd_d_d_d(dst, src, src2)) } -inst_vqadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqadd_d_d_d(dst, src, src2)) } -inst_vqsub_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqsub_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqsub_d_d_d(dst, src, src2)) } -inst_vmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmull_q_d_d(dst, src, src2)) } -inst_vmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlal_q_d_d(dst, src, src2)) } -inst_vmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsl_q_d_d(dst, src, src2)) } -inst_vqdmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmull_q_d_d(dst, src, src2)) } -inst_vqdmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlal_q_d_d(dst, src, src2)) } -inst_vqdmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsl_q_d_d(dst, src, src2)) } -inst_vqdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmulh_d_d_d(dst, src, src2)) } -inst_vqrdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmulh_d_d_d(dst, src, src2)) } -inst_vqrdmlah_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrdmlah_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlah_d_d_d(dst, src, src2)) } -inst_vqrdmlsh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrdmlsh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsh_d_d_d(dst, src, src2)) } -inst_vaba_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vaba_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaba_d_d_d(dst, src, src2)) } -inst_vabd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vabd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabd_d_d_d(dst, src, src2)) } -inst_vand_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vand_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vand_d_d_d(dst, src, src2)) } -inst_vbic_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vbic_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbic_d_d_d(dst, src, src2)) } -inst_vorr_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vorr_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorr_d_d_d(dst, src, src2)) } -inst_vorn_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vorn_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorn_d_d_d(dst, src, src2)) } -inst_veor_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_veor_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_veor_d_d_d(dst, src, src2)) } -inst_vbsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vbsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbsl_d_d_d(dst, src, src2)) } -inst_vbit_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vbit_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbit_d_d_d(dst, src, src2)) } -inst_vbif_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIF, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vbif_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbif_d_d_d(dst, src, src2)) } -inst_vmvn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -inst_vmvn_d_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } -emit_vmvn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmvn_d_d(dst, src)) } -emit_vmvn_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmvn_d_imm(dst, imm)) } -inst_vmovn_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmovn_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovn_d_q(dst, src)) } -inst_vqmovn_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovn_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovn_d_q(dst, src)) } -inst_vqmovun_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovun_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovun_d_q(dst, src)) } -inst_vmovl_q_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmovl_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovl_q_d(dst, src)) } -inst_vtst_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTST, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vtst_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtst_d_d_d(dst, src, src2)) } -inst_vceq_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCEQ, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vceq_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vceq_d_d_d(dst, src, src2)) } -inst_vcge_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCGE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vcge_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcge_d_d_d(dst, src, src2)) } -inst_vcgt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCGT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vcgt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcgt_d_d_d(dst, src, src2)) } -inst_vacge_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACGE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vacge_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacge_d_d_d(dst, src, src2)) } -inst_vacgt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACGT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vacgt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacgt_d_d_d(dst, src, src2)) } -inst_vmax_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmax_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmax_d_d_d(dst, src, src2)) } -inst_vmin_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMIN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmin_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmin_d_d_d(dst, src, src2)) } -inst_vpmax_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vpmax_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmax_d_d_d(dst, src, src2)) } -inst_vpmin_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMIN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vpmin_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmin_d_d_d(dst, src, src2)) } -inst_vpadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vpadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpadd_d_d_d(dst, src, src2)) } -inst_vpaddl_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPADDL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vpaddl_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpaddl_d_d(dst, src)) } -inst_vpadal_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPADAL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vpadal_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpadal_d_d(dst, src)) } -inst_vrecpe_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRECPE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrecpe_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrecpe_d_d(dst, src)) } -inst_vrecps_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRECPS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vrecps_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrecps_d_d_d(dst, src, src2)) } -inst_vrsqrte_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrsqrte_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrte_d_d(dst, src)) } -inst_vrsqrts_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vrsqrts_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrsqrts_d_d_d(dst, src, src2)) } -inst_vshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vshl_d_d_d(dst, src, src2)) } -inst_vshr_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshr_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshr_d_d_imm(dst, src, imm)) } -inst_vsra_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSRA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vsra_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsra_d_d_imm(dst, src, imm)) } -inst_vrshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vrshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrshl_d_d_d(dst, src, src2)) } -inst_vrshr_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vrshr_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshr_d_d_imm(dst, src, imm)) } -inst_vsli_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSLI, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vsli_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsli_d_d_imm(dst, src, imm)) } -inst_vsri_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSRI, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vsri_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsri_d_d_imm(dst, src, imm)) } -inst_vqshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -inst_vqshl_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqshl_d_d_d(dst, src, src2)) } -emit_vqshl_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshl_d_d_imm(dst, src, imm)) } -inst_vqshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrn_d_q_imm(dst, src, imm)) } -inst_vqshrun_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrun_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrun_d_q_imm(dst, src, imm)) } -inst_vqrshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrn_d_q_imm(dst, src, imm)) } -inst_vqrshrun_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrun_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrun_d_q_imm(dst, src, imm)) } -inst_vshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrn_d_q_imm(dst, src, imm)) } -inst_vrshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vrshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrn_d_q_imm(dst, src, imm)) } -inst_vshll_q_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -inst_vshll_q_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vshll_q_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshll_q_d_imm(dst, src, imm)) } -emit_vshll_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vshll_q_d(dst, src)) } -inst_vcls_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcls_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcls_d_d(dst, src)) } -inst_vclz_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vclz_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclz_d_d(dst, src)) } -inst_vcnt_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCNT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcnt_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcnt_d_d(dst, src)) } -inst_vrev16_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrev16_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev16_d_d(dst, src)) } -inst_vrev32_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV32, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrev32_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev32_d_d(dst, src)) } -inst_vrev64_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV64, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vrev64_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev64_d_d(dst, src)) } -inst_vext_d_d_d_imm4 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VEXT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_vext_d_d_d_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vext_d_d_d_imm4(dst, src, src2, imm)) } -inst_vtbl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vtbl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbl_d_d_d(dst, src, src2)) } -inst_vtbx_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vtbx_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbx_d_d_d(dst, src, src2)) } -inst_vtrn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VTRN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vtrn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vtrn_d_d(dst, src)) } -inst_vuzp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUZP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vuzp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vuzp_d_d(dst, src)) } -inst_vzip_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VZIP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vzip_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vzip_d_d(dst, src)) } -inst_vdup_d_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VDUP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vdup_d_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vdup_d_r(dst, src)) } -inst_vswp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSWP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vswp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vswp_d_d(dst, src)) } -inst_aese_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_aese_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_q_q(dst, src)) } -inst_aesd_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_aesd_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_q_q(dst, src)) } -inst_aesmc_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_aesmc_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_q_q(dst, src)) } -inst_aesimc_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_aesimc_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_q_q(dst, src)) } -inst_sha1h_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1H, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sha1h_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_q_q(dst, src)) } -inst_sha1su0_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha1su0_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_q_q_q(dst, src, src2)) } -inst_sha1su1_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sha1su1_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_q_q(dst, src)) } -inst_sha1c_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha1c_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_q_q_q(dst, src, src2)) } -inst_sha1m_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha1m_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_q_q_q(dst, src, src2)) } -inst_sha1p_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha1p_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_q_q_q(dst, src, src2)) } -inst_sha256h_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha256h_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_q_q_q(dst, src, src2)) } -inst_sha256h2_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha256h2_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_q_q_q(dst, src, src2)) } -inst_sha256su0_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_sha256su0_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_q_q(dst, src)) } -inst_sha256su1_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_sha256su1_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_q_q_q(dst, src, src2)) } -inst_vjcvt_s_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VJCVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vjcvt_s_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vjcvt_s_d(dst, src)) } -inst_vsdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vsdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsdot_d_d_d(dst, src, src2)) } -inst_vudot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vudot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vudot_d_d_d(dst, src, src2)) } -inst_vcvt_bf16_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVT_BF16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcvt_bf16_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvt_bf16_d_q(dst, src)) } -inst_vdot_bf16_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDOT_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vdot_bf16_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdot_bf16_d_d_d(dst, src, src2)) } -inst_vfma_bf16_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfma_bf16_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_bf16_q_q_q(dst, src, src2)) } -inst_vmmla_bf16_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMMLA_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmmla_bf16_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmmla_bf16_q_q_q(dst, src, src2)) } -inst_vfmal_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfmal_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmal_d_d_d(dst, src, src2)) } -inst_vfmsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vfmsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmsl_d_d_d(dst, src, src2)) } -inst_vcmla_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_vcmla_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcmla_d_d_d_imm(dst, src, src2, imm)) } -inst_vcadd_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCADD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_vcadd_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcadd_d_d_d_imm(dst, src, src2, imm)) } -inst_vsmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vsmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsmmla_q_q_q(dst, src, src2)) } -inst_vummla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vummla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vummla_q_q_q(dst, src, src2)) } -inst_vusmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vusmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusmmla_q_q_q(dst, src, src2)) } -inst_vsudot_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vsudot_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsudot_q_q_q(dst, src, src2)) } -inst_vusdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vusdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusdot_d_d_d(dst, src, src2)) } -inst_vqabs_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQABS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqabs_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqabs_q_q(dst, src)) } -inst_vqneg_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQNEG, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqneg_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqneg_q_q(dst, src)) } -inst_vmovx_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVX, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmovx_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovx_s_s(dst, src)) } -inst_vins_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VINS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vins_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vins_s_s(dst, src)) } -inst_vldrb_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRB_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vldrb_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrb_gather_q_mem_q(dst, src, src2)) } -inst_vldrh_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRH_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vldrh_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrh_gather_q_mem_q(dst, src, src2)) } -inst_vldrw_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRW_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vldrw_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrw_gather_q_mem_q(dst, src, src2)) } -inst_vldrd_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRD_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vldrd_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrd_gather_q_mem_q(dst, src, src2)) } -inst_vstrb_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRB_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vstrb_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrb_scatter_q_mem_q(dst, src, src2)) } -inst_vstrh_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRH_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vstrh_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrh_scatter_q_mem_q(dst, src, src2)) } -inst_vstrw_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRW_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vstrw_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrw_scatter_q_mem_q(dst, src, src2)) } -inst_vstrd_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRD_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } -emit_vstrd_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrd_scatter_q_mem_q(dst, src, src2)) } -inst_vceq_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCEQ_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vceq_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vceq_z_d_d(dst, src)) } -inst_vcge_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCGE_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcge_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcge_z_d_d(dst, src)) } -inst_vcgt_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCGT_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcgt_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcgt_z_d_d(dst, src)) } -inst_vcle_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLE_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vcle_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcle_z_d_d(dst, src)) } -inst_vclt_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLT_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vclt_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclt_z_d_d(dst, src)) } -inst_vcvt_fixed_s_s_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCVT_FIXED, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vcvt_fixed_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vcvt_fixed_s_s_imm(dst, src, imm)) } -inst_tt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_tt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tt_r_r(dst, src)) } -inst_ttt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_ttt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ttt_r_r(dst, src)) } -inst_tta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTA, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_tta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tta_r_r(dst, src)) } -inst_ttat_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTAT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_ttat_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ttat_r_r(dst, src)) } -inst_sg_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SG, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_sg_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sg_none()) } -inst_bxns_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BXNS, operand_count = 1, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), {}, {}, {}}} } -emit_bxns_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bxns_r(dst)) } -inst_blxns_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BLXNS, operand_count = 1, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), {}, {}, {}}} } -emit_blxns_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blxns_r(dst)) } -inst_pac_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PAC, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_pac_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pac_none()) } -inst_pacbti_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PACBTI, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_pacbti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacbti_none()) } -inst_aut_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .AUT, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_aut_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_aut_none()) } -inst_autg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AUTG, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_autg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_autg_r_r_r(dst, src, src2)) } -inst_bti_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_bti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_none()) } -inst_wls_r_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .WLS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } -emit_wls_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_wls_r_rel(dst, offset)) } -inst_wlstp_r_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .WLSTP, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } -emit_wlstp_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_wlstp_r_rel(dst, offset)) } -inst_dls_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .DLS, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_dls_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dls_r(dst)) } -inst_dlstp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .DLSTP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_dlstp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dlstp_r(dst)) } -inst_le_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .LE, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } -emit_le_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_le_rel(offset)) } -inst_letp_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .LETP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } -emit_letp_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_letp_rel(offset)) } -inst_lctp_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .LCTP, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_lctp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lctp_none()) } -inst_vpsel_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPSEL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vpsel_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpsel_q_q_q(dst, src, src2)) } -inst_vpnot_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .VPNOT, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } -emit_vpnot_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vpnot_none()) } -inst_vctp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCTP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vctp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vctp_r(dst)) } -inst_vaddv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VADDV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vaddv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vaddv_r_q(dst, src)) } -inst_vaddva_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VADDVA, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vaddva_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vaddva_r_q(dst, src)) } -inst_vaddlv_r_r_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDLV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vaddlv_r_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddlv_r_r_q(dst, src, src2)) } -inst_vaddlva_r_r_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDLVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vaddlva_r_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddlva_r_r_q(dst, src, src2)) } -inst_vmaxv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmaxv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxv_r_q(dst, src)) } -inst_vmaxav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmaxav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxav_r_q(dst, src)) } -inst_vminv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vminv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminv_r_q(dst, src)) } -inst_vminav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vminav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminav_r_q(dst, src)) } -inst_vmaxnmv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXNMV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmaxnmv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxnmv_r_q(dst, src)) } -inst_vmaxnmav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXNMAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmaxnmav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxnmav_r_q(dst, src)) } -inst_vminnmv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINNMV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vminnmv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminnmv_r_q(dst, src)) } -inst_vminnmav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINNMAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vminnmav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminnmav_r_q(dst, src)) } -inst_vabav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vabav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabav_r_q_q(dst, src, src2)) } -inst_vmladav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmladav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladav_r_q_q(dst, src, src2)) } -inst_vmladava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmladava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladava_r_q_q(dst, src, src2)) } -inst_vmladavx_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmladavx_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladavx_r_q_q(dst, src, src2)) } -inst_vmladavax_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVAX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmladavax_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladavax_r_q_q(dst, src, src2)) } -inst_vmlaldav_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlaldav_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldav_r_r_q_q(dst, src, src2, src3)) } -inst_vmlaldava_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlaldava_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldava_r_r_q_q(dst, src, src2, src3)) } -inst_vmlaldavx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlaldavx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldavx_r_r_q_q(dst, src, src2, src3)) } -inst_vmlaldavax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlaldavax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldavax_r_r_q_q(dst, src, src2, src3)) } -inst_vmlsdav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlsdav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdav_r_q_q(dst, src, src2)) } -inst_vmlsdava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlsdava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdava_r_q_q(dst, src, src2)) } -inst_vmlsdavx_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlsdavx_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdavx_r_q_q(dst, src, src2)) } -inst_vmlsdavax_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVAX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlsdavax_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdavax_r_q_q(dst, src, src2)) } -inst_vmlsldav_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlsldav_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldav_r_r_q_q(dst, src, src2, src3)) } -inst_vmlsldava_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlsldava_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldava_r_r_q_q(dst, src, src2, src3)) } -inst_vmlsldavx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlsldavx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldavx_r_r_q_q(dst, src, src2, src3)) } -inst_vmlsldavax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vmlsldavax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldavax_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlaldavh_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVH, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlaldavh_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavh_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlaldavha_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlaldavha_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavha_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlaldavhx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlaldavhx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavhx_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlaldavhax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlaldavhax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavhax_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlsldavh_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVH, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlsldavh_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavh_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlsldavha_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlsldavha_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavha_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlsldavhx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlsldavhx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavhx_r_r_q_q(dst, src, src2, src3)) } -inst_vrmlsldavhax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } -emit_vrmlsldavhax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavhax_r_r_q_q(dst, src, src2, src3)) } -inst_vmlav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlav_r_q_q(dst, src, src2)) } -inst_vmlava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlava_r_q_q(dst, src, src2)) } -inst_vcmul_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMUL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vcmul_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmul_q_q_q(dst, src, src2)) } -inst_vhcadd_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHCADD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vhcadd_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhcadd_q_q_q(dst, src, src2)) } -inst_vbrsr_q_q_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBRSR, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vbrsr_q_q_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbrsr_q_q_r(dst, src, src2)) } -inst_vshlc_q_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLC, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshlc_q_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshlc_q_r_imm5(dst, src, imm)) } -inst_vddup_q_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VDDUP, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vddup_q_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vddup_q_r_imm(dst, src, imm)) } -inst_vidup_q_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VIDUP, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vidup_q_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vidup_q_r_imm(dst, src, imm)) } -inst_vdwdup_q_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VDWDUP, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_vdwdup_q_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vdwdup_q_r_r_imm(dst, src, src2, imm)) } -inst_viwdup_q_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VIWDUP, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } -emit_viwdup_q_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_viwdup_q_r_r_imm(dst, src, src2, imm)) } -inst_vmovnb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmovnb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovnb_q_q(dst, src)) } -inst_vmovnt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vmovnt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovnt_q_q(dst, src)) } -inst_vqmovnb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovnb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovnb_q_q(dst, src)) } -inst_vqmovnt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovnt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovnt_q_q(dst, src)) } -inst_vqmovunb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovunb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovunb_q_q(dst, src)) } -inst_vqmovunt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } -emit_vqmovunt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovunt_q_q(dst, src)) } -inst_vshllb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshllb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshllb_q_q_imm5(dst, src, imm)) } -inst_vshllt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshllt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshllt_q_q_imm5(dst, src, imm)) } -inst_vmullb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmullb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmullb_q_q_q(dst, src, src2)) } -inst_vmullt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmullt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmullt_q_q_q(dst, src, src2)) } -inst_vmlalb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLALB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlalb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlalb_q_q_q(dst, src, src2)) } -inst_vmlalt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLALT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlalt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlalt_q_q_q(dst, src, src2)) } -inst_vmlslb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlslb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlslb_q_q_q(dst, src, src2)) } -inst_vmlslt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vmlslt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlslt_q_q_q(dst, src, src2)) } -inst_vshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrnb_q_q_imm5(dst, src, imm)) } -inst_vshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrnt_q_q_imm5(dst, src, imm)) } -inst_vrshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vrshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrnb_q_q_imm5(dst, src, imm)) } -inst_vrshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vrshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrnt_q_q_imm5(dst, src, imm)) } -inst_vqshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrnb_q_q_imm5(dst, src, imm)) } -inst_vqshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrnt_q_q_imm5(dst, src, imm)) } -inst_vqrshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrnb_q_q_imm5(dst, src, imm)) } -inst_vqrshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrnt_q_q_imm5(dst, src, imm)) } -inst_vqshrunb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrunb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrunb_q_q_imm5(dst, src, imm)) } -inst_vqshrunt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqshrunt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrunt_q_q_imm5(dst, src, imm)) } -inst_vqrshrunb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrunb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrunb_q_q_imm5(dst, src, imm)) } -inst_vqrshrunt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } -emit_vqrshrunt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrunt_q_q_imm5(dst, src, imm)) } -inst_vqdmladh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLADH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmladh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmladh_q_q_q(dst, src, src2)) } -inst_vqdmladhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLADHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmladhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmladhx_q_q_q(dst, src, src2)) } -inst_vqdmlsdh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSDH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmlsdh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsdh_q_q_q(dst, src, src2)) } -inst_vqdmlsdhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSDHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqdmlsdhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsdhx_q_q_q(dst, src, src2)) } -inst_vqrdmladh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLADH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrdmladh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmladh_q_q_q(dst, src, src2)) } -inst_vqrdmladhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLADHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrdmladhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmladhx_q_q_q(dst, src, src2)) } -inst_vqrdmlsdh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSDH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrdmlsdh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsdh_q_q_q(dst, src, src2)) } -inst_vqrdmlsdhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSDHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } -emit_vqrdmlsdhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsdhx_q_q_q(dst, src, src2)) } -inst_vldrb_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vldrb_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrb_q_mem(dst, src)) } -inst_vldrh_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vldrh_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrh_q_mem(dst, src)) } -inst_vldrw_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRW, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vldrw_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrw_q_mem(dst, src)) } -inst_vldrd_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRD, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vldrd_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrd_q_mem(dst, src)) } -inst_vstrb_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vstrb_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrb_q_mem(dst, src)) } -inst_vstrh_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vstrh_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrh_q_mem(dst, src)) } -inst_vstrw_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRW, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vstrw_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrw_q_mem(dst, src)) } -inst_vstrd_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRD, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } -emit_vstrd_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrd_q_mem(dst, src)) } +inst_and_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_and_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_and_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_and_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AND, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_and_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_r_r_immm(dst, src, imm)) } +emit_and_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_and_r_r_rsh(dst, src, src2, shift, amount)) } +emit_and_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_and_r_r_rsr(dst, src, src2, shift, rs)) } +emit_and_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_and_rlo_rlo(dst, src)) } +inst_eor_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_eor_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_eor_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_eor_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .EOR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_eor_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_r_r_immm(dst, src, imm)) } +emit_eor_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_eor_r_r_rsh(dst, src, src2, shift, amount)) } +emit_eor_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_eor_r_r_rsr(dst, src, src2, shift, rs)) } +emit_eor_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_eor_rlo_rlo(dst, src)) } +inst_sub_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_sub_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_sub_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_sub_rlo_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_sub_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SUB, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_sub_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_r_r_immm(dst, src, imm)) } +emit_sub_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_sub_r_r_rsh(dst, src, src2, shift, amount)) } +emit_sub_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_sub_r_r_rsr(dst, src, src2, shift, rs)) } +emit_sub_rlo_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_rlo_rlo_rlo(dst, src, src2)) } +emit_sub_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_sub_rlo_imm8(dst, imm)) } +inst_rsb_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_rsb_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_rsb_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .RSB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +emit_rsb_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rsb_r_r_immm(dst, src, imm)) } +emit_rsb_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_rsb_r_r_rsh(dst, src, src2, shift, amount)) } +emit_rsb_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_rsb_r_r_rsr(dst, src, src2, shift, rs)) } +inst_add_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_add_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_add_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_add_rlo_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 3, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_add_rlo_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_add_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADD, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_add_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_r_r_immm(dst, src, imm)) } +emit_add_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_add_r_r_rsh(dst, src, src2, shift, amount)) } +emit_add_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_add_r_r_rsr(dst, src, src2, shift, rs)) } +emit_add_rlo_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_rlo_rlo_rlo(dst, src, src2)) } +emit_add_rlo_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_add_rlo_imm8(dst, imm)) } +emit_add_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_add_r_r(dst, src)) } +inst_adc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_adc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_adc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_adc_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ADC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_adc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adc_r_r_immm(dst, src, imm)) } +emit_adc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_adc_r_r_rsh(dst, src, src2, shift, amount)) } +emit_adc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_adc_r_r_rsr(dst, src, src2, shift, rs)) } +emit_adc_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_adc_rlo_rlo(dst, src)) } +inst_sbc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_sbc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_sbc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_sbc_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SBC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sbc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sbc_r_r_immm(dst, src, imm)) } +emit_sbc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_sbc_r_r_rsh(dst, src, src2, shift, amount)) } +emit_sbc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_sbc_r_r_rsr(dst, src, src2, shift, rs)) } +emit_sbc_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sbc_rlo_rlo(dst, src)) } +inst_rsc_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_rsc_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_rsc_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .RSC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +emit_rsc_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_rsc_r_r_immm(dst, src, imm)) } +emit_rsc_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_rsc_r_r_rsh(dst, src, src2, shift, amount)) } +emit_rsc_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_rsc_r_r_rsr(dst, src, src2, shift, rs)) } +inst_tst_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_tst_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_tst_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +inst_tst_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_tst_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_r_immm(dst, imm)) } +emit_tst_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_tst_r_rsh(dst, src, shift, amount)) } +emit_tst_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_tst_r_rsr(dst, src, shift, rs)) } +emit_tst_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tst_rlo_rlo(dst, src)) } +inst_teq_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_teq_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_teq_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .TEQ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +emit_teq_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_teq_r_immm(dst, imm)) } +emit_teq_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_teq_r_rsh(dst, src, shift, amount)) } +emit_teq_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_teq_r_rsr(dst, src, shift, rs)) } +inst_cmp_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_cmp_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_cmp_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +inst_cmp_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMP, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_cmp_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_r_immm(dst, imm)) } +emit_cmp_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_cmp_r_rsh(dst, src, shift, amount)) } +emit_cmp_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_cmp_r_rsr(dst, src, shift, rs)) } +emit_cmp_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmp_rlo_rlo(dst, src)) } +inst_cmn_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_cmn_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_cmn_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +inst_cmn_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CMN, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_cmn_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmn_r_immm(dst, imm)) } +emit_cmn_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_cmn_r_rsh(dst, src, shift, amount)) } +emit_cmn_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_cmn_r_rsr(dst, src, shift, rs)) } +emit_cmn_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cmn_rlo_rlo(dst, src)) } +inst_orr_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_orr_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_orr_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_orr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ORR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_orr_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_r_r_immm(dst, src, imm)) } +emit_orr_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_orr_r_r_rsh(dst, src, src2, shift, amount)) } +emit_orr_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_orr_r_r_rsr(dst, src, src2, shift, rs)) } +emit_orr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_orr_rlo_rlo(dst, src)) } +inst_mov_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_mov_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_mov_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +inst_mov_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_mov_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_r_immm(dst, imm)) } +emit_mov_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_mov_r_rsh(dst, src, shift, amount)) } +emit_mov_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_mov_r_rsr(dst, src, shift, rs)) } +emit_mov_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_r_r(dst, src)) } +inst_bic_r_r_immm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_bic_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +inst_bic_r_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, u8(reg_hw(rs))), {}}} } +inst_bic_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BIC, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_bic_r_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_bic_r_r_immm(dst, src, imm)) } +emit_bic_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_bic_r_r_rsh(dst, src, src2, shift, amount)) } +emit_bic_r_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_bic_r_r_rsr(dst, src, src2, shift, rs)) } +emit_bic_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bic_rlo_rlo(dst, src)) } +inst_mvn_r_immm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_mvn_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, amount), {}, {}}} } +inst_mvn_r_rsr :: #force_inline proc "contextless" (dst: Register, src: Register, shift: Shift_Type, rs: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_shifted(src, shift, u8(reg_hw(rs))), {}, {}}} } +inst_mvn_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MVN, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_mvn_r_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mvn_r_immm(dst, imm)) } +emit_mvn_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_mvn_r_rsh(dst, src, shift, amount)) } +emit_mvn_r_rsr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, shift: Shift_Type, rs: Register) { append(instructions, inst_mvn_r_rsr(dst, src, shift, rs)) } +emit_mvn_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_rlo_rlo(dst, src)) } +inst_lsl_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_lsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_lsl_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .LSL, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_lsl_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_r_r_imm5(dst, src, imm)) } +emit_lsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsl_r_r_r(dst, src, src2)) } +emit_lsl_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_lsl_rlo_rlo(dst, src)) } +inst_lsr_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_lsr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_lsr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .LSR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_lsr_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_r_r_imm5(dst, src, imm)) } +emit_lsr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsr_r_r_r(dst, src, src2)) } +emit_lsr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_lsr_rlo_rlo(dst, src)) } +inst_asr_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_asr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_asr_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ASR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_asr_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_r_r_imm5(dst, src, imm)) } +emit_asr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asr_r_r_r(dst, src, src2)) } +emit_asr_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_asr_rlo_rlo(dst, src)) } +inst_ror_r_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_ror_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_ror_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .ROR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ror_r_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_r_r_imm5(dst, src, imm)) } +emit_ror_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ror_r_r_r(dst, src, src2)) } +emit_ror_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ror_rlo_rlo(dst, src)) } +inst_rrx_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RRX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_rrx_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rrx_r_r(dst, src)) } +inst_adr_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } +emit_adr_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_adr_rlo_rel(dst, offset)) } +inst_neg_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NEG, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_neg_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_neg_rlo_rlo(dst, src)) } +inst_movw_r_imm16 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVW, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_movw_r_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movw_r_imm16(dst, imm)) } +inst_movt_r_imm16 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MOVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_movt_r_imm16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_movt_r_imm16(dst, imm)) } +inst_bfc_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .BFC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_imm(imm2), {}}} } +emit_bfc_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_bfc_r_imm5_imm5w(dst, imm, imm2)) } +inst_bfi_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .BFI, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } +emit_bfi_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_bfi_r_r_imm5_imm5w(dst, src, imm, imm2)) } +inst_sbfx_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SBFX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } +emit_sbfx_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_sbfx_r_r_imm5_imm5w(dst, src, imm, imm2)) } +inst_ubfx_r_r_imm5_imm5w :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .UBFX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), op_imm(imm2)}} } +emit_ubfx_r_r_imm5_imm5w :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_ubfx_r_r_imm5_imm5w(dst, src, imm, imm2)) } +inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) } +inst_sxtb16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTB16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sxtb16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb16_r_r(dst, src)) } +inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SXTH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) } +inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) } +inst_uxtb16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTB16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_uxtb16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb16_r_r(dst, src)) } +inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UXTH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) } +inst_sxtab_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sxtab_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtab_r_r_r(dst, src, src2)) } +inst_sxtab16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sxtab16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtab16_r_r_r(dst, src, src2)) } +inst_sxtah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SXTAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sxtah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sxtah_r_r_r(dst, src, src2)) } +inst_uxtab_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uxtab_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtab_r_r_r(dst, src, src2)) } +inst_uxtab16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uxtab16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtab16_r_r_r(dst, src, src2)) } +inst_uxtah_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UXTAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uxtah_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uxtah_r_r_r(dst, src, src2)) } +inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .CLZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } +inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .RBIT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } +inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } +inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } +inst_revsh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .REVSH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_revsh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_revsh_r_r(dst, src)) } +inst_sel_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SEL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sel_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sel_r_r_r(dst, src, src2)) } +inst_pkhbt_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .PKHBT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +emit_pkhbt_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_pkhbt_r_r_rsh(dst, src, src2, shift, amount)) } +inst_pkhtb_r_r_rsh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .PKHTB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg_shifted(src2, shift, amount), {}}} } +emit_pkhtb_r_r_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_pkhtb_r_r_rsh(dst, src, src2, shift, amount)) } +inst_usad8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USAD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_usad8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usad8_r_r_r(dst, src, src2)) } +inst_usada8_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .USADA8, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_usada8_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_usada8_r_r_r_r(dst, src, src2, src3)) } +inst_ssat_r_imm4s_rsh :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .SSAT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg_shifted(src, shift, amount), {}}} } +emit_ssat_r_imm4s_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_ssat_r_imm4s_rsh(dst, imm, src, shift, amount)) } +inst_usat_r_imm4s_rsh :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) -> Instruction { return Instruction{mnemonic = .USAT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg_shifted(src, shift, amount), {}}} } +emit_usat_r_imm4s_rsh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, shift: Shift_Type, amount: u8) { append(instructions, inst_usat_r_imm4s_rsh(dst, imm, src, shift, amount)) } +inst_ssat16_r_imm4s_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .SSAT16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), {}}} } +emit_ssat16_r_imm4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_ssat16_r_imm4s_r(dst, imm, src)) } +inst_usat16_r_imm4s_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .USAT16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), {}}} } +emit_usat16_r_imm4s_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register) { append(instructions, inst_usat16_r_imm4s_r(dst, imm, src)) } +inst_qadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd_r_r_r(dst, src, src2)) } +inst_qsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub_r_r_r(dst, src, src2)) } +inst_qdadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QDADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qdadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qdadd_r_r_r(dst, src, src2)) } +inst_qdsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QDSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qdsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qdsub_r_r_r(dst, src, src2)) } +inst_sadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sadd8_r_r_r(dst, src, src2)) } +inst_sadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sadd16_r_r_r(dst, src, src2)) } +inst_sasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sasx_r_r_r(dst, src, src2)) } +inst_ssax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_ssax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssax_r_r_r(dst, src, src2)) } +inst_ssub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_ssub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssub8_r_r_r(dst, src, src2)) } +inst_ssub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_ssub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssub16_r_r_r(dst, src, src2)) } +inst_uadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uadd8_r_r_r(dst, src, src2)) } +inst_uadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uadd16_r_r_r(dst, src, src2)) } +inst_uasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uasx_r_r_r(dst, src, src2)) } +inst_usax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_usax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usax_r_r_r(dst, src, src2)) } +inst_usub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_usub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usub8_r_r_r(dst, src, src2)) } +inst_usub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_usub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usub16_r_r_r(dst, src, src2)) } +inst_qadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd8_r_r_r(dst, src, src2)) } +inst_qadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qadd16_r_r_r(dst, src, src2)) } +inst_qasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qasx_r_r_r(dst, src, src2)) } +inst_qsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsax_r_r_r(dst, src, src2)) } +inst_qsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub8_r_r_r(dst, src, src2)) } +inst_qsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .QSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_qsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_qsub16_r_r_r(dst, src, src2)) } +inst_uqadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd8_r_r_r(dst, src, src2)) } +inst_uqadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqadd16_r_r_r(dst, src, src2)) } +inst_uqasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqasx_r_r_r(dst, src, src2)) } +inst_uqsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsax_r_r_r(dst, src, src2)) } +inst_uqsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub8_r_r_r(dst, src, src2)) } +inst_uqsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UQSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uqsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uqsub16_r_r_r(dst, src, src2)) } +inst_shadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd8_r_r_r(dst, src, src2)) } +inst_shadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shadd16_r_r_r(dst, src, src2)) } +inst_shasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shasx_r_r_r(dst, src, src2)) } +inst_shsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsax_r_r_r(dst, src, src2)) } +inst_shsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub8_r_r_r(dst, src, src2)) } +inst_shsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_shsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_shsub16_r_r_r(dst, src, src2)) } +inst_uhadd8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhadd8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd8_r_r_r(dst, src, src2)) } +inst_uhadd16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHADD16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhadd16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhadd16_r_r_r(dst, src, src2)) } +inst_uhasx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHASX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhasx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhasx_r_r_r(dst, src, src2)) } +inst_uhsax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhsax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsax_r_r_r(dst, src, src2)) } +inst_uhsub8_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB8, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhsub8_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub8_r_r_r(dst, src, src2)) } +inst_uhsub16_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UHSUB16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_uhsub16_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uhsub16_r_r_r(dst, src, src2)) } +inst_smuad_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUAD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smuad_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smuad_r_r_r(dst, src, src2)) } +inst_smuadx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUADX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smuadx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smuadx_r_r_r(dst, src, src2)) } +inst_smusd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUSD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smusd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smusd_r_r_r(dst, src, src2)) } +inst_smusdx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMUSDX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smusdx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smusdx_r_r_r(dst, src, src2)) } +inst_smlad_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlad_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlad_r_r_r_r(dst, src, src2, src3)) } +inst_smladx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLADX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smladx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smladx_r_r_r_r(dst, src, src2, src3)) } +inst_smlsd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlsd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsd_r_r_r_r(dst, src, src2, src3)) } +inst_smlsdx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlsdx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsdx_r_r_r_r(dst, src, src2, src3)) } +inst_smlald_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlald_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlald_r_r_r_r(dst, src, src2, src3)) } +inst_smlaldx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlaldx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaldx_r_r_r_r(dst, src, src2, src3)) } +inst_smlsld_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSLD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlsld_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsld_r_r_r_r(dst, src, src2, src3)) } +inst_smlsldx_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLSLDX, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlsldx_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlsldx_r_r_r_r(dst, src, src2, src3)) } +inst_smmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smmul_r_r_r(dst, src, src2)) } +inst_smmulr_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMMULR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smmulr_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smmulr_r_r_r(dst, src, src2)) } +inst_smmla_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smmla_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmla_r_r_r_r(dst, src, src2, src3)) } +inst_smmlar_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLAR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smmlar_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmlar_r_r_r_r(dst, src, src2, src3)) } +inst_smmls_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLS, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smmls_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmls_r_r_r_r(dst, src, src2, src3)) } +inst_smmlsr_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMMLSR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smmlsr_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smmlsr_r_r_r_r(dst, src, src2, src3)) } +inst_mul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_mul_rlo_rlo :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MUL, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_mul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_r_r_r(dst, src, src2)) } +emit_mul_rlo_rlo :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mul_rlo_rlo(dst, src)) } +inst_mla_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_mla_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_mla_r_r_r_r(dst, src, src2, src3)) } +inst_mls_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .MLS, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_mls_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_mls_r_r_r_r(dst, src, src2, src3)) } +inst_umull_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMULL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_umull_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umull_r_r_r_r(dst, src, src2, src3)) } +inst_umlal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMLAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_umlal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umlal_r_r_r_r(dst, src, src2, src3)) } +inst_smull_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMULL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smull_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smull_r_r_r_r(dst, src, src2, src3)) } +inst_smlal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlal_r_r_r_r(dst, src, src2, src3)) } +inst_umaal_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .UMAAL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_umaal_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaal_r_r_r_r(dst, src, src2, src3)) } +inst_smlabb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLABB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlabb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlabb_r_r_r_r(dst, src, src2, src3)) } +inst_smlabt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLABT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlabt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlabt_r_r_r_r(dst, src, src2, src3)) } +inst_smlatb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLATB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlatb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlatb_r_r_r_r(dst, src, src2, src3)) } +inst_smlatt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLATT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlatt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlatt_r_r_r_r(dst, src, src2, src3)) } +inst_smlawb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAWB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlawb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlawb_r_r_r_r(dst, src, src2, src3)) } +inst_smlawt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLAWT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlawt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlawt_r_r_r_r(dst, src, src2, src3)) } +inst_smulbb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULBB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smulbb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulbb_r_r_r(dst, src, src2)) } +inst_smulbt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULBT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smulbt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulbt_r_r_r(dst, src, src2)) } +inst_smultb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULTB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smultb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smultb_r_r_r(dst, src, src2)) } +inst_smultt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULTT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smultt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smultt_r_r_r(dst, src, src2)) } +inst_smulwb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULWB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smulwb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulwb_r_r_r(dst, src, src2)) } +inst_smulwt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULWT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_smulwt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulwt_r_r_r(dst, src, src2)) } +inst_smlalbb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALBB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlalbb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlalbb_r_r_r_r(dst, src, src2, src3)) } +inst_smlalbt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALBT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlalbt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlalbt_r_r_r_r(dst, src, src2, src3)) } +inst_smlaltb_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALTB, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlaltb_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaltb_r_r_r_r(dst, src, src2, src3)) } +inst_smlaltt_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SMLALTT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_smlaltt_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smlaltt_r_r_r_r(dst, src, src2, src3)) } +inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } +inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } +inst_b_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .B, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } +inst_b_rel_cond :: #force_inline proc "contextless" (offset: i64, imm: i64) -> Instruction { return Instruction{mnemonic = .B, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_rel_offset(offset), op_imm(imm), {}, {}}} } +emit_b_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_b_rel(offset)) } +emit_b_rel_cond :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, imm: i64) { append(instructions, inst_b_rel_cond(offset, imm)) } +inst_bl_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .BL, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } +emit_bl_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_bl_rel(offset)) } +inst_bx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_bx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bx_r(dst)) } +inst_blx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BLX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +inst_blx_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .BLX, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } +emit_blx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blx_r(dst)) } +emit_blx_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_blx_rel(offset)) } +inst_bxj_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BXJ, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_bxj_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bxj_r(dst)) } +inst_cbz_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } +emit_cbz_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_cbz_rlo_rel(dst, offset)) } +inst_cbnz_rlo_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } +emit_cbnz_rlo_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_cbnz_rlo_rel(dst, offset)) } +inst_tbb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TBB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_tbb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tbb_r_r(dst, src)) } +inst_tbh_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TBH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_tbh_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tbh_r_r(dst, src)) } +inst_msr_psr_immm :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), op_imm(imm2), {}, {}}} } +inst_msr_psr_r :: #force_inline proc "contextless" (imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .MSR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), {}, {}}} } +emit_msr_psr_immm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_msr_psr_immm(imm, imm2)) } +emit_msr_psr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) { append(instructions, inst_msr_psr_r(imm, src)) } +inst_mrs_r_psr :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .MRS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_mrs_r_psr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mrs_r_psr(dst, imm)) } +inst_cps_ifl :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .CPS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_cps_ifl :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_cps_ifl(imm)) } +inst_setend_end :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SETEND, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_setend_end :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_setend_end(imm)) } +inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .NOP, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) } +inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .YIELD, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) } +inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .WFE, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) } +inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .WFI, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) } +inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SEV, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } +inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SEVL, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } +inst_dbg_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DBG, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_dbg_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dbg_hint(imm)) } +inst_hint_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HINT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_hint_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hint_hint(imm)) } +inst_dmb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_dmb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_barr(imm)) } +inst_dsb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_dsb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_barr(imm)) } +inst_isb_barr :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_isb_barr :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_barr(imm)) } +inst_clrex_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .CLREX, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_clrex_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_clrex_none()) } +inst_pld_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLD, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } +emit_pld_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pld_mem(dst)) } +inst_pldw_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLDW, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } +emit_pldw_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pldw_mem(dst)) } +inst_pli_mem :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return Instruction{mnemonic = .PLI, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_mem(dst), {}, {}, {}}} } +emit_pli_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { append(instructions, inst_pli_mem(dst)) } +inst_hlt_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_hlt_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_imm(imm)) } +inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ERET, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } +inst_esb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .ESB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_esb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_esb_none()) } +inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PSB_CSYNC, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) } +inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .TSB_CSYNC, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) } +inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .CSDB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) } +inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SB, operand_count = 0, mode = .A32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } +inst_setpan_hint :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SETPAN, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_setpan_hint :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_setpan_hint(imm)) } +inst_svc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_svc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_imm(imm)) } +inst_bkpt_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BKPT, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_bkpt_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bkpt_imm(imm)) } +inst_hvc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_hvc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_imm(imm)) } +inst_smc_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_smc_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_imm(imm)) } +inst_udf_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .UDF, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_udf_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_udf_imm(imm)) } +inst_ldr_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldr_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldr_r_mem(dst, src)) } +inst_str_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_str_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_str_r_mem(dst, src)) } +inst_ldrb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrb_r_mem(dst, src)) } +inst_strb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_strb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strb_r_mem(dst, src)) } +inst_ldrh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrh_r_mem(dst, src)) } +inst_strh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_strh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strh_r_mem(dst, src)) } +inst_ldrsb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrsb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsb_r_mem(dst, src)) } +inst_ldrsh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRSH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrsh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrsh_r_mem(dst, src)) } +inst_ldrd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_ldrd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_ldrd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrd_r_mem(dst, src)) } +emit_ldrd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldrd_r_r_mem(dst, src, src2)) } +inst_strd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_strd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STRD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_strd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_strd_r_mem(dst, src)) } +emit_strd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strd_r_r_mem(dst, src, src2)) } +inst_lda_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_lda_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_lda_r_mem(dst, src)) } +inst_stl_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_stl_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stl_r_mem(dst, src)) } +inst_ldab_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldab_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldab_r_mem(dst, src)) } +inst_stlb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STLB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_stlb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stlb_r_mem(dst, src)) } +inst_ldah_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldah_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldah_r_mem(dst, src)) } +inst_stlh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .STLH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_stlh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_stlh_r_mem(dst, src)) } +inst_ldrex_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrex_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrex_r_mem(dst, src)) } +inst_strex_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_strex_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strex_r_r_mem(dst, src, src2)) } +inst_ldrexb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrexb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexb_r_mem(dst, src)) } +inst_strexb_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_strexb_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexb_r_r_mem(dst, src, src2)) } +inst_ldrexh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldrexh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexh_r_mem(dst, src)) } +inst_strexh_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_strexh_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexh_r_r_mem(dst, src, src2)) } +inst_ldrexd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDREXD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +inst_ldrexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDREXD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_ldrexd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldrexd_r_mem(dst, src)) } +emit_ldrexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldrexd_r_r_mem(dst, src, src2)) } +inst_strexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STREXD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +inst_strexd_r_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Memory) -> Instruction { return Instruction{mnemonic = .STREXD, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(src3)}} } +emit_strexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_strexd_r_r_mem(dst, src, src2)) } +emit_strexd_r_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Memory) { append(instructions, inst_strexd_r_r_r_mem(dst, src, src2, src3)) } +inst_ldaex_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldaex_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaex_r_mem(dst, src)) } +inst_stlex_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stlex_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlex_r_r_mem(dst, src, src2)) } +inst_ldaexb_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldaexb_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexb_r_mem(dst, src)) } +inst_stlexb_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stlexb_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexb_r_r_mem(dst, src, src2)) } +inst_ldaexh_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXH, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldaexh_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexh_r_mem(dst, src)) } +inst_stlexh_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stlexh_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexh_r_r_mem(dst, src, src2)) } +inst_ldaexd_r_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .LDAEXD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_ldaexd_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_ldaexd_r_mem(dst, src)) } +inst_stlexd_r_r_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STLEXD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stlexd_r_r_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stlexd_r_r_mem(dst, src, src2)) } +inst_ldm_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .LDM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_ldm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_ldm_r_list(dst, regs)) } +inst_stm_r_list :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .STM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_stm_r_list :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_stm_r_list(dst, regs)) } +inst_push_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .PUSH, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } +emit_push_list :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_push_list(regs)) } +inst_pop_list :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .POP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } +emit_pop_list :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_pop_list(regs)) } +inst_swp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWP, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_swp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swp_r_r_r(dst, src, src2)) } +inst_swpb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWPB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_swpb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swpb_r_r_r(dst, src, src2)) } +inst_rfe_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_rfe_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfe_r(dst)) } +inst_srs_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_srs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_srs_imm(imm)) } +inst_cdp_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_cdp_cpn_cpop_crd_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cdp_cpn_cpop_crd_crd(dst, imm, src, src2)) } +inst_cdp2_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_cdp2_cpn_cpop_crd_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cdp2_cpn_cpop_crd_crd(dst, imm, src, src2)) } +inst_mcr_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mcr_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcr_cpn_cpop_r_crd(dst, imm, src, src2)) } +inst_mcr2_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCR2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mcr2_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcr2_cpn_cpop_r_crd(dst, imm, src, src2)) } +inst_mrc_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRC, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mrc_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrc_cpn_cpop_r_crd(dst, imm, src, src2)) } +inst_mrc2_cpn_cpop_r_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRC2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mrc2_cpn_cpop_r_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrc2_cpn_cpop_r_crd(dst, imm, src, src2)) } +inst_mcrr_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCRR, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mcrr_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcrr_cpn_cpop_r_r(dst, imm, src, src2)) } +inst_mcrr2_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MCRR2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mcrr2_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mcrr2_cpn_cpop_r_r(dst, imm, src, src2)) } +inst_mrrc_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRRC, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mrrc_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrrc_cpn_cpop_r_r(dst, imm, src, src2)) } +inst_mrrc2_cpn_cpop_r_r :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MRRC2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } +emit_mrrc2_cpn_cpop_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_mrrc2_cpn_cpop_r_r(dst, imm, src, src2)) } +inst_ldc_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_ldc_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldc_cpn_crd_mem(dst, src, src2)) } +inst_ldc2_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .LDC2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_ldc2_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_ldc2_cpn_crd_mem(dst, src, src2)) } +inst_stc_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stc_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stc_cpn_crd_mem(dst, src, src2)) } +inst_stc2_cpn_crd_mem :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Memory) -> Instruction { return Instruction{mnemonic = .STC2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_mem(src2), {}}} } +emit_stc2_cpn_crd_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Memory) { append(instructions, inst_stc2_cpn_crd_mem(dst, src, src2)) } +inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32B, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) } +inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32H, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) } +inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32W, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) } +inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) } +inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) } +inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CRC32CW, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } +inst_vadd_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vadd_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vadd_s_s_s(dst, src, src2)) } +inst_vsub_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vsub_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsub_s_s_s(dst, src, src2)) } +inst_vmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmul_s_s_s(dst, src, src2)) } +inst_vdiv_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDIV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vdiv_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdiv_s_s_s(dst, src, src2)) } +inst_vmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmla_s_s_s(dst, src, src2)) } +inst_vmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmls_s_s_s(dst, src, src2)) } +inst_vnmul_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMUL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vnmul_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmul_s_s_s(dst, src, src2)) } +inst_vnmla_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vnmla_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmla_s_s_s(dst, src, src2)) } +inst_vnmls_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VNMLS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vnmls_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vnmls_s_s_s(dst, src, src2)) } +inst_vfma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_s_s_s(dst, src, src2)) } +inst_vfms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfms_s_s_s(dst, src, src2)) } +inst_vfnma_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfnma_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnma_s_s_s(dst, src, src2)) } +inst_vfnms_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFNMS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfnms_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfnms_s_s_s(dst, src, src2)) } +inst_vabs_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VABS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vabs_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vabs_s_s(dst, src)) } +inst_vneg_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VNEG, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vneg_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vneg_s_s(dst, src)) } +inst_vsqrt_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSQRT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vsqrt_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vsqrt_s_s(dst, src)) } +inst_vcmp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCMP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +inst_vcmp_s :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCMP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_vcmp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcmp_s_s(dst, src)) } +emit_vcmp_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vcmp_s(dst)) } +inst_vcmpe_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCMPE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +inst_vcmpe_s :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCMPE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_vcmpe_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcmpe_s_s(dst, src)) } +emit_vcmpe_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vcmpe_s(dst)) } +inst_vcvt_d_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvt_d_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvt_d_s(dst, src)) } +inst_vcvtb_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvtb_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtb_s_s(dst, src)) } +inst_vcvtt_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvtt_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtt_s_s(dst, src)) } +inst_vcvta_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvta_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvta_s_s(dst, src)) } +inst_vcvtn_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvtn_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtn_s_s(dst, src)) } +inst_vcvtp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvtp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtp_s_s(dst, src)) } +inst_vcvtm_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvtm_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvtm_s_s(dst, src)) } +inst_vmov_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +inst_vmov_s_imm8 :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +inst_vmov_r_r_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vmov_r_r_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +inst_vmov_r_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_dpr_lane(src, lane), {}, {}}} } +inst_vmov_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} } +emit_vmov_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmov_s_s(dst, src)) } +emit_vmov_s_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmov_s_imm8(dst, imm)) } +emit_vmov_r_r_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmov_r_r_d(dst, src, src2)) } +emit_vmov_r_r_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmov_r_r_s_s(dst, src, src2, src3)) } +emit_vmov_r_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_dlane(dst, src, lane)) } +emit_vmov_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_dlane_r(dst, lane, src)) } +inst_vmrs_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_vmrs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmrs_r(dst)) } +inst_vmsr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMSR, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_vmsr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmsr_r(dst)) } +inst_vldr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vldr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldr_s_mem(dst, src)) } +inst_vstr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vstr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstr_s_mem(dst, src)) } +inst_vldm_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VLDM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_vldm_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vldm_r_slist(dst, regs)) } +inst_vstm_r_slist :: #force_inline proc "contextless" (dst: Register, regs: u16) -> Instruction { return Instruction{mnemonic = .VSTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), {}, {}}} } +emit_vstm_r_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16) { append(instructions, inst_vstm_r_slist(dst, regs)) } +inst_vpush_slist :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .VPUSH, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } +emit_vpush_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_vpush_slist(regs)) } +inst_vpop_slist :: #force_inline proc "contextless" (regs: u16) -> Instruction { return Instruction{mnemonic = .VPOP, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), {}, {}, {}}} } +emit_vpop_slist :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16) { append(instructions, inst_vpop_slist(regs)) } +inst_vsel_s_s_s_cond :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSEL, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_vsel_s_s_s_cond :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vsel_s_s_s_cond(dst, src, src2, imm)) } +inst_vmaxnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAXNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmaxnm_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmaxnm_s_s_s(dst, src, src2)) } +inst_vminnm_s_s_s :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMINNM, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vminnm_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vminnm_s_s_s(dst, src, src2)) } +inst_vrinta_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrinta_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrinta_s_s(dst, src)) } +inst_vrintn_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintn_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintn_s_s(dst, src)) } +inst_vrintp_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintp_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintp_s_s(dst, src)) } +inst_vrintm_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTM, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintm_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintm_s_s(dst, src)) } +inst_vrintr_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintr_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintr_s_s(dst, src)) } +inst_vrintz_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintz_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintz_s_s(dst, src)) } +inst_vrintx_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRINTX, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrintx_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrintx_s_s(dst, src)) } +inst_vhadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vhadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhadd_d_d_d(dst, src, src2)) } +inst_vhsub_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vhsub_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhsub_d_d_d(dst, src, src2)) } +inst_vrhadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRHADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vrhadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrhadd_d_d_d(dst, src, src2)) } +inst_vqadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqadd_d_d_d(dst, src, src2)) } +inst_vqsub_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQSUB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqsub_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqsub_d_d_d(dst, src, src2)) } +inst_vmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmull_q_d_d(dst, src, src2)) } +inst_vmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlal_q_d_d(dst, src, src2)) } +inst_vmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsl_q_d_d(dst, src, src2)) } +inst_vqdmull_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmull_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmull_q_d_d(dst, src, src2)) } +inst_vqdmlal_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmlal_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlal_q_d_d(dst, src, src2)) } +inst_vqdmlsl_q_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmlsl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsl_q_d_d(dst, src, src2)) } +inst_vqdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmulh_d_d_d(dst, src, src2)) } +inst_vqrdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmulh_d_d_d(dst, src, src2)) } +inst_vqrdmlah_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrdmlah_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlah_d_d_d(dst, src, src2)) } +inst_vqrdmlsh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrdmlsh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsh_d_d_d(dst, src, src2)) } +inst_vaba_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vaba_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaba_d_d_d(dst, src, src2)) } +inst_vabd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vabd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabd_d_d_d(dst, src, src2)) } +inst_vand_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vand_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vand_d_d_d(dst, src, src2)) } +inst_vbic_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbic_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbic_d_d_d(dst, src, src2)) } +inst_vorr_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vorr_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorr_d_d_d(dst, src, src2)) } +inst_vorn_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vorn_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorn_d_d_d(dst, src, src2)) } +inst_veor_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VEOR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_veor_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_veor_d_d_d(dst, src, src2)) } +inst_vbsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbsl_d_d_d(dst, src, src2)) } +inst_vbit_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbit_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbit_d_d_d(dst, src, src2)) } +inst_vbif_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIF, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbif_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbif_d_d_d(dst, src, src2)) } +inst_vmvn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +inst_vmvn_d_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_vmvn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmvn_d_d(dst, src)) } +emit_vmvn_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmvn_d_imm(dst, imm)) } +inst_vmovn_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmovn_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovn_d_q(dst, src)) } +inst_vqmovn_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovn_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovn_d_q(dst, src)) } +inst_vqmovun_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovun_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovun_d_q(dst, src)) } +inst_vmovl_q_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmovl_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovl_q_d(dst, src)) } +inst_vtst_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTST, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vtst_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtst_d_d_d(dst, src, src2)) } +inst_vceq_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCEQ, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vceq_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vceq_d_d_d(dst, src, src2)) } +inst_vcge_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCGE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vcge_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcge_d_d_d(dst, src, src2)) } +inst_vcgt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCGT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vcgt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcgt_d_d_d(dst, src, src2)) } +inst_vacge_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACGE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vacge_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacge_d_d_d(dst, src, src2)) } +inst_vacgt_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VACGT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vacgt_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vacgt_d_d_d(dst, src, src2)) } +inst_vmax_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmax_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmax_d_d_d(dst, src, src2)) } +inst_vmin_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMIN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmin_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmin_d_d_d(dst, src, src2)) } +inst_vpmax_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMAX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vpmax_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmax_d_d_d(dst, src, src2)) } +inst_vpmin_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPMIN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vpmin_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpmin_d_d_d(dst, src, src2)) } +inst_vpadd_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPADD, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vpadd_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpadd_d_d_d(dst, src, src2)) } +inst_vpaddl_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPADDL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vpaddl_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpaddl_d_d(dst, src)) } +inst_vpadal_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VPADAL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vpadal_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vpadal_d_d(dst, src)) } +inst_vrecpe_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRECPE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrecpe_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrecpe_d_d(dst, src)) } +inst_vrecps_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRECPS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vrecps_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrecps_d_d_d(dst, src, src2)) } +inst_vrsqrte_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrsqrte_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrsqrte_d_d(dst, src)) } +inst_vrsqrts_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRSQRTS, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vrsqrts_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrsqrts_d_d_d(dst, src, src2)) } +inst_vshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vshl_d_d_d(dst, src, src2)) } +inst_vshr_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshr_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshr_d_d_imm(dst, src, imm)) } +inst_vsra_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSRA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vsra_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsra_d_d_imm(dst, src, imm)) } +inst_vrshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VRSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vrshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vrshl_d_d_d(dst, src, src2)) } +inst_vrshr_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vrshr_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshr_d_d_imm(dst, src, imm)) } +inst_vsli_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSLI, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vsli_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsli_d_d_imm(dst, src, imm)) } +inst_vsri_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSRI, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vsri_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vsri_d_d_imm(dst, src, imm)) } +inst_vqshl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vqshl_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqshl_d_d_d(dst, src, src2)) } +emit_vqshl_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshl_d_d_imm(dst, src, imm)) } +inst_vqshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrn_d_q_imm(dst, src, imm)) } +inst_vqshrun_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrun_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrun_d_q_imm(dst, src, imm)) } +inst_vqrshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrn_d_q_imm(dst, src, imm)) } +inst_vqrshrun_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrun_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrun_d_q_imm(dst, src, imm)) } +inst_vshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrn_d_q_imm(dst, src, imm)) } +inst_vrshrn_d_q_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vrshrn_d_q_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrn_d_q_imm(dst, src, imm)) } +inst_vshll_q_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +inst_vshll_q_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSHLL, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vshll_q_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshll_q_d_imm(dst, src, imm)) } +emit_vshll_q_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vshll_q_d(dst, src)) } +inst_vcls_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcls_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcls_d_d(dst, src)) } +inst_vclz_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLZ, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vclz_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclz_d_d(dst, src)) } +inst_vcnt_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCNT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcnt_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcnt_d_d(dst, src)) } +inst_vrev16_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrev16_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev16_d_d(dst, src)) } +inst_vrev32_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV32, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrev32_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev32_d_d(dst, src)) } +inst_vrev64_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VREV64, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vrev64_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vrev64_d_d(dst, src)) } +inst_vext_d_d_d_imm4 :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VEXT, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_vext_d_d_d_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vext_d_d_d_imm4(dst, src, src2, imm)) } +inst_vtbl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vtbl_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} } +emit_vtbl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbl_d_d_d(dst, src, src2)) } +emit_vtbl_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbl_d_dlist_d(dst, regs, src)) } +inst_vtbx_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +inst_vtbx_d_dlist_d :: #force_inline proc "contextless" (dst: Register, regs: u16, src: Register) -> Instruction { return Instruction{mnemonic = .VTBX, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg_list(regs), op_reg(src), {}}} } +emit_vtbx_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vtbx_d_d_d(dst, src, src2)) } +emit_vtbx_d_dlist_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, regs: u16, src: Register) { append(instructions, inst_vtbx_d_dlist_d(dst, regs, src)) } +inst_vtrn_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VTRN, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vtrn_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vtrn_d_d(dst, src)) } +inst_vuzp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VUZP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vuzp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vuzp_d_d(dst, src)) } +inst_vzip_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VZIP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vzip_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vzip_d_d(dst, src)) } +inst_vdup_d_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VDUP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +inst_vdup_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VDUP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_dpr_lane(src, lane), {}, {}}} } +emit_vdup_d_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vdup_d_r(dst, src)) } +emit_vdup_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vdup_d_dlane(dst, src, lane)) } +inst_vswp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSWP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vswp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vswp_d_d(dst, src)) } +inst_vld1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +inst_vld1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } +emit_vld1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld1_dlist_mem(regs, src)) } +emit_vld1_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vld1_dlane_mem(dst, lane, src)) } +inst_vld2_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld2_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2_dlist_mem(regs, src)) } +inst_vld3_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld3_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3_dlist_mem(regs, src)) } +inst_vld4_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld4_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4_dlist_mem(regs, src)) } +inst_vst1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +inst_vst1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } +emit_vst1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst1_dlist_mem(regs, src)) } +emit_vst1_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vst1_dlane_mem(dst, lane, src)) } +inst_vst2_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST2, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst2_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst2_dlist_mem(regs, src)) } +inst_vst3_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST3, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst3_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst3_dlist_mem(regs, src)) } +inst_vst4_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST4, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst4_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst4_dlist_mem(regs, src)) } +inst_aese_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_aese_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_q_q(dst, src)) } +inst_aesd_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_aesd_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_q_q(dst, src)) } +inst_aesmc_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_aesmc_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_q_q(dst, src)) } +inst_aesimc_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_aesimc_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_q_q(dst, src)) } +inst_sha1h_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1H, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sha1h_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_q_q(dst, src)) } +inst_sha1su0_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha1su0_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_q_q_q(dst, src, src2)) } +inst_sha1su1_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sha1su1_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_q_q(dst, src)) } +inst_sha1c_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha1c_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_q_q_q(dst, src, src2)) } +inst_sha1m_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha1m_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_q_q_q(dst, src, src2)) } +inst_sha1p_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha1p_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_q_q_q(dst, src, src2)) } +inst_sha256h_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha256h_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_q_q_q(dst, src, src2)) } +inst_sha256h2_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha256h2_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_q_q_q(dst, src, src2)) } +inst_sha256su0_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_sha256su0_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_q_q(dst, src)) } +inst_sha256su1_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_sha256su1_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_q_q_q(dst, src, src2)) } +inst_vjcvt_s_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VJCVT, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vjcvt_s_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vjcvt_s_d(dst, src)) } +inst_vsdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vsdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsdot_d_d_d(dst, src, src2)) } +inst_vudot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vudot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vudot_d_d_d(dst, src, src2)) } +inst_vsdot_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vsdot_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsdot_lane_d_d_dlane(dst, src, src2, lane)) } +inst_vudot_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vudot_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vudot_lane_d_d_dlane(dst, src, src2, lane)) } +inst_vcvt_bf16_d_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCVT_BF16, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcvt_bf16_d_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcvt_bf16_d_q(dst, src)) } +inst_vdot_bf16_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VDOT_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vdot_bf16_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vdot_bf16_d_d_d(dst, src, src2)) } +inst_vfma_bf16_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMA_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfma_bf16_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfma_bf16_q_q_q(dst, src, src2)) } +inst_vmmla_bf16_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMMLA_BF16, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmmla_bf16_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmmla_bf16_q_q_q(dst, src, src2)) } +inst_vfmal_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMAL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfmal_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmal_d_d_d(dst, src, src2)) } +inst_vfmsl_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VFMSL, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vfmsl_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vfmsl_d_d_d(dst, src, src2)) } +inst_vcmla_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_vcmla_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcmla_d_d_d_imm(dst, src, src2, imm)) } +inst_vcadd_d_d_d_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCADD, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_vcadd_d_d_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vcadd_d_d_d_imm(dst, src, src2, imm)) } +inst_vcmla_lane_d_d_dlane_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .VCMLA_LANE, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), op_imm(imm)}} } +emit_vcmla_lane_d_d_dlane_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8, imm: i64) { append(instructions, inst_vcmla_lane_d_d_dlane_imm(dst, src, src2, lane, imm)) } +inst_vsmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vsmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsmmla_q_q_q(dst, src, src2)) } +inst_vummla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vummla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vummla_q_q_q(dst, src, src2)) } +inst_vusmmla_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSMMLA, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vusmmla_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusmmla_q_q_q(dst, src, src2)) } +inst_vsudot_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VSUDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vsudot_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vsudot_q_q_q(dst, src, src2)) } +inst_vusdot_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VUSDOT, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vusdot_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vusdot_d_d_d(dst, src, src2)) } +inst_vsudot_lane_q_q_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VSUDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vsudot_lane_q_q_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vsudot_lane_q_q_dlane(dst, src, src2, lane)) } +inst_vusdot_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VUSDOT_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vusdot_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vusdot_lane_d_d_dlane(dst, src, src2, lane)) } +inst_vmul_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMUL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmul_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmul_lane_d_d_dlane(dst, src, src2, lane)) } +inst_vmla_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLA_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmla_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmla_lane_d_d_dlane(dst, src, src2, lane)) } +inst_vmls_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLS_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmls_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmls_lane_d_d_dlane(dst, src, src2, lane)) } +inst_vmull_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMULL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmull_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmull_lane_q_d_dlane(dst, src, src2, lane)) } +inst_vmlal_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLAL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmlal_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlal_lane_q_d_dlane(dst, src, src2, lane)) } +inst_vmlsl_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMLSL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vmlsl_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vmlsl_lane_q_d_dlane(dst, src, src2, lane)) } +inst_vqdmull_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqdmull_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmull_lane_q_d_dlane(dst, src, src2, lane)) } +inst_vqdmlal_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLAL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqdmlal_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlal_lane_q_d_dlane(dst, src, src2, lane)) } +inst_vqdmlsl_lane_q_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMLSL_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqdmlsl_lane_q_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmlsl_lane_q_d_dlane(dst, src, src2, lane)) } +inst_vfma_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMA_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vfma_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfma_lane_d_d_dlane(dst, src, src2, lane)) } +inst_vfms_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VFMS_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vfms_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vfms_lane_d_d_dlane(dst, src, src2, lane)) } +inst_vqrdmlah_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLAH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqrdmlah_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlah_lane_d_d_dlane(dst, src, src2, lane)) } +inst_vqrdmlsh_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMLSH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} } +emit_vqrdmlsh_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmlsh_lane_d_d_dlane(dst, src, src2, lane)) } +inst_vqabs_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQABS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqabs_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqabs_q_q(dst, src)) } +inst_vqneg_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQNEG, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqneg_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqneg_q_q(dst, src)) } +inst_vmovx_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVX, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmovx_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovx_s_s(dst, src)) } +inst_vins_s_s :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VINS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vins_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vins_s_s(dst, src)) } +inst_vldrb_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRB_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vldrb_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrb_gather_q_mem_q(dst, src, src2)) } +inst_vldrh_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRH_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vldrh_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrh_gather_q_mem_q(dst, src, src2)) } +inst_vldrw_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRW_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vldrw_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrw_gather_q_mem_q(dst, src, src2)) } +inst_vldrd_gather_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VLDRD_GATHER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vldrd_gather_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vldrd_gather_q_mem_q(dst, src, src2)) } +inst_vstrb_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRB_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vstrb_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrb_scatter_q_mem_q(dst, src, src2)) } +inst_vstrh_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRH_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vstrh_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrh_scatter_q_mem_q(dst, src, src2)) } +inst_vstrw_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRW_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vstrw_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrw_scatter_q_mem_q(dst, src, src2)) } +inst_vstrd_scatter_q_mem_q :: #force_inline proc "contextless" (dst: Register, src: Memory, src2: Register) -> Instruction { return Instruction{mnemonic = .VSTRD_SCATTER, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), op_reg(src2), {}}} } +emit_vstrd_scatter_q_mem_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory, src2: Register) { append(instructions, inst_vstrd_scatter_q_mem_q(dst, src, src2)) } +inst_vceq_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCEQ_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vceq_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vceq_z_d_d(dst, src)) } +inst_vcge_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCGE_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcge_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcge_z_d_d(dst, src)) } +inst_vcgt_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCGT_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcgt_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcgt_z_d_d(dst, src)) } +inst_vcle_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLE_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vcle_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vcle_z_d_d(dst, src)) } +inst_vclt_z_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VCLT_Z, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vclt_z_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vclt_z_d_d(dst, src)) } +inst_vld2r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld2r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2r_dlist_mem(regs, src)) } +inst_vld3r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld3r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3r_dlist_mem(regs, src)) } +inst_vld4r_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4R, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld4r_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4r_dlist_mem(regs, src)) } +inst_vld1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } +emit_vld1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vld1_lane_dlane_mem(dst, lane, src)) } +inst_vld2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld2_lane_dlist_mem(regs, src)) } +inst_vld3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld3_lane_dlist_mem(regs, src)) } +inst_vld4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld4_lane_dlist_mem(regs, src)) } +inst_vst1_lane_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VST1_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} } +emit_vst1_lane_dlane_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Memory) { append(instructions, inst_vst1_lane_dlane_mem(dst, lane, src)) } +inst_vst2_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST2_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst2_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst2_lane_dlist_mem(regs, src)) } +inst_vst3_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST3_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst3_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst3_lane_dlist_mem(regs, src)) } +inst_vst4_lane_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST4_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst4_lane_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst4_lane_dlist_mem(regs, src)) } +inst_vcvt_fixed_s_s_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VCVT_FIXED, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vcvt_fixed_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vcvt_fixed_s_s_imm(dst, src, imm)) } +inst_it_cond_imm4 :: #force_inline proc "contextless" (imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .IT, operand_count = 2, mode = .T32, cond = 14, length = 2, ops = {op_imm(imm), op_imm(imm2), {}, {}}} } +emit_it_cond_imm4 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64) { append(instructions, inst_it_cond_imm4(imm, imm2)) } +inst_tt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_tt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tt_r_r(dst, src)) } +inst_ttt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ttt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ttt_r_r(dst, src)) } +inst_tta_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTA, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_tta_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_tta_r_r(dst, src)) } +inst_ttat_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .TTAT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_ttat_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ttat_r_r(dst, src)) } +inst_sg_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .SG, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_sg_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sg_none()) } +inst_bxns_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BXNS, operand_count = 1, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), {}, {}, {}}} } +emit_bxns_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_bxns_r(dst)) } +inst_blxns_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .BLXNS, operand_count = 1, mode = .T32, cond = 14, length = 2, ops = {op_reg(dst), {}, {}, {}}} } +emit_blxns_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blxns_r(dst)) } +inst_pac_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PAC, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_pac_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pac_none()) } +inst_pacbti_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .PACBTI, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_pacbti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacbti_none()) } +inst_aut_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .AUT, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_aut_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_aut_none()) } +inst_autg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AUTG, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_autg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_autg_r_r_r(dst, src, src2)) } +inst_bti_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_bti_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_none()) } +inst_wls_r_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .WLS, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } +emit_wls_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_wls_r_rel(dst, offset)) } +inst_wlstp_r_rel :: #force_inline proc "contextless" (dst: Register, offset: i64) -> Instruction { return Instruction{mnemonic = .WLSTP, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_rel_offset(offset), {}, {}}} } +emit_wlstp_r_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, offset: i64) { append(instructions, inst_wlstp_r_rel(dst, offset)) } +inst_dls_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .DLS, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_dls_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dls_r(dst)) } +inst_dlstp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .DLSTP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_dlstp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dlstp_r(dst)) } +inst_le_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .LE, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } +emit_le_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_le_rel(offset)) } +inst_letp_rel :: #force_inline proc "contextless" (offset: i64) -> Instruction { return Instruction{mnemonic = .LETP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), {}, {}, {}}} } +emit_letp_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_letp_rel(offset)) } +inst_lctp_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .LCTP, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_lctp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lctp_none()) } +inst_cx1_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_cx1_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1_cp_r_imm(imm, src, imm2)) } +inst_cx1a_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1A, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_cx1a_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1a_cp_r_imm(imm, src, imm2)) } +inst_cx1d_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1D, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_cx1d_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1d_cp_r_imm(imm, src, imm2)) } +inst_cx1da_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1DA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_cx1da_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1da_cp_r_imm(imm, src, imm2)) } +inst_cx2_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_cx2_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2_cp_r_r_imm(imm, src, src2, imm2)) } +inst_cx2a_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_cx2a_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2a_cp_r_r_imm(imm, src, src2, imm2)) } +inst_cx2d_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2D, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_cx2d_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2d_cp_r_r_imm(imm, src, src2, imm2)) } +inst_cx2da_cp_r_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX2DA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_cx2da_cp_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_cx2da_cp_r_r_imm(imm, src, src2, imm2)) } +inst_cx3_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_cx3_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3_cp_r_r_r(imm, src, src2, src3)) } +inst_cx3a_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_cx3a_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3a_cp_r_r_r(imm, src, src2, src3)) } +inst_cx3d_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3D, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_cx3d_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3d_cp_r_r_r(imm, src, src2, src3)) } +inst_cx3da_cp_r_r_r :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .CX3DA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_cx3da_cp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_cx3da_cp_r_r_r(imm, src, src2, src3)) } +inst_vcx1_cp_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX1, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_vcx1_cp_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_vcx1_cp_s_imm(imm, src, imm2)) } +inst_vcx1a_cp_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX1A, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } +emit_vcx1a_cp_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_vcx1a_cp_s_imm(imm, src, imm2)) } +inst_vcx2_cp_s_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX2, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_vcx2_cp_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_vcx2_cp_s_s_imm(imm, src, src2, imm2)) } +inst_vcx2a_cp_s_s_imm :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .VCX2A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_imm(imm2)}} } +emit_vcx2a_cp_s_s_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, imm2: i64) { append(instructions, inst_vcx2a_cp_s_s_imm(imm, src, src2, imm2)) } +inst_vcx3_cp_s_s_s :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VCX3, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vcx3_cp_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_vcx3_cp_s_s_s(imm, src, src2, src3)) } +inst_vcx3a_cp_s_s_s :: #force_inline proc "contextless" (imm: i64, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VCX3A, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vcx3a_cp_s_s_s :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, src2: Register, src3: Register) { append(instructions, inst_vcx3a_cp_s_s_s(imm, src, src2, src3)) } +inst_vpt_vpt_cond_q_q :: #force_inline proc "contextless" (imm: i64, imm2: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPT, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_imm(imm2), op_reg(src), op_reg(src2)}} } +emit_vpt_vpt_cond_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, imm2: i64, src: Register, src2: Register) { append(instructions, inst_vpt_vpt_cond_q_q(imm, imm2, src, src2)) } +inst_vpst_vpt :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .VPST, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } +emit_vpst_vpt :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_vpst_vpt(imm)) } +inst_vpsel_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VPSEL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vpsel_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vpsel_q_q_q(dst, src, src2)) } +inst_vpnot_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .VPNOT, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } +emit_vpnot_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_vpnot_none()) } +inst_vctp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VCTP, operand_count = 1, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_vctp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vctp_r(dst)) } +inst_vaddv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VADDV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vaddv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vaddv_r_q(dst, src)) } +inst_vaddva_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VADDVA, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vaddva_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vaddva_r_q(dst, src)) } +inst_vaddlv_r_r_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDLV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vaddlv_r_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddlv_r_r_q(dst, src, src2)) } +inst_vaddlva_r_r_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VADDLVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vaddlva_r_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vaddlva_r_r_q(dst, src, src2)) } +inst_vmaxv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmaxv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxv_r_q(dst, src)) } +inst_vmaxav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmaxav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxav_r_q(dst, src)) } +inst_vminv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vminv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminv_r_q(dst, src)) } +inst_vminav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vminav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminav_r_q(dst, src)) } +inst_vmaxnmv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXNMV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmaxnmv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxnmv_r_q(dst, src)) } +inst_vmaxnmav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMAXNMAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmaxnmav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmaxnmav_r_q(dst, src)) } +inst_vminnmv_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINNMV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vminnmv_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminnmv_r_q(dst, src)) } +inst_vminnmav_r_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMINNMAV, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vminnmav_r_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vminnmav_r_q(dst, src)) } +inst_vabav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VABAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vabav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabav_r_q_q(dst, src, src2)) } +inst_vmladav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmladav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladav_r_q_q(dst, src, src2)) } +inst_vmladava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmladava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladava_r_q_q(dst, src, src2)) } +inst_vmladavx_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmladavx_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladavx_r_q_q(dst, src, src2)) } +inst_vmladavax_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLADAVAX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmladavax_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmladavax_r_q_q(dst, src, src2)) } +inst_vmlaldav_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlaldav_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldav_r_r_q_q(dst, src, src2, src3)) } +inst_vmlaldava_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlaldava_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldava_r_r_q_q(dst, src, src2, src3)) } +inst_vmlaldavx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlaldavx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldavx_r_r_q_q(dst, src, src2, src3)) } +inst_vmlaldavax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLALDAVAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlaldavax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlaldavax_r_r_q_q(dst, src, src2, src3)) } +inst_vmlsdav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlsdav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdav_r_q_q(dst, src, src2)) } +inst_vmlsdava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlsdava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdava_r_q_q(dst, src, src2)) } +inst_vmlsdavx_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlsdavx_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdavx_r_q_q(dst, src, src2)) } +inst_vmlsdavax_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSDAVAX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlsdavax_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlsdavax_r_q_q(dst, src, src2)) } +inst_vmlsldav_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAV, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlsldav_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldav_r_r_q_q(dst, src, src2, src3)) } +inst_vmlsldava_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlsldava_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldava_r_r_q_q(dst, src, src2, src3)) } +inst_vmlsldavx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlsldavx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldavx_r_r_q_q(dst, src, src2, src3)) } +inst_vmlsldavax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMLSLDAVAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vmlsldavax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vmlsldavax_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlaldavh_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVH, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlaldavh_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavh_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlaldavha_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlaldavha_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavha_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlaldavhx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlaldavhx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavhx_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlaldavhax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLALDAVHAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlaldavhax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlaldavhax_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlsldavh_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVH, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlsldavh_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavh_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlsldavha_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHA, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlsldavha_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavha_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlsldavhx_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlsldavhx_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavhx_r_r_q_q(dst, src, src2, src3)) } +inst_vrmlsldavhax_r_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VRMLSLDAVHAX, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_reg(src3)}} } +emit_vrmlsldavhax_r_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_vrmlsldavhax_r_r_q_q(dst, src, src2, src3)) } +inst_vmlav_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAV, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlav_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlav_r_q_q(dst, src, src2)) } +inst_vmlava_r_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLAVA, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlava_r_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlava_r_q_q(dst, src, src2)) } +inst_vcmul_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VCMUL, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vcmul_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vcmul_q_q_q(dst, src, src2)) } +inst_vhcadd_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VHCADD, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vhcadd_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vhcadd_q_q_q(dst, src, src2)) } +inst_vbrsr_q_q_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBRSR, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbrsr_q_q_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbrsr_q_q_r(dst, src, src2)) } +inst_vshlc_q_r_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLC, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshlc_q_r_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshlc_q_r_imm5(dst, src, imm)) } +inst_vddup_q_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VDDUP, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vddup_q_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vddup_q_r_imm(dst, src, imm)) } +inst_vidup_q_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VIDUP, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vidup_q_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vidup_q_r_imm(dst, src, imm)) } +inst_vdwdup_q_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VDWDUP, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_vdwdup_q_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_vdwdup_q_r_r_imm(dst, src, src2, imm)) } +inst_viwdup_q_r_r_imm :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VIWDUP, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm)}} } +emit_viwdup_q_r_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_viwdup_q_r_r_imm(dst, src, src2, imm)) } +inst_vmovnb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmovnb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovnb_q_q(dst, src)) } +inst_vmovnt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VMOVNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vmovnt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vmovnt_q_q(dst, src)) } +inst_vqmovnb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovnb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovnb_q_q(dst, src)) } +inst_vqmovnt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovnt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovnt_q_q(dst, src)) } +inst_vqmovunb_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUNB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovunb_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovunb_q_q(dst, src)) } +inst_vqmovunt_q_q :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VQMOVUNT, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} } +emit_vqmovunt_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vqmovunt_q_q(dst, src)) } +inst_vshllb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshllb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshllb_q_q_imm5(dst, src, imm)) } +inst_vshllt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHLLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshllt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshllt_q_q_imm5(dst, src, imm)) } +inst_vmullb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmullb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmullb_q_q_q(dst, src, src2)) } +inst_vmullt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMULLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmullt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmullt_q_q_q(dst, src, src2)) } +inst_vmlalb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLALB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlalb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlalb_q_q_q(dst, src, src2)) } +inst_vmlalt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLALT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlalt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlalt_q_q_q(dst, src, src2)) } +inst_vmlslb_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSLB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlslb_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlslb_q_q_q(dst, src, src2)) } +inst_vmlslt_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VMLSLT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vmlslt_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vmlslt_q_q_q(dst, src, src2)) } +inst_vshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrnb_q_q_imm5(dst, src, imm)) } +inst_vshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vshrnt_q_q_imm5(dst, src, imm)) } +inst_vrshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vrshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrnb_q_q_imm5(dst, src, imm)) } +inst_vrshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VRSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vrshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vrshrnt_q_q_imm5(dst, src, imm)) } +inst_vqshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrnb_q_q_imm5(dst, src, imm)) } +inst_vqshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrnt_q_q_imm5(dst, src, imm)) } +inst_vqrshrnb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrnb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrnb_q_q_imm5(dst, src, imm)) } +inst_vqrshrnt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrnt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrnt_q_q_imm5(dst, src, imm)) } +inst_vqshrunb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrunb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrunb_q_q_imm5(dst, src, imm)) } +inst_vqshrunt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQSHRUNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqshrunt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqshrunt_q_q_imm5(dst, src, imm)) } +inst_vqrshrunb_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUNB, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrunb_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrunb_q_q_imm5(dst, src, imm)) } +inst_vqrshrunt_q_q_imm5 :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VQRSHRUNT, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm), {}}} } +emit_vqrshrunt_q_q_imm5 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_vqrshrunt_q_q_imm5(dst, src, imm)) } +inst_vmov_q_r_qlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_Q_R, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_reg(src), {}, {}}} } +emit_vmov_q_r_qlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_q_r_qlane_r(dst, lane, src)) } +inst_vmov_r_q_r_qlane :: #force_inline proc "contextless" (dst: Register, src: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VMOV_R_Q, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_qpr_lane(src, lane), {}, {}}} } +emit_vmov_r_q_r_qlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_q_r_qlane(dst, src, lane)) } +inst_vmov_2gpr_q_qlane_qlane_r_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .VMOV_2GPR_Q, operand_count = 4, mode = .T32, cond = 14, length = 4, ops = {op_qpr_lane(dst, lane), op_qpr_lane(src, lane2), op_reg(src2), op_reg(src3)}} } +emit_vmov_2gpr_q_qlane_qlane_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) { append(instructions, inst_vmov_2gpr_q_qlane_qlane_r_r(dst, lane, src, lane2, src2, src3)) } +inst_vqdmladh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLADH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmladh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmladh_q_q_q(dst, src, src2)) } +inst_vqdmladhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLADHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmladhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmladhx_q_q_q(dst, src, src2)) } +inst_vqdmlsdh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSDH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmlsdh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsdh_q_q_q(dst, src, src2)) } +inst_vqdmlsdhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQDMLSDHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqdmlsdhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmlsdhx_q_q_q(dst, src, src2)) } +inst_vqrdmladh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLADH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrdmladh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmladh_q_q_q(dst, src, src2)) } +inst_vqrdmladhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLADHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrdmladhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmladhx_q_q_q(dst, src, src2)) } +inst_vqrdmlsdh_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSDH, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrdmlsdh_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsdh_q_q_q(dst, src, src2)) } +inst_vqrdmlsdhx_q_q_q :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSDHX, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vqrdmlsdhx_q_q_q :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlsdhx_q_q_q(dst, src, src2)) } +inst_vldrb_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vldrb_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrb_q_mem(dst, src)) } +inst_vldrh_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vldrh_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrh_q_mem(dst, src)) } +inst_vldrw_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRW, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vldrw_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrw_q_mem(dst, src)) } +inst_vldrd_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDRD, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vldrd_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldrd_q_mem(dst, src)) } +inst_vstrb_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRB, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vstrb_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrb_q_mem(dst, src)) } +inst_vstrh_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRH, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vstrh_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrh_q_mem(dst, src)) } +inst_vstrw_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRW, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vstrw_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrw_q_mem(dst, src)) } +inst_vstrd_q_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTRD, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } +emit_vstrd_q_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vstrd_q_mem(dst, src)) } +inst_vld20_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD20, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld20_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld20_qlist_mem(regs, src)) } +inst_vld21_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD21, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld21_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld21_qlist_mem(regs, src)) } +inst_vld40_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD40, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld40_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld40_qlist_mem(regs, src)) } +inst_vld41_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD41, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld41_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld41_qlist_mem(regs, src)) } +inst_vld42_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD42, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld42_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld42_qlist_mem(regs, src)) } +inst_vld43_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD43, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vld43_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld43_qlist_mem(regs, src)) } +inst_vst20_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST20, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst20_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst20_qlist_mem(regs, src)) } +inst_vst21_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST21, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst21_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst21_qlist_mem(regs, src)) } +inst_vst40_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST40, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst40_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst40_qlist_mem(regs, src)) } +inst_vst41_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST41, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst41_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst41_qlist_mem(regs, src)) } +inst_vst42_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST42, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst42_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst42_qlist_mem(regs, src)) } +inst_vst43_qlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VST43, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} } +emit_vst43_qlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vst43_qlist_mem(regs, src)) } // ============================================================================= // Overload Groups // ============================================================================= -inst_and :: inst_and_rlo_rlo -emit_and :: emit_and_rlo_rlo -inst_eor :: inst_eor_rlo_rlo -emit_eor :: emit_eor_rlo_rlo -inst_sub :: proc{ inst_sub_rlo_rlo_rlo, inst_sub_rlo_rlo_imm3, inst_sub_rlo_imm8 } -emit_sub :: proc{ emit_sub_rlo_rlo_rlo, emit_sub_rlo_rlo_imm3, emit_sub_rlo_imm8 } -inst_add :: proc{ inst_add_rlo_rlo_rlo, inst_add_rlo_rlo_imm3, inst_add_rlo_imm8, inst_add_r_r } -emit_add :: proc{ emit_add_rlo_rlo_rlo, emit_add_rlo_rlo_imm3, emit_add_rlo_imm8, emit_add_r_r } -inst_adc :: inst_adc_rlo_rlo -emit_adc :: emit_adc_rlo_rlo -inst_sbc :: inst_sbc_rlo_rlo -emit_sbc :: emit_sbc_rlo_rlo -inst_tst :: inst_tst_rlo_rlo -emit_tst :: emit_tst_rlo_rlo -inst_cmp :: proc{ inst_cmp_rlo_imm8, inst_cmp_rlo_rlo } -emit_cmp :: proc{ emit_cmp_rlo_imm8, emit_cmp_rlo_rlo } -inst_cmn :: inst_cmn_rlo_rlo -emit_cmn :: emit_cmn_rlo_rlo -inst_orr :: inst_orr_rlo_rlo -emit_orr :: emit_orr_rlo_rlo -inst_mov :: proc{ inst_mov_rlo_imm8, inst_mov_r_r } -emit_mov :: proc{ emit_mov_rlo_imm8, emit_mov_r_r } -inst_bic :: inst_bic_rlo_rlo -emit_bic :: emit_bic_rlo_rlo -inst_mvn :: inst_mvn_rlo_rlo -emit_mvn :: emit_mvn_rlo_rlo -inst_lsl :: proc{ inst_lsl_r_r_imm5, inst_lsl_r_r_r, inst_lsl_rlo_rlo } -emit_lsl :: proc{ emit_lsl_r_r_imm5, emit_lsl_r_r_r, emit_lsl_rlo_rlo } -inst_lsr :: proc{ inst_lsr_r_r_imm5, inst_lsr_r_r_r, inst_lsr_rlo_rlo } -emit_lsr :: proc{ emit_lsr_r_r_imm5, emit_lsr_r_r_r, emit_lsr_rlo_rlo } -inst_asr :: proc{ inst_asr_r_r_imm5, inst_asr_r_r_r, inst_asr_rlo_rlo } -emit_asr :: proc{ emit_asr_r_r_imm5, emit_asr_r_r_r, emit_asr_rlo_rlo } -inst_ror :: proc{ inst_ror_r_r_imm5, inst_ror_r_r_r, inst_ror_rlo_rlo } -emit_ror :: proc{ emit_ror_r_r_imm5, emit_ror_r_r_r, emit_ror_rlo_rlo } -inst_rrx :: inst_rrx_r_r -emit_rrx :: emit_rrx_r_r -inst_adr :: inst_adr_rlo_rel -emit_adr :: emit_adr_rlo_rel -inst_neg :: inst_neg_rlo_rlo -emit_neg :: emit_neg_rlo_rlo -inst_movw :: inst_movw_r_imm16 -emit_movw :: emit_movw_r_imm16 -inst_movt :: inst_movt_r_imm16 -emit_movt :: emit_movt_r_imm16 -inst_bfc :: inst_bfc_r_imm5_imm5w -emit_bfc :: emit_bfc_r_imm5_imm5w -inst_bfi :: inst_bfi_r_r_imm5_imm5w -emit_bfi :: emit_bfi_r_r_imm5_imm5w -inst_sbfx :: inst_sbfx_r_r_imm5_imm5w -emit_sbfx :: emit_sbfx_r_r_imm5_imm5w -inst_ubfx :: inst_ubfx_r_r_imm5_imm5w -emit_ubfx :: emit_ubfx_r_r_imm5_imm5w -inst_sxtb :: inst_sxtb_r_r -emit_sxtb :: emit_sxtb_r_r -inst_sxtb16 :: inst_sxtb16_r_r -emit_sxtb16 :: emit_sxtb16_r_r -inst_sxth :: inst_sxth_r_r -emit_sxth :: emit_sxth_r_r -inst_uxtb :: inst_uxtb_r_r -emit_uxtb :: emit_uxtb_r_r -inst_uxtb16 :: inst_uxtb16_r_r -emit_uxtb16 :: emit_uxtb16_r_r -inst_uxth :: inst_uxth_r_r -emit_uxth :: emit_uxth_r_r -inst_sxtab :: inst_sxtab_r_r_r -emit_sxtab :: emit_sxtab_r_r_r -inst_sxtab16 :: inst_sxtab16_r_r_r -emit_sxtab16 :: emit_sxtab16_r_r_r -inst_sxtah :: inst_sxtah_r_r_r -emit_sxtah :: emit_sxtah_r_r_r -inst_uxtab :: inst_uxtab_r_r_r -emit_uxtab :: emit_uxtab_r_r_r -inst_uxtab16 :: inst_uxtab16_r_r_r -emit_uxtab16 :: emit_uxtab16_r_r_r -inst_uxtah :: inst_uxtah_r_r_r -emit_uxtah :: emit_uxtah_r_r_r -inst_clz :: inst_clz_r_r -emit_clz :: emit_clz_r_r -inst_rbit :: inst_rbit_r_r -emit_rbit :: emit_rbit_r_r -inst_rev :: inst_rev_r_r -emit_rev :: emit_rev_r_r -inst_rev16 :: inst_rev16_r_r -emit_rev16 :: emit_rev16_r_r -inst_revsh :: inst_revsh_r_r -emit_revsh :: emit_revsh_r_r -inst_sel :: inst_sel_r_r_r -emit_sel :: emit_sel_r_r_r -inst_usad8 :: inst_usad8_r_r_r -emit_usad8 :: emit_usad8_r_r_r -inst_usada8 :: inst_usada8_r_r_r_r -emit_usada8 :: emit_usada8_r_r_r_r -inst_ssat16 :: inst_ssat16_r_imm4s_r -emit_ssat16 :: emit_ssat16_r_imm4s_r -inst_usat16 :: inst_usat16_r_imm4s_r -emit_usat16 :: emit_usat16_r_imm4s_r -inst_qadd :: inst_qadd_r_r_r -emit_qadd :: emit_qadd_r_r_r -inst_qsub :: inst_qsub_r_r_r -emit_qsub :: emit_qsub_r_r_r -inst_qdadd :: inst_qdadd_r_r_r -emit_qdadd :: emit_qdadd_r_r_r -inst_qdsub :: inst_qdsub_r_r_r -emit_qdsub :: emit_qdsub_r_r_r -inst_sadd8 :: inst_sadd8_r_r_r -emit_sadd8 :: emit_sadd8_r_r_r -inst_sadd16 :: inst_sadd16_r_r_r -emit_sadd16 :: emit_sadd16_r_r_r -inst_sasx :: inst_sasx_r_r_r -emit_sasx :: emit_sasx_r_r_r -inst_ssax :: inst_ssax_r_r_r -emit_ssax :: emit_ssax_r_r_r -inst_ssub8 :: inst_ssub8_r_r_r -emit_ssub8 :: emit_ssub8_r_r_r -inst_ssub16 :: inst_ssub16_r_r_r -emit_ssub16 :: emit_ssub16_r_r_r -inst_uadd8 :: inst_uadd8_r_r_r -emit_uadd8 :: emit_uadd8_r_r_r -inst_uadd16 :: inst_uadd16_r_r_r -emit_uadd16 :: emit_uadd16_r_r_r -inst_uasx :: inst_uasx_r_r_r -emit_uasx :: emit_uasx_r_r_r -inst_usax :: inst_usax_r_r_r -emit_usax :: emit_usax_r_r_r -inst_usub8 :: inst_usub8_r_r_r -emit_usub8 :: emit_usub8_r_r_r -inst_usub16 :: inst_usub16_r_r_r -emit_usub16 :: emit_usub16_r_r_r -inst_qadd8 :: inst_qadd8_r_r_r -emit_qadd8 :: emit_qadd8_r_r_r -inst_qadd16 :: inst_qadd16_r_r_r -emit_qadd16 :: emit_qadd16_r_r_r -inst_qasx :: inst_qasx_r_r_r -emit_qasx :: emit_qasx_r_r_r -inst_qsax :: inst_qsax_r_r_r -emit_qsax :: emit_qsax_r_r_r -inst_qsub8 :: inst_qsub8_r_r_r -emit_qsub8 :: emit_qsub8_r_r_r -inst_qsub16 :: inst_qsub16_r_r_r -emit_qsub16 :: emit_qsub16_r_r_r -inst_uqadd8 :: inst_uqadd8_r_r_r -emit_uqadd8 :: emit_uqadd8_r_r_r -inst_uqadd16 :: inst_uqadd16_r_r_r -emit_uqadd16 :: emit_uqadd16_r_r_r -inst_uqasx :: inst_uqasx_r_r_r -emit_uqasx :: emit_uqasx_r_r_r -inst_uqsax :: inst_uqsax_r_r_r -emit_uqsax :: emit_uqsax_r_r_r -inst_uqsub8 :: inst_uqsub8_r_r_r -emit_uqsub8 :: emit_uqsub8_r_r_r -inst_uqsub16 :: inst_uqsub16_r_r_r -emit_uqsub16 :: emit_uqsub16_r_r_r -inst_shadd8 :: inst_shadd8_r_r_r -emit_shadd8 :: emit_shadd8_r_r_r -inst_shadd16 :: inst_shadd16_r_r_r -emit_shadd16 :: emit_shadd16_r_r_r -inst_shasx :: inst_shasx_r_r_r -emit_shasx :: emit_shasx_r_r_r -inst_shsax :: inst_shsax_r_r_r -emit_shsax :: emit_shsax_r_r_r -inst_shsub8 :: inst_shsub8_r_r_r -emit_shsub8 :: emit_shsub8_r_r_r -inst_shsub16 :: inst_shsub16_r_r_r -emit_shsub16 :: emit_shsub16_r_r_r -inst_uhadd8 :: inst_uhadd8_r_r_r -emit_uhadd8 :: emit_uhadd8_r_r_r -inst_uhadd16 :: inst_uhadd16_r_r_r -emit_uhadd16 :: emit_uhadd16_r_r_r -inst_uhasx :: inst_uhasx_r_r_r -emit_uhasx :: emit_uhasx_r_r_r -inst_uhsax :: inst_uhsax_r_r_r -emit_uhsax :: emit_uhsax_r_r_r -inst_uhsub8 :: inst_uhsub8_r_r_r -emit_uhsub8 :: emit_uhsub8_r_r_r -inst_uhsub16 :: inst_uhsub16_r_r_r -emit_uhsub16 :: emit_uhsub16_r_r_r -inst_smuad :: inst_smuad_r_r_r -emit_smuad :: emit_smuad_r_r_r -inst_smuadx :: inst_smuadx_r_r_r -emit_smuadx :: emit_smuadx_r_r_r -inst_smusd :: inst_smusd_r_r_r -emit_smusd :: emit_smusd_r_r_r -inst_smusdx :: inst_smusdx_r_r_r -emit_smusdx :: emit_smusdx_r_r_r -inst_smlad :: inst_smlad_r_r_r_r -emit_smlad :: emit_smlad_r_r_r_r -inst_smladx :: inst_smladx_r_r_r_r -emit_smladx :: emit_smladx_r_r_r_r -inst_smlsd :: inst_smlsd_r_r_r_r -emit_smlsd :: emit_smlsd_r_r_r_r -inst_smlsdx :: inst_smlsdx_r_r_r_r -emit_smlsdx :: emit_smlsdx_r_r_r_r -inst_smlald :: inst_smlald_r_r_r_r -emit_smlald :: emit_smlald_r_r_r_r -inst_smlaldx :: inst_smlaldx_r_r_r_r -emit_smlaldx :: emit_smlaldx_r_r_r_r -inst_smlsld :: inst_smlsld_r_r_r_r -emit_smlsld :: emit_smlsld_r_r_r_r -inst_smlsldx :: inst_smlsldx_r_r_r_r -emit_smlsldx :: emit_smlsldx_r_r_r_r -inst_smmul :: inst_smmul_r_r_r -emit_smmul :: emit_smmul_r_r_r -inst_smmulr :: inst_smmulr_r_r_r -emit_smmulr :: emit_smmulr_r_r_r -inst_smmla :: inst_smmla_r_r_r_r -emit_smmla :: emit_smmla_r_r_r_r -inst_smmlar :: inst_smmlar_r_r_r_r -emit_smmlar :: emit_smmlar_r_r_r_r -inst_smmls :: inst_smmls_r_r_r_r -emit_smmls :: emit_smmls_r_r_r_r -inst_smmlsr :: inst_smmlsr_r_r_r_r -emit_smmlsr :: emit_smmlsr_r_r_r_r -inst_mul :: proc{ inst_mul_r_r_r, inst_mul_rlo_rlo } -emit_mul :: proc{ emit_mul_r_r_r, emit_mul_rlo_rlo } -inst_mla :: inst_mla_r_r_r_r -emit_mla :: emit_mla_r_r_r_r -inst_mls :: inst_mls_r_r_r_r -emit_mls :: emit_mls_r_r_r_r -inst_umull :: inst_umull_r_r_r_r -emit_umull :: emit_umull_r_r_r_r -inst_umlal :: inst_umlal_r_r_r_r -emit_umlal :: emit_umlal_r_r_r_r -inst_smull :: inst_smull_r_r_r_r -emit_smull :: emit_smull_r_r_r_r -inst_smlal :: inst_smlal_r_r_r_r -emit_smlal :: emit_smlal_r_r_r_r -inst_umaal :: inst_umaal_r_r_r_r -emit_umaal :: emit_umaal_r_r_r_r -inst_smlabb :: inst_smlabb_r_r_r_r -emit_smlabb :: emit_smlabb_r_r_r_r -inst_smlabt :: inst_smlabt_r_r_r_r -emit_smlabt :: emit_smlabt_r_r_r_r -inst_smlatb :: inst_smlatb_r_r_r_r -emit_smlatb :: emit_smlatb_r_r_r_r -inst_smlatt :: inst_smlatt_r_r_r_r -emit_smlatt :: emit_smlatt_r_r_r_r -inst_smlawb :: inst_smlawb_r_r_r_r -emit_smlawb :: emit_smlawb_r_r_r_r -inst_smlawt :: inst_smlawt_r_r_r_r -emit_smlawt :: emit_smlawt_r_r_r_r -inst_smulbb :: inst_smulbb_r_r_r -emit_smulbb :: emit_smulbb_r_r_r -inst_smulbt :: inst_smulbt_r_r_r -emit_smulbt :: emit_smulbt_r_r_r -inst_smultb :: inst_smultb_r_r_r -emit_smultb :: emit_smultb_r_r_r -inst_smultt :: inst_smultt_r_r_r -emit_smultt :: emit_smultt_r_r_r -inst_smulwb :: inst_smulwb_r_r_r -emit_smulwb :: emit_smulwb_r_r_r -inst_smulwt :: inst_smulwt_r_r_r -emit_smulwt :: emit_smulwt_r_r_r -inst_smlalbb :: inst_smlalbb_r_r_r_r -emit_smlalbb :: emit_smlalbb_r_r_r_r -inst_smlalbt :: inst_smlalbt_r_r_r_r -emit_smlalbt :: emit_smlalbt_r_r_r_r -inst_smlaltb :: inst_smlaltb_r_r_r_r -emit_smlaltb :: emit_smlaltb_r_r_r_r -inst_smlaltt :: inst_smlaltt_r_r_r_r -emit_smlaltt :: emit_smlaltt_r_r_r_r -inst_sdiv :: inst_sdiv_r_r_r -emit_sdiv :: emit_sdiv_r_r_r -inst_udiv :: inst_udiv_r_r_r -emit_udiv :: emit_udiv_r_r_r -inst_b :: inst_b_rel -emit_b :: emit_b_rel -inst_bl :: inst_bl_rel -emit_bl :: emit_bl_rel -inst_bx :: inst_bx_r -emit_bx :: emit_bx_r -inst_blx :: proc{ inst_blx_r, inst_blx_rel } -emit_blx :: proc{ emit_blx_r, emit_blx_rel } -inst_bxj :: inst_bxj_r -emit_bxj :: emit_bxj_r -inst_cbz :: inst_cbz_rlo_rel -emit_cbz :: emit_cbz_rlo_rel -inst_cbnz :: inst_cbnz_rlo_rel -emit_cbnz :: emit_cbnz_rlo_rel -inst_tbb :: inst_tbb_r_r -emit_tbb :: emit_tbb_r_r -inst_tbh :: inst_tbh_r_r -emit_tbh :: emit_tbh_r_r -inst_nop :: inst_nop_none -emit_nop :: emit_nop_none -inst_yield :: inst_yield_none -emit_yield :: emit_yield_none -inst_wfe :: inst_wfe_none -emit_wfe :: emit_wfe_none -inst_wfi :: inst_wfi_none -emit_wfi :: emit_wfi_none -inst_sev :: inst_sev_none -emit_sev :: emit_sev_none -inst_sevl :: inst_sevl_none -emit_sevl :: emit_sevl_none -inst_clrex :: inst_clrex_none -emit_clrex :: emit_clrex_none -inst_pld :: inst_pld_mem -emit_pld :: emit_pld_mem -inst_pldw :: inst_pldw_mem -emit_pldw :: emit_pldw_mem -inst_pli :: inst_pli_mem -emit_pli :: emit_pli_mem -inst_hlt :: inst_hlt_imm -emit_hlt :: emit_hlt_imm -inst_eret :: inst_eret_none -emit_eret :: emit_eret_none -inst_esb :: inst_esb_none -emit_esb :: emit_esb_none -inst_psb_csync :: inst_psb_csync_none -emit_psb_csync :: emit_psb_csync_none -inst_tsb_csync :: inst_tsb_csync_none -emit_tsb_csync :: emit_tsb_csync_none -inst_csdb :: inst_csdb_none -emit_csdb :: emit_csdb_none -inst_sb :: inst_sb_none -emit_sb :: emit_sb_none -inst_svc :: inst_svc_imm -emit_svc :: emit_svc_imm -inst_bkpt :: inst_bkpt_imm -emit_bkpt :: emit_bkpt_imm -inst_hvc :: inst_hvc_imm -emit_hvc :: emit_hvc_imm -inst_smc :: inst_smc_imm -emit_smc :: emit_smc_imm -inst_udf :: inst_udf_imm -emit_udf :: emit_udf_imm -inst_ldr :: inst_ldr_r_mem -emit_ldr :: emit_ldr_r_mem -inst_str :: inst_str_r_mem -emit_str :: emit_str_r_mem -inst_ldrb :: inst_ldrb_r_mem -emit_ldrb :: emit_ldrb_r_mem -inst_strb :: inst_strb_r_mem -emit_strb :: emit_strb_r_mem -inst_ldrh :: inst_ldrh_r_mem -emit_ldrh :: emit_ldrh_r_mem -inst_strh :: inst_strh_r_mem -emit_strh :: emit_strh_r_mem -inst_ldrsb :: inst_ldrsb_r_mem -emit_ldrsb :: emit_ldrsb_r_mem -inst_ldrsh :: inst_ldrsh_r_mem -emit_ldrsh :: emit_ldrsh_r_mem -inst_ldrd :: proc{ inst_ldrd_r_mem, inst_ldrd_r_r_mem } -emit_ldrd :: proc{ emit_ldrd_r_mem, emit_ldrd_r_r_mem } -inst_strd :: proc{ inst_strd_r_mem, inst_strd_r_r_mem } -emit_strd :: proc{ emit_strd_r_mem, emit_strd_r_r_mem } -inst_lda :: inst_lda_r_mem -emit_lda :: emit_lda_r_mem -inst_stl :: inst_stl_r_mem -emit_stl :: emit_stl_r_mem -inst_ldab :: inst_ldab_r_mem -emit_ldab :: emit_ldab_r_mem -inst_stlb :: inst_stlb_r_mem -emit_stlb :: emit_stlb_r_mem -inst_ldah :: inst_ldah_r_mem -emit_ldah :: emit_ldah_r_mem -inst_stlh :: inst_stlh_r_mem -emit_stlh :: emit_stlh_r_mem -inst_ldrex :: inst_ldrex_r_mem -emit_ldrex :: emit_ldrex_r_mem -inst_strex :: inst_strex_r_r_mem -emit_strex :: emit_strex_r_r_mem -inst_ldrexb :: inst_ldrexb_r_mem -emit_ldrexb :: emit_ldrexb_r_mem -inst_strexb :: inst_strexb_r_r_mem -emit_strexb :: emit_strexb_r_r_mem -inst_ldrexh :: inst_ldrexh_r_mem -emit_ldrexh :: emit_ldrexh_r_mem -inst_strexh :: inst_strexh_r_r_mem -emit_strexh :: emit_strexh_r_r_mem -inst_ldrexd :: proc{ inst_ldrexd_r_mem, inst_ldrexd_r_r_mem } -emit_ldrexd :: proc{ emit_ldrexd_r_mem, emit_ldrexd_r_r_mem } -inst_strexd :: proc{ inst_strexd_r_r_mem, inst_strexd_r_r_r_mem } -emit_strexd :: proc{ emit_strexd_r_r_mem, emit_strexd_r_r_r_mem } -inst_ldaex :: inst_ldaex_r_mem -emit_ldaex :: emit_ldaex_r_mem -inst_stlex :: inst_stlex_r_r_mem -emit_stlex :: emit_stlex_r_r_mem -inst_ldaexb :: inst_ldaexb_r_mem -emit_ldaexb :: emit_ldaexb_r_mem -inst_stlexb :: inst_stlexb_r_r_mem -emit_stlexb :: emit_stlexb_r_r_mem -inst_ldaexh :: inst_ldaexh_r_mem -emit_ldaexh :: emit_ldaexh_r_mem -inst_stlexh :: inst_stlexh_r_r_mem -emit_stlexh :: emit_stlexh_r_r_mem -inst_ldaexd :: inst_ldaexd_r_mem -emit_ldaexd :: emit_ldaexd_r_mem -inst_stlexd :: inst_stlexd_r_r_mem -emit_stlexd :: emit_stlexd_r_r_mem -inst_swp :: inst_swp_r_r_r -emit_swp :: emit_swp_r_r_r -inst_swpb :: inst_swpb_r_r_r -emit_swpb :: emit_swpb_r_r_r -inst_rfe :: inst_rfe_r -emit_rfe :: emit_rfe_r -inst_srs :: inst_srs_imm -emit_srs :: emit_srs_imm -inst_crc32b :: inst_crc32b_r_r_r -emit_crc32b :: emit_crc32b_r_r_r -inst_crc32h :: inst_crc32h_r_r_r -emit_crc32h :: emit_crc32h_r_r_r -inst_crc32w :: inst_crc32w_r_r_r -emit_crc32w :: emit_crc32w_r_r_r -inst_crc32cb :: inst_crc32cb_r_r_r -emit_crc32cb :: emit_crc32cb_r_r_r -inst_crc32ch :: inst_crc32ch_r_r_r -emit_crc32ch :: emit_crc32ch_r_r_r -inst_crc32cw :: inst_crc32cw_r_r_r -emit_crc32cw :: emit_crc32cw_r_r_r -inst_vadd :: inst_vadd_s_s_s -emit_vadd :: emit_vadd_s_s_s -inst_vsub :: inst_vsub_s_s_s -emit_vsub :: emit_vsub_s_s_s -inst_vmul :: inst_vmul_s_s_s -emit_vmul :: emit_vmul_s_s_s -inst_vdiv :: inst_vdiv_s_s_s -emit_vdiv :: emit_vdiv_s_s_s -inst_vmla :: inst_vmla_s_s_s -emit_vmla :: emit_vmla_s_s_s -inst_vmls :: inst_vmls_s_s_s -emit_vmls :: emit_vmls_s_s_s -inst_vnmul :: inst_vnmul_s_s_s -emit_vnmul :: emit_vnmul_s_s_s -inst_vnmla :: inst_vnmla_s_s_s -emit_vnmla :: emit_vnmla_s_s_s -inst_vnmls :: inst_vnmls_s_s_s -emit_vnmls :: emit_vnmls_s_s_s -inst_vfma :: inst_vfma_s_s_s -emit_vfma :: emit_vfma_s_s_s -inst_vfms :: inst_vfms_s_s_s -emit_vfms :: emit_vfms_s_s_s -inst_vfnma :: inst_vfnma_s_s_s -emit_vfnma :: emit_vfnma_s_s_s -inst_vfnms :: inst_vfnms_s_s_s -emit_vfnms :: emit_vfnms_s_s_s -inst_vabs :: inst_vabs_s_s -emit_vabs :: emit_vabs_s_s -inst_vneg :: inst_vneg_s_s -emit_vneg :: emit_vneg_s_s -inst_vsqrt :: inst_vsqrt_s_s -emit_vsqrt :: emit_vsqrt_s_s -inst_vcmp :: proc{ inst_vcmp_s_s, inst_vcmp_s } -emit_vcmp :: proc{ emit_vcmp_s_s, emit_vcmp_s } -inst_vcmpe :: proc{ inst_vcmpe_s_s, inst_vcmpe_s } -emit_vcmpe :: proc{ emit_vcmpe_s_s, emit_vcmpe_s } -inst_vcvt :: inst_vcvt_d_s -emit_vcvt :: emit_vcvt_d_s -inst_vcvtb :: inst_vcvtb_s_s -emit_vcvtb :: emit_vcvtb_s_s -inst_vcvtt :: inst_vcvtt_s_s -emit_vcvtt :: emit_vcvtt_s_s -inst_vcvta :: inst_vcvta_s_s -emit_vcvta :: emit_vcvta_s_s -inst_vcvtn :: inst_vcvtn_s_s -emit_vcvtn :: emit_vcvtn_s_s -inst_vcvtp :: inst_vcvtp_s_s -emit_vcvtp :: emit_vcvtp_s_s -inst_vcvtm :: inst_vcvtm_s_s -emit_vcvtm :: emit_vcvtm_s_s -inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s } -emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s } -inst_vmrs :: inst_vmrs_r -emit_vmrs :: emit_vmrs_r -inst_vmsr :: inst_vmsr_r -emit_vmsr :: emit_vmsr_r -inst_vldr :: inst_vldr_s_mem -emit_vldr :: emit_vldr_s_mem -inst_vstr :: inst_vstr_s_mem -emit_vstr :: emit_vstr_s_mem -inst_vmaxnm :: inst_vmaxnm_s_s_s -emit_vmaxnm :: emit_vmaxnm_s_s_s -inst_vminnm :: inst_vminnm_s_s_s -emit_vminnm :: emit_vminnm_s_s_s -inst_vrinta :: inst_vrinta_s_s -emit_vrinta :: emit_vrinta_s_s -inst_vrintn :: inst_vrintn_s_s -emit_vrintn :: emit_vrintn_s_s -inst_vrintp :: inst_vrintp_s_s -emit_vrintp :: emit_vrintp_s_s -inst_vrintm :: inst_vrintm_s_s -emit_vrintm :: emit_vrintm_s_s -inst_vrintr :: inst_vrintr_s_s -emit_vrintr :: emit_vrintr_s_s -inst_vrintz :: inst_vrintz_s_s -emit_vrintz :: emit_vrintz_s_s -inst_vrintx :: inst_vrintx_s_s -emit_vrintx :: emit_vrintx_s_s -inst_vhadd :: inst_vhadd_d_d_d -emit_vhadd :: emit_vhadd_d_d_d -inst_vhsub :: inst_vhsub_d_d_d -emit_vhsub :: emit_vhsub_d_d_d -inst_vrhadd :: inst_vrhadd_d_d_d -emit_vrhadd :: emit_vrhadd_d_d_d -inst_vqadd :: inst_vqadd_d_d_d -emit_vqadd :: emit_vqadd_d_d_d -inst_vqsub :: inst_vqsub_d_d_d -emit_vqsub :: emit_vqsub_d_d_d -inst_vmull :: inst_vmull_q_d_d -emit_vmull :: emit_vmull_q_d_d -inst_vmlal :: inst_vmlal_q_d_d -emit_vmlal :: emit_vmlal_q_d_d -inst_vmlsl :: inst_vmlsl_q_d_d -emit_vmlsl :: emit_vmlsl_q_d_d -inst_vqdmull :: inst_vqdmull_q_d_d -emit_vqdmull :: emit_vqdmull_q_d_d -inst_vqdmlal :: inst_vqdmlal_q_d_d -emit_vqdmlal :: emit_vqdmlal_q_d_d -inst_vqdmlsl :: inst_vqdmlsl_q_d_d -emit_vqdmlsl :: emit_vqdmlsl_q_d_d -inst_vqdmulh :: inst_vqdmulh_d_d_d -emit_vqdmulh :: emit_vqdmulh_d_d_d -inst_vqrdmulh :: inst_vqrdmulh_d_d_d -emit_vqrdmulh :: emit_vqrdmulh_d_d_d -inst_vqrdmlah :: inst_vqrdmlah_d_d_d -emit_vqrdmlah :: emit_vqrdmlah_d_d_d -inst_vqrdmlsh :: inst_vqrdmlsh_d_d_d -emit_vqrdmlsh :: emit_vqrdmlsh_d_d_d -inst_vaba :: inst_vaba_d_d_d -emit_vaba :: emit_vaba_d_d_d -inst_vabd :: inst_vabd_d_d_d -emit_vabd :: emit_vabd_d_d_d -inst_vand :: inst_vand_d_d_d -emit_vand :: emit_vand_d_d_d -inst_vbic :: inst_vbic_d_d_d -emit_vbic :: emit_vbic_d_d_d -inst_vorr :: inst_vorr_d_d_d -emit_vorr :: emit_vorr_d_d_d -inst_vorn :: inst_vorn_d_d_d -emit_vorn :: emit_vorn_d_d_d -inst_veor :: inst_veor_d_d_d -emit_veor :: emit_veor_d_d_d -inst_vbsl :: inst_vbsl_d_d_d -emit_vbsl :: emit_vbsl_d_d_d -inst_vbit :: inst_vbit_d_d_d -emit_vbit :: emit_vbit_d_d_d -inst_vbif :: inst_vbif_d_d_d -emit_vbif :: emit_vbif_d_d_d -inst_vmvn :: proc{ inst_vmvn_d_d, inst_vmvn_d_imm } -emit_vmvn :: proc{ emit_vmvn_d_d, emit_vmvn_d_imm } -inst_vmovn :: inst_vmovn_d_q -emit_vmovn :: emit_vmovn_d_q -inst_vqmovn :: inst_vqmovn_d_q -emit_vqmovn :: emit_vqmovn_d_q -inst_vqmovun :: inst_vqmovun_d_q -emit_vqmovun :: emit_vqmovun_d_q -inst_vmovl :: inst_vmovl_q_d -emit_vmovl :: emit_vmovl_q_d -inst_vtst :: inst_vtst_d_d_d -emit_vtst :: emit_vtst_d_d_d -inst_vceq :: inst_vceq_d_d_d -emit_vceq :: emit_vceq_d_d_d -inst_vcge :: inst_vcge_d_d_d -emit_vcge :: emit_vcge_d_d_d -inst_vcgt :: inst_vcgt_d_d_d -emit_vcgt :: emit_vcgt_d_d_d -inst_vacge :: inst_vacge_d_d_d -emit_vacge :: emit_vacge_d_d_d -inst_vacgt :: inst_vacgt_d_d_d -emit_vacgt :: emit_vacgt_d_d_d -inst_vmax :: inst_vmax_d_d_d -emit_vmax :: emit_vmax_d_d_d -inst_vmin :: inst_vmin_d_d_d -emit_vmin :: emit_vmin_d_d_d -inst_vpmax :: inst_vpmax_d_d_d -emit_vpmax :: emit_vpmax_d_d_d -inst_vpmin :: inst_vpmin_d_d_d -emit_vpmin :: emit_vpmin_d_d_d -inst_vpadd :: inst_vpadd_d_d_d -emit_vpadd :: emit_vpadd_d_d_d -inst_vpaddl :: inst_vpaddl_d_d -emit_vpaddl :: emit_vpaddl_d_d -inst_vpadal :: inst_vpadal_d_d -emit_vpadal :: emit_vpadal_d_d -inst_vrecpe :: inst_vrecpe_d_d -emit_vrecpe :: emit_vrecpe_d_d -inst_vrecps :: inst_vrecps_d_d_d -emit_vrecps :: emit_vrecps_d_d_d -inst_vrsqrte :: inst_vrsqrte_d_d -emit_vrsqrte :: emit_vrsqrte_d_d -inst_vrsqrts :: inst_vrsqrts_d_d_d -emit_vrsqrts :: emit_vrsqrts_d_d_d -inst_vshl :: inst_vshl_d_d_d -emit_vshl :: emit_vshl_d_d_d -inst_vshr :: inst_vshr_d_d_imm -emit_vshr :: emit_vshr_d_d_imm -inst_vsra :: inst_vsra_d_d_imm -emit_vsra :: emit_vsra_d_d_imm -inst_vrshl :: inst_vrshl_d_d_d -emit_vrshl :: emit_vrshl_d_d_d -inst_vrshr :: inst_vrshr_d_d_imm -emit_vrshr :: emit_vrshr_d_d_imm -inst_vsli :: inst_vsli_d_d_imm -emit_vsli :: emit_vsli_d_d_imm -inst_vsri :: inst_vsri_d_d_imm -emit_vsri :: emit_vsri_d_d_imm -inst_vqshl :: proc{ inst_vqshl_d_d_d, inst_vqshl_d_d_imm } -emit_vqshl :: proc{ emit_vqshl_d_d_d, emit_vqshl_d_d_imm } -inst_vqshrn :: inst_vqshrn_d_q_imm -emit_vqshrn :: emit_vqshrn_d_q_imm -inst_vqshrun :: inst_vqshrun_d_q_imm -emit_vqshrun :: emit_vqshrun_d_q_imm -inst_vqrshrn :: inst_vqrshrn_d_q_imm -emit_vqrshrn :: emit_vqrshrn_d_q_imm -inst_vqrshrun :: inst_vqrshrun_d_q_imm -emit_vqrshrun :: emit_vqrshrun_d_q_imm -inst_vshrn :: inst_vshrn_d_q_imm -emit_vshrn :: emit_vshrn_d_q_imm -inst_vrshrn :: inst_vrshrn_d_q_imm -emit_vrshrn :: emit_vrshrn_d_q_imm -inst_vshll :: proc{ inst_vshll_q_d_imm, inst_vshll_q_d } -emit_vshll :: proc{ emit_vshll_q_d_imm, emit_vshll_q_d } -inst_vcls :: inst_vcls_d_d -emit_vcls :: emit_vcls_d_d -inst_vclz :: inst_vclz_d_d -emit_vclz :: emit_vclz_d_d -inst_vcnt :: inst_vcnt_d_d -emit_vcnt :: emit_vcnt_d_d -inst_vrev16 :: inst_vrev16_d_d -emit_vrev16 :: emit_vrev16_d_d -inst_vrev32 :: inst_vrev32_d_d -emit_vrev32 :: emit_vrev32_d_d -inst_vrev64 :: inst_vrev64_d_d -emit_vrev64 :: emit_vrev64_d_d -inst_vext :: inst_vext_d_d_d_imm4 -emit_vext :: emit_vext_d_d_d_imm4 -inst_vtbl :: inst_vtbl_d_d_d -emit_vtbl :: emit_vtbl_d_d_d -inst_vtbx :: inst_vtbx_d_d_d -emit_vtbx :: emit_vtbx_d_d_d -inst_vtrn :: inst_vtrn_d_d -emit_vtrn :: emit_vtrn_d_d -inst_vuzp :: inst_vuzp_d_d -emit_vuzp :: emit_vuzp_d_d -inst_vzip :: inst_vzip_d_d -emit_vzip :: emit_vzip_d_d -inst_vdup :: inst_vdup_d_r -emit_vdup :: emit_vdup_d_r -inst_vswp :: inst_vswp_d_d -emit_vswp :: emit_vswp_d_d -inst_aese :: inst_aese_q_q -emit_aese :: emit_aese_q_q -inst_aesd :: inst_aesd_q_q -emit_aesd :: emit_aesd_q_q -inst_aesmc :: inst_aesmc_q_q -emit_aesmc :: emit_aesmc_q_q -inst_aesimc :: inst_aesimc_q_q -emit_aesimc :: emit_aesimc_q_q -inst_sha1h :: inst_sha1h_q_q -emit_sha1h :: emit_sha1h_q_q -inst_sha1su0 :: inst_sha1su0_q_q_q -emit_sha1su0 :: emit_sha1su0_q_q_q -inst_sha1su1 :: inst_sha1su1_q_q -emit_sha1su1 :: emit_sha1su1_q_q -inst_sha1c :: inst_sha1c_q_q_q -emit_sha1c :: emit_sha1c_q_q_q -inst_sha1m :: inst_sha1m_q_q_q -emit_sha1m :: emit_sha1m_q_q_q -inst_sha1p :: inst_sha1p_q_q_q -emit_sha1p :: emit_sha1p_q_q_q -inst_sha256h :: inst_sha256h_q_q_q -emit_sha256h :: emit_sha256h_q_q_q -inst_sha256h2 :: inst_sha256h2_q_q_q -emit_sha256h2 :: emit_sha256h2_q_q_q -inst_sha256su0 :: inst_sha256su0_q_q -emit_sha256su0 :: emit_sha256su0_q_q -inst_sha256su1 :: inst_sha256su1_q_q_q -emit_sha256su1 :: emit_sha256su1_q_q_q -inst_vjcvt :: inst_vjcvt_s_d -emit_vjcvt :: emit_vjcvt_s_d -inst_vsdot :: inst_vsdot_d_d_d -emit_vsdot :: emit_vsdot_d_d_d -inst_vudot :: inst_vudot_d_d_d -emit_vudot :: emit_vudot_d_d_d -inst_vcvt_bf16 :: inst_vcvt_bf16_d_q -emit_vcvt_bf16 :: emit_vcvt_bf16_d_q -inst_vdot_bf16 :: inst_vdot_bf16_d_d_d -emit_vdot_bf16 :: emit_vdot_bf16_d_d_d -inst_vfma_bf16 :: inst_vfma_bf16_q_q_q -emit_vfma_bf16 :: emit_vfma_bf16_q_q_q -inst_vmmla_bf16 :: inst_vmmla_bf16_q_q_q -emit_vmmla_bf16 :: emit_vmmla_bf16_q_q_q -inst_vfmal :: inst_vfmal_d_d_d -emit_vfmal :: emit_vfmal_d_d_d -inst_vfmsl :: inst_vfmsl_d_d_d -emit_vfmsl :: emit_vfmsl_d_d_d -inst_vcmla :: inst_vcmla_d_d_d_imm -emit_vcmla :: emit_vcmla_d_d_d_imm -inst_vcadd :: inst_vcadd_d_d_d_imm -emit_vcadd :: emit_vcadd_d_d_d_imm -inst_vsmmla :: inst_vsmmla_q_q_q -emit_vsmmla :: emit_vsmmla_q_q_q -inst_vummla :: inst_vummla_q_q_q -emit_vummla :: emit_vummla_q_q_q -inst_vusmmla :: inst_vusmmla_q_q_q -emit_vusmmla :: emit_vusmmla_q_q_q -inst_vsudot :: inst_vsudot_q_q_q -emit_vsudot :: emit_vsudot_q_q_q -inst_vusdot :: inst_vusdot_d_d_d -emit_vusdot :: emit_vusdot_d_d_d -inst_vqabs :: inst_vqabs_q_q -emit_vqabs :: emit_vqabs_q_q -inst_vqneg :: inst_vqneg_q_q -emit_vqneg :: emit_vqneg_q_q -inst_vmovx :: inst_vmovx_s_s -emit_vmovx :: emit_vmovx_s_s -inst_vins :: inst_vins_s_s -emit_vins :: emit_vins_s_s -inst_vldrb_gather :: inst_vldrb_gather_q_mem_q -emit_vldrb_gather :: emit_vldrb_gather_q_mem_q -inst_vldrh_gather :: inst_vldrh_gather_q_mem_q -emit_vldrh_gather :: emit_vldrh_gather_q_mem_q -inst_vldrw_gather :: inst_vldrw_gather_q_mem_q -emit_vldrw_gather :: emit_vldrw_gather_q_mem_q -inst_vldrd_gather :: inst_vldrd_gather_q_mem_q -emit_vldrd_gather :: emit_vldrd_gather_q_mem_q -inst_vstrb_scatter :: inst_vstrb_scatter_q_mem_q -emit_vstrb_scatter :: emit_vstrb_scatter_q_mem_q -inst_vstrh_scatter :: inst_vstrh_scatter_q_mem_q -emit_vstrh_scatter :: emit_vstrh_scatter_q_mem_q -inst_vstrw_scatter :: inst_vstrw_scatter_q_mem_q -emit_vstrw_scatter :: emit_vstrw_scatter_q_mem_q -inst_vstrd_scatter :: inst_vstrd_scatter_q_mem_q -emit_vstrd_scatter :: emit_vstrd_scatter_q_mem_q -inst_vceq_z :: inst_vceq_z_d_d -emit_vceq_z :: emit_vceq_z_d_d -inst_vcge_z :: inst_vcge_z_d_d -emit_vcge_z :: emit_vcge_z_d_d -inst_vcgt_z :: inst_vcgt_z_d_d -emit_vcgt_z :: emit_vcgt_z_d_d -inst_vcle_z :: inst_vcle_z_d_d -emit_vcle_z :: emit_vcle_z_d_d -inst_vclt_z :: inst_vclt_z_d_d -emit_vclt_z :: emit_vclt_z_d_d -inst_vcvt_fixed :: inst_vcvt_fixed_s_s_imm -emit_vcvt_fixed :: emit_vcvt_fixed_s_s_imm -inst_tt :: inst_tt_r_r -emit_tt :: emit_tt_r_r -inst_ttt :: inst_ttt_r_r -emit_ttt :: emit_ttt_r_r -inst_tta :: inst_tta_r_r -emit_tta :: emit_tta_r_r -inst_ttat :: inst_ttat_r_r -emit_ttat :: emit_ttat_r_r -inst_sg :: inst_sg_none -emit_sg :: emit_sg_none -inst_bxns :: inst_bxns_r -emit_bxns :: emit_bxns_r -inst_blxns :: inst_blxns_r -emit_blxns :: emit_blxns_r -inst_pac :: inst_pac_none -emit_pac :: emit_pac_none -inst_pacbti :: inst_pacbti_none -emit_pacbti :: emit_pacbti_none -inst_aut :: inst_aut_none -emit_aut :: emit_aut_none -inst_autg :: inst_autg_r_r_r -emit_autg :: emit_autg_r_r_r -inst_bti :: inst_bti_none -emit_bti :: emit_bti_none -inst_wls :: inst_wls_r_rel -emit_wls :: emit_wls_r_rel -inst_wlstp :: inst_wlstp_r_rel -emit_wlstp :: emit_wlstp_r_rel -inst_dls :: inst_dls_r -emit_dls :: emit_dls_r -inst_dlstp :: inst_dlstp_r -emit_dlstp :: emit_dlstp_r -inst_le :: inst_le_rel -emit_le :: emit_le_rel -inst_letp :: inst_letp_rel -emit_letp :: emit_letp_rel -inst_lctp :: inst_lctp_none -emit_lctp :: emit_lctp_none -inst_vpsel :: inst_vpsel_q_q_q -emit_vpsel :: emit_vpsel_q_q_q -inst_vpnot :: inst_vpnot_none -emit_vpnot :: emit_vpnot_none -inst_vctp :: inst_vctp_r -emit_vctp :: emit_vctp_r -inst_vaddv :: inst_vaddv_r_q -emit_vaddv :: emit_vaddv_r_q -inst_vaddva :: inst_vaddva_r_q -emit_vaddva :: emit_vaddva_r_q -inst_vaddlv :: inst_vaddlv_r_r_q -emit_vaddlv :: emit_vaddlv_r_r_q -inst_vaddlva :: inst_vaddlva_r_r_q -emit_vaddlva :: emit_vaddlva_r_r_q -inst_vmaxv :: inst_vmaxv_r_q -emit_vmaxv :: emit_vmaxv_r_q -inst_vmaxav :: inst_vmaxav_r_q -emit_vmaxav :: emit_vmaxav_r_q -inst_vminv :: inst_vminv_r_q -emit_vminv :: emit_vminv_r_q -inst_vminav :: inst_vminav_r_q -emit_vminav :: emit_vminav_r_q -inst_vmaxnmv :: inst_vmaxnmv_r_q -emit_vmaxnmv :: emit_vmaxnmv_r_q -inst_vmaxnmav :: inst_vmaxnmav_r_q -emit_vmaxnmav :: emit_vmaxnmav_r_q -inst_vminnmv :: inst_vminnmv_r_q -emit_vminnmv :: emit_vminnmv_r_q -inst_vminnmav :: inst_vminnmav_r_q -emit_vminnmav :: emit_vminnmav_r_q -inst_vabav :: inst_vabav_r_q_q -emit_vabav :: emit_vabav_r_q_q -inst_vmladav :: inst_vmladav_r_q_q -emit_vmladav :: emit_vmladav_r_q_q -inst_vmladava :: inst_vmladava_r_q_q -emit_vmladava :: emit_vmladava_r_q_q -inst_vmladavx :: inst_vmladavx_r_q_q -emit_vmladavx :: emit_vmladavx_r_q_q -inst_vmladavax :: inst_vmladavax_r_q_q -emit_vmladavax :: emit_vmladavax_r_q_q -inst_vmlaldav :: inst_vmlaldav_r_r_q_q -emit_vmlaldav :: emit_vmlaldav_r_r_q_q -inst_vmlaldava :: inst_vmlaldava_r_r_q_q -emit_vmlaldava :: emit_vmlaldava_r_r_q_q -inst_vmlaldavx :: inst_vmlaldavx_r_r_q_q -emit_vmlaldavx :: emit_vmlaldavx_r_r_q_q -inst_vmlaldavax :: inst_vmlaldavax_r_r_q_q -emit_vmlaldavax :: emit_vmlaldavax_r_r_q_q -inst_vmlsdav :: inst_vmlsdav_r_q_q -emit_vmlsdav :: emit_vmlsdav_r_q_q -inst_vmlsdava :: inst_vmlsdava_r_q_q -emit_vmlsdava :: emit_vmlsdava_r_q_q -inst_vmlsdavx :: inst_vmlsdavx_r_q_q -emit_vmlsdavx :: emit_vmlsdavx_r_q_q -inst_vmlsdavax :: inst_vmlsdavax_r_q_q -emit_vmlsdavax :: emit_vmlsdavax_r_q_q -inst_vmlsldav :: inst_vmlsldav_r_r_q_q -emit_vmlsldav :: emit_vmlsldav_r_r_q_q -inst_vmlsldava :: inst_vmlsldava_r_r_q_q -emit_vmlsldava :: emit_vmlsldava_r_r_q_q -inst_vmlsldavx :: inst_vmlsldavx_r_r_q_q -emit_vmlsldavx :: emit_vmlsldavx_r_r_q_q -inst_vmlsldavax :: inst_vmlsldavax_r_r_q_q -emit_vmlsldavax :: emit_vmlsldavax_r_r_q_q -inst_vrmlaldavh :: inst_vrmlaldavh_r_r_q_q -emit_vrmlaldavh :: emit_vrmlaldavh_r_r_q_q -inst_vrmlaldavha :: inst_vrmlaldavha_r_r_q_q -emit_vrmlaldavha :: emit_vrmlaldavha_r_r_q_q -inst_vrmlaldavhx :: inst_vrmlaldavhx_r_r_q_q -emit_vrmlaldavhx :: emit_vrmlaldavhx_r_r_q_q -inst_vrmlaldavhax :: inst_vrmlaldavhax_r_r_q_q -emit_vrmlaldavhax :: emit_vrmlaldavhax_r_r_q_q -inst_vrmlsldavh :: inst_vrmlsldavh_r_r_q_q -emit_vrmlsldavh :: emit_vrmlsldavh_r_r_q_q -inst_vrmlsldavha :: inst_vrmlsldavha_r_r_q_q -emit_vrmlsldavha :: emit_vrmlsldavha_r_r_q_q -inst_vrmlsldavhx :: inst_vrmlsldavhx_r_r_q_q -emit_vrmlsldavhx :: emit_vrmlsldavhx_r_r_q_q -inst_vrmlsldavhax :: inst_vrmlsldavhax_r_r_q_q -emit_vrmlsldavhax :: emit_vrmlsldavhax_r_r_q_q -inst_vmlav :: inst_vmlav_r_q_q -emit_vmlav :: emit_vmlav_r_q_q -inst_vmlava :: inst_vmlava_r_q_q -emit_vmlava :: emit_vmlava_r_q_q -inst_vcmul :: inst_vcmul_q_q_q -emit_vcmul :: emit_vcmul_q_q_q -inst_vhcadd :: inst_vhcadd_q_q_q -emit_vhcadd :: emit_vhcadd_q_q_q -inst_vbrsr :: inst_vbrsr_q_q_r -emit_vbrsr :: emit_vbrsr_q_q_r -inst_vshlc :: inst_vshlc_q_r_imm5 -emit_vshlc :: emit_vshlc_q_r_imm5 -inst_vddup :: inst_vddup_q_r_imm -emit_vddup :: emit_vddup_q_r_imm -inst_vidup :: inst_vidup_q_r_imm -emit_vidup :: emit_vidup_q_r_imm -inst_vdwdup :: inst_vdwdup_q_r_r_imm -emit_vdwdup :: emit_vdwdup_q_r_r_imm -inst_viwdup :: inst_viwdup_q_r_r_imm -emit_viwdup :: emit_viwdup_q_r_r_imm -inst_vmovnb :: inst_vmovnb_q_q -emit_vmovnb :: emit_vmovnb_q_q -inst_vmovnt :: inst_vmovnt_q_q -emit_vmovnt :: emit_vmovnt_q_q -inst_vqmovnb :: inst_vqmovnb_q_q -emit_vqmovnb :: emit_vqmovnb_q_q -inst_vqmovnt :: inst_vqmovnt_q_q -emit_vqmovnt :: emit_vqmovnt_q_q -inst_vqmovunb :: inst_vqmovunb_q_q -emit_vqmovunb :: emit_vqmovunb_q_q -inst_vqmovunt :: inst_vqmovunt_q_q -emit_vqmovunt :: emit_vqmovunt_q_q -inst_vshllb :: inst_vshllb_q_q_imm5 -emit_vshllb :: emit_vshllb_q_q_imm5 -inst_vshllt :: inst_vshllt_q_q_imm5 -emit_vshllt :: emit_vshllt_q_q_imm5 -inst_vmullb :: inst_vmullb_q_q_q -emit_vmullb :: emit_vmullb_q_q_q -inst_vmullt :: inst_vmullt_q_q_q -emit_vmullt :: emit_vmullt_q_q_q -inst_vmlalb :: inst_vmlalb_q_q_q -emit_vmlalb :: emit_vmlalb_q_q_q -inst_vmlalt :: inst_vmlalt_q_q_q -emit_vmlalt :: emit_vmlalt_q_q_q -inst_vmlslb :: inst_vmlslb_q_q_q -emit_vmlslb :: emit_vmlslb_q_q_q -inst_vmlslt :: inst_vmlslt_q_q_q -emit_vmlslt :: emit_vmlslt_q_q_q -inst_vshrnb :: inst_vshrnb_q_q_imm5 -emit_vshrnb :: emit_vshrnb_q_q_imm5 -inst_vshrnt :: inst_vshrnt_q_q_imm5 -emit_vshrnt :: emit_vshrnt_q_q_imm5 -inst_vrshrnb :: inst_vrshrnb_q_q_imm5 -emit_vrshrnb :: emit_vrshrnb_q_q_imm5 -inst_vrshrnt :: inst_vrshrnt_q_q_imm5 -emit_vrshrnt :: emit_vrshrnt_q_q_imm5 -inst_vqshrnb :: inst_vqshrnb_q_q_imm5 -emit_vqshrnb :: emit_vqshrnb_q_q_imm5 -inst_vqshrnt :: inst_vqshrnt_q_q_imm5 -emit_vqshrnt :: emit_vqshrnt_q_q_imm5 -inst_vqrshrnb :: inst_vqrshrnb_q_q_imm5 -emit_vqrshrnb :: emit_vqrshrnb_q_q_imm5 -inst_vqrshrnt :: inst_vqrshrnt_q_q_imm5 -emit_vqrshrnt :: emit_vqrshrnt_q_q_imm5 -inst_vqshrunb :: inst_vqshrunb_q_q_imm5 -emit_vqshrunb :: emit_vqshrunb_q_q_imm5 -inst_vqshrunt :: inst_vqshrunt_q_q_imm5 -emit_vqshrunt :: emit_vqshrunt_q_q_imm5 -inst_vqrshrunb :: inst_vqrshrunb_q_q_imm5 -emit_vqrshrunb :: emit_vqrshrunb_q_q_imm5 -inst_vqrshrunt :: inst_vqrshrunt_q_q_imm5 -emit_vqrshrunt :: emit_vqrshrunt_q_q_imm5 -inst_vqdmladh :: inst_vqdmladh_q_q_q -emit_vqdmladh :: emit_vqdmladh_q_q_q -inst_vqdmladhx :: inst_vqdmladhx_q_q_q -emit_vqdmladhx :: emit_vqdmladhx_q_q_q -inst_vqdmlsdh :: inst_vqdmlsdh_q_q_q -emit_vqdmlsdh :: emit_vqdmlsdh_q_q_q -inst_vqdmlsdhx :: inst_vqdmlsdhx_q_q_q -emit_vqdmlsdhx :: emit_vqdmlsdhx_q_q_q -inst_vqrdmladh :: inst_vqrdmladh_q_q_q -emit_vqrdmladh :: emit_vqrdmladh_q_q_q -inst_vqrdmladhx :: inst_vqrdmladhx_q_q_q -emit_vqrdmladhx :: emit_vqrdmladhx_q_q_q -inst_vqrdmlsdh :: inst_vqrdmlsdh_q_q_q -emit_vqrdmlsdh :: emit_vqrdmlsdh_q_q_q -inst_vqrdmlsdhx :: inst_vqrdmlsdhx_q_q_q -emit_vqrdmlsdhx :: emit_vqrdmlsdhx_q_q_q -inst_vldrb :: inst_vldrb_q_mem -emit_vldrb :: emit_vldrb_q_mem -inst_vldrh :: inst_vldrh_q_mem -emit_vldrh :: emit_vldrh_q_mem -inst_vldrw :: inst_vldrw_q_mem -emit_vldrw :: emit_vldrw_q_mem -inst_vldrd :: inst_vldrd_q_mem -emit_vldrd :: emit_vldrd_q_mem -inst_vstrb :: inst_vstrb_q_mem -emit_vstrb :: emit_vstrb_q_mem -inst_vstrh :: inst_vstrh_q_mem -emit_vstrh :: emit_vstrh_q_mem -inst_vstrw :: inst_vstrw_q_mem -emit_vstrw :: emit_vstrw_q_mem -inst_vstrd :: inst_vstrd_q_mem -emit_vstrd :: emit_vstrd_q_mem +inst_and :: proc{ inst_and_r_r_immm, inst_and_r_r_rsh, inst_and_r_r_rsr, inst_and_rlo_rlo } +emit_and :: proc{ emit_and_r_r_immm, emit_and_r_r_rsh, emit_and_r_r_rsr, emit_and_rlo_rlo } +inst_eor :: proc{ inst_eor_r_r_immm, inst_eor_r_r_rsh, inst_eor_r_r_rsr, inst_eor_rlo_rlo } +emit_eor :: proc{ emit_eor_r_r_immm, emit_eor_r_r_rsh, emit_eor_r_r_rsr, emit_eor_rlo_rlo } +inst_sub :: proc{ inst_sub_r_r_immm, inst_sub_r_r_rsh, inst_sub_r_r_rsr, inst_sub_rlo_rlo_rlo, inst_sub_rlo_imm8 } +emit_sub :: proc{ emit_sub_r_r_immm, emit_sub_r_r_rsh, emit_sub_r_r_rsr, emit_sub_rlo_rlo_rlo, emit_sub_rlo_imm8 } +inst_rsb :: proc{ inst_rsb_r_r_immm, inst_rsb_r_r_rsh, inst_rsb_r_r_rsr } +emit_rsb :: proc{ emit_rsb_r_r_immm, emit_rsb_r_r_rsh, emit_rsb_r_r_rsr } +inst_add :: proc{ inst_add_r_r_immm, inst_add_r_r_rsh, inst_add_r_r_rsr, inst_add_rlo_rlo_rlo, inst_add_rlo_imm8, inst_add_r_r } +emit_add :: proc{ emit_add_r_r_immm, emit_add_r_r_rsh, emit_add_r_r_rsr, emit_add_rlo_rlo_rlo, emit_add_rlo_imm8, emit_add_r_r } +inst_adc :: proc{ inst_adc_r_r_immm, inst_adc_r_r_rsh, inst_adc_r_r_rsr, inst_adc_rlo_rlo } +emit_adc :: proc{ emit_adc_r_r_immm, emit_adc_r_r_rsh, emit_adc_r_r_rsr, emit_adc_rlo_rlo } +inst_sbc :: proc{ inst_sbc_r_r_immm, inst_sbc_r_r_rsh, inst_sbc_r_r_rsr, inst_sbc_rlo_rlo } +emit_sbc :: proc{ emit_sbc_r_r_immm, emit_sbc_r_r_rsh, emit_sbc_r_r_rsr, emit_sbc_rlo_rlo } +inst_rsc :: proc{ inst_rsc_r_r_immm, inst_rsc_r_r_rsh, inst_rsc_r_r_rsr } +emit_rsc :: proc{ emit_rsc_r_r_immm, emit_rsc_r_r_rsh, emit_rsc_r_r_rsr } +inst_tst :: proc{ inst_tst_r_immm, inst_tst_r_rsh, inst_tst_r_rsr, inst_tst_rlo_rlo } +emit_tst :: proc{ emit_tst_r_immm, emit_tst_r_rsh, emit_tst_r_rsr, emit_tst_rlo_rlo } +inst_teq :: proc{ inst_teq_r_immm, inst_teq_r_rsh, inst_teq_r_rsr } +emit_teq :: proc{ emit_teq_r_immm, emit_teq_r_rsh, emit_teq_r_rsr } +inst_cmp :: proc{ inst_cmp_r_immm, inst_cmp_r_rsh, inst_cmp_r_rsr, inst_cmp_rlo_rlo } +emit_cmp :: proc{ emit_cmp_r_immm, emit_cmp_r_rsh, emit_cmp_r_rsr, emit_cmp_rlo_rlo } +inst_cmn :: proc{ inst_cmn_r_immm, inst_cmn_r_rsh, inst_cmn_r_rsr, inst_cmn_rlo_rlo } +emit_cmn :: proc{ emit_cmn_r_immm, emit_cmn_r_rsh, emit_cmn_r_rsr, emit_cmn_rlo_rlo } +inst_orr :: proc{ inst_orr_r_r_immm, inst_orr_r_r_rsh, inst_orr_r_r_rsr, inst_orr_rlo_rlo } +emit_orr :: proc{ emit_orr_r_r_immm, emit_orr_r_r_rsh, emit_orr_r_r_rsr, emit_orr_rlo_rlo } +inst_mov :: proc{ inst_mov_r_immm, inst_mov_r_rsh, inst_mov_r_rsr, inst_mov_r_r } +emit_mov :: proc{ emit_mov_r_immm, emit_mov_r_rsh, emit_mov_r_rsr, emit_mov_r_r } +inst_bic :: proc{ inst_bic_r_r_immm, inst_bic_r_r_rsh, inst_bic_r_r_rsr, inst_bic_rlo_rlo } +emit_bic :: proc{ emit_bic_r_r_immm, emit_bic_r_r_rsh, emit_bic_r_r_rsr, emit_bic_rlo_rlo } +inst_mvn :: proc{ inst_mvn_r_immm, inst_mvn_r_rsh, inst_mvn_r_rsr, inst_mvn_rlo_rlo } +emit_mvn :: proc{ emit_mvn_r_immm, emit_mvn_r_rsh, emit_mvn_r_rsr, emit_mvn_rlo_rlo } +inst_lsl :: proc{ inst_lsl_r_r_imm5, inst_lsl_r_r_r, inst_lsl_rlo_rlo } +emit_lsl :: proc{ emit_lsl_r_r_imm5, emit_lsl_r_r_r, emit_lsl_rlo_rlo } +inst_lsr :: proc{ inst_lsr_r_r_imm5, inst_lsr_r_r_r, inst_lsr_rlo_rlo } +emit_lsr :: proc{ emit_lsr_r_r_imm5, emit_lsr_r_r_r, emit_lsr_rlo_rlo } +inst_asr :: proc{ inst_asr_r_r_imm5, inst_asr_r_r_r, inst_asr_rlo_rlo } +emit_asr :: proc{ emit_asr_r_r_imm5, emit_asr_r_r_r, emit_asr_rlo_rlo } +inst_ror :: proc{ inst_ror_r_r_imm5, inst_ror_r_r_r, inst_ror_rlo_rlo } +emit_ror :: proc{ emit_ror_r_r_imm5, emit_ror_r_r_r, emit_ror_rlo_rlo } +inst_rrx :: inst_rrx_r_r +emit_rrx :: emit_rrx_r_r +inst_adr :: inst_adr_rlo_rel +emit_adr :: emit_adr_rlo_rel +inst_neg :: inst_neg_rlo_rlo +emit_neg :: emit_neg_rlo_rlo +inst_movw :: inst_movw_r_imm16 +emit_movw :: emit_movw_r_imm16 +inst_movt :: inst_movt_r_imm16 +emit_movt :: emit_movt_r_imm16 +inst_bfc :: inst_bfc_r_imm5_imm5w +emit_bfc :: emit_bfc_r_imm5_imm5w +inst_bfi :: inst_bfi_r_r_imm5_imm5w +emit_bfi :: emit_bfi_r_r_imm5_imm5w +inst_sbfx :: inst_sbfx_r_r_imm5_imm5w +emit_sbfx :: emit_sbfx_r_r_imm5_imm5w +inst_ubfx :: inst_ubfx_r_r_imm5_imm5w +emit_ubfx :: emit_ubfx_r_r_imm5_imm5w +inst_sxtb :: inst_sxtb_r_r +emit_sxtb :: emit_sxtb_r_r +inst_sxtb16 :: inst_sxtb16_r_r +emit_sxtb16 :: emit_sxtb16_r_r +inst_sxth :: inst_sxth_r_r +emit_sxth :: emit_sxth_r_r +inst_uxtb :: inst_uxtb_r_r +emit_uxtb :: emit_uxtb_r_r +inst_uxtb16 :: inst_uxtb16_r_r +emit_uxtb16 :: emit_uxtb16_r_r +inst_uxth :: inst_uxth_r_r +emit_uxth :: emit_uxth_r_r +inst_sxtab :: inst_sxtab_r_r_r +emit_sxtab :: emit_sxtab_r_r_r +inst_sxtab16 :: inst_sxtab16_r_r_r +emit_sxtab16 :: emit_sxtab16_r_r_r +inst_sxtah :: inst_sxtah_r_r_r +emit_sxtah :: emit_sxtah_r_r_r +inst_uxtab :: inst_uxtab_r_r_r +emit_uxtab :: emit_uxtab_r_r_r +inst_uxtab16 :: inst_uxtab16_r_r_r +emit_uxtab16 :: emit_uxtab16_r_r_r +inst_uxtah :: inst_uxtah_r_r_r +emit_uxtah :: emit_uxtah_r_r_r +inst_clz :: inst_clz_r_r +emit_clz :: emit_clz_r_r +inst_rbit :: inst_rbit_r_r +emit_rbit :: emit_rbit_r_r +inst_rev :: inst_rev_r_r +emit_rev :: emit_rev_r_r +inst_rev16 :: inst_rev16_r_r +emit_rev16 :: emit_rev16_r_r +inst_revsh :: inst_revsh_r_r +emit_revsh :: emit_revsh_r_r +inst_sel :: inst_sel_r_r_r +emit_sel :: emit_sel_r_r_r +inst_pkhbt :: inst_pkhbt_r_r_rsh +emit_pkhbt :: emit_pkhbt_r_r_rsh +inst_pkhtb :: inst_pkhtb_r_r_rsh +emit_pkhtb :: emit_pkhtb_r_r_rsh +inst_usad8 :: inst_usad8_r_r_r +emit_usad8 :: emit_usad8_r_r_r +inst_usada8 :: inst_usada8_r_r_r_r +emit_usada8 :: emit_usada8_r_r_r_r +inst_ssat :: inst_ssat_r_imm4s_rsh +emit_ssat :: emit_ssat_r_imm4s_rsh +inst_usat :: inst_usat_r_imm4s_rsh +emit_usat :: emit_usat_r_imm4s_rsh +inst_ssat16 :: inst_ssat16_r_imm4s_r +emit_ssat16 :: emit_ssat16_r_imm4s_r +inst_usat16 :: inst_usat16_r_imm4s_r +emit_usat16 :: emit_usat16_r_imm4s_r +inst_qadd :: inst_qadd_r_r_r +emit_qadd :: emit_qadd_r_r_r +inst_qsub :: inst_qsub_r_r_r +emit_qsub :: emit_qsub_r_r_r +inst_qdadd :: inst_qdadd_r_r_r +emit_qdadd :: emit_qdadd_r_r_r +inst_qdsub :: inst_qdsub_r_r_r +emit_qdsub :: emit_qdsub_r_r_r +inst_sadd8 :: inst_sadd8_r_r_r +emit_sadd8 :: emit_sadd8_r_r_r +inst_sadd16 :: inst_sadd16_r_r_r +emit_sadd16 :: emit_sadd16_r_r_r +inst_sasx :: inst_sasx_r_r_r +emit_sasx :: emit_sasx_r_r_r +inst_ssax :: inst_ssax_r_r_r +emit_ssax :: emit_ssax_r_r_r +inst_ssub8 :: inst_ssub8_r_r_r +emit_ssub8 :: emit_ssub8_r_r_r +inst_ssub16 :: inst_ssub16_r_r_r +emit_ssub16 :: emit_ssub16_r_r_r +inst_uadd8 :: inst_uadd8_r_r_r +emit_uadd8 :: emit_uadd8_r_r_r +inst_uadd16 :: inst_uadd16_r_r_r +emit_uadd16 :: emit_uadd16_r_r_r +inst_uasx :: inst_uasx_r_r_r +emit_uasx :: emit_uasx_r_r_r +inst_usax :: inst_usax_r_r_r +emit_usax :: emit_usax_r_r_r +inst_usub8 :: inst_usub8_r_r_r +emit_usub8 :: emit_usub8_r_r_r +inst_usub16 :: inst_usub16_r_r_r +emit_usub16 :: emit_usub16_r_r_r +inst_qadd8 :: inst_qadd8_r_r_r +emit_qadd8 :: emit_qadd8_r_r_r +inst_qadd16 :: inst_qadd16_r_r_r +emit_qadd16 :: emit_qadd16_r_r_r +inst_qasx :: inst_qasx_r_r_r +emit_qasx :: emit_qasx_r_r_r +inst_qsax :: inst_qsax_r_r_r +emit_qsax :: emit_qsax_r_r_r +inst_qsub8 :: inst_qsub8_r_r_r +emit_qsub8 :: emit_qsub8_r_r_r +inst_qsub16 :: inst_qsub16_r_r_r +emit_qsub16 :: emit_qsub16_r_r_r +inst_uqadd8 :: inst_uqadd8_r_r_r +emit_uqadd8 :: emit_uqadd8_r_r_r +inst_uqadd16 :: inst_uqadd16_r_r_r +emit_uqadd16 :: emit_uqadd16_r_r_r +inst_uqasx :: inst_uqasx_r_r_r +emit_uqasx :: emit_uqasx_r_r_r +inst_uqsax :: inst_uqsax_r_r_r +emit_uqsax :: emit_uqsax_r_r_r +inst_uqsub8 :: inst_uqsub8_r_r_r +emit_uqsub8 :: emit_uqsub8_r_r_r +inst_uqsub16 :: inst_uqsub16_r_r_r +emit_uqsub16 :: emit_uqsub16_r_r_r +inst_shadd8 :: inst_shadd8_r_r_r +emit_shadd8 :: emit_shadd8_r_r_r +inst_shadd16 :: inst_shadd16_r_r_r +emit_shadd16 :: emit_shadd16_r_r_r +inst_shasx :: inst_shasx_r_r_r +emit_shasx :: emit_shasx_r_r_r +inst_shsax :: inst_shsax_r_r_r +emit_shsax :: emit_shsax_r_r_r +inst_shsub8 :: inst_shsub8_r_r_r +emit_shsub8 :: emit_shsub8_r_r_r +inst_shsub16 :: inst_shsub16_r_r_r +emit_shsub16 :: emit_shsub16_r_r_r +inst_uhadd8 :: inst_uhadd8_r_r_r +emit_uhadd8 :: emit_uhadd8_r_r_r +inst_uhadd16 :: inst_uhadd16_r_r_r +emit_uhadd16 :: emit_uhadd16_r_r_r +inst_uhasx :: inst_uhasx_r_r_r +emit_uhasx :: emit_uhasx_r_r_r +inst_uhsax :: inst_uhsax_r_r_r +emit_uhsax :: emit_uhsax_r_r_r +inst_uhsub8 :: inst_uhsub8_r_r_r +emit_uhsub8 :: emit_uhsub8_r_r_r +inst_uhsub16 :: inst_uhsub16_r_r_r +emit_uhsub16 :: emit_uhsub16_r_r_r +inst_smuad :: inst_smuad_r_r_r +emit_smuad :: emit_smuad_r_r_r +inst_smuadx :: inst_smuadx_r_r_r +emit_smuadx :: emit_smuadx_r_r_r +inst_smusd :: inst_smusd_r_r_r +emit_smusd :: emit_smusd_r_r_r +inst_smusdx :: inst_smusdx_r_r_r +emit_smusdx :: emit_smusdx_r_r_r +inst_smlad :: inst_smlad_r_r_r_r +emit_smlad :: emit_smlad_r_r_r_r +inst_smladx :: inst_smladx_r_r_r_r +emit_smladx :: emit_smladx_r_r_r_r +inst_smlsd :: inst_smlsd_r_r_r_r +emit_smlsd :: emit_smlsd_r_r_r_r +inst_smlsdx :: inst_smlsdx_r_r_r_r +emit_smlsdx :: emit_smlsdx_r_r_r_r +inst_smlald :: inst_smlald_r_r_r_r +emit_smlald :: emit_smlald_r_r_r_r +inst_smlaldx :: inst_smlaldx_r_r_r_r +emit_smlaldx :: emit_smlaldx_r_r_r_r +inst_smlsld :: inst_smlsld_r_r_r_r +emit_smlsld :: emit_smlsld_r_r_r_r +inst_smlsldx :: inst_smlsldx_r_r_r_r +emit_smlsldx :: emit_smlsldx_r_r_r_r +inst_smmul :: inst_smmul_r_r_r +emit_smmul :: emit_smmul_r_r_r +inst_smmulr :: inst_smmulr_r_r_r +emit_smmulr :: emit_smmulr_r_r_r +inst_smmla :: inst_smmla_r_r_r_r +emit_smmla :: emit_smmla_r_r_r_r +inst_smmlar :: inst_smmlar_r_r_r_r +emit_smmlar :: emit_smmlar_r_r_r_r +inst_smmls :: inst_smmls_r_r_r_r +emit_smmls :: emit_smmls_r_r_r_r +inst_smmlsr :: inst_smmlsr_r_r_r_r +emit_smmlsr :: emit_smmlsr_r_r_r_r +inst_mul :: proc{ inst_mul_r_r_r, inst_mul_rlo_rlo } +emit_mul :: proc{ emit_mul_r_r_r, emit_mul_rlo_rlo } +inst_mla :: inst_mla_r_r_r_r +emit_mla :: emit_mla_r_r_r_r +inst_mls :: inst_mls_r_r_r_r +emit_mls :: emit_mls_r_r_r_r +inst_umull :: inst_umull_r_r_r_r +emit_umull :: emit_umull_r_r_r_r +inst_umlal :: inst_umlal_r_r_r_r +emit_umlal :: emit_umlal_r_r_r_r +inst_smull :: inst_smull_r_r_r_r +emit_smull :: emit_smull_r_r_r_r +inst_smlal :: inst_smlal_r_r_r_r +emit_smlal :: emit_smlal_r_r_r_r +inst_umaal :: inst_umaal_r_r_r_r +emit_umaal :: emit_umaal_r_r_r_r +inst_smlabb :: inst_smlabb_r_r_r_r +emit_smlabb :: emit_smlabb_r_r_r_r +inst_smlabt :: inst_smlabt_r_r_r_r +emit_smlabt :: emit_smlabt_r_r_r_r +inst_smlatb :: inst_smlatb_r_r_r_r +emit_smlatb :: emit_smlatb_r_r_r_r +inst_smlatt :: inst_smlatt_r_r_r_r +emit_smlatt :: emit_smlatt_r_r_r_r +inst_smlawb :: inst_smlawb_r_r_r_r +emit_smlawb :: emit_smlawb_r_r_r_r +inst_smlawt :: inst_smlawt_r_r_r_r +emit_smlawt :: emit_smlawt_r_r_r_r +inst_smulbb :: inst_smulbb_r_r_r +emit_smulbb :: emit_smulbb_r_r_r +inst_smulbt :: inst_smulbt_r_r_r +emit_smulbt :: emit_smulbt_r_r_r +inst_smultb :: inst_smultb_r_r_r +emit_smultb :: emit_smultb_r_r_r +inst_smultt :: inst_smultt_r_r_r +emit_smultt :: emit_smultt_r_r_r +inst_smulwb :: inst_smulwb_r_r_r +emit_smulwb :: emit_smulwb_r_r_r +inst_smulwt :: inst_smulwt_r_r_r +emit_smulwt :: emit_smulwt_r_r_r +inst_smlalbb :: inst_smlalbb_r_r_r_r +emit_smlalbb :: emit_smlalbb_r_r_r_r +inst_smlalbt :: inst_smlalbt_r_r_r_r +emit_smlalbt :: emit_smlalbt_r_r_r_r +inst_smlaltb :: inst_smlaltb_r_r_r_r +emit_smlaltb :: emit_smlaltb_r_r_r_r +inst_smlaltt :: inst_smlaltt_r_r_r_r +emit_smlaltt :: emit_smlaltt_r_r_r_r +inst_sdiv :: inst_sdiv_r_r_r +emit_sdiv :: emit_sdiv_r_r_r +inst_udiv :: inst_udiv_r_r_r +emit_udiv :: emit_udiv_r_r_r +inst_b :: proc{ inst_b_rel, inst_b_rel_cond } +emit_b :: proc{ emit_b_rel, emit_b_rel_cond } +inst_bl :: inst_bl_rel +emit_bl :: emit_bl_rel +inst_bx :: inst_bx_r +emit_bx :: emit_bx_r +inst_blx :: proc{ inst_blx_r, inst_blx_rel } +emit_blx :: proc{ emit_blx_r, emit_blx_rel } +inst_bxj :: inst_bxj_r +emit_bxj :: emit_bxj_r +inst_cbz :: inst_cbz_rlo_rel +emit_cbz :: emit_cbz_rlo_rel +inst_cbnz :: inst_cbnz_rlo_rel +emit_cbnz :: emit_cbnz_rlo_rel +inst_tbb :: inst_tbb_r_r +emit_tbb :: emit_tbb_r_r +inst_tbh :: inst_tbh_r_r +emit_tbh :: emit_tbh_r_r +inst_msr :: proc{ inst_msr_psr_immm, inst_msr_psr_r } +emit_msr :: proc{ emit_msr_psr_immm, emit_msr_psr_r } +inst_mrs :: inst_mrs_r_psr +emit_mrs :: emit_mrs_r_psr +inst_cps :: inst_cps_ifl +emit_cps :: emit_cps_ifl +inst_setend :: inst_setend_end +emit_setend :: emit_setend_end +inst_nop :: inst_nop_none +emit_nop :: emit_nop_none +inst_yield :: inst_yield_none +emit_yield :: emit_yield_none +inst_wfe :: inst_wfe_none +emit_wfe :: emit_wfe_none +inst_wfi :: inst_wfi_none +emit_wfi :: emit_wfi_none +inst_sev :: inst_sev_none +emit_sev :: emit_sev_none +inst_sevl :: inst_sevl_none +emit_sevl :: emit_sevl_none +inst_dbg :: inst_dbg_hint +emit_dbg :: emit_dbg_hint +inst_hint :: inst_hint_hint +emit_hint :: emit_hint_hint +inst_dmb :: inst_dmb_barr +emit_dmb :: emit_dmb_barr +inst_dsb :: inst_dsb_barr +emit_dsb :: emit_dsb_barr +inst_isb :: inst_isb_barr +emit_isb :: emit_isb_barr +inst_clrex :: inst_clrex_none +emit_clrex :: emit_clrex_none +inst_pld :: inst_pld_mem +emit_pld :: emit_pld_mem +inst_pldw :: inst_pldw_mem +emit_pldw :: emit_pldw_mem +inst_pli :: inst_pli_mem +emit_pli :: emit_pli_mem +inst_hlt :: inst_hlt_imm +emit_hlt :: emit_hlt_imm +inst_eret :: inst_eret_none +emit_eret :: emit_eret_none +inst_esb :: inst_esb_none +emit_esb :: emit_esb_none +inst_psb_csync :: inst_psb_csync_none +emit_psb_csync :: emit_psb_csync_none +inst_tsb_csync :: inst_tsb_csync_none +emit_tsb_csync :: emit_tsb_csync_none +inst_csdb :: inst_csdb_none +emit_csdb :: emit_csdb_none +inst_sb :: inst_sb_none +emit_sb :: emit_sb_none +inst_setpan :: inst_setpan_hint +emit_setpan :: emit_setpan_hint +inst_svc :: inst_svc_imm +emit_svc :: emit_svc_imm +inst_bkpt :: inst_bkpt_imm +emit_bkpt :: emit_bkpt_imm +inst_hvc :: inst_hvc_imm +emit_hvc :: emit_hvc_imm +inst_smc :: inst_smc_imm +emit_smc :: emit_smc_imm +inst_udf :: inst_udf_imm +emit_udf :: emit_udf_imm +inst_ldr :: inst_ldr_r_mem +emit_ldr :: emit_ldr_r_mem +inst_str :: inst_str_r_mem +emit_str :: emit_str_r_mem +inst_ldrb :: inst_ldrb_r_mem +emit_ldrb :: emit_ldrb_r_mem +inst_strb :: inst_strb_r_mem +emit_strb :: emit_strb_r_mem +inst_ldrh :: inst_ldrh_r_mem +emit_ldrh :: emit_ldrh_r_mem +inst_strh :: inst_strh_r_mem +emit_strh :: emit_strh_r_mem +inst_ldrsb :: inst_ldrsb_r_mem +emit_ldrsb :: emit_ldrsb_r_mem +inst_ldrsh :: inst_ldrsh_r_mem +emit_ldrsh :: emit_ldrsh_r_mem +inst_ldrd :: proc{ inst_ldrd_r_mem, inst_ldrd_r_r_mem } +emit_ldrd :: proc{ emit_ldrd_r_mem, emit_ldrd_r_r_mem } +inst_strd :: proc{ inst_strd_r_mem, inst_strd_r_r_mem } +emit_strd :: proc{ emit_strd_r_mem, emit_strd_r_r_mem } +inst_lda :: inst_lda_r_mem +emit_lda :: emit_lda_r_mem +inst_stl :: inst_stl_r_mem +emit_stl :: emit_stl_r_mem +inst_ldab :: inst_ldab_r_mem +emit_ldab :: emit_ldab_r_mem +inst_stlb :: inst_stlb_r_mem +emit_stlb :: emit_stlb_r_mem +inst_ldah :: inst_ldah_r_mem +emit_ldah :: emit_ldah_r_mem +inst_stlh :: inst_stlh_r_mem +emit_stlh :: emit_stlh_r_mem +inst_ldrex :: inst_ldrex_r_mem +emit_ldrex :: emit_ldrex_r_mem +inst_strex :: inst_strex_r_r_mem +emit_strex :: emit_strex_r_r_mem +inst_ldrexb :: inst_ldrexb_r_mem +emit_ldrexb :: emit_ldrexb_r_mem +inst_strexb :: inst_strexb_r_r_mem +emit_strexb :: emit_strexb_r_r_mem +inst_ldrexh :: inst_ldrexh_r_mem +emit_ldrexh :: emit_ldrexh_r_mem +inst_strexh :: inst_strexh_r_r_mem +emit_strexh :: emit_strexh_r_r_mem +inst_ldrexd :: proc{ inst_ldrexd_r_mem, inst_ldrexd_r_r_mem } +emit_ldrexd :: proc{ emit_ldrexd_r_mem, emit_ldrexd_r_r_mem } +inst_strexd :: proc{ inst_strexd_r_r_mem, inst_strexd_r_r_r_mem } +emit_strexd :: proc{ emit_strexd_r_r_mem, emit_strexd_r_r_r_mem } +inst_ldaex :: inst_ldaex_r_mem +emit_ldaex :: emit_ldaex_r_mem +inst_stlex :: inst_stlex_r_r_mem +emit_stlex :: emit_stlex_r_r_mem +inst_ldaexb :: inst_ldaexb_r_mem +emit_ldaexb :: emit_ldaexb_r_mem +inst_stlexb :: inst_stlexb_r_r_mem +emit_stlexb :: emit_stlexb_r_r_mem +inst_ldaexh :: inst_ldaexh_r_mem +emit_ldaexh :: emit_ldaexh_r_mem +inst_stlexh :: inst_stlexh_r_r_mem +emit_stlexh :: emit_stlexh_r_r_mem +inst_ldaexd :: inst_ldaexd_r_mem +emit_ldaexd :: emit_ldaexd_r_mem +inst_stlexd :: inst_stlexd_r_r_mem +emit_stlexd :: emit_stlexd_r_r_mem +inst_ldm :: inst_ldm_r_list +emit_ldm :: emit_ldm_r_list +inst_stm :: inst_stm_r_list +emit_stm :: emit_stm_r_list +inst_push :: inst_push_list +emit_push :: emit_push_list +inst_pop :: inst_pop_list +emit_pop :: emit_pop_list +inst_swp :: inst_swp_r_r_r +emit_swp :: emit_swp_r_r_r +inst_swpb :: inst_swpb_r_r_r +emit_swpb :: emit_swpb_r_r_r +inst_rfe :: inst_rfe_r +emit_rfe :: emit_rfe_r +inst_srs :: inst_srs_imm +emit_srs :: emit_srs_imm +inst_cdp :: inst_cdp_cpn_cpop_crd_crd +emit_cdp :: emit_cdp_cpn_cpop_crd_crd +inst_cdp2 :: inst_cdp2_cpn_cpop_crd_crd +emit_cdp2 :: emit_cdp2_cpn_cpop_crd_crd +inst_mcr :: inst_mcr_cpn_cpop_r_crd +emit_mcr :: emit_mcr_cpn_cpop_r_crd +inst_mcr2 :: inst_mcr2_cpn_cpop_r_crd +emit_mcr2 :: emit_mcr2_cpn_cpop_r_crd +inst_mrc :: inst_mrc_cpn_cpop_r_crd +emit_mrc :: emit_mrc_cpn_cpop_r_crd +inst_mrc2 :: inst_mrc2_cpn_cpop_r_crd +emit_mrc2 :: emit_mrc2_cpn_cpop_r_crd +inst_mcrr :: inst_mcrr_cpn_cpop_r_r +emit_mcrr :: emit_mcrr_cpn_cpop_r_r +inst_mcrr2 :: inst_mcrr2_cpn_cpop_r_r +emit_mcrr2 :: emit_mcrr2_cpn_cpop_r_r +inst_mrrc :: inst_mrrc_cpn_cpop_r_r +emit_mrrc :: emit_mrrc_cpn_cpop_r_r +inst_mrrc2 :: inst_mrrc2_cpn_cpop_r_r +emit_mrrc2 :: emit_mrrc2_cpn_cpop_r_r +inst_ldc :: inst_ldc_cpn_crd_mem +emit_ldc :: emit_ldc_cpn_crd_mem +inst_ldc2 :: inst_ldc2_cpn_crd_mem +emit_ldc2 :: emit_ldc2_cpn_crd_mem +inst_stc :: inst_stc_cpn_crd_mem +emit_stc :: emit_stc_cpn_crd_mem +inst_stc2 :: inst_stc2_cpn_crd_mem +emit_stc2 :: emit_stc2_cpn_crd_mem +inst_crc32b :: inst_crc32b_r_r_r +emit_crc32b :: emit_crc32b_r_r_r +inst_crc32h :: inst_crc32h_r_r_r +emit_crc32h :: emit_crc32h_r_r_r +inst_crc32w :: inst_crc32w_r_r_r +emit_crc32w :: emit_crc32w_r_r_r +inst_crc32cb :: inst_crc32cb_r_r_r +emit_crc32cb :: emit_crc32cb_r_r_r +inst_crc32ch :: inst_crc32ch_r_r_r +emit_crc32ch :: emit_crc32ch_r_r_r +inst_crc32cw :: inst_crc32cw_r_r_r +emit_crc32cw :: emit_crc32cw_r_r_r +inst_vadd :: inst_vadd_s_s_s +emit_vadd :: emit_vadd_s_s_s +inst_vsub :: inst_vsub_s_s_s +emit_vsub :: emit_vsub_s_s_s +inst_vmul :: inst_vmul_s_s_s +emit_vmul :: emit_vmul_s_s_s +inst_vdiv :: inst_vdiv_s_s_s +emit_vdiv :: emit_vdiv_s_s_s +inst_vmla :: inst_vmla_s_s_s +emit_vmla :: emit_vmla_s_s_s +inst_vmls :: inst_vmls_s_s_s +emit_vmls :: emit_vmls_s_s_s +inst_vnmul :: inst_vnmul_s_s_s +emit_vnmul :: emit_vnmul_s_s_s +inst_vnmla :: inst_vnmla_s_s_s +emit_vnmla :: emit_vnmla_s_s_s +inst_vnmls :: inst_vnmls_s_s_s +emit_vnmls :: emit_vnmls_s_s_s +inst_vfma :: inst_vfma_s_s_s +emit_vfma :: emit_vfma_s_s_s +inst_vfms :: inst_vfms_s_s_s +emit_vfms :: emit_vfms_s_s_s +inst_vfnma :: inst_vfnma_s_s_s +emit_vfnma :: emit_vfnma_s_s_s +inst_vfnms :: inst_vfnms_s_s_s +emit_vfnms :: emit_vfnms_s_s_s +inst_vabs :: inst_vabs_s_s +emit_vabs :: emit_vabs_s_s +inst_vneg :: inst_vneg_s_s +emit_vneg :: emit_vneg_s_s +inst_vsqrt :: inst_vsqrt_s_s +emit_vsqrt :: emit_vsqrt_s_s +inst_vcmp :: proc{ inst_vcmp_s_s, inst_vcmp_s } +emit_vcmp :: proc{ emit_vcmp_s_s, emit_vcmp_s } +inst_vcmpe :: proc{ inst_vcmpe_s_s, inst_vcmpe_s } +emit_vcmpe :: proc{ emit_vcmpe_s_s, emit_vcmpe_s } +inst_vcvt :: inst_vcvt_d_s +emit_vcvt :: emit_vcvt_d_s +inst_vcvtb :: inst_vcvtb_s_s +emit_vcvtb :: emit_vcvtb_s_s +inst_vcvtt :: inst_vcvtt_s_s +emit_vcvtt :: emit_vcvtt_s_s +inst_vcvta :: inst_vcvta_s_s +emit_vcvta :: emit_vcvta_s_s +inst_vcvtn :: inst_vcvtn_s_s +emit_vcvtn :: emit_vcvtn_s_s +inst_vcvtp :: inst_vcvtp_s_s +emit_vcvtp :: emit_vcvtp_s_s +inst_vcvtm :: inst_vcvtm_s_s +emit_vcvtm :: emit_vcvtm_s_s +inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_dlane_r } +emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_dlane_r } +inst_vmrs :: inst_vmrs_r +emit_vmrs :: emit_vmrs_r +inst_vmsr :: inst_vmsr_r +emit_vmsr :: emit_vmsr_r +inst_vldr :: inst_vldr_s_mem +emit_vldr :: emit_vldr_s_mem +inst_vstr :: inst_vstr_s_mem +emit_vstr :: emit_vstr_s_mem +inst_vldm :: inst_vldm_r_slist +emit_vldm :: emit_vldm_r_slist +inst_vstm :: inst_vstm_r_slist +emit_vstm :: emit_vstm_r_slist +inst_vpush :: inst_vpush_slist +emit_vpush :: emit_vpush_slist +inst_vpop :: inst_vpop_slist +emit_vpop :: emit_vpop_slist +inst_vsel :: inst_vsel_s_s_s_cond +emit_vsel :: emit_vsel_s_s_s_cond +inst_vmaxnm :: inst_vmaxnm_s_s_s +emit_vmaxnm :: emit_vmaxnm_s_s_s +inst_vminnm :: inst_vminnm_s_s_s +emit_vminnm :: emit_vminnm_s_s_s +inst_vrinta :: inst_vrinta_s_s +emit_vrinta :: emit_vrinta_s_s +inst_vrintn :: inst_vrintn_s_s +emit_vrintn :: emit_vrintn_s_s +inst_vrintp :: inst_vrintp_s_s +emit_vrintp :: emit_vrintp_s_s +inst_vrintm :: inst_vrintm_s_s +emit_vrintm :: emit_vrintm_s_s +inst_vrintr :: inst_vrintr_s_s +emit_vrintr :: emit_vrintr_s_s +inst_vrintz :: inst_vrintz_s_s +emit_vrintz :: emit_vrintz_s_s +inst_vrintx :: inst_vrintx_s_s +emit_vrintx :: emit_vrintx_s_s +inst_vhadd :: inst_vhadd_d_d_d +emit_vhadd :: emit_vhadd_d_d_d +inst_vhsub :: inst_vhsub_d_d_d +emit_vhsub :: emit_vhsub_d_d_d +inst_vrhadd :: inst_vrhadd_d_d_d +emit_vrhadd :: emit_vrhadd_d_d_d +inst_vqadd :: inst_vqadd_d_d_d +emit_vqadd :: emit_vqadd_d_d_d +inst_vqsub :: inst_vqsub_d_d_d +emit_vqsub :: emit_vqsub_d_d_d +inst_vmull :: inst_vmull_q_d_d +emit_vmull :: emit_vmull_q_d_d +inst_vmlal :: inst_vmlal_q_d_d +emit_vmlal :: emit_vmlal_q_d_d +inst_vmlsl :: inst_vmlsl_q_d_d +emit_vmlsl :: emit_vmlsl_q_d_d +inst_vqdmull :: inst_vqdmull_q_d_d +emit_vqdmull :: emit_vqdmull_q_d_d +inst_vqdmlal :: inst_vqdmlal_q_d_d +emit_vqdmlal :: emit_vqdmlal_q_d_d +inst_vqdmlsl :: inst_vqdmlsl_q_d_d +emit_vqdmlsl :: emit_vqdmlsl_q_d_d +inst_vqdmulh :: inst_vqdmulh_d_d_d +emit_vqdmulh :: emit_vqdmulh_d_d_d +inst_vqrdmulh :: inst_vqrdmulh_d_d_d +emit_vqrdmulh :: emit_vqrdmulh_d_d_d +inst_vqrdmlah :: inst_vqrdmlah_d_d_d +emit_vqrdmlah :: emit_vqrdmlah_d_d_d +inst_vqrdmlsh :: inst_vqrdmlsh_d_d_d +emit_vqrdmlsh :: emit_vqrdmlsh_d_d_d +inst_vaba :: inst_vaba_d_d_d +emit_vaba :: emit_vaba_d_d_d +inst_vabd :: inst_vabd_d_d_d +emit_vabd :: emit_vabd_d_d_d +inst_vand :: inst_vand_d_d_d +emit_vand :: emit_vand_d_d_d +inst_vbic :: inst_vbic_d_d_d +emit_vbic :: emit_vbic_d_d_d +inst_vorr :: inst_vorr_d_d_d +emit_vorr :: emit_vorr_d_d_d +inst_vorn :: inst_vorn_d_d_d +emit_vorn :: emit_vorn_d_d_d +inst_veor :: inst_veor_d_d_d +emit_veor :: emit_veor_d_d_d +inst_vbsl :: inst_vbsl_d_d_d +emit_vbsl :: emit_vbsl_d_d_d +inst_vbit :: inst_vbit_d_d_d +emit_vbit :: emit_vbit_d_d_d +inst_vbif :: inst_vbif_d_d_d +emit_vbif :: emit_vbif_d_d_d +inst_vmvn :: proc{ inst_vmvn_d_d, inst_vmvn_d_imm } +emit_vmvn :: proc{ emit_vmvn_d_d, emit_vmvn_d_imm } +inst_vmovn :: inst_vmovn_d_q +emit_vmovn :: emit_vmovn_d_q +inst_vqmovn :: inst_vqmovn_d_q +emit_vqmovn :: emit_vqmovn_d_q +inst_vqmovun :: inst_vqmovun_d_q +emit_vqmovun :: emit_vqmovun_d_q +inst_vmovl :: inst_vmovl_q_d +emit_vmovl :: emit_vmovl_q_d +inst_vtst :: inst_vtst_d_d_d +emit_vtst :: emit_vtst_d_d_d +inst_vceq :: inst_vceq_d_d_d +emit_vceq :: emit_vceq_d_d_d +inst_vcge :: inst_vcge_d_d_d +emit_vcge :: emit_vcge_d_d_d +inst_vcgt :: inst_vcgt_d_d_d +emit_vcgt :: emit_vcgt_d_d_d +inst_vacge :: inst_vacge_d_d_d +emit_vacge :: emit_vacge_d_d_d +inst_vacgt :: inst_vacgt_d_d_d +emit_vacgt :: emit_vacgt_d_d_d +inst_vmax :: inst_vmax_d_d_d +emit_vmax :: emit_vmax_d_d_d +inst_vmin :: inst_vmin_d_d_d +emit_vmin :: emit_vmin_d_d_d +inst_vpmax :: inst_vpmax_d_d_d +emit_vpmax :: emit_vpmax_d_d_d +inst_vpmin :: inst_vpmin_d_d_d +emit_vpmin :: emit_vpmin_d_d_d +inst_vpadd :: inst_vpadd_d_d_d +emit_vpadd :: emit_vpadd_d_d_d +inst_vpaddl :: inst_vpaddl_d_d +emit_vpaddl :: emit_vpaddl_d_d +inst_vpadal :: inst_vpadal_d_d +emit_vpadal :: emit_vpadal_d_d +inst_vrecpe :: inst_vrecpe_d_d +emit_vrecpe :: emit_vrecpe_d_d +inst_vrecps :: inst_vrecps_d_d_d +emit_vrecps :: emit_vrecps_d_d_d +inst_vrsqrte :: inst_vrsqrte_d_d +emit_vrsqrte :: emit_vrsqrte_d_d +inst_vrsqrts :: inst_vrsqrts_d_d_d +emit_vrsqrts :: emit_vrsqrts_d_d_d +inst_vshl :: inst_vshl_d_d_d +emit_vshl :: emit_vshl_d_d_d +inst_vshr :: inst_vshr_d_d_imm +emit_vshr :: emit_vshr_d_d_imm +inst_vsra :: inst_vsra_d_d_imm +emit_vsra :: emit_vsra_d_d_imm +inst_vrshl :: inst_vrshl_d_d_d +emit_vrshl :: emit_vrshl_d_d_d +inst_vrshr :: inst_vrshr_d_d_imm +emit_vrshr :: emit_vrshr_d_d_imm +inst_vsli :: inst_vsli_d_d_imm +emit_vsli :: emit_vsli_d_d_imm +inst_vsri :: inst_vsri_d_d_imm +emit_vsri :: emit_vsri_d_d_imm +inst_vqshl :: proc{ inst_vqshl_d_d_d, inst_vqshl_d_d_imm } +emit_vqshl :: proc{ emit_vqshl_d_d_d, emit_vqshl_d_d_imm } +inst_vqshrn :: inst_vqshrn_d_q_imm +emit_vqshrn :: emit_vqshrn_d_q_imm +inst_vqshrun :: inst_vqshrun_d_q_imm +emit_vqshrun :: emit_vqshrun_d_q_imm +inst_vqrshrn :: inst_vqrshrn_d_q_imm +emit_vqrshrn :: emit_vqrshrn_d_q_imm +inst_vqrshrun :: inst_vqrshrun_d_q_imm +emit_vqrshrun :: emit_vqrshrun_d_q_imm +inst_vshrn :: inst_vshrn_d_q_imm +emit_vshrn :: emit_vshrn_d_q_imm +inst_vrshrn :: inst_vrshrn_d_q_imm +emit_vrshrn :: emit_vrshrn_d_q_imm +inst_vshll :: proc{ inst_vshll_q_d_imm, inst_vshll_q_d } +emit_vshll :: proc{ emit_vshll_q_d_imm, emit_vshll_q_d } +inst_vcls :: inst_vcls_d_d +emit_vcls :: emit_vcls_d_d +inst_vclz :: inst_vclz_d_d +emit_vclz :: emit_vclz_d_d +inst_vcnt :: inst_vcnt_d_d +emit_vcnt :: emit_vcnt_d_d +inst_vrev16 :: inst_vrev16_d_d +emit_vrev16 :: emit_vrev16_d_d +inst_vrev32 :: inst_vrev32_d_d +emit_vrev32 :: emit_vrev32_d_d +inst_vrev64 :: inst_vrev64_d_d +emit_vrev64 :: emit_vrev64_d_d +inst_vext :: inst_vext_d_d_d_imm4 +emit_vext :: emit_vext_d_d_d_imm4 +inst_vtbl :: proc{ inst_vtbl_d_d_d, inst_vtbl_d_dlist_d } +emit_vtbl :: proc{ emit_vtbl_d_d_d, emit_vtbl_d_dlist_d } +inst_vtbx :: proc{ inst_vtbx_d_d_d, inst_vtbx_d_dlist_d } +emit_vtbx :: proc{ emit_vtbx_d_d_d, emit_vtbx_d_dlist_d } +inst_vtrn :: inst_vtrn_d_d +emit_vtrn :: emit_vtrn_d_d +inst_vuzp :: inst_vuzp_d_d +emit_vuzp :: emit_vuzp_d_d +inst_vzip :: inst_vzip_d_d +emit_vzip :: emit_vzip_d_d +inst_vdup :: proc{ inst_vdup_d_r, inst_vdup_d_dlane } +emit_vdup :: proc{ emit_vdup_d_r, emit_vdup_d_dlane } +inst_vswp :: inst_vswp_d_d +emit_vswp :: emit_vswp_d_d +inst_vld1 :: proc{ inst_vld1_dlist_mem, inst_vld1_dlane_mem } +emit_vld1 :: proc{ emit_vld1_dlist_mem, emit_vld1_dlane_mem } +inst_vld2 :: inst_vld2_dlist_mem +emit_vld2 :: emit_vld2_dlist_mem +inst_vld3 :: inst_vld3_dlist_mem +emit_vld3 :: emit_vld3_dlist_mem +inst_vld4 :: inst_vld4_dlist_mem +emit_vld4 :: emit_vld4_dlist_mem +inst_vst1 :: proc{ inst_vst1_dlist_mem, inst_vst1_dlane_mem } +emit_vst1 :: proc{ emit_vst1_dlist_mem, emit_vst1_dlane_mem } +inst_vst2 :: inst_vst2_dlist_mem +emit_vst2 :: emit_vst2_dlist_mem +inst_vst3 :: inst_vst3_dlist_mem +emit_vst3 :: emit_vst3_dlist_mem +inst_vst4 :: inst_vst4_dlist_mem +emit_vst4 :: emit_vst4_dlist_mem +inst_aese :: inst_aese_q_q +emit_aese :: emit_aese_q_q +inst_aesd :: inst_aesd_q_q +emit_aesd :: emit_aesd_q_q +inst_aesmc :: inst_aesmc_q_q +emit_aesmc :: emit_aesmc_q_q +inst_aesimc :: inst_aesimc_q_q +emit_aesimc :: emit_aesimc_q_q +inst_sha1h :: inst_sha1h_q_q +emit_sha1h :: emit_sha1h_q_q +inst_sha1su0 :: inst_sha1su0_q_q_q +emit_sha1su0 :: emit_sha1su0_q_q_q +inst_sha1su1 :: inst_sha1su1_q_q +emit_sha1su1 :: emit_sha1su1_q_q +inst_sha1c :: inst_sha1c_q_q_q +emit_sha1c :: emit_sha1c_q_q_q +inst_sha1m :: inst_sha1m_q_q_q +emit_sha1m :: emit_sha1m_q_q_q +inst_sha1p :: inst_sha1p_q_q_q +emit_sha1p :: emit_sha1p_q_q_q +inst_sha256h :: inst_sha256h_q_q_q +emit_sha256h :: emit_sha256h_q_q_q +inst_sha256h2 :: inst_sha256h2_q_q_q +emit_sha256h2 :: emit_sha256h2_q_q_q +inst_sha256su0 :: inst_sha256su0_q_q +emit_sha256su0 :: emit_sha256su0_q_q +inst_sha256su1 :: inst_sha256su1_q_q_q +emit_sha256su1 :: emit_sha256su1_q_q_q +inst_vjcvt :: inst_vjcvt_s_d +emit_vjcvt :: emit_vjcvt_s_d +inst_vsdot :: inst_vsdot_d_d_d +emit_vsdot :: emit_vsdot_d_d_d +inst_vudot :: inst_vudot_d_d_d +emit_vudot :: emit_vudot_d_d_d +inst_vsdot_lane :: inst_vsdot_lane_d_d_dlane +emit_vsdot_lane :: emit_vsdot_lane_d_d_dlane +inst_vudot_lane :: inst_vudot_lane_d_d_dlane +emit_vudot_lane :: emit_vudot_lane_d_d_dlane +inst_vcvt_bf16 :: inst_vcvt_bf16_d_q +emit_vcvt_bf16 :: emit_vcvt_bf16_d_q +inst_vdot_bf16 :: inst_vdot_bf16_d_d_d +emit_vdot_bf16 :: emit_vdot_bf16_d_d_d +inst_vfma_bf16 :: inst_vfma_bf16_q_q_q +emit_vfma_bf16 :: emit_vfma_bf16_q_q_q +inst_vmmla_bf16 :: inst_vmmla_bf16_q_q_q +emit_vmmla_bf16 :: emit_vmmla_bf16_q_q_q +inst_vfmal :: inst_vfmal_d_d_d +emit_vfmal :: emit_vfmal_d_d_d +inst_vfmsl :: inst_vfmsl_d_d_d +emit_vfmsl :: emit_vfmsl_d_d_d +inst_vcmla :: inst_vcmla_d_d_d_imm +emit_vcmla :: emit_vcmla_d_d_d_imm +inst_vcadd :: inst_vcadd_d_d_d_imm +emit_vcadd :: emit_vcadd_d_d_d_imm +inst_vcmla_lane :: inst_vcmla_lane_d_d_dlane_imm +emit_vcmla_lane :: emit_vcmla_lane_d_d_dlane_imm +inst_vsmmla :: inst_vsmmla_q_q_q +emit_vsmmla :: emit_vsmmla_q_q_q +inst_vummla :: inst_vummla_q_q_q +emit_vummla :: emit_vummla_q_q_q +inst_vusmmla :: inst_vusmmla_q_q_q +emit_vusmmla :: emit_vusmmla_q_q_q +inst_vsudot :: inst_vsudot_q_q_q +emit_vsudot :: emit_vsudot_q_q_q +inst_vusdot :: inst_vusdot_d_d_d +emit_vusdot :: emit_vusdot_d_d_d +inst_vsudot_lane :: inst_vsudot_lane_q_q_dlane +emit_vsudot_lane :: emit_vsudot_lane_q_q_dlane +inst_vusdot_lane :: inst_vusdot_lane_d_d_dlane +emit_vusdot_lane :: emit_vusdot_lane_d_d_dlane +inst_vmul_lane :: inst_vmul_lane_d_d_dlane +emit_vmul_lane :: emit_vmul_lane_d_d_dlane +inst_vmla_lane :: inst_vmla_lane_d_d_dlane +emit_vmla_lane :: emit_vmla_lane_d_d_dlane +inst_vmls_lane :: inst_vmls_lane_d_d_dlane +emit_vmls_lane :: emit_vmls_lane_d_d_dlane +inst_vmull_lane :: inst_vmull_lane_q_d_dlane +emit_vmull_lane :: emit_vmull_lane_q_d_dlane +inst_vmlal_lane :: inst_vmlal_lane_q_d_dlane +emit_vmlal_lane :: emit_vmlal_lane_q_d_dlane +inst_vmlsl_lane :: inst_vmlsl_lane_q_d_dlane +emit_vmlsl_lane :: emit_vmlsl_lane_q_d_dlane +inst_vqdmull_lane :: inst_vqdmull_lane_q_d_dlane +emit_vqdmull_lane :: emit_vqdmull_lane_q_d_dlane +inst_vqdmlal_lane :: inst_vqdmlal_lane_q_d_dlane +emit_vqdmlal_lane :: emit_vqdmlal_lane_q_d_dlane +inst_vqdmlsl_lane :: inst_vqdmlsl_lane_q_d_dlane +emit_vqdmlsl_lane :: emit_vqdmlsl_lane_q_d_dlane +inst_vfma_lane :: inst_vfma_lane_d_d_dlane +emit_vfma_lane :: emit_vfma_lane_d_d_dlane +inst_vfms_lane :: inst_vfms_lane_d_d_dlane +emit_vfms_lane :: emit_vfms_lane_d_d_dlane +inst_vqrdmlah_lane :: inst_vqrdmlah_lane_d_d_dlane +emit_vqrdmlah_lane :: emit_vqrdmlah_lane_d_d_dlane +inst_vqrdmlsh_lane :: inst_vqrdmlsh_lane_d_d_dlane +emit_vqrdmlsh_lane :: emit_vqrdmlsh_lane_d_d_dlane +inst_vqabs :: inst_vqabs_q_q +emit_vqabs :: emit_vqabs_q_q +inst_vqneg :: inst_vqneg_q_q +emit_vqneg :: emit_vqneg_q_q +inst_vmovx :: inst_vmovx_s_s +emit_vmovx :: emit_vmovx_s_s +inst_vins :: inst_vins_s_s +emit_vins :: emit_vins_s_s +inst_vldrb_gather :: inst_vldrb_gather_q_mem_q +emit_vldrb_gather :: emit_vldrb_gather_q_mem_q +inst_vldrh_gather :: inst_vldrh_gather_q_mem_q +emit_vldrh_gather :: emit_vldrh_gather_q_mem_q +inst_vldrw_gather :: inst_vldrw_gather_q_mem_q +emit_vldrw_gather :: emit_vldrw_gather_q_mem_q +inst_vldrd_gather :: inst_vldrd_gather_q_mem_q +emit_vldrd_gather :: emit_vldrd_gather_q_mem_q +inst_vstrb_scatter :: inst_vstrb_scatter_q_mem_q +emit_vstrb_scatter :: emit_vstrb_scatter_q_mem_q +inst_vstrh_scatter :: inst_vstrh_scatter_q_mem_q +emit_vstrh_scatter :: emit_vstrh_scatter_q_mem_q +inst_vstrw_scatter :: inst_vstrw_scatter_q_mem_q +emit_vstrw_scatter :: emit_vstrw_scatter_q_mem_q +inst_vstrd_scatter :: inst_vstrd_scatter_q_mem_q +emit_vstrd_scatter :: emit_vstrd_scatter_q_mem_q +inst_vceq_z :: inst_vceq_z_d_d +emit_vceq_z :: emit_vceq_z_d_d +inst_vcge_z :: inst_vcge_z_d_d +emit_vcge_z :: emit_vcge_z_d_d +inst_vcgt_z :: inst_vcgt_z_d_d +emit_vcgt_z :: emit_vcgt_z_d_d +inst_vcle_z :: inst_vcle_z_d_d +emit_vcle_z :: emit_vcle_z_d_d +inst_vclt_z :: inst_vclt_z_d_d +emit_vclt_z :: emit_vclt_z_d_d +inst_vld2r :: inst_vld2r_dlist_mem +emit_vld2r :: emit_vld2r_dlist_mem +inst_vld3r :: inst_vld3r_dlist_mem +emit_vld3r :: emit_vld3r_dlist_mem +inst_vld4r :: inst_vld4r_dlist_mem +emit_vld4r :: emit_vld4r_dlist_mem +inst_vld1_lane :: inst_vld1_lane_dlane_mem +emit_vld1_lane :: emit_vld1_lane_dlane_mem +inst_vld2_lane :: inst_vld2_lane_dlist_mem +emit_vld2_lane :: emit_vld2_lane_dlist_mem +inst_vld3_lane :: inst_vld3_lane_dlist_mem +emit_vld3_lane :: emit_vld3_lane_dlist_mem +inst_vld4_lane :: inst_vld4_lane_dlist_mem +emit_vld4_lane :: emit_vld4_lane_dlist_mem +inst_vst1_lane :: inst_vst1_lane_dlane_mem +emit_vst1_lane :: emit_vst1_lane_dlane_mem +inst_vst2_lane :: inst_vst2_lane_dlist_mem +emit_vst2_lane :: emit_vst2_lane_dlist_mem +inst_vst3_lane :: inst_vst3_lane_dlist_mem +emit_vst3_lane :: emit_vst3_lane_dlist_mem +inst_vst4_lane :: inst_vst4_lane_dlist_mem +emit_vst4_lane :: emit_vst4_lane_dlist_mem +inst_vcvt_fixed :: inst_vcvt_fixed_s_s_imm +emit_vcvt_fixed :: emit_vcvt_fixed_s_s_imm +inst_it :: inst_it_cond_imm4 +emit_it :: emit_it_cond_imm4 +inst_tt :: inst_tt_r_r +emit_tt :: emit_tt_r_r +inst_ttt :: inst_ttt_r_r +emit_ttt :: emit_ttt_r_r +inst_tta :: inst_tta_r_r +emit_tta :: emit_tta_r_r +inst_ttat :: inst_ttat_r_r +emit_ttat :: emit_ttat_r_r +inst_sg :: inst_sg_none +emit_sg :: emit_sg_none +inst_bxns :: inst_bxns_r +emit_bxns :: emit_bxns_r +inst_blxns :: inst_blxns_r +emit_blxns :: emit_blxns_r +inst_pac :: inst_pac_none +emit_pac :: emit_pac_none +inst_pacbti :: inst_pacbti_none +emit_pacbti :: emit_pacbti_none +inst_aut :: inst_aut_none +emit_aut :: emit_aut_none +inst_autg :: inst_autg_r_r_r +emit_autg :: emit_autg_r_r_r +inst_bti :: inst_bti_none +emit_bti :: emit_bti_none +inst_wls :: inst_wls_r_rel +emit_wls :: emit_wls_r_rel +inst_wlstp :: inst_wlstp_r_rel +emit_wlstp :: emit_wlstp_r_rel +inst_dls :: inst_dls_r +emit_dls :: emit_dls_r +inst_dlstp :: inst_dlstp_r +emit_dlstp :: emit_dlstp_r +inst_le :: inst_le_rel +emit_le :: emit_le_rel +inst_letp :: inst_letp_rel +emit_letp :: emit_letp_rel +inst_lctp :: inst_lctp_none +emit_lctp :: emit_lctp_none +inst_cx1 :: inst_cx1_cp_r_imm +emit_cx1 :: emit_cx1_cp_r_imm +inst_cx1a :: inst_cx1a_cp_r_imm +emit_cx1a :: emit_cx1a_cp_r_imm +inst_cx1d :: inst_cx1d_cp_r_imm +emit_cx1d :: emit_cx1d_cp_r_imm +inst_cx1da :: inst_cx1da_cp_r_imm +emit_cx1da :: emit_cx1da_cp_r_imm +inst_cx2 :: inst_cx2_cp_r_r_imm +emit_cx2 :: emit_cx2_cp_r_r_imm +inst_cx2a :: inst_cx2a_cp_r_r_imm +emit_cx2a :: emit_cx2a_cp_r_r_imm +inst_cx2d :: inst_cx2d_cp_r_r_imm +emit_cx2d :: emit_cx2d_cp_r_r_imm +inst_cx2da :: inst_cx2da_cp_r_r_imm +emit_cx2da :: emit_cx2da_cp_r_r_imm +inst_cx3 :: inst_cx3_cp_r_r_r +emit_cx3 :: emit_cx3_cp_r_r_r +inst_cx3a :: inst_cx3a_cp_r_r_r +emit_cx3a :: emit_cx3a_cp_r_r_r +inst_cx3d :: inst_cx3d_cp_r_r_r +emit_cx3d :: emit_cx3d_cp_r_r_r +inst_cx3da :: inst_cx3da_cp_r_r_r +emit_cx3da :: emit_cx3da_cp_r_r_r +inst_vcx1 :: inst_vcx1_cp_s_imm +emit_vcx1 :: emit_vcx1_cp_s_imm +inst_vcx1a :: inst_vcx1a_cp_s_imm +emit_vcx1a :: emit_vcx1a_cp_s_imm +inst_vcx2 :: inst_vcx2_cp_s_s_imm +emit_vcx2 :: emit_vcx2_cp_s_s_imm +inst_vcx2a :: inst_vcx2a_cp_s_s_imm +emit_vcx2a :: emit_vcx2a_cp_s_s_imm +inst_vcx3 :: inst_vcx3_cp_s_s_s +emit_vcx3 :: emit_vcx3_cp_s_s_s +inst_vcx3a :: inst_vcx3a_cp_s_s_s +emit_vcx3a :: emit_vcx3a_cp_s_s_s +inst_vpt :: inst_vpt_vpt_cond_q_q +emit_vpt :: emit_vpt_vpt_cond_q_q +inst_vpst :: inst_vpst_vpt +emit_vpst :: emit_vpst_vpt +inst_vpsel :: inst_vpsel_q_q_q +emit_vpsel :: emit_vpsel_q_q_q +inst_vpnot :: inst_vpnot_none +emit_vpnot :: emit_vpnot_none +inst_vctp :: inst_vctp_r +emit_vctp :: emit_vctp_r +inst_vaddv :: inst_vaddv_r_q +emit_vaddv :: emit_vaddv_r_q +inst_vaddva :: inst_vaddva_r_q +emit_vaddva :: emit_vaddva_r_q +inst_vaddlv :: inst_vaddlv_r_r_q +emit_vaddlv :: emit_vaddlv_r_r_q +inst_vaddlva :: inst_vaddlva_r_r_q +emit_vaddlva :: emit_vaddlva_r_r_q +inst_vmaxv :: inst_vmaxv_r_q +emit_vmaxv :: emit_vmaxv_r_q +inst_vmaxav :: inst_vmaxav_r_q +emit_vmaxav :: emit_vmaxav_r_q +inst_vminv :: inst_vminv_r_q +emit_vminv :: emit_vminv_r_q +inst_vminav :: inst_vminav_r_q +emit_vminav :: emit_vminav_r_q +inst_vmaxnmv :: inst_vmaxnmv_r_q +emit_vmaxnmv :: emit_vmaxnmv_r_q +inst_vmaxnmav :: inst_vmaxnmav_r_q +emit_vmaxnmav :: emit_vmaxnmav_r_q +inst_vminnmv :: inst_vminnmv_r_q +emit_vminnmv :: emit_vminnmv_r_q +inst_vminnmav :: inst_vminnmav_r_q +emit_vminnmav :: emit_vminnmav_r_q +inst_vabav :: inst_vabav_r_q_q +emit_vabav :: emit_vabav_r_q_q +inst_vmladav :: inst_vmladav_r_q_q +emit_vmladav :: emit_vmladav_r_q_q +inst_vmladava :: inst_vmladava_r_q_q +emit_vmladava :: emit_vmladava_r_q_q +inst_vmladavx :: inst_vmladavx_r_q_q +emit_vmladavx :: emit_vmladavx_r_q_q +inst_vmladavax :: inst_vmladavax_r_q_q +emit_vmladavax :: emit_vmladavax_r_q_q +inst_vmlaldav :: inst_vmlaldav_r_r_q_q +emit_vmlaldav :: emit_vmlaldav_r_r_q_q +inst_vmlaldava :: inst_vmlaldava_r_r_q_q +emit_vmlaldava :: emit_vmlaldava_r_r_q_q +inst_vmlaldavx :: inst_vmlaldavx_r_r_q_q +emit_vmlaldavx :: emit_vmlaldavx_r_r_q_q +inst_vmlaldavax :: inst_vmlaldavax_r_r_q_q +emit_vmlaldavax :: emit_vmlaldavax_r_r_q_q +inst_vmlsdav :: inst_vmlsdav_r_q_q +emit_vmlsdav :: emit_vmlsdav_r_q_q +inst_vmlsdava :: inst_vmlsdava_r_q_q +emit_vmlsdava :: emit_vmlsdava_r_q_q +inst_vmlsdavx :: inst_vmlsdavx_r_q_q +emit_vmlsdavx :: emit_vmlsdavx_r_q_q +inst_vmlsdavax :: inst_vmlsdavax_r_q_q +emit_vmlsdavax :: emit_vmlsdavax_r_q_q +inst_vmlsldav :: inst_vmlsldav_r_r_q_q +emit_vmlsldav :: emit_vmlsldav_r_r_q_q +inst_vmlsldava :: inst_vmlsldava_r_r_q_q +emit_vmlsldava :: emit_vmlsldava_r_r_q_q +inst_vmlsldavx :: inst_vmlsldavx_r_r_q_q +emit_vmlsldavx :: emit_vmlsldavx_r_r_q_q +inst_vmlsldavax :: inst_vmlsldavax_r_r_q_q +emit_vmlsldavax :: emit_vmlsldavax_r_r_q_q +inst_vrmlaldavh :: inst_vrmlaldavh_r_r_q_q +emit_vrmlaldavh :: emit_vrmlaldavh_r_r_q_q +inst_vrmlaldavha :: inst_vrmlaldavha_r_r_q_q +emit_vrmlaldavha :: emit_vrmlaldavha_r_r_q_q +inst_vrmlaldavhx :: inst_vrmlaldavhx_r_r_q_q +emit_vrmlaldavhx :: emit_vrmlaldavhx_r_r_q_q +inst_vrmlaldavhax :: inst_vrmlaldavhax_r_r_q_q +emit_vrmlaldavhax :: emit_vrmlaldavhax_r_r_q_q +inst_vrmlsldavh :: inst_vrmlsldavh_r_r_q_q +emit_vrmlsldavh :: emit_vrmlsldavh_r_r_q_q +inst_vrmlsldavha :: inst_vrmlsldavha_r_r_q_q +emit_vrmlsldavha :: emit_vrmlsldavha_r_r_q_q +inst_vrmlsldavhx :: inst_vrmlsldavhx_r_r_q_q +emit_vrmlsldavhx :: emit_vrmlsldavhx_r_r_q_q +inst_vrmlsldavhax :: inst_vrmlsldavhax_r_r_q_q +emit_vrmlsldavhax :: emit_vrmlsldavhax_r_r_q_q +inst_vmlav :: inst_vmlav_r_q_q +emit_vmlav :: emit_vmlav_r_q_q +inst_vmlava :: inst_vmlava_r_q_q +emit_vmlava :: emit_vmlava_r_q_q +inst_vcmul :: inst_vcmul_q_q_q +emit_vcmul :: emit_vcmul_q_q_q +inst_vhcadd :: inst_vhcadd_q_q_q +emit_vhcadd :: emit_vhcadd_q_q_q +inst_vbrsr :: inst_vbrsr_q_q_r +emit_vbrsr :: emit_vbrsr_q_q_r +inst_vshlc :: inst_vshlc_q_r_imm5 +emit_vshlc :: emit_vshlc_q_r_imm5 +inst_vddup :: inst_vddup_q_r_imm +emit_vddup :: emit_vddup_q_r_imm +inst_vidup :: inst_vidup_q_r_imm +emit_vidup :: emit_vidup_q_r_imm +inst_vdwdup :: inst_vdwdup_q_r_r_imm +emit_vdwdup :: emit_vdwdup_q_r_r_imm +inst_viwdup :: inst_viwdup_q_r_r_imm +emit_viwdup :: emit_viwdup_q_r_r_imm +inst_vmovnb :: inst_vmovnb_q_q +emit_vmovnb :: emit_vmovnb_q_q +inst_vmovnt :: inst_vmovnt_q_q +emit_vmovnt :: emit_vmovnt_q_q +inst_vqmovnb :: inst_vqmovnb_q_q +emit_vqmovnb :: emit_vqmovnb_q_q +inst_vqmovnt :: inst_vqmovnt_q_q +emit_vqmovnt :: emit_vqmovnt_q_q +inst_vqmovunb :: inst_vqmovunb_q_q +emit_vqmovunb :: emit_vqmovunb_q_q +inst_vqmovunt :: inst_vqmovunt_q_q +emit_vqmovunt :: emit_vqmovunt_q_q +inst_vshllb :: inst_vshllb_q_q_imm5 +emit_vshllb :: emit_vshllb_q_q_imm5 +inst_vshllt :: inst_vshllt_q_q_imm5 +emit_vshllt :: emit_vshllt_q_q_imm5 +inst_vmullb :: inst_vmullb_q_q_q +emit_vmullb :: emit_vmullb_q_q_q +inst_vmullt :: inst_vmullt_q_q_q +emit_vmullt :: emit_vmullt_q_q_q +inst_vmlalb :: inst_vmlalb_q_q_q +emit_vmlalb :: emit_vmlalb_q_q_q +inst_vmlalt :: inst_vmlalt_q_q_q +emit_vmlalt :: emit_vmlalt_q_q_q +inst_vmlslb :: inst_vmlslb_q_q_q +emit_vmlslb :: emit_vmlslb_q_q_q +inst_vmlslt :: inst_vmlslt_q_q_q +emit_vmlslt :: emit_vmlslt_q_q_q +inst_vshrnb :: inst_vshrnb_q_q_imm5 +emit_vshrnb :: emit_vshrnb_q_q_imm5 +inst_vshrnt :: inst_vshrnt_q_q_imm5 +emit_vshrnt :: emit_vshrnt_q_q_imm5 +inst_vrshrnb :: inst_vrshrnb_q_q_imm5 +emit_vrshrnb :: emit_vrshrnb_q_q_imm5 +inst_vrshrnt :: inst_vrshrnt_q_q_imm5 +emit_vrshrnt :: emit_vrshrnt_q_q_imm5 +inst_vqshrnb :: inst_vqshrnb_q_q_imm5 +emit_vqshrnb :: emit_vqshrnb_q_q_imm5 +inst_vqshrnt :: inst_vqshrnt_q_q_imm5 +emit_vqshrnt :: emit_vqshrnt_q_q_imm5 +inst_vqrshrnb :: inst_vqrshrnb_q_q_imm5 +emit_vqrshrnb :: emit_vqrshrnb_q_q_imm5 +inst_vqrshrnt :: inst_vqrshrnt_q_q_imm5 +emit_vqrshrnt :: emit_vqrshrnt_q_q_imm5 +inst_vqshrunb :: inst_vqshrunb_q_q_imm5 +emit_vqshrunb :: emit_vqshrunb_q_q_imm5 +inst_vqshrunt :: inst_vqshrunt_q_q_imm5 +emit_vqshrunt :: emit_vqshrunt_q_q_imm5 +inst_vqrshrunb :: inst_vqrshrunb_q_q_imm5 +emit_vqrshrunb :: emit_vqrshrunb_q_q_imm5 +inst_vqrshrunt :: inst_vqrshrunt_q_q_imm5 +emit_vqrshrunt :: emit_vqrshrunt_q_q_imm5 +inst_vmov_q_r :: inst_vmov_q_r_qlane_r +emit_vmov_q_r :: emit_vmov_q_r_qlane_r +inst_vmov_r_q :: inst_vmov_r_q_r_qlane +emit_vmov_r_q :: emit_vmov_r_q_r_qlane +inst_vmov_2gpr_q :: inst_vmov_2gpr_q_qlane_qlane_r_r +emit_vmov_2gpr_q :: emit_vmov_2gpr_q_qlane_qlane_r_r +inst_vqdmladh :: inst_vqdmladh_q_q_q +emit_vqdmladh :: emit_vqdmladh_q_q_q +inst_vqdmladhx :: inst_vqdmladhx_q_q_q +emit_vqdmladhx :: emit_vqdmladhx_q_q_q +inst_vqdmlsdh :: inst_vqdmlsdh_q_q_q +emit_vqdmlsdh :: emit_vqdmlsdh_q_q_q +inst_vqdmlsdhx :: inst_vqdmlsdhx_q_q_q +emit_vqdmlsdhx :: emit_vqdmlsdhx_q_q_q +inst_vqrdmladh :: inst_vqrdmladh_q_q_q +emit_vqrdmladh :: emit_vqrdmladh_q_q_q +inst_vqrdmladhx :: inst_vqrdmladhx_q_q_q +emit_vqrdmladhx :: emit_vqrdmladhx_q_q_q +inst_vqrdmlsdh :: inst_vqrdmlsdh_q_q_q +emit_vqrdmlsdh :: emit_vqrdmlsdh_q_q_q +inst_vqrdmlsdhx :: inst_vqrdmlsdhx_q_q_q +emit_vqrdmlsdhx :: emit_vqrdmlsdhx_q_q_q +inst_vldrb :: inst_vldrb_q_mem +emit_vldrb :: emit_vldrb_q_mem +inst_vldrh :: inst_vldrh_q_mem +emit_vldrh :: emit_vldrh_q_mem +inst_vldrw :: inst_vldrw_q_mem +emit_vldrw :: emit_vldrw_q_mem +inst_vldrd :: inst_vldrd_q_mem +emit_vldrd :: emit_vldrd_q_mem +inst_vstrb :: inst_vstrb_q_mem +emit_vstrb :: emit_vstrb_q_mem +inst_vstrh :: inst_vstrh_q_mem +emit_vstrh :: emit_vstrh_q_mem +inst_vstrw :: inst_vstrw_q_mem +emit_vstrw :: emit_vstrw_q_mem +inst_vstrd :: inst_vstrd_q_mem +emit_vstrd :: emit_vstrd_q_mem +inst_vld20 :: inst_vld20_qlist_mem +emit_vld20 :: emit_vld20_qlist_mem +inst_vld21 :: inst_vld21_qlist_mem +emit_vld21 :: emit_vld21_qlist_mem +inst_vld40 :: inst_vld40_qlist_mem +emit_vld40 :: emit_vld40_qlist_mem +inst_vld41 :: inst_vld41_qlist_mem +emit_vld41 :: emit_vld41_qlist_mem +inst_vld42 :: inst_vld42_qlist_mem +emit_vld42 :: emit_vld42_qlist_mem +inst_vld43 :: inst_vld43_qlist_mem +emit_vld43 :: emit_vld43_qlist_mem +inst_vst20 :: inst_vst20_qlist_mem +emit_vst20 :: emit_vst20_qlist_mem +inst_vst21 :: inst_vst21_qlist_mem +emit_vst21 :: emit_vst21_qlist_mem +inst_vst40 :: inst_vst40_qlist_mem +emit_vst40 :: emit_vst40_qlist_mem +inst_vst41 :: inst_vst41_qlist_mem +emit_vst41 :: emit_vst41_qlist_mem +inst_vst42 :: inst_vst42_qlist_mem +emit_vst42 :: emit_vst42_qlist_mem +inst_vst43 :: inst_vst43_qlist_mem +emit_vst43 :: emit_vst43_qlist_mem diff --git a/core/rexcode/arm32/tools/gen_mnemonic_builders.odin b/core/rexcode/arm32/tools/gen_mnemonic_builders.odin index 877cf2fe8..1fc045503 100644 --- a/core/rexcode/arm32/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/arm32/tools/gen_mnemonic_builders.odin @@ -15,18 +15,28 @@ package main // // arm32 has a very rich operand set (shifted/extended regs, register-shifted // register, NEON lane/vector forms, modified immediates, register lists, -// coprocessor selectors, MVE/CDE classes, ...). Many of these have no clean -// single-value constructor, so — like x86 skips far pointers / moffs — we only -// emit a builder for a form when EVERY one of its operands is cleanly -// constructible from a single typed parameter. The skipped operand classes are -// listed in is_buildable_operand() below. +// coprocessor selectors, MVE/CDE classes, ...). EVERY operand type maps to one +// or more typed parameters here — there are no skipped operand classes — so a +// builder is emitted for every form whose operands fit in <=4 slots (which is +// every real form). The mapping mirrors what the encoder's pack_operand_inline +// reads out of each Operand: +// +// plain reg -> op_reg(Register) +// shifted reg (imm) -> op_reg_shifted(Register, Shift_Type, u8) +// register-shifted reg -> op_reg_shifted(Register, Shift_Type, u8(reg_hw(Rs))) +// register list -> op_reg_list(u16 mask) +// NEON D/Q lane elem -> op_dpr_lane / op_qpr_lane (Register, u8 lane) +// any immediate class -> op_imm(i64) (the encoder does the field packing: +// modified-imm, barrier, endian, iflags, sysm, coproc, +// saturating, PSR field, hint, cond-operand, ...) +// memory -> op_mem(Memory) +// PC-relative / loop -> op_rel_offset(i64) // // Note: arm32's Register is a single distinct-u16 type with NO per-class typed // enums (GPR / SPR / DPR / QPR all share the `Register` type). Every register // parameter is therefore `Register`. Two forms of one mnemonic that reduce to -// the same parameter-type tuple would create an ambiguous overload set, so we -// additionally dedup by the Odin parameter-type signature, keeping the first -// (table-order) form. +// the same ordered Odin parameter-type tuple would create an ambiguous overload +// set, so we dedup by that tuple, keeping the first (table-order) form. import "core:fmt" import "core:os" @@ -36,7 +46,7 @@ import a "../" GEN_ATTRIB :: "// rexcode · Brendan Punsky (dotbmp@github), original author\n\n" -// Per-form operand signature (explicit, buildable operands only). +// Per-form operand signature. Operand_Signature :: struct { types: [4]a.Operand_Type, mode: a.Mode, @@ -59,113 +69,171 @@ mnemonic_to_lower :: proc(m: a.Mnemonic) -> string { // Truly-implicit operands carry no user value and emit no bits. Note: a .NONE // encoding slot does NOT mean implicit — many real operands (immediates, some // regs) have enc == .NONE because the encoder derives their bit placement from -// the operand TYPE rather than a named slot. Presence is keyed on the operand -// type (ops[i] != .NONE); only enc == .IMPL is dropped. (The current arm32 -// table contains zero .IMPL operands; this guard is for forward-compat.) +// the operand TYPE rather than a named slot (or, for COND-as-operand, the value +// rides in a sibling field). Presence is keyed on the operand TYPE +// (ops[i] != .NONE); only enc == .IMPL is dropped. (The current arm32 table +// contains zero .IMPL operands; this guard is for forward-compat.) is_implicit_operand :: proc(enc: a.Operand_Encoding) -> bool { return enc == .IMPL } +// A build class describes the shape of the typed parameter(s) an operand needs +// and which op_* constructor assembles it. Unlike the old generator, this is +// TOTAL over Operand_Type: every type maps to exactly one class so no form is +// ever skipped for operand reasons. Operand_Class :: enum { - NONE, // not buildable - REG, // single Register - IMM, // i64 immediate - MEM, // Memory operand - REL, // branch target (raw i64 offset) + REG, // op_reg(Register) + IMM, // op_imm(i64) -- includes all encoded-imm subclasses + MEM, // op_mem(Memory) + REL, // op_rel_offset(i64) + SHIFTED, // op_reg_shifted(Register, Shift_Type, u8) -- imm shift + RSR, // op_reg_shifted(Register, Shift_Type, u8(reg_hw(Rs))) -- reg shift + LIST, // op_reg_list(u16) + LANE_D, // op_dpr_lane(Register, u8) + LANE_Q, // op_qpr_lane(Register, u8) } -// Map an operand TYPE to a build class. Returns .NONE for operand types that -// have no clean single-value constructor (these forms are skipped wholesale). -// -// Covered : plain GPR/FP/SIMD registers, plain numeric immediates, MEM, -// PC-relative branch targets. -// Skipped : shifted/RSR regs, register lists, NEON lane/vector elem forms, -// modified immediates, NEON imm, condition-code operand, coprocessor -// selectors, PSR field, MVE/CDE classes, special encoded immediates -// (barrier/endian/iflags/banked/sysm/coproc/hint). +// Map an operand TYPE to its build class. Total: every Operand_Type that can +// appear in a form has a mapping. The encoder's operand_matches_inline / +// pack_operand_inline define the contract each class must satisfy. operand_class :: proc(ot: a.Operand_Type) -> Operand_Class { #partial switch ot { - // ---- Plain registers (single Register value) ---- - case .GPR, .GPR_NOPC, .GPR_NOSP, .GPR_LOW: - return .REG - case .SPR, .DPR, .QPR, .SPR_ELEM, .QPR_MVE: - return .REG + // ---- Shifted / register-shifted GPR ---- + case .GPR_SHIFTED: + return .SHIFTED + case .GPR_RSR: + return .RSR - // ---- Plain numeric immediates (single i64 value) ---- - case .IMM, .IMM12, .IMM5, .IMM5_W, .IMM4, .IMM4_SAT, .IMM8, .IMM3, .IMM16_LO_HI: - return .IMM + // ---- Register lists (GPR/SPR/DPR/MVE-Q) ---- + case .GPR_LIST, .SPR_LIST, .DPR_LIST, .QPR_MVE_LIST: + return .LIST + + // ---- NEON lane elements ---- + case .DPR_ELEM: + return .LANE_D + case .QPR_ELEM: + return .LANE_Q // ---- Memory ---- case .MEM: return .MEM - // ---- PC-relative branch targets ---- - case .REL24, .REL24_T32, .REL20, .REL11, .REL8: + // ---- PC-relative branch targets & low-overhead-loop targets ---- + case .REL24, .REL24_T32, .REL20, .REL11, .REL8, .REL_LDR_LITERAL, .MVE_LOOP_TGT: return .REL + + // ---- Plain registers (single Register value) ---- + case .GPR, .GPR_NOPC, .GPR_NOSP, .GPR_LOW, + .SPR, .DPR, .QPR, .SPR_ELEM, .QPR_MVE, .VPR, + .COPROC_REG, .COPROC_NUM, .CDE_VFP_REG: + return .REG } - // Everything else is not cleanly buildable -> skip the form. - return .NONE + // Everything else is an immediate the encoder packs from op.immediate: + // IMM/IMM12/IMM5/.../modified-imm/barrier/endian/iflags/banked/sysm/coproc/ + // coproc-op/NEON-imm/hint/PSR_FIELD/COND/MVE-size/MVE-vpt-mask/CDE-imm/ + // CDE-coproc, etc. All single i64 via op_imm. + return .IMM } -// Suffix used in the procedure name for an operand type. +// Suffix used in the procedure name for an operand type. Distinct per type so +// proc names stay readable; overload ambiguity is handled separately by the +// Odin param-type-tuple dedup. operand_suffix :: proc(ot: a.Operand_Type) -> string { #partial switch ot { - case .GPR: return "r" - case .GPR_NOPC: return "r" - case .GPR_NOSP: return "r" - case .GPR_LOW: return "rlo" - case .SPR: return "s" - case .SPR_ELEM: return "s" - case .DPR: return "d" - case .QPR: return "q" - case .QPR_MVE: return "qm" - case .IMM: return "imm" - case .IMM12: return "imm12" - case .IMM5: return "imm5" - case .IMM5_W: return "imm5w" - case .IMM4: return "imm4" - case .IMM4_SAT: return "imm4s" - case .IMM8: return "imm8" - case .IMM3: return "imm3" - case .IMM16_LO_HI: return "imm16" - case .MEM: return "mem" - case .REL24: return "rel" - case .REL24_T32: return "rel" - case .REL20: return "rel" - case .REL11: return "rel" - case .REL8: return "rel" + case .GPR: return "r" + case .GPR_NOPC: return "r" + case .GPR_NOSP: return "r" + case .GPR_LOW: return "rlo" + case .GPR_SHIFTED: return "rsh" + case .GPR_RSR: return "rsr" + case .GPR_LIST: return "list" + case .SPR: return "s" + case .SPR_ELEM: return "s" + case .SPR_LIST: return "slist" + case .DPR: return "d" + case .DPR_ELEM: return "dlane" + case .DPR_LIST: return "dlist" + case .QPR: return "q" + case .QPR_ELEM: return "qlane" + case .QPR_MVE: return "qm" + case .QPR_MVE_LIST: return "qlist" + case .VPR: return "vpr" + case .IMM: return "imm" + case .IMM_MOD: return "immm" + case .IMM_T32_MOD: return "immtm" + case .IMM12: return "imm12" + case .IMM5: return "imm5" + case .IMM5_W: return "imm5w" + case .IMM4: return "imm4" + case .IMM4_SAT: return "imm4s" + case .IMM8: return "imm8" + case .IMM3: return "imm3" + case .IMM16_LO_HI: return "imm16" + case .IMM_HINT: return "hint" + case .IMM_BARRIER: return "barr" + case .IMM_ENDIAN: return "end" + case .IMM_IFLAGS: return "ifl" + case .IMM_BANKED: return "bank" + case .IMM_SYSM: return "sysm" + case .IMM_COPROC: return "cp" + case .IMM_COPROC_OP: return "cpop" + case .NEON_IMM: return "nimm" + case .COND: return "cond" + case .MEM: return "mem" + case .REL24: return "rel" + case .REL24_T32: return "rel" + case .REL20: return "rel" + case .REL11: return "rel" + case .REL8: return "rel" + case .REL_LDR_LITERAL: return "rel" + case .COPROC_REG: return "crd" + case .COPROC_NUM: return "cpn" + case .PSR_FIELD: return "psr" + case .MVE_VPT_MASK: return "vpt" + case .MVE_VCTP_SIZE: return "vsz" + case .MVE_LOOP_TGT: return "loop" + case .CDE_COPROC: return "cdec" + case .CDE_IMM: return "cdei" + case .CDE_VFP_REG: return "cdev" } return "x" } -// Odin parameter type for an operand type. -operand_odin_type :: proc(ot: a.Operand_Type) -> string { - switch operand_class(ot) { - case .REG: return "Register" - case .IMM: return "i64" - case .MEM: return "Memory" - case .REL: return "i64" - case .NONE: return "unknown" - } - return "unknown" -} +// Static parameter-type lists (returned as slices into rodata, so they don't +// alias a stack frame). +@(rodata) PT_REG := []string{"Register"} +@(rodata) PT_IMM := []string{"i64"} +@(rodata) PT_MEM := []string{"Memory"} +@(rodata) PT_REL := []string{"i64"} +@(rodata) PT_SHIFTED := []string{"Register", "Shift_Type", "u8"} +@(rodata) PT_RSR := []string{"Register", "Shift_Type", "Register"} +@(rodata) PT_LIST := []string{"u16"} +@(rodata) PT_LANE := []string{"Register", "u8"} -// Build the op_* expression for one operand. -operand_expr :: proc(sb: ^strings.Builder, ot: a.Operand_Type, name: string) { +// The ordered list of Odin parameter TYPES an operand expands to. Most operands +// are a single param; shifted / register-shifted regs and NEON lane elems take +// extra params (shift kind + amount, or lane index). +operand_param_types :: proc(ot: a.Operand_Type) -> []string { switch operand_class(ot) { - case .REG: fmt.sbprintf(sb, "op_reg(%s)", name) - case .IMM: fmt.sbprintf(sb, "op_imm(%s)", name) - case .MEM: fmt.sbprintf(sb, "op_mem(%s)", name) - case .REL: fmt.sbprintf(sb, "op_rel_offset(%s)", name) - case .NONE: strings.write_string(sb, "{}") + case .REG: return PT_REG + case .IMM: return PT_IMM + case .MEM: return PT_MEM + case .REL: return PT_REL + case .SHIFTED: return PT_SHIFTED + case .RSR: return PT_RSR + case .LIST: return PT_LIST + case .LANE_D: return PT_LANE + case .LANE_Q: return PT_LANE } + return PT_REG } // ---- Signature extraction --------------------------------------------------- -// Returns ok=false if the form has any non-buildable explicit operand, or if it -// has more than 4 explicit operands. An all-NONE form yields count=0 (e.g. NOP). +// Returns ok=false only if the form has more than 4 explicit operands (no real +// arm32 form does). An all-NONE form yields count=0 (e.g. NOP). No form is +// skipped for operand-type reasons — operand_class is total. form_signature :: proc(form: a.Encoding) -> (sig: Operand_Signature, ok: bool) { sig.mode = form.mode sig.length = a.inst_size_from_bits(form.bits, form.mode) @@ -173,9 +241,6 @@ form_signature :: proc(form: a.Encoding) -> (sig: Operand_Signature, ok: bool) { if ot == .NONE { continue } if is_implicit_operand(form.enc[i]) { continue } - if operand_class(ot) == .NONE { - return {}, false - } if sig.count >= 4 { return {}, false } @@ -207,43 +272,128 @@ proc_name_for :: proc(m: a.Mnemonic, sig: Operand_Signature) -> string { return strings.clone(strings.to_string(sb)) } -// Parameter names: dst / src / src2 / src3 for register & memory operands; -// imm / imm2 for immediates; offset for branch targets. -param_names :: proc(sig: Operand_Signature) -> [4]string { - out: [4]string - src_count := 0 - imm_count := 0 +// One concrete parameter: a name and an Odin type. +Param :: struct { + name: string, + type: string, +} + +// Flatten a signature into the ordered list of concrete (name, type) params. +// Names are derived per role so the generated source is readable and unique +// within a proc: +// register/memory dst -> dst; subsequent -> src, src2, ... +// immediates -> imm, imm2, ... +// branch targets -> offset +// shift kind / amount -> shift / amount (suffixed when repeated) +// lane index -> lane (suffixed when repeated) +// register list mask -> regs (suffixed when repeated) +// RSR shift register -> rs (suffixed when repeated) +flatten_params :: proc(sig: Operand_Signature) -> [dynamic]Param { + out: [dynamic]Param + src_count := 0 + imm_count := 0 + off_count := 0 + shift_count := 0 + amt_count := 0 + lane_count := 0 + list_count := 0 + rs_count := 0 + + uniq :: proc(base: string, n: ^int) -> string { + defer n^ += 1 + return n^ == 0 ? strings.clone(base) : fmt.aprintf("%s%d", base, n^ + 1) + } + for i in 0.. int { + switch operand_class(ot) { + case .REG: + fmt.sbprintf(sb, "op_reg(%s)", ps[pi].name) + return pi + 1 + case .IMM: + fmt.sbprintf(sb, "op_imm(%s)", ps[pi].name) + return pi + 1 + case .MEM: + fmt.sbprintf(sb, "op_mem(%s)", ps[pi].name) + return pi + 1 + case .REL: + fmt.sbprintf(sb, "op_rel_offset(%s)", ps[pi].name) + return pi + 1 + case .SHIFTED: + fmt.sbprintf(sb, "op_reg_shifted(%s, %s, %s)", ps[pi].name, ps[pi+1].name, ps[pi+2].name) + return pi + 3 + case .RSR: + // op_reg_shifted's amount slot carries the Rs hardware number for + // register-shifted-register forms (see pack_operand_inline / RM_A32). + fmt.sbprintf(sb, "op_reg_shifted(%s, %s, u8(reg_hw(%s)))", ps[pi].name, ps[pi+1].name, ps[pi+2].name) + return pi + 3 + case .LIST: + fmt.sbprintf(sb, "op_reg_list(%s)", ps[pi].name) + return pi + 1 + case .LANE_D: + fmt.sbprintf(sb, "op_dpr_lane(%s, %s)", ps[pi].name, ps[pi+1].name) + return pi + 2 + case .LANE_Q: + fmt.sbprintf(sb, "op_qpr_lane(%s, %s)", ps[pi].name, ps[pi+1].name) + return pi + 2 + } + strings.write_string(sb, "{}") + return pi + 1 +} + +// Type-signature key for overload-ambiguity dedup: the ordered tuple of Odin +// parameter types plus the mnemonic. Two forms with identical param-type tuples +// cannot coexist in one overload set, so we keep only the first. type_sig_key :: proc(m: a.Mnemonic, sig: Operand_Signature) -> string { sb := strings.builder_make() defer strings.builder_destroy(&sb) fmt.sbprintf(&sb, "%v|", m) for i in 0.. string { // causes the encoder to reject them. Baking `length` from the form via // inst_size_from_bits() keeps A32 (4), T16 (2) and T32-wide (4) all correct. // cond defaults to 14 (AL); sets_flags / wide are left at their zero defaults. -inst_body :: proc(sb: ^strings.Builder, entry: Proc_Entry) { +inst_body :: proc(sb: ^strings.Builder, entry: Proc_Entry, ps: []Param) { sig := entry.sig - names := param_names(sig) mn := fmt.tprintf("%v", entry.mnemonic) ops := strings.builder_make() defer strings.builder_destroy(&ops) + pi := 0 for i in 0..<4 { if i > 0 { strings.write_string(&ops, ", ") } if i < sig.count { - operand_expr(&ops, sig.types[i], names[i]) + pi = operand_expr(&ops, sig.types[i], ps, pi) } else { strings.write_string(&ops, "{}") } @@ -279,24 +429,24 @@ inst_body :: proc(sb: ^strings.Builder, entry: Proc_Entry) { // ---- Emitters --------------------------------------------------------------- +write_param_list :: proc(sb: ^strings.Builder, ps: []Param) { + for p, i in ps { + if i > 0 { strings.write_string(sb, ", ") } + fmt.sbprintf(sb, "%s: %s", p.name, p.type) + } +} + // inst_ procedure (compact one line). #force_inline contextless like x86. write_inst_proc :: proc(sb: ^strings.Builder, entry: Proc_Entry, pad: int) { - sig := entry.sig - names := param_names(sig) - - params := strings.builder_make() - defer strings.builder_destroy(¶ms) - for i in 0.. 0 { strings.write_string(¶ms, ", ") } - fmt.sbprintf(¶ms, "%s: %s", names[i], operand_odin_type(sig.types[i])) - } + ps := flatten_params(entry.sig) + defer { for p in ps { delete(p.name) }; delete(ps) } strings.write_string(sb, entry.proc_name) for n := pad - len(entry.proc_name); n > 0; n -= 1 { strings.write_byte(sb, ' ') } strings.write_string(sb, " :: #force_inline proc \"contextless\" (") - strings.write_string(sb, strings.to_string(params)) + write_param_list(sb, ps[:]) strings.write_string(sb, ") -> Instruction { return ") - inst_body(sb, entry) + inst_body(sb, entry, ps[:]) strings.write_string(sb, " }\n") } @@ -304,28 +454,24 @@ write_inst_proc :: proc(sb: ^strings.Builder, entry: Proc_Entry, pad: int) { // append needs context. arm32 has no encoder-level emit_* helpers, so these // simply wrap the inst_ builder. write_emit_proc :: proc(sb: ^strings.Builder, entry: Proc_Entry, pad: int) { - sig := entry.sig - names := param_names(sig) + ps := flatten_params(entry.sig) + defer { for p in ps { delete(p.name) }; delete(ps) } + emit_name := strings.concatenate({"emit_", entry.proc_name[5:]}) defer delete(emit_name) - params := strings.builder_make() - defer strings.builder_destroy(¶ms) - strings.write_string(¶ms, "instructions: ^[dynamic]Instruction") - for i in 0.. 0; n -= 1 { strings.write_byte(sb, ' ') } - strings.write_string(sb, " :: #force_inline proc(") - strings.write_string(sb, strings.to_string(params)) + strings.write_string(sb, " :: #force_inline proc(instructions: ^[dynamic]Instruction") + for p in ps { + fmt.sbprintf(sb, ", %s: %s", p.name, p.type) + } strings.write_string(sb, ") { append(instructions, ") strings.write_string(sb, entry.proc_name) strings.write_byte(sb, '(') - for i in 0.. 0 { strings.write_string(sb, ", ") } - strings.write_string(sb, names[i]) + strings.write_string(sb, p.name) } strings.write_string(sb, ")) }\n") } @@ -347,13 +493,23 @@ main :: proc() { defer delete(seen_names) defer delete(seen_type_sigs) - total_forms := 0 - skipped_forms := 0 + // Zero-form mnemonics (no encode forms at all) get no builder. + zero_form: [dynamic]a.Mnemonic + defer delete(zero_form) + + total_forms := 0 + skipped_forms := 0 // forms dropped for >4 operands (expected: 0) + dropped_overload := 0 // forms collapsed into an existing overload signature for m in a.Mnemonic { if m == .INVALID { continue } + if m == ._COUNT { continue } // enum-size sentinel, not a real mnemonic _run := a.ENCODE_RUNS[u16(m)] + if _run.count == 0 { + append(&zero_form, m) + continue + } forms := a.ENCODE_FORMS[_run.start:][:_run.count] for form in forms { @@ -366,12 +522,16 @@ main :: proc() { } name := proc_name_for(m, sig) - if name in seen_names { continue } + if name in seen_names { delete(name); continue } tkey := type_sig_key(m, sig) if tkey in seen_type_sigs { // Same param-type tuple already taken for this mnemonic; a second - // one would make the overload set ambiguous. + // one would make the overload set ambiguous (all arm32 register + // classes share the single `Register` type). + dropped_overload += 1 + delete(name) + delete(tkey) continue } @@ -462,10 +622,13 @@ main :: proc() { total_procs := 0 for m in mlist { total_procs += len(procs_by_mnemonic[m]) } fmt.println("Generated mnemonic_builders.odin successfully!") - fmt.printf("Mnemonics with builders: %d\n", len(mlist)) - fmt.printf("Procedures generated: %d\n", total_procs) - fmt.printf("Forms total: %d\n", total_forms) - fmt.printf("Forms skipped (operand): %d\n", skipped_forms) + fmt.printf("Mnemonics with builders: %d\n", len(mlist)) + fmt.printf("Procedures generated: %d\n", total_procs) + fmt.printf("Forms total: %d\n", total_forms) + fmt.printf("Forms skipped (>4 ops): %d\n", skipped_forms) + fmt.printf("Forms folded (overload): %d\n", dropped_overload) + fmt.printf("Zero-form mnemonics: %d\n", len(zero_form)) + for zm in zero_form { fmt.printf(" %v\n", zm) } } else { fmt.eprintln("Failed to write mnemonic_builders.odin") os.exit(1) @@ -482,13 +645,18 @@ write_header :: proc(sb: ^strings.Builder) { // Generated by tools/gen_mnemonic_builders.odin from ENCODE_FORMS / ENCODE_RUNS. // Regenerate with: odin run arm32/tools/gen_mnemonic_builders.odin -file // -// Typed mnemonic builder procedures with overloading. Each mnemonic exposes an -// inst_ overload set (returns Instruction) and an emit_ overload -// set (appends to a ^[dynamic]Instruction). Only forms whose every operand is -// cleanly constructible from a single typed parameter are generated; shifted / -// register-shifted registers, register lists, NEON lane/vector forms, modified -// immediates, condition-code operands, coprocessor / PSR / MVE / CDE selectors -// and special encoded immediates are intentionally omitted. +// Typed mnemonic builder procedures with overloading. Each mnemonic with at +// least one encode form exposes an inst_ overload set (returns +// Instruction) and an emit_ overload set (appends to a +// ^[dynamic]Instruction). EVERY operand type is mapped to typed parameters: +// shifted / register-shifted registers (Register, Shift_Type, u8/Register), +// register lists (u16 mask), NEON D/Q lane elems (Register, u8), and every +// immediate subclass (modified-imm / barrier / endian / iflags / sysm / coproc +// / saturating / PSR field / hint / condition-operand / MVE / CDE) as i64 — the +// encoder performs the field packing. Forms whose ordered Odin parameter-type +// tuple duplicates an earlier form of the same mnemonic are folded out to keep +// each overload set unambiguous (all arm32 register classes share one Register +// type). `) } diff --git a/core/rexcode/arm64/instructions.odin b/core/rexcode/arm64/instructions.odin index 6bef2dd58..9d28a0011 100644 --- a/core/rexcode/arm64/instructions.odin +++ b/core/rexcode/arm64/instructions.odin @@ -99,30 +99,8 @@ inst_branch :: #force_inline proc "contextless" (m: Mnemonic, label_id: u32) -> ops = {op_label(label_id, 4), {}, {}, {}}} } -// Conditional branch (B.cond label). -@(require_results) -inst_b_cond :: #force_inline proc "contextless" (c: Cond, label_id: u32) -> Instruction { - return Instruction{mnemonic = .B_COND, operand_count = 2, length = 4, - ops = {op_cond(c), op_label(label_id, 4), {}, {}}} -} - -// CBZ/CBNZ: Rt, label. -@(require_results) -inst_cbz :: #force_inline proc "contextless" (m: Mnemonic, rt: Register, label_id: u32) -> Instruction { - return Instruction{mnemonic = m, operand_count = 2, length = 4, - ops = {op_reg(rt), op_label(label_id, 4), {}, {}}} -} - -// TBZ/TBNZ: Rt, bit, label. -@(require_results) -inst_tbz :: #force_inline proc "contextless" (m: Mnemonic, rt: Register, bit: u8, label_id: u32) -> Instruction { - return Instruction{mnemonic = m, operand_count = 3, length = 4, - ops = {op_reg(rt), op_imm(i64(bit), 1), op_label(label_id, 4), {}}} -} - -// CSEL/CSINC/CSINV/CSNEG: Rd, Rn, Rm, cond. -@(require_results) -inst_csel :: #force_inline proc "contextless" (m: Mnemonic, rd, rn, rm: Register, c: Cond) -> Instruction { - return Instruction{mnemonic = m, operand_count = 4, length = 4, - ops = {op_reg(rd), op_reg(rn), op_reg(rm), op_cond(c)}} -} +// NOTE: inst_b_cond / inst_cbz (+cbnz) / inst_tbz (+tbnz) / +// inst_csel (+csinc/csinv/csneg) are now generated per-mnemonic in +// mnemonic_builders.odin (e.g. inst_cbz(rt, label), inst_cbnz(rt, label), +// inst_csinc(rd, rn, rm, cond)). They are no longer hand-written here so the +// generator can own those names for full mnemonic coverage. diff --git a/core/rexcode/arm64/mnemonic_builders.odin b/core/rexcode/arm64/mnemonic_builders.odin index 1bce09f52..eab687b8e 100644 --- a/core/rexcode/arm64/mnemonic_builders.odin +++ b/core/rexcode/arm64/mnemonic_builders.odin @@ -9,1727 +9,3130 @@ package rexcode_arm64 // Generated by tools/gen_mnemonic_builders.odin from ENCODE_FORMS. // Regenerate with: odin run arm64/tools/gen_mnemonic_builders.odin -file // -// Typed mnemonic builder procedures with overloading. Each supported mnemonic -// form gets an inst_* (returns Instruction) and emit_* (appends to a -// [dynamic]Instruction). Forms touching exotic operand types -// (SVE/SME/NEON-arrangement/shifted/extended/bitmask/sysreg/...) are skipped. +// Typed mnemonic builder procedures with overloading. Every mnemonic that has +// at least one encode form gets an inst_* (returns Instruction) and emit_* +// (appends to a [dynamic]Instruction) overload group covering all of its +// distinct operand SHAPES. Forms that share an Odin signature (e.g. the W/X +// variants, or NEON arrangement / SVE element-size variants which are all +// passed as a Register/u8) collapse to one builder; the encoder's matcher +// disambiguates by register class / size at encode time. // ============================================================================= // Individual Typed Builder Procedures // ============================================================================= -inst_add_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADD_IMM, dst, src, imm) } -emit_add_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_imm_r_r_i(dst, src, imm)) } -inst_adds_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADDS_IMM, dst, src, imm) } -emit_adds_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adds_imm_r_r_i(dst, src, imm)) } -inst_sub_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUB_IMM, dst, src, imm) } -emit_sub_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_imm_r_r_i(dst, src, imm)) } -inst_subs_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUBS_IMM, dst, src, imm) } -emit_subs_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subs_imm_r_r_i(dst, src, imm)) } -inst_movz_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } -emit_movz_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movz_r_i_i(dst, imm, imm2)) } -inst_movn_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVN, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } -emit_movn_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movn_r_i_i(dst, imm, imm2)) } -inst_movk_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVK, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } -emit_movk_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movk_r_i_i(dst, imm, imm2)) } -inst_adr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return inst_cbz(.ADR, dst, label) } -emit_adr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adr_r_l(dst, label)) } -inst_adrp_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return inst_cbz(.ADRP, dst, label) } -emit_adrp_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adrp_r_l(dst, label)) } -inst_lslv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSLV, dst, src, src2) } -emit_lslv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lslv_r_r_r(dst, src, src2)) } -inst_lsrv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSRV, dst, src, src2) } -emit_lsrv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsrv_r_r_r(dst, src, src2)) } -inst_asrv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ASRV, dst, src, src2) } -emit_asrv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asrv_r_r_r(dst, src, src2)) } -inst_rorv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.RORV, dst, src, src2) } -emit_rorv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rorv_r_r_r(dst, src, src2)) } -inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UDIV, dst, src, src2) } -emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } -inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SDIV, dst, src, src2) } -emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } -inst_madd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MADD, dst, src, src2, src3) } -emit_madd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_madd_r_r_r_r(dst, src, src2, src3)) } -inst_msub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MSUB, dst, src, src2, src3) } -emit_msub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_msub_r_r_r_r(dst, src, src2, src3)) } -inst_smaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMADDL, dst, src, src2, src3) } -emit_smaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smaddl_r_r_r_r(dst, src, src2, src3)) } -inst_smsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMSUBL, dst, src, src2, src3) } -emit_smsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smsubl_r_r_r_r(dst, src, src2, src3)) } -inst_umaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMADDL, dst, src, src2, src3) } -emit_umaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaddl_r_r_r_r(dst, src, src2, src3)) } -inst_umsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMSUBL, dst, src, src2, src3) } -emit_umsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umsubl_r_r_r_r(dst, src, src2, src3)) } -inst_smulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SMULH, dst, src, src2) } -emit_smulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulh_r_r_r(dst, src, src2)) } -inst_umulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UMULH, dst, src, src2) } -emit_umulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umulh_r_r_r(dst, src, src2)) } -inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLZ, dst, src) } -emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } -inst_cls_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLS, dst, src) } -emit_cls_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_r_r(dst, src)) } -inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.RBIT, dst, src) } -emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } -inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV, dst, src) } -emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } -inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV16, dst, src) } -emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } -inst_rev32_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV32, dst, src) } -emit_rev32_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_r_r(dst, src)) } -inst_csinc_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_csinc_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinc_r_r_r_c(dst, src, src2, cond)) } -inst_csinv_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINV, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_csinv_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinv_r_r_r_c(dst, src, src2, cond)) } -inst_csneg_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSNEG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_csneg_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csneg_r_r_r_c(dst, src, src2, cond)) } -inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1)}} } -emit_extr_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_extr_r_r_r_i(dst, src, src2, imm)) } -inst_b_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B, label) } -emit_b_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_l(label)) } -inst_bl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BL, label) } -emit_bl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bl_l(label)) } -inst_br_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BR, dst) } -emit_br_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_br_r(dst)) } -inst_blr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLR, dst) } -emit_blr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blr_r(dst)) } -inst_ret_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.RET, dst) } -inst_ret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RET) } -emit_ret_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ret_r(dst)) } -emit_ret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ret_none()) } -inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return inst_cbz(.CBNZ, dst, label) } -emit_cbnz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbnz_r_l(dst, label)) } -inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBNZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } -emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbnz_r_i_l(dst, imm, label)) } -inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } -emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } -inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } -emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } -inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) } -emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) } -inst_strb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB, dst, mem) } -emit_strb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_r_m(dst, mem)) } -inst_ldrsb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSB, dst, mem) } -emit_ldrsb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsb_r_m(dst, mem)) } -inst_ldrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH, dst, mem) } -emit_ldrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_r_m(dst, mem)) } -inst_strh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH, dst, mem) } -emit_strh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_r_m(dst, mem)) } -inst_ldrsh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSH, dst, mem) } -emit_ldrsh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsh_r_m(dst, mem)) } -inst_ldrsw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSW, dst, mem) } -emit_ldrsw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsw_r_m(dst, mem)) } -inst_ldp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP, dst, src, mem) } -emit_ldp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_r_r_m(dst, src, mem)) } -inst_stp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP, dst, src, mem) } -emit_stp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_r_r_m(dst, src, mem)) } -inst_ldpsw_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW, dst, src, mem) } -emit_ldpsw_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_r_r_m(dst, src, mem)) } -inst_ldr_lit_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return inst_cbz(.LDR_LIT, dst, label) } -emit_ldr_lit_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_lit_r_l(dst, label)) } -inst_ldar_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAR, dst, mem) } -emit_ldar_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldar_r_m(dst, mem)) } -inst_stlr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLR, dst, mem) } -emit_stlr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlr_r_m(dst, mem)) } -inst_ldarb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARB, dst, mem) } -emit_ldarb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarb_r_m(dst, mem)) } -inst_stlrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRB, dst, mem) } -emit_stlrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrb_r_m(dst, mem)) } -inst_ldarh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARH, dst, mem) } -emit_ldarh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarh_r_m(dst, mem)) } -inst_stlrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRH, dst, mem) } -emit_stlrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrh_r_m(dst, mem)) } -inst_ldxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXR, dst, mem) } -emit_ldxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxr_r_m(dst, mem)) } -inst_stxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXR, dst, src, mem) } -emit_stxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxr_r_r_m(dst, src, mem)) } -inst_ldaxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXR, dst, mem) } -emit_ldaxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxr_r_m(dst, mem)) } -inst_stlxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXR, dst, src, mem) } -emit_stlxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxr_r_r_m(dst, src, mem)) } -inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.NOP) } -emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) } -inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.YIELD) } -emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) } -inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFE) } -emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) } -inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFI) } -emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) } -inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEV) } -emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } -inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEVL) } -emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } -inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_isb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_i(imm)) } -inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_dsb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_i(imm)) } -inst_dmb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_dmb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_i(imm)) } -inst_svc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_svc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_i(imm)) } -inst_hvc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_hvc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_i(imm)) } -inst_smc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_smc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_i(imm)) } -inst_brk_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BRK, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_brk_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_brk_i(imm)) } -inst_hlt_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_hlt_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_i(imm)) } -inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERET) } -emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } -inst_fmov_reg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_REG, dst, src) } -emit_fmov_reg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_reg_r_r(dst, src)) } -inst_fmov_gen_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_GEN, dst, src) } -emit_fmov_gen_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_gen_r_r(dst, src)) } -inst_fabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS, dst, src) } -emit_fabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_r_r(dst, src)) } -inst_fneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG, dst, src) } -emit_fneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_r_r(dst, src)) } -inst_fsqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT, dst, src) } -emit_fsqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_r_r(dst, src)) } -inst_fadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD, dst, src, src2) } -emit_fadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_r_r_r(dst, src, src2)) } -inst_fsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB, dst, src, src2) } -emit_fsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_r_r_r(dst, src, src2)) } -inst_fmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL, dst, src, src2) } -emit_fmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_r_r_r(dst, src, src2)) } -inst_fdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV, dst, src, src2) } -emit_fdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_r_r_r(dst, src, src2)) } -inst_fnmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL, dst, src, src2) } -emit_fnmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_r_r_r(dst, src, src2)) } -inst_fmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD, dst, src, src2, src3) } -emit_fmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_r_r_r_r(dst, src, src2, src3)) } -inst_fmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMSUB, dst, src, src2, src3) } -emit_fmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_r_r_r_r(dst, src, src2, src3)) } -inst_fnmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMADD, dst, src, src2, src3) } -emit_fnmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_r_r_r_r(dst, src, src2, src3)) } -inst_fnmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMSUB, dst, src, src2, src3) } -emit_fnmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_r_r_r_r(dst, src, src2, src3)) } -inst_fcmp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMP, dst, src) } -emit_fcmp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_r_r(dst, src)) } -inst_fcmpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE, dst, src) } -emit_fcmpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_r_r(dst, src)) } -inst_fcsel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_fcsel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_r_r_r_c(dst, src, src2, cond)) } -inst_fmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX, dst, src, src2) } -emit_fmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_r_r_r(dst, src, src2)) } -inst_fmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN, dst, src, src2) } -emit_fmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_r_r_r(dst, src, src2)) } -inst_fmaxnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM, dst, src, src2) } -emit_fmaxnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_r_r_r(dst, src, src2)) } -inst_fminnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM, dst, src, src2) } -emit_fminnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_r_r_r(dst, src, src2)) } -inst_fcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT, dst, src) } -emit_fcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_r_r(dst, src)) } -inst_scvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF, dst, src) } -emit_scvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_r_r(dst, src)) } -inst_ucvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF, dst, src) } -emit_ucvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_r_r(dst, src)) } -inst_fcvtzs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS, dst, src) } -emit_fcvtzs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_r_r(dst, src)) } -inst_fcvtzu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU, dst, src) } -emit_fcvtzu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_r_r(dst, src)) } -inst_ldur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDUR, dst, mem) } -emit_ldur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldur_r_m(dst, mem)) } -inst_stur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STUR, dst, mem) } -emit_stur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stur_r_m(dst, mem)) } -inst_ldurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURB, dst, mem) } -emit_ldurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurb_r_m(dst, mem)) } -inst_sturb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURB, dst, mem) } -emit_sturb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturb_r_m(dst, mem)) } -inst_ldursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSB, dst, mem) } -emit_ldursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursb_r_m(dst, mem)) } -inst_ldurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURH, dst, mem) } -emit_ldurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurh_r_m(dst, mem)) } -inst_sturh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURH, dst, mem) } -emit_sturh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturh_r_m(dst, mem)) } -inst_ldursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSH, dst, mem) } -emit_ldursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursh_r_m(dst, mem)) } -inst_ldursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSW, dst, mem) } -emit_ldursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursw_r_m(dst, mem)) } -inst_ldr_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_PRE, dst, mem) } -emit_ldr_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_pre_r_m(dst, mem)) } -inst_str_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_PRE, dst, mem) } -emit_str_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_pre_r_m(dst, mem)) } -inst_ldr_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_POST, dst, mem) } -emit_ldr_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_post_r_m(dst, mem)) } -inst_str_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_POST, dst, mem) } -emit_str_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_post_r_m(dst, mem)) } -inst_ldr_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_REG, dst, mem) } -emit_ldr_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_reg_r_m(dst, mem)) } -inst_str_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_REG, dst, mem) } -emit_str_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_reg_r_m(dst, mem)) } -inst_ldp_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP_PRE, dst, src, mem) } -emit_ldp_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_pre_r_r_m(dst, src, mem)) } -inst_stp_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP_PRE, dst, src, mem) } -emit_stp_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_pre_r_r_m(dst, src, mem)) } -inst_ldp_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP_POST, dst, src, mem) } -emit_ldp_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_post_r_r_m(dst, src, mem)) } -inst_stp_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP_POST, dst, src, mem) } -emit_stp_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_post_r_r_m(dst, src, mem)) } -inst_ldpsw_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW_PRE, dst, src, mem) } -emit_ldpsw_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_pre_r_r_m(dst, src, mem)) } -inst_ldpsw_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW_POST, dst, src, mem) } -emit_ldpsw_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_post_r_r_m(dst, src, mem)) } -inst_ldnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDNP, dst, src, mem) } -emit_ldnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldnp_r_r_m(dst, src, mem)) } -inst_stnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STNP, dst, src, mem) } -emit_stnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stnp_r_r_m(dst, src, mem)) } -inst_ldxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDXP, dst, src, mem) } -emit_ldxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldxp_r_r_m(dst, src, mem)) } -inst_stxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } -emit_stxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stxp_r_r_r_m(dst, src, src2, mem)) } -inst_ldaxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDAXP, dst, src, mem) } -emit_ldaxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaxp_r_r_m(dst, src, mem)) } -inst_stlxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STLXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } -emit_stlxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stlxp_r_r_r_m(dst, src, src2, mem)) } -inst_ldxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRB, dst, mem) } -emit_ldxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrb_r_m(dst, mem)) } -inst_stxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRB, dst, src, mem) } -emit_stxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrb_r_r_m(dst, src, mem)) } -inst_ldaxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRB, dst, mem) } -emit_ldaxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrb_r_m(dst, mem)) } -inst_stlxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRB, dst, src, mem) } -emit_stlxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrb_r_r_m(dst, src, mem)) } -inst_ldxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRH, dst, mem) } -emit_ldxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrh_r_m(dst, mem)) } -inst_stxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRH, dst, src, mem) } -emit_stxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrh_r_r_m(dst, src, mem)) } -inst_ldaxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRH, dst, mem) } -emit_ldaxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrh_r_m(dst, mem)) } -inst_stlxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRH, dst, src, mem) } -emit_stlxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrh_r_r_m(dst, src, mem)) } -inst_ldapr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPR, dst, mem) } -emit_ldapr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapr_r_m(dst, mem)) } -inst_ldaprb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRB, dst, mem) } -emit_ldaprb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprb_r_m(dst, mem)) } -inst_ldaprh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRH, dst, mem) } -emit_ldaprh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprh_r_m(dst, mem)) } -inst_ldadd_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADD, dst, src, mem) } -emit_ldadd_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadd_r_r_m(dst, src, mem)) } -inst_ldadda_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDA, dst, src, mem) } -emit_ldadda_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadda_r_r_m(dst, src, mem)) } -inst_ldaddl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDL, dst, src, mem) } -emit_ldaddl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddl_r_r_m(dst, src, mem)) } -inst_ldaddal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDAL, dst, src, mem) } -emit_ldaddal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddal_r_r_m(dst, src, mem)) } -inst_ldclr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLR, dst, src, mem) } -emit_ldclr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclr_r_r_m(dst, src, mem)) } -inst_ldclra_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRA, dst, src, mem) } -emit_ldclra_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclra_r_r_m(dst, src, mem)) } -inst_ldclrl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRL, dst, src, mem) } -emit_ldclrl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclrl_r_r_m(dst, src, mem)) } -inst_ldclral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRAL, dst, src, mem) } -emit_ldclral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclral_r_r_m(dst, src, mem)) } -inst_ldeor_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEOR, dst, src, mem) } -emit_ldeor_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeor_r_r_m(dst, src, mem)) } -inst_ldeora_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORA, dst, src, mem) } -emit_ldeora_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeora_r_r_m(dst, src, mem)) } -inst_ldeorl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORL, dst, src, mem) } -emit_ldeorl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeorl_r_r_m(dst, src, mem)) } -inst_ldeoral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORAL, dst, src, mem) } -emit_ldeoral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeoral_r_r_m(dst, src, mem)) } -inst_ldset_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSET, dst, src, mem) } -emit_ldset_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldset_r_r_m(dst, src, mem)) } -inst_ldseta_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETA, dst, src, mem) } -emit_ldseta_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldseta_r_r_m(dst, src, mem)) } -inst_ldsetl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETL, dst, src, mem) } -emit_ldsetl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetl_r_r_m(dst, src, mem)) } -inst_ldsetal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETAL, dst, src, mem) } -emit_ldsetal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetal_r_r_m(dst, src, mem)) } -inst_ldsmax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAX, dst, src, mem) } -emit_ldsmax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmax_r_r_m(dst, src, mem)) } -inst_ldsmaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXA, dst, src, mem) } -emit_ldsmaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxa_r_r_m(dst, src, mem)) } -inst_ldsmaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXL, dst, src, mem) } -emit_ldsmaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxl_r_r_m(dst, src, mem)) } -inst_ldsmaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXAL, dst, src, mem) } -emit_ldsmaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxal_r_r_m(dst, src, mem)) } -inst_ldsmin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMIN, dst, src, mem) } -emit_ldsmin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmin_r_r_m(dst, src, mem)) } -inst_ldsmina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINA, dst, src, mem) } -emit_ldsmina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmina_r_r_m(dst, src, mem)) } -inst_ldsminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINL, dst, src, mem) } -emit_ldsminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminl_r_r_m(dst, src, mem)) } -inst_ldsminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINAL, dst, src, mem) } -emit_ldsminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminal_r_r_m(dst, src, mem)) } -inst_ldumax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAX, dst, src, mem) } -emit_ldumax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumax_r_r_m(dst, src, mem)) } -inst_ldumaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXA, dst, src, mem) } -emit_ldumaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxa_r_r_m(dst, src, mem)) } -inst_ldumaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXL, dst, src, mem) } -emit_ldumaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxl_r_r_m(dst, src, mem)) } -inst_ldumaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXAL, dst, src, mem) } -emit_ldumaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxal_r_r_m(dst, src, mem)) } -inst_ldumin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMIN, dst, src, mem) } -emit_ldumin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumin_r_r_m(dst, src, mem)) } -inst_ldumina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINA, dst, src, mem) } -emit_ldumina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumina_r_r_m(dst, src, mem)) } -inst_lduminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINL, dst, src, mem) } -emit_lduminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminl_r_r_m(dst, src, mem)) } -inst_lduminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINAL, dst, src, mem) } -emit_lduminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminal_r_r_m(dst, src, mem)) } -inst_swp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWP, dst, src, mem) } -emit_swp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swp_r_r_m(dst, src, mem)) } -inst_swpa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPA, dst, src, mem) } -emit_swpa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpa_r_r_m(dst, src, mem)) } -inst_swpl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPL, dst, src, mem) } -emit_swpl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpl_r_r_m(dst, src, mem)) } -inst_swpal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPAL, dst, src, mem) } -emit_swpal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpal_r_r_m(dst, src, mem)) } -inst_cas_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CAS, dst, src, mem) } -emit_cas_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cas_r_r_m(dst, src, mem)) } -inst_casa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASA, dst, src, mem) } -emit_casa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casa_r_r_m(dst, src, mem)) } -inst_casl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASL, dst, src, mem) } -emit_casl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casl_r_r_m(dst, src, mem)) } -inst_casal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAL, dst, src, mem) } -emit_casal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casal_r_r_m(dst, src, mem)) } -inst_casb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASB, dst, src, mem) } -emit_casb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casb_r_r_m(dst, src, mem)) } -inst_casab_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAB, dst, src, mem) } -emit_casab_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casab_r_r_m(dst, src, mem)) } -inst_caslb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLB, dst, src, mem) } -emit_caslb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslb_r_r_m(dst, src, mem)) } -inst_casalb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALB, dst, src, mem) } -emit_casalb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalb_r_r_m(dst, src, mem)) } -inst_cash_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASH, dst, src, mem) } -emit_cash_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cash_r_r_m(dst, src, mem)) } -inst_casah_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAH, dst, src, mem) } -emit_casah_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casah_r_r_m(dst, src, mem)) } -inst_caslh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLH, dst, src, mem) } -emit_caslh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslh_r_r_m(dst, src, mem)) } -inst_casalh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALH, dst, src, mem) } -emit_casalh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalh_r_r_m(dst, src, mem)) } -inst_casp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASP, dst, src, mem) } -emit_casp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casp_r_r_m(dst, src, mem)) } -inst_caspa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPA, dst, src, mem) } -emit_caspa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspa_r_r_m(dst, src, mem)) } -inst_caspl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPL, dst, src, mem) } -emit_caspl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspl_r_r_m(dst, src, mem)) } -inst_caspal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPAL, dst, src, mem) } -emit_caspal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspal_r_r_m(dst, src, mem)) } -inst_pacia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIA, dst, src) } -emit_pacia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacia_r_r(dst, src)) } -inst_pacib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIB, dst, src) } -emit_pacib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacib_r_r(dst, src)) } -inst_pacda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDA, dst, src) } -emit_pacda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacda_r_r(dst, src)) } -inst_pacdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDB, dst, src) } -emit_pacdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacdb_r_r(dst, src)) } -inst_paciza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZA, dst) } -emit_paciza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_paciza_r(dst)) } -inst_pacizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZB, dst) } -emit_pacizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacizb_r(dst)) } -inst_pacdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZA, dst) } -emit_pacdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdza_r(dst)) } -inst_pacdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZB, dst) } -emit_pacdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdzb_r(dst)) } -inst_autia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIA, dst, src) } -emit_autia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autia_r_r(dst, src)) } -inst_autib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIB, dst, src) } -emit_autib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autib_r_r(dst, src)) } -inst_autda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDA, dst, src) } -emit_autda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autda_r_r(dst, src)) } -inst_autdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDB, dst, src) } -emit_autdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autdb_r_r(dst, src)) } -inst_autiza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZA, dst) } -emit_autiza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autiza_r(dst)) } -inst_autizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZB, dst) } -emit_autizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autizb_r(dst)) } -inst_autdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZA, dst) } -emit_autdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdza_r(dst)) } -inst_autdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZB, dst) } -emit_autdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdzb_r(dst)) } -inst_paciasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIASP) } -emit_paciasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_paciasp_none()) } -inst_pacibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIBSP) } -emit_pacibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacibsp_none()) } -inst_autiasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIASP) } -emit_autiasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autiasp_none()) } -inst_autibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIBSP) } -emit_autibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autibsp_none()) } -inst_pacia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIA1716) } -emit_pacia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacia1716_none()) } -inst_pacib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIB1716) } -emit_pacib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacib1716_none()) } -inst_autia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIA1716) } -emit_autia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autia1716_none()) } -inst_autib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIB1716) } -emit_autib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autib1716_none()) } -inst_pacga_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.PACGA, dst, src, src2) } -emit_pacga_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pacga_r_r_r(dst, src, src2)) } -inst_xpaci_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACI, dst) } -emit_xpaci_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpaci_r(dst)) } -inst_xpacd_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACD, dst) } -emit_xpacd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpacd_r(dst)) } -inst_xpaclri_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.XPACLRI) } -emit_xpaclri_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xpaclri_none()) } -inst_retaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAA) } -emit_retaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retaa_none()) } -inst_retab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAB) } -emit_retab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retab_none()) } -inst_braa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAA, dst, src) } -emit_braa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_braa_r_r(dst, src)) } -inst_brab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAB, dst, src) } -emit_brab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_brab_r_r(dst, src)) } -inst_braaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRAAZ, dst) } -emit_braaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_braaz_r(dst)) } -inst_brabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRABZ, dst) } -emit_brabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_brabz_r(dst)) } -inst_blraa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAA, dst, src) } -emit_blraa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blraa_r_r(dst, src)) } -inst_blrab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAB, dst, src) } -emit_blrab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blrab_r_r(dst, src)) } -inst_blraaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRAAZ, dst) } -emit_blraaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blraaz_r(dst)) } -inst_blrabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRABZ, dst) } -emit_blrabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blrabz_r(dst)) } -inst_eretaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAA) } -emit_eretaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretaa_none()) } -inst_eretab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAB) } -emit_eretab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretab_none()) } -inst_bti_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } -emit_bti_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bti_i(imm)) } -inst_irg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.IRG, dst, src, src2) } -emit_irg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_irg_r_r_r(dst, src, src2)) } -inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } -emit_addg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_addg_r_r_i_i(dst, src, imm, imm2)) } -inst_subg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SUBG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } -emit_subg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_subg_r_r_i_i(dst, src, imm, imm2)) } -inst_gmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.GMI, dst, src, src2) } -emit_gmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_gmi_r_r_r(dst, src, src2)) } -inst_subp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBP, dst, src, src2) } -emit_subp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subp_r_r_r(dst, src, src2)) } -inst_subps_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBPS, dst, src, src2) } -emit_subps_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subps_r_r_r(dst, src, src2)) } -inst_ldg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDG, dst, mem) } -emit_ldg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldg_r_m(dst, mem)) } -inst_stg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STG, dst, mem) } -emit_stg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stg_r_m(dst, mem)) } -inst_st2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.ST2G, dst, mem) } -emit_st2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2g_r_m(dst, mem)) } -inst_stzg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZG, dst, mem) } -emit_stzg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzg_r_m(dst, mem)) } -inst_stz2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZ2G, dst, mem) } -emit_stz2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stz2g_r_m(dst, mem)) } -inst_stgp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STGP, dst, src, mem) } -emit_stgp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stgp_r_r_m(dst, src, mem)) } -inst_ldgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDGM, dst, mem) } -emit_ldgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldgm_r_m(dst, mem)) } -inst_stgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STGM, dst, mem) } -emit_stgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stgm_r_m(dst, mem)) } -inst_stzgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZGM, dst, mem) } -emit_stzgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzgm_r_m(dst, mem)) } -inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32B, dst, src, src2) } -emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) } -inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32H, dst, src, src2) } -emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) } -inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32W, dst, src, src2) } -emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) } -inst_crc32x_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32X, dst, src, src2) } -emit_crc32x_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32x_r_r_r(dst, src, src2)) } -inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CB, dst, src, src2) } -emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) } -inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CH, dst, src, src2) } -emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) } -inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CW, dst, src, src2) } -emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } -inst_crc32cx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CX, dst, src, src2) } -emit_crc32cx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cx_r_r_r(dst, src, src2)) } -inst_sha1h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SHA1H, dst, src) } -emit_sha1h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_r_r(dst, src)) } -inst_fabs_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS_H, dst, src) } -emit_fabs_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_h_r_r(dst, src)) } -inst_fneg_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG_H, dst, src) } -emit_fneg_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_h_r_r(dst, src)) } -inst_fsqrt_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT_H, dst, src) } -emit_fsqrt_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_h_r_r(dst, src)) } -inst_fadd_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD_H, dst, src, src2) } -emit_fadd_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_h_r_r_r(dst, src, src2)) } -inst_fsub_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB_H, dst, src, src2) } -emit_fsub_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_h_r_r_r(dst, src, src2)) } -inst_fmul_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL_H, dst, src, src2) } -emit_fmul_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_h_r_r_r(dst, src, src2)) } -inst_fdiv_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV_H, dst, src, src2) } -emit_fdiv_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_h_r_r_r(dst, src, src2)) } -inst_fnmul_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL_H, dst, src, src2) } -emit_fnmul_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_h_r_r_r(dst, src, src2)) } -inst_fmadd_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD_H, dst, src, src2, src3) } -emit_fmadd_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_h_r_r_r_r(dst, src, src2, src3)) } -inst_fmsub_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMSUB_H, dst, src, src2, src3) } -emit_fmsub_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_h_r_r_r_r(dst, src, src2, src3)) } -inst_fnmadd_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMADD_H, dst, src, src2, src3) } -emit_fnmadd_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_h_r_r_r_r(dst, src, src2, src3)) } -inst_fnmsub_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMSUB_H, dst, src, src2, src3) } -emit_fnmsub_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_h_r_r_r_r(dst, src, src2, src3)) } -inst_fcmp_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMP_H, dst, src) } -emit_fcmp_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_h_r_r(dst, src)) } -inst_fcmpe_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE_H, dst, src) } -emit_fcmpe_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_h_r_r(dst, src)) } -inst_fcsel_h_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL_H, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } -emit_fcsel_h_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_h_r_r_r_c(dst, src, src2, cond)) } -inst_fmax_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX_H, dst, src, src2) } -emit_fmax_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_h_r_r_r(dst, src, src2)) } -inst_fmin_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN_H, dst, src, src2) } -emit_fmin_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_h_r_r_r(dst, src, src2)) } -inst_fmaxnm_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM_H, dst, src, src2) } -emit_fmaxnm_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_h_r_r_r(dst, src, src2)) } -inst_fminnm_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM_H, dst, src, src2) } -emit_fminnm_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_h_r_r_r(dst, src, src2)) } -inst_fcvt_h_s_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_H_S, dst, src) } -emit_fcvt_h_s_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_h_s_r_r(dst, src)) } -inst_fcvt_h_d_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_H_D, dst, src) } -emit_fcvt_h_d_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_h_d_r_r(dst, src)) } -inst_fcvt_s_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_S_H, dst, src) } -emit_fcvt_s_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_s_h_r_r(dst, src)) } -inst_fcvt_d_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_D_H, dst, src) } -emit_fcvt_d_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_d_h_r_r(dst, src)) } -inst_fmov_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_H, dst, src) } -emit_fmov_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_h_r_r(dst, src)) } -inst_scvtf_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF_H, dst, src) } -emit_scvtf_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_h_r_r(dst, src)) } -inst_ucvtf_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF_H, dst, src) } -emit_ucvtf_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_h_r_r(dst, src)) } -inst_fcvtzs_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS_H, dst, src) } -emit_fcvtzs_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_h_r_r(dst, src)) } -inst_fcvtzu_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU_H, dst, src) } -emit_fcvtzu_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_h_r_r(dst, src)) } -inst_bfcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BFCVT, dst, src) } -emit_bfcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvt_r_r(dst, src)) } -inst_ldr_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_V, dst, mem) } -emit_ldr_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_v_r_m(dst, mem)) } -inst_str_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_V, dst, mem) } -emit_str_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_v_r_m(dst, mem)) } -inst_sme_smstart_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SME_SMSTART) } -emit_sme_smstart_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sme_smstart_none()) } -inst_sme_smstop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SME_SMSTOP) } -emit_sme_smstop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sme_smstop_none()) } -inst_sme_rdsvl_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.SME_RDSVL, dst, imm) } -emit_sme_rdsvl_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_sme_rdsvl_r_i(dst, imm)) } -inst_sme_ldr_za_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LDR_ZA, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -emit_sme_ldr_za_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_sme_ldr_za_i_m(imm, mem)) } -inst_sme_str_za_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_STR_ZA, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -emit_sme_str_za_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_sme_str_za_i_m(imm, mem)) } -inst_ldraa_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA, dst, mem) } -emit_ldraa_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_r_m(dst, mem)) } -inst_ldrab_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB, dst, mem) } -emit_ldrab_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrab_r_m(dst, mem)) } -inst_ldraa_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA_PRE, dst, mem) } -emit_ldraa_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_pre_r_m(dst, mem)) } -inst_ldrab_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB_PRE, dst, mem) } -emit_ldrab_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrab_pre_r_m(dst, mem)) } -inst_tstart_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TSTART, dst) } -emit_tstart_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tstart_r(dst)) } -inst_tcommit_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TCOMMIT) } -emit_tcommit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tcommit_none()) } -inst_tcancel_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TCANCEL, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } -emit_tcancel_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_tcancel_i(imm)) } -inst_ttest_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TTEST, dst) } -emit_ttest_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ttest_r(dst)) } -inst_wfet_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFET, dst) } -emit_wfet_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfet_r(dst)) } -inst_wfit_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFIT, dst) } -emit_wfit_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfit_r(dst)) } -inst_bc_cond_c_l :: #force_inline proc "contextless" (cond: Cond, label: u32) -> Instruction { return Instruction{mnemonic = .BC_COND, operand_count = 2, length = 4, ops = {op_cond(cond), op_label(label, 4), {}, {}}} } -emit_bc_cond_c_l :: #force_inline proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) { append(instructions, inst_bc_cond_c_l(cond, label)) } -inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTB, dst, src) } -emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) } -inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTH, dst, src) } -emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) } -inst_uxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTW, dst, src) } -emit_uxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtw_r_r(dst, src)) } -inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTB, dst, src) } -emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) } -inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTH, dst, src) } -emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) } -inst_sxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTW, dst, src) } -emit_sxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtw_r_r(dst, src)) } -inst_adc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADC, dst, src, src2) } -emit_adc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adc_r_r_r(dst, src, src2)) } -inst_adcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADCS, dst, src, src2) } -emit_adcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adcs_r_r_r(dst, src, src2)) } -inst_sbc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBC, dst, src, src2) } -emit_sbc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbc_r_r_r(dst, src, src2)) } -inst_sbcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBCS, dst, src, src2) } -emit_sbcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbcs_r_r_r(dst, src, src2)) } -inst_ngc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGC, dst, src) } -emit_ngc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngc_r_r(dst, src)) } -inst_ngcs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGCS, dst, src) } -emit_ngcs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngcs_r_r(dst, src)) } -inst_ldapur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPUR, dst, mem) } -emit_ldapur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapur_r_m(dst, mem)) } -inst_stlur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLUR, dst, mem) } -emit_stlur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlur_r_m(dst, mem)) } -inst_ldapurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURB, dst, mem) } -emit_ldapurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurb_r_m(dst, mem)) } -inst_stlurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURB, dst, mem) } -emit_stlurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurb_r_m(dst, mem)) } -inst_ldapurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURH, dst, mem) } -emit_ldapurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurh_r_m(dst, mem)) } -inst_stlurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURH, dst, mem) } -emit_stlurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurh_r_m(dst, mem)) } -inst_ldapursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSB, dst, mem) } -emit_ldapursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursb_r_m(dst, mem)) } -inst_ldapursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSH, dst, mem) } -emit_ldapursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursh_r_m(dst, mem)) } -inst_ldapursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSW, dst, mem) } -emit_ldapursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursw_r_m(dst, mem)) } -inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SB) } -emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } -inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.CSDB) } -emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) } -inst_dgh_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.DGH) } -emit_dgh_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dgh_none()) } -inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PSB_CSYNC) } -emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) } -inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TSB_CSYNC) } -emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) } -inst_bti_j_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_J) } -emit_bti_j_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_j_none()) } -inst_bti_c_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_C) } -emit_bti_c_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_c_none()) } -inst_bti_jc_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_JC) } -emit_bti_jc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_jc_none()) } -inst_lsl_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSL_IMM, dst, src, imm) } -emit_lsl_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_imm_r_r_i(dst, src, imm)) } -inst_lsr_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSR_IMM, dst, src, imm) } -emit_lsr_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_imm_r_r_i(dst, src, imm)) } -inst_asr_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ASR_IMM, dst, src, imm) } -emit_asr_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_imm_r_r_i(dst, src, imm)) } -inst_ror_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ROR_IMM, dst, src, imm) } -emit_ror_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_imm_r_r_i(dst, src, imm)) } -inst_tlbi_rpalos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPALOS, dst) } -emit_tlbi_rpalos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpalos_r(dst)) } -inst_tlbi_rpaos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPAOS, dst) } -emit_tlbi_rpaos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpaos_r(dst)) } -inst_at_s1e1a_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1A, dst) } -emit_at_s1e1a_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1a_r(dst)) } -inst_dc_cipapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIPAPA, dst) } -emit_dc_cipapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cipapa_r(dst)) } -inst_dc_cigdpapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIGDPAPA, dst) } -emit_dc_cigdpapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cigdpapa_r(dst)) } -inst_tlbi_paall_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALL) } -emit_tlbi_paall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paall_none()) } -inst_tlbi_paallos_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALLOS) } -emit_tlbi_paallos_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paallos_none()) } -inst_amx_ldx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDX, dst) } -emit_amx_ldx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldx_r(dst)) } -inst_amx_ldy_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDY, dst) } -emit_amx_ldy_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldy_r(dst)) } -inst_amx_stx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STX, dst) } -emit_amx_stx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stx_r(dst)) } -inst_amx_sty_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STY, dst) } -emit_amx_sty_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_sty_r(dst)) } -inst_amx_ldz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZ, dst) } -emit_amx_ldz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldz_r(dst)) } -inst_amx_stz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZ, dst) } -emit_amx_stz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stz_r(dst)) } -inst_amx_ldzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZI, dst) } -emit_amx_ldzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldzi_r(dst)) } -inst_amx_stzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZI, dst) } -emit_amx_stzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stzi_r(dst)) } -inst_amx_extrx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRX, dst) } -emit_amx_extrx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extrx_r(dst)) } -inst_amx_extry_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRY, dst) } -emit_amx_extry_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extry_r(dst)) } -inst_amx_fma64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA64, dst) } -emit_amx_fma64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma64_r(dst)) } -inst_amx_fms64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS64, dst) } -emit_amx_fms64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms64_r(dst)) } -inst_amx_fma32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA32, dst) } -emit_amx_fma32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma32_r(dst)) } -inst_amx_fms32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS32, dst) } -emit_amx_fms32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms32_r(dst)) } -inst_amx_mac16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MAC16, dst) } -emit_amx_mac16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_mac16_r(dst)) } -inst_amx_fma16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA16, dst) } -emit_amx_fma16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma16_r(dst)) } -inst_amx_fms16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS16, dst) } -emit_amx_fms16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms16_r(dst)) } -inst_amx_set_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_SET) } -emit_amx_set_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_set_none()) } -inst_amx_clr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_CLR) } -emit_amx_clr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_clr_none()) } -inst_amx_vecint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECINT, dst) } -emit_amx_vecint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecint_r(dst)) } -inst_amx_vecfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECFP, dst) } -emit_amx_vecfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecfp_r(dst)) } -inst_amx_matint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATINT, dst) } -emit_amx_matint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matint_r(dst)) } -inst_amx_matfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATFP, dst) } -emit_amx_matfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matfp_r(dst)) } -inst_amx_genlut_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_GENLUT, dst) } -emit_amx_genlut_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_genlut_r(dst)) } -inst_cpyp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYP, dst, src, src2) } -emit_cpyp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyp_r_r_r(dst, src, src2)) } -inst_cpym_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYM, dst, src, src2) } -emit_cpym_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpym_r_r_r(dst, src, src2)) } -inst_cpye_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYE, dst, src, src2) } -emit_cpye_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpye_r_r_r(dst, src, src2)) } -inst_cpyfp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFP, dst, src, src2) } -emit_cpyfp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfp_r_r_r(dst, src, src2)) } -inst_cpyfm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFM, dst, src, src2) } -emit_cpyfm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfm_r_r_r(dst, src, src2)) } -inst_cpyfe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFE, dst, src, src2) } -emit_cpyfe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfe_r_r_r(dst, src, src2)) } -inst_setp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETP, dst, src, src2) } -emit_setp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setp_r_r_r(dst, src, src2)) } -inst_setm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETM, dst, src, src2) } -emit_setm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setm_r_r_r(dst, src, src2)) } -inst_sete_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETE, dst, src, src2) } -emit_sete_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sete_r_r_r(dst, src, src2)) } -inst_dc_ivac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_IVAC, dst) } -emit_dc_ivac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_ivac_r(dst)) } -inst_dc_isw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ISW, dst) } -emit_dc_isw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_isw_r(dst)) } -inst_dc_csw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CSW, dst) } -emit_dc_csw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_csw_r(dst)) } -inst_dc_cisw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CISW, dst) } -emit_dc_cisw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cisw_r(dst)) } -inst_dc_zva_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ZVA, dst) } -emit_dc_zva_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_zva_r(dst)) } -inst_dc_cvac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAC, dst) } -emit_dc_cvac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvac_r(dst)) } -inst_dc_cvau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAU, dst) } -emit_dc_cvau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvau_r(dst)) } -inst_dc_civac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIVAC, dst) } -emit_dc_civac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_civac_r(dst)) } -inst_ic_ialluis_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLUIS) } -emit_ic_ialluis_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_ialluis_none()) } -inst_ic_iallu_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLU) } -emit_ic_iallu_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_iallu_none()) } -inst_ic_ivau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.IC_IVAU, dst) } -emit_ic_ivau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ic_ivau_r(dst)) } -inst_at_s1e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1R, dst) } -emit_at_s1e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1r_r(dst)) } -inst_at_s1e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1W, dst) } -emit_at_s1e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1w_r(dst)) } -inst_at_s1e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0R, dst) } -emit_at_s1e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0r_r(dst)) } -inst_at_s1e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0W, dst) } -emit_at_s1e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0w_r(dst)) } -inst_at_s1e2r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2R, dst) } -emit_at_s1e2r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2r_r(dst)) } -inst_at_s1e2w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2W, dst) } -emit_at_s1e2w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2w_r(dst)) } -inst_at_s1e3r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3R, dst) } -emit_at_s1e3r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3r_r(dst)) } -inst_at_s1e3w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3W, dst) } -emit_at_s1e3w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3w_r(dst)) } -inst_at_s12e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1R, dst) } -emit_at_s12e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1r_r(dst)) } -inst_at_s12e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1W, dst) } -emit_at_s12e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1w_r(dst)) } -inst_at_s12e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0R, dst) } -emit_at_s12e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0r_r(dst)) } -inst_at_s12e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0W, dst) } -emit_at_s12e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0w_r(dst)) } -inst_tlbi_vmalle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1) } -emit_tlbi_vmalle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1_none()) } -inst_tlbi_vmalle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1IS) } -emit_tlbi_vmalle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1is_none()) } -inst_tlbi_vae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1, dst) } -emit_tlbi_vae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1_r(dst)) } -inst_tlbi_vae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1IS, dst) } -emit_tlbi_vae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1is_r(dst)) } -inst_tlbi_aside1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1, dst) } -emit_tlbi_aside1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1_r(dst)) } -inst_tlbi_aside1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1IS, dst) } -emit_tlbi_aside1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1is_r(dst)) } -inst_tlbi_vaae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1, dst) } -emit_tlbi_vaae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1_r(dst)) } -inst_tlbi_vaae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1IS, dst) } -emit_tlbi_vaae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1is_r(dst)) } -inst_tlbi_vale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1, dst) } -emit_tlbi_vale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1_r(dst)) } -inst_tlbi_vale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1IS, dst) } -emit_tlbi_vale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1is_r(dst)) } -inst_tlbi_vaale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1, dst) } -emit_tlbi_vaale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1_r(dst)) } -inst_tlbi_vaale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1IS, dst) } -emit_tlbi_vaale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1is_r(dst)) } -inst_tlbi_alle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1) } -emit_tlbi_alle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1_none()) } -inst_tlbi_alle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1IS) } -emit_tlbi_alle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1is_none()) } -inst_tlbi_alle2_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2) } -emit_tlbi_alle2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2_none()) } -inst_tlbi_alle2is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2IS) } -emit_tlbi_alle2is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2is_none()) } -inst_tlbi_alle3_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3) } -emit_tlbi_alle3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3_none()) } -inst_tlbi_alle3is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3IS) } -emit_tlbi_alle3is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3is_none()) } -inst_prfm_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -emit_prfm_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfm_i_m(imm, mem)) } -inst_prfum_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFUM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } -emit_prfum_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfum_i_m(imm, mem)) } -inst_prfm_lit_i_l :: #force_inline proc "contextless" (imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .PRFM_LIT, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_label(label, 4), {}, {}}} } -emit_prfm_lit_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, label: u32) { append(instructions, inst_prfm_lit_i_l(imm, label)) } -inst_mov_reg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MOV_REG, dst, src) } -emit_mov_reg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_reg_r_r(dst, src)) } -inst_mvn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MVN, dst, src) } -emit_mvn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_r_r(dst, src)) } -inst_cmp_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMP_IMM, dst, imm) } -emit_cmp_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_imm_r_i(dst, imm)) } -inst_cmn_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMN_IMM, dst, imm) } -emit_cmn_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmn_imm_r_i(dst, imm)) } +inst_add_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADD_IMM, dst, src, imm) } +emit_add_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_add_imm_r_r_i(dst, src, imm)) } +inst_adds_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ADDS_IMM, dst, src, imm) } +emit_adds_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_adds_imm_r_r_i(dst, src, imm)) } +inst_sub_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUB_IMM, dst, src, imm) } +emit_sub_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_sub_imm_r_r_i(dst, src, imm)) } +inst_subs_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.SUBS_IMM, dst, src, imm) } +emit_subs_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_subs_imm_r_r_i(dst, src, imm)) } +inst_movz_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +emit_movz_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movz_r_i_i(dst, imm, imm2)) } +inst_movn_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVN, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +emit_movn_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movn_r_i_i(dst, imm, imm2)) } +inst_movk_r_i_i :: #force_inline proc "contextless" (dst: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .MOVK, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 2), op_imm(imm2, 1), {}}} } +emit_movk_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, imm2: i64) { append(instructions, inst_movk_r_i_i(dst, imm, imm2)) } +inst_adr_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADR, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_adr_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adr_r_l(dst, label)) } +inst_adrp_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .ADRP, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_adrp_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_adrp_r_l(dst, label)) } +inst_add_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_add_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_add_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_adds_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_adds_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_adds_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_sub_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_sub_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_sub_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_subs_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_subs_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_subs_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_and_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .AND_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_and_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_and_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_ands_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ANDS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_ands_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_ands_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_orr_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORR_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_orr_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orr_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_eor_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EOR_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_eor_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eor_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_bic_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BIC_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_bic_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bic_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_bics_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .BICS_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_bics_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_bics_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_orn_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ORN_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_orn_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_orn_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_eon_sr_r_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .EON_SR, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_shifted(src2, src2_shift, src2_amount), {}}} } +emit_eon_sr_r_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_shift: Shift_Type, src2_amount: u8) { append(instructions, inst_eon_sr_r_r_sh(dst, src, src2, src2_shift, src2_amount)) } +inst_add_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADD_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +emit_add_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_add_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +inst_adds_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .ADDS_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +emit_adds_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_adds_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +inst_sub_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUB_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +emit_sub_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_sub_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +inst_subs_er_r_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) -> Instruction { return Instruction{mnemonic = .SUBS_ER, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_extended(src2, src2_ext, src2_amount), {}}} } +emit_subs_er_r_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src2_ext: Extend, src2_amount: u8) { append(instructions, inst_subs_er_r_r_ex(dst, src, src2, src2_ext, src2_amount)) } +inst_lslv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSLV, dst, src, src2) } +emit_lslv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lslv_r_r_r(dst, src, src2)) } +inst_lsrv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.LSRV, dst, src, src2) } +emit_lsrv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_lsrv_r_r_r(dst, src, src2)) } +inst_asrv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ASRV, dst, src, src2) } +emit_asrv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_asrv_r_r_r(dst, src, src2)) } +inst_rorv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.RORV, dst, src, src2) } +emit_rorv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rorv_r_r_r(dst, src, src2)) } +inst_udiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UDIV, dst, src, src2) } +emit_udiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udiv_r_r_r(dst, src, src2)) } +inst_sdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SDIV, dst, src, src2) } +emit_sdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdiv_r_r_r(dst, src, src2)) } +inst_madd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MADD, dst, src, src2, src3) } +emit_madd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_madd_r_r_r_r(dst, src, src2, src3)) } +inst_msub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.MSUB, dst, src, src2, src3) } +emit_msub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_msub_r_r_r_r(dst, src, src2, src3)) } +inst_smaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMADDL, dst, src, src2, src3) } +emit_smaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smaddl_r_r_r_r(dst, src, src2, src3)) } +inst_smsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.SMSUBL, dst, src, src2, src3) } +emit_smsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_smsubl_r_r_r_r(dst, src, src2, src3)) } +inst_umaddl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMADDL, dst, src, src2, src3) } +emit_umaddl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umaddl_r_r_r_r(dst, src, src2, src3)) } +inst_umsubl_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.UMSUBL, dst, src, src2, src3) } +emit_umsubl_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_umsubl_r_r_r_r(dst, src, src2, src3)) } +inst_smulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SMULH, dst, src, src2) } +emit_smulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smulh_r_r_r(dst, src, src2)) } +inst_umulh_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.UMULH, dst, src, src2) } +emit_umulh_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_umulh_r_r_r(dst, src, src2)) } +inst_clz_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLZ, dst, src) } +emit_clz_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_clz_r_r(dst, src)) } +inst_cls_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.CLS, dst, src) } +emit_cls_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_cls_r_r(dst, src)) } +inst_rbit_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.RBIT, dst, src) } +emit_rbit_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rbit_r_r(dst, src)) } +inst_rev_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV, dst, src) } +emit_rev_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev_r_r(dst, src)) } +inst_rev16_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV16, dst, src) } +emit_rev16_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev16_r_r(dst, src)) } +inst_rev32_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.REV32, dst, src) } +emit_rev32_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_rev32_r_r(dst, src)) } +inst_csel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csel_r_r_r_c(dst, src, src2, cond)) } +inst_csinc_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINC, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csinc_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinc_r_r_r_c(dst, src, src2, cond)) } +inst_csinv_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSINV, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csinv_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csinv_r_r_r_c(dst, src, src2, cond)) } +inst_csneg_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .CSNEG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_csneg_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_csneg_r_r_r_c(dst, src, src2, cond)) } +inst_extr_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .EXTR, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_imm(imm, 1)}} } +emit_extr_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_extr_r_r_r_i(dst, src, src2, imm)) } +inst_b_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.B, label) } +emit_b_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_b_l(label)) } +inst_bl_l :: #force_inline proc "contextless" (label: u32) -> Instruction { return inst_branch(.BL, label) } +emit_bl_l :: #force_inline proc(instructions: ^[dynamic]Instruction, label: u32) { append(instructions, inst_bl_l(label)) } +inst_br_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BR, dst) } +emit_br_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_br_r(dst)) } +inst_blr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLR, dst) } +emit_blr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blr_r(dst)) } +inst_ret_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.RET, dst) } +inst_ret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RET) } +emit_ret_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ret_r(dst)) } +emit_ret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ret_none()) } +inst_b_cond_c_l :: #force_inline proc "contextless" (cond: Cond, label: u32) -> Instruction { return Instruction{mnemonic = .B_COND, operand_count = 2, length = 4, ops = {op_cond(cond), op_label(label, 4), {}, {}}} } +emit_b_cond_c_l :: #force_inline proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) { append(instructions, inst_b_cond_c_l(cond, label)) } +inst_cbz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_cbz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbz_r_l(dst, label)) } +inst_cbnz_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .CBNZ, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_cbnz_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_cbnz_r_l(dst, label)) } +inst_tbz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } +emit_tbz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbz_r_i_l(dst, imm, label)) } +inst_tbnz_r_i_l :: #force_inline proc "contextless" (dst: Register, imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .TBNZ, operand_count = 3, length = 4, ops = {op_reg(dst), op_imm(imm, 1), op_label(label, 4), {}}} } +emit_tbnz_r_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, label: u32) { append(instructions, inst_tbnz_r_i_l(dst, imm, label)) } +inst_ldr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR, dst, mem) } +emit_ldr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_r_m(dst, mem)) } +inst_str_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR, dst, mem) } +emit_str_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_r_m(dst, mem)) } +inst_ldrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRB, dst, mem) } +emit_ldrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrb_r_m(dst, mem)) } +inst_strb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRB, dst, mem) } +emit_strb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strb_r_m(dst, mem)) } +inst_ldrsb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSB, dst, mem) } +emit_ldrsb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsb_r_m(dst, mem)) } +inst_ldrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRH, dst, mem) } +emit_ldrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrh_r_m(dst, mem)) } +inst_strh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STRH, dst, mem) } +emit_strh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_strh_r_m(dst, mem)) } +inst_ldrsh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSH, dst, mem) } +emit_ldrsh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsh_r_m(dst, mem)) } +inst_ldrsw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRSW, dst, mem) } +emit_ldrsw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrsw_r_m(dst, mem)) } +inst_ldp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP, dst, src, mem) } +emit_ldp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_r_r_m(dst, src, mem)) } +inst_stp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP, dst, src, mem) } +emit_stp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_r_r_m(dst, src, mem)) } +inst_ldpsw_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW, dst, src, mem) } +emit_ldpsw_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_r_r_m(dst, src, mem)) } +inst_ldr_lit_r_l :: #force_inline proc "contextless" (dst: Register, label: u32) -> Instruction { return Instruction{mnemonic = .LDR_LIT, operand_count = 2, length = 4, ops = {op_reg(dst), op_label(label, 4), {}, {}}} } +emit_ldr_lit_r_l :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, label: u32) { append(instructions, inst_ldr_lit_r_l(dst, label)) } +inst_ldar_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAR, dst, mem) } +emit_ldar_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldar_r_m(dst, mem)) } +inst_stlr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLR, dst, mem) } +emit_stlr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlr_r_m(dst, mem)) } +inst_ldarb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARB, dst, mem) } +emit_ldarb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarb_r_m(dst, mem)) } +inst_stlrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRB, dst, mem) } +emit_stlrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrb_r_m(dst, mem)) } +inst_ldarh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDARH, dst, mem) } +emit_ldarh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldarh_r_m(dst, mem)) } +inst_stlrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLRH, dst, mem) } +emit_stlrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlrh_r_m(dst, mem)) } +inst_ldxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXR, dst, mem) } +emit_ldxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxr_r_m(dst, mem)) } +inst_stxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXR, dst, src, mem) } +emit_stxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxr_r_r_m(dst, src, mem)) } +inst_ldaxr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXR, dst, mem) } +emit_ldaxr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxr_r_m(dst, mem)) } +inst_stlxr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXR, dst, src, mem) } +emit_stlxr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxr_r_r_m(dst, src, mem)) } +inst_nop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.NOP) } +emit_nop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_nop_none()) } +inst_yield_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.YIELD) } +emit_yield_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_yield_none()) } +inst_wfe_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFE) } +emit_wfe_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfe_none()) } +inst_wfi_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.WFI) } +emit_wfi_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_wfi_none()) } +inst_sev_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEV) } +emit_sev_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sev_none()) } +inst_sevl_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SEVL) } +emit_sevl_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sevl_none()) } +inst_mrs_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MRS, dst, imm) } +emit_mrs_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mrs_r_i(dst, imm)) } +inst_msr_reg_i_r :: #force_inline proc "contextless" (imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .MSR_REG, operand_count = 2, length = 4, ops = {op_imm(imm, 4), op_reg(src), {}, {}}} } +emit_msr_reg_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) { append(instructions, inst_msr_reg_i_r(imm, src)) } +inst_isb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .ISB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_isb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_isb_i(imm)) } +inst_dsb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DSB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_dsb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dsb_i(imm)) } +inst_dmb_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .DMB, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_dmb_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_dmb_i(imm)) } +inst_svc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_svc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_svc_i(imm)) } +inst_hvc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HVC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_hvc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hvc_i(imm)) } +inst_smc_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SMC, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_smc_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_smc_i(imm)) } +inst_brk_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BRK, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_brk_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_brk_i(imm)) } +inst_hlt_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .HLT, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_hlt_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_hlt_i(imm)) } +inst_eret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERET) } +emit_eret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eret_none()) } +inst_fmov_reg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_REG, dst, src) } +emit_fmov_reg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_reg_r_r(dst, src)) } +inst_fmov_gen_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_GEN, dst, src) } +emit_fmov_gen_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_gen_r_r(dst, src)) } +inst_fabs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS, dst, src) } +emit_fabs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_r_r(dst, src)) } +inst_fneg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG, dst, src) } +emit_fneg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_r_r(dst, src)) } +inst_fsqrt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT, dst, src) } +emit_fsqrt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_r_r(dst, src)) } +inst_fadd_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD, dst, src, src2) } +emit_fadd_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_r_r_r(dst, src, src2)) } +inst_fsub_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB, dst, src, src2) } +emit_fsub_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_r_r_r(dst, src, src2)) } +inst_fmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL, dst, src, src2) } +emit_fmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_r_r_r(dst, src, src2)) } +inst_fdiv_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV, dst, src, src2) } +emit_fdiv_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_r_r_r(dst, src, src2)) } +inst_fnmul_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL, dst, src, src2) } +emit_fnmul_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_r_r_r(dst, src, src2)) } +inst_fmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD, dst, src, src2, src3) } +emit_fmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_r_r_r_r(dst, src, src2, src3)) } +inst_fmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMSUB, dst, src, src2, src3) } +emit_fmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_r_r_r_r(dst, src, src2, src3)) } +inst_fnmadd_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMADD, dst, src, src2, src3) } +emit_fnmadd_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_r_r_r_r(dst, src, src2, src3)) } +inst_fnmsub_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMSUB, dst, src, src2, src3) } +emit_fnmsub_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_r_r_r_r(dst, src, src2, src3)) } +inst_fcmp_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMP, dst, src) } +emit_fcmp_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_r_r(dst, src)) } +inst_fcmpe_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE, dst, src) } +emit_fcmpe_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_r_r(dst, src)) } +inst_fcsel_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_fcsel_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_r_r_r_c(dst, src, src2, cond)) } +inst_fmax_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX, dst, src, src2) } +emit_fmax_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_r_r_r(dst, src, src2)) } +inst_fmin_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN, dst, src, src2) } +emit_fmin_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_r_r_r(dst, src, src2)) } +inst_fmaxnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM, dst, src, src2) } +emit_fmaxnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_r_r_r(dst, src, src2)) } +inst_fminnm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM, dst, src, src2) } +emit_fminnm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_r_r_r(dst, src, src2)) } +inst_fcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT, dst, src) } +emit_fcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_r_r(dst, src)) } +inst_scvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF, dst, src) } +emit_scvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_r_r(dst, src)) } +inst_ucvtf_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF, dst, src) } +emit_ucvtf_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_r_r(dst, src)) } +inst_fcvtzs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS, dst, src) } +emit_fcvtzs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_r_r(dst, src)) } +inst_fcvtzu_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU, dst, src) } +emit_fcvtzu_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_r_r(dst, src)) } +inst_and_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.AND_IMM, dst, src, imm) } +emit_and_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_and_imm_r_r_i(dst, src, imm)) } +inst_ands_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ANDS_IMM, dst, src, imm) } +emit_ands_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ands_imm_r_r_i(dst, src, imm)) } +inst_orr_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ORR_IMM, dst, src, imm) } +emit_orr_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_orr_imm_r_r_i(dst, src, imm)) } +inst_eor_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.EOR_IMM, dst, src, imm) } +emit_eor_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_eor_imm_r_r_i(dst, src, imm)) } +inst_tst_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.TST_IMM, dst, imm) } +emit_tst_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_tst_imm_r_i(dst, imm)) } +inst_ldur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDUR, dst, mem) } +emit_ldur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldur_r_m(dst, mem)) } +inst_stur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STUR, dst, mem) } +emit_stur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stur_r_m(dst, mem)) } +inst_ldurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURB, dst, mem) } +emit_ldurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurb_r_m(dst, mem)) } +inst_sturb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURB, dst, mem) } +emit_sturb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturb_r_m(dst, mem)) } +inst_ldursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSB, dst, mem) } +emit_ldursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursb_r_m(dst, mem)) } +inst_ldurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURH, dst, mem) } +emit_ldurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldurh_r_m(dst, mem)) } +inst_sturh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STURH, dst, mem) } +emit_sturh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_sturh_r_m(dst, mem)) } +inst_ldursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSH, dst, mem) } +emit_ldursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursh_r_m(dst, mem)) } +inst_ldursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDURSW, dst, mem) } +emit_ldursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldursw_r_m(dst, mem)) } +inst_ldr_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_PRE, dst, mem) } +emit_ldr_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_pre_r_m(dst, mem)) } +inst_str_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_PRE, dst, mem) } +emit_str_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_pre_r_m(dst, mem)) } +inst_ldr_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_POST, dst, mem) } +emit_ldr_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_post_r_m(dst, mem)) } +inst_str_post_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_POST, dst, mem) } +emit_str_post_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_post_r_m(dst, mem)) } +inst_ldr_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_REG, dst, mem) } +emit_ldr_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_reg_r_m(dst, mem)) } +inst_str_reg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_REG, dst, mem) } +emit_str_reg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_reg_r_m(dst, mem)) } +inst_ldp_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP_PRE, dst, src, mem) } +emit_ldp_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_pre_r_r_m(dst, src, mem)) } +inst_stp_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP_PRE, dst, src, mem) } +emit_stp_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_pre_r_r_m(dst, src, mem)) } +inst_ldp_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDP_POST, dst, src, mem) } +emit_ldp_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldp_post_r_r_m(dst, src, mem)) } +inst_stp_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STP_POST, dst, src, mem) } +emit_stp_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stp_post_r_r_m(dst, src, mem)) } +inst_ldpsw_pre_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW_PRE, dst, src, mem) } +emit_ldpsw_pre_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_pre_r_r_m(dst, src, mem)) } +inst_ldpsw_post_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDPSW_POST, dst, src, mem) } +emit_ldpsw_post_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldpsw_post_r_r_m(dst, src, mem)) } +inst_ldnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDNP, dst, src, mem) } +emit_ldnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldnp_r_r_m(dst, src, mem)) } +inst_stnp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STNP, dst, src, mem) } +emit_stnp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stnp_r_r_m(dst, src, mem)) } +inst_ldxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDXP, dst, src, mem) } +emit_ldxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldxp_r_r_m(dst, src, mem)) } +inst_stxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } +emit_stxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stxp_r_r_r_m(dst, src, src2, mem)) } +inst_ldaxp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDAXP, dst, src, mem) } +emit_ldaxp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaxp_r_r_m(dst, src, mem)) } +inst_stlxp_r_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .STLXP, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_mem(mem)}} } +emit_stlxp_r_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, mem: Memory) { append(instructions, inst_stlxp_r_r_r_m(dst, src, src2, mem)) } +inst_ldxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRB, dst, mem) } +emit_ldxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrb_r_m(dst, mem)) } +inst_stxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRB, dst, src, mem) } +emit_stxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrb_r_r_m(dst, src, mem)) } +inst_ldaxrb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRB, dst, mem) } +emit_ldaxrb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrb_r_m(dst, mem)) } +inst_stlxrb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRB, dst, src, mem) } +emit_stlxrb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrb_r_r_m(dst, src, mem)) } +inst_ldxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDXRH, dst, mem) } +emit_ldxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldxrh_r_m(dst, mem)) } +inst_stxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STXRH, dst, src, mem) } +emit_stxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stxrh_r_r_m(dst, src, mem)) } +inst_ldaxrh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAXRH, dst, mem) } +emit_ldaxrh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaxrh_r_m(dst, mem)) } +inst_stlxrh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STLXRH, dst, src, mem) } +emit_stlxrh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stlxrh_r_r_m(dst, src, mem)) } +inst_ldapr_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPR, dst, mem) } +emit_ldapr_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapr_r_m(dst, mem)) } +inst_ldaprb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRB, dst, mem) } +emit_ldaprb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprb_r_m(dst, mem)) } +inst_ldaprh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPRH, dst, mem) } +emit_ldaprh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldaprh_r_m(dst, mem)) } +inst_ldadd_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADD, dst, src, mem) } +emit_ldadd_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadd_r_r_m(dst, src, mem)) } +inst_ldadda_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDA, dst, src, mem) } +emit_ldadda_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldadda_r_r_m(dst, src, mem)) } +inst_ldaddl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDL, dst, src, mem) } +emit_ldaddl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddl_r_r_m(dst, src, mem)) } +inst_ldaddal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDADDAL, dst, src, mem) } +emit_ldaddal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldaddal_r_r_m(dst, src, mem)) } +inst_ldclr_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLR, dst, src, mem) } +emit_ldclr_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclr_r_r_m(dst, src, mem)) } +inst_ldclra_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRA, dst, src, mem) } +emit_ldclra_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclra_r_r_m(dst, src, mem)) } +inst_ldclrl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRL, dst, src, mem) } +emit_ldclrl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclrl_r_r_m(dst, src, mem)) } +inst_ldclral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDCLRAL, dst, src, mem) } +emit_ldclral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldclral_r_r_m(dst, src, mem)) } +inst_ldeor_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEOR, dst, src, mem) } +emit_ldeor_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeor_r_r_m(dst, src, mem)) } +inst_ldeora_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORA, dst, src, mem) } +emit_ldeora_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeora_r_r_m(dst, src, mem)) } +inst_ldeorl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORL, dst, src, mem) } +emit_ldeorl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeorl_r_r_m(dst, src, mem)) } +inst_ldeoral_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDEORAL, dst, src, mem) } +emit_ldeoral_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldeoral_r_r_m(dst, src, mem)) } +inst_ldset_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSET, dst, src, mem) } +emit_ldset_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldset_r_r_m(dst, src, mem)) } +inst_ldseta_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETA, dst, src, mem) } +emit_ldseta_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldseta_r_r_m(dst, src, mem)) } +inst_ldsetl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETL, dst, src, mem) } +emit_ldsetl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetl_r_r_m(dst, src, mem)) } +inst_ldsetal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSETAL, dst, src, mem) } +emit_ldsetal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsetal_r_r_m(dst, src, mem)) } +inst_ldsmax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAX, dst, src, mem) } +emit_ldsmax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmax_r_r_m(dst, src, mem)) } +inst_ldsmaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXA, dst, src, mem) } +emit_ldsmaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxa_r_r_m(dst, src, mem)) } +inst_ldsmaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXL, dst, src, mem) } +emit_ldsmaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxl_r_r_m(dst, src, mem)) } +inst_ldsmaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMAXAL, dst, src, mem) } +emit_ldsmaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmaxal_r_r_m(dst, src, mem)) } +inst_ldsmin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMIN, dst, src, mem) } +emit_ldsmin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmin_r_r_m(dst, src, mem)) } +inst_ldsmina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINA, dst, src, mem) } +emit_ldsmina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsmina_r_r_m(dst, src, mem)) } +inst_ldsminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINL, dst, src, mem) } +emit_ldsminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminl_r_r_m(dst, src, mem)) } +inst_ldsminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDSMINAL, dst, src, mem) } +emit_ldsminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldsminal_r_r_m(dst, src, mem)) } +inst_ldumax_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAX, dst, src, mem) } +emit_ldumax_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumax_r_r_m(dst, src, mem)) } +inst_ldumaxa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXA, dst, src, mem) } +emit_ldumaxa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxa_r_r_m(dst, src, mem)) } +inst_ldumaxl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXL, dst, src, mem) } +emit_ldumaxl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxl_r_r_m(dst, src, mem)) } +inst_ldumaxal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMAXAL, dst, src, mem) } +emit_ldumaxal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumaxal_r_r_m(dst, src, mem)) } +inst_ldumin_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMIN, dst, src, mem) } +emit_ldumin_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumin_r_r_m(dst, src, mem)) } +inst_ldumina_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINA, dst, src, mem) } +emit_ldumina_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_ldumina_r_r_m(dst, src, mem)) } +inst_lduminl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINL, dst, src, mem) } +emit_lduminl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminl_r_r_m(dst, src, mem)) } +inst_lduminal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.LDUMINAL, dst, src, mem) } +emit_lduminal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_lduminal_r_r_m(dst, src, mem)) } +inst_swp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWP, dst, src, mem) } +emit_swp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swp_r_r_m(dst, src, mem)) } +inst_swpa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPA, dst, src, mem) } +emit_swpa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpa_r_r_m(dst, src, mem)) } +inst_swpl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPL, dst, src, mem) } +emit_swpl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpl_r_r_m(dst, src, mem)) } +inst_swpal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.SWPAL, dst, src, mem) } +emit_swpal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_swpal_r_r_m(dst, src, mem)) } +inst_cas_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CAS, dst, src, mem) } +emit_cas_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cas_r_r_m(dst, src, mem)) } +inst_casa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASA, dst, src, mem) } +emit_casa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casa_r_r_m(dst, src, mem)) } +inst_casl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASL, dst, src, mem) } +emit_casl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casl_r_r_m(dst, src, mem)) } +inst_casal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAL, dst, src, mem) } +emit_casal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casal_r_r_m(dst, src, mem)) } +inst_casb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASB, dst, src, mem) } +emit_casb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casb_r_r_m(dst, src, mem)) } +inst_casab_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAB, dst, src, mem) } +emit_casab_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casab_r_r_m(dst, src, mem)) } +inst_caslb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLB, dst, src, mem) } +emit_caslb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslb_r_r_m(dst, src, mem)) } +inst_casalb_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALB, dst, src, mem) } +emit_casalb_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalb_r_r_m(dst, src, mem)) } +inst_cash_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASH, dst, src, mem) } +emit_cash_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_cash_r_r_m(dst, src, mem)) } +inst_casah_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASAH, dst, src, mem) } +emit_casah_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casah_r_r_m(dst, src, mem)) } +inst_caslh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASLH, dst, src, mem) } +emit_caslh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caslh_r_r_m(dst, src, mem)) } +inst_casalh_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASALH, dst, src, mem) } +emit_casalh_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casalh_r_r_m(dst, src, mem)) } +inst_casp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASP, dst, src, mem) } +emit_casp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_casp_r_r_m(dst, src, mem)) } +inst_caspa_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPA, dst, src, mem) } +emit_caspa_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspa_r_r_m(dst, src, mem)) } +inst_caspl_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPL, dst, src, mem) } +emit_caspl_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspl_r_r_m(dst, src, mem)) } +inst_caspal_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.CASPAL, dst, src, mem) } +emit_caspal_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_caspal_r_r_m(dst, src, mem)) } +inst_pacia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIA, dst, src) } +emit_pacia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacia_r_r(dst, src)) } +inst_pacib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACIB, dst, src) } +emit_pacib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacib_r_r(dst, src)) } +inst_pacda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDA, dst, src) } +emit_pacda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacda_r_r(dst, src)) } +inst_pacdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.PACDB, dst, src) } +emit_pacdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_pacdb_r_r(dst, src)) } +inst_paciza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZA, dst) } +emit_paciza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_paciza_r(dst)) } +inst_pacizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACIZB, dst) } +emit_pacizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacizb_r(dst)) } +inst_pacdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZA, dst) } +emit_pacdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdza_r(dst)) } +inst_pacdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.PACDZB, dst) } +emit_pacdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_pacdzb_r(dst)) } +inst_autia_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIA, dst, src) } +emit_autia_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autia_r_r(dst, src)) } +inst_autib_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTIB, dst, src) } +emit_autib_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autib_r_r(dst, src)) } +inst_autda_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDA, dst, src) } +emit_autda_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autda_r_r(dst, src)) } +inst_autdb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.AUTDB, dst, src) } +emit_autdb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_autdb_r_r(dst, src)) } +inst_autiza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZA, dst) } +emit_autiza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autiza_r(dst)) } +inst_autizb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTIZB, dst) } +emit_autizb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autizb_r(dst)) } +inst_autdza_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZA, dst) } +emit_autdza_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdza_r(dst)) } +inst_autdzb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AUTDZB, dst) } +emit_autdzb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_autdzb_r(dst)) } +inst_paciasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIASP) } +emit_paciasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_paciasp_none()) } +inst_pacibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIBSP) } +emit_pacibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacibsp_none()) } +inst_autiasp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIASP) } +emit_autiasp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autiasp_none()) } +inst_autibsp_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIBSP) } +emit_autibsp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autibsp_none()) } +inst_pacia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIA1716) } +emit_pacia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacia1716_none()) } +inst_pacib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PACIB1716) } +emit_pacib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_pacib1716_none()) } +inst_autia1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIA1716) } +emit_autia1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autia1716_none()) } +inst_autib1716_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AUTIB1716) } +emit_autib1716_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_autib1716_none()) } +inst_pacga_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.PACGA, dst, src, src2) } +emit_pacga_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pacga_r_r_r(dst, src, src2)) } +inst_xpaci_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACI, dst) } +emit_xpaci_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpaci_r(dst)) } +inst_xpacd_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.XPACD, dst) } +emit_xpacd_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_xpacd_r(dst)) } +inst_xpaclri_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.XPACLRI) } +emit_xpaclri_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_xpaclri_none()) } +inst_retaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAA) } +emit_retaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retaa_none()) } +inst_retab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RETAB) } +emit_retab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_retab_none()) } +inst_braa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAA, dst, src) } +emit_braa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_braa_r_r(dst, src)) } +inst_brab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BRAB, dst, src) } +emit_brab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_brab_r_r(dst, src)) } +inst_braaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRAAZ, dst) } +emit_braaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_braaz_r(dst)) } +inst_brabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BRABZ, dst) } +emit_brabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_brabz_r(dst)) } +inst_blraa_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAA, dst, src) } +emit_blraa_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blraa_r_r(dst, src)) } +inst_blrab_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BLRAB, dst, src) } +emit_blrab_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_blrab_r_r(dst, src)) } +inst_blraaz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRAAZ, dst) } +emit_blraaz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blraaz_r(dst)) } +inst_blrabz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.BLRABZ, dst) } +emit_blrabz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_blrabz_r(dst)) } +inst_eretaa_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAA) } +emit_eretaa_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretaa_none()) } +inst_eretab_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.ERETAB) } +emit_eretab_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_eretab_none()) } +inst_bti_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .BTI, operand_count = 1, length = 4, ops = {op_imm(imm, 1), {}, {}, {}}} } +emit_bti_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_bti_i(imm)) } +inst_irg_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.IRG, dst, src, src2) } +emit_irg_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_irg_r_r_r(dst, src, src2)) } +inst_addg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .ADDG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } +emit_addg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_addg_r_r_i_i(dst, src, imm, imm2)) } +inst_subg_r_r_i_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SUBG, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_imm(imm, 1), op_imm(imm2, 1)}} } +emit_subg_r_r_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64, imm2: i64) { append(instructions, inst_subg_r_r_i_i(dst, src, imm, imm2)) } +inst_gmi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.GMI, dst, src, src2) } +emit_gmi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_gmi_r_r_r(dst, src, src2)) } +inst_subp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBP, dst, src, src2) } +emit_subp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subp_r_r_r(dst, src, src2)) } +inst_subps_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SUBPS, dst, src, src2) } +emit_subps_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subps_r_r_r(dst, src, src2)) } +inst_ldg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDG, dst, mem) } +emit_ldg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldg_r_m(dst, mem)) } +inst_stg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STG, dst, mem) } +emit_stg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stg_r_m(dst, mem)) } +inst_st2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.ST2G, dst, mem) } +emit_st2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st2g_r_m(dst, mem)) } +inst_stzg_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZG, dst, mem) } +emit_stzg_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzg_r_m(dst, mem)) } +inst_stz2g_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZ2G, dst, mem) } +emit_stz2g_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stz2g_r_m(dst, mem)) } +inst_stgp_r_r_m :: #force_inline proc "contextless" (dst: Register, src: Register, mem: Memory) -> Instruction { return inst_ldp_stp(.STGP, dst, src, mem) } +emit_stgp_r_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, mem: Memory) { append(instructions, inst_stgp_r_r_m(dst, src, mem)) } +inst_ldgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDGM, dst, mem) } +emit_ldgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldgm_r_m(dst, mem)) } +inst_stgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STGM, dst, mem) } +emit_stgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stgm_r_m(dst, mem)) } +inst_stzgm_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STZGM, dst, mem) } +emit_stzgm_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stzgm_r_m(dst, mem)) } +inst_crc32b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32B, dst, src, src2) } +emit_crc32b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32b_r_r_r(dst, src, src2)) } +inst_crc32h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32H, dst, src, src2) } +emit_crc32h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32h_r_r_r(dst, src, src2)) } +inst_crc32w_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32W, dst, src, src2) } +emit_crc32w_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32w_r_r_r(dst, src, src2)) } +inst_crc32x_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32X, dst, src, src2) } +emit_crc32x_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32x_r_r_r(dst, src, src2)) } +inst_crc32cb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CB, dst, src, src2) } +emit_crc32cb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cb_r_r_r(dst, src, src2)) } +inst_crc32ch_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CH, dst, src, src2) } +emit_crc32ch_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32ch_r_r_r(dst, src, src2)) } +inst_crc32cw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CW, dst, src, src2) } +emit_crc32cw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cw_r_r_r(dst, src, src2)) } +inst_crc32cx_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CRC32CX, dst, src, src2) } +emit_crc32cx_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_crc32cx_r_r_r(dst, src, src2)) } +inst_aese_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESE, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } +emit_aese_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aese_r_r(dst, src)) } +inst_aesd_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESD, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } +emit_aesd_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesd_r_r(dst, src)) } +inst_aesmc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESMC, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } +emit_aesmc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesmc_r_r(dst, src)) } +inst_aesimc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .AESIMC, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), {}, {}}} } +emit_aesimc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_aesimc_r_r(dst, src)) } +inst_sha1h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SHA1H, dst, src) } +emit_sha1h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1h_r_r(dst, src)) } +inst_sha1c_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1C, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha1c_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1c_r_r_r(dst, src, src2)) } +inst_sha1p_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1P, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha1p_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1p_r_r_r(dst, src, src2)) } +inst_sha1m_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1M, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha1m_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1m_r_r_r(dst, src, src2)) } +inst_sha1su0_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU0, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha1su0_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha1su0_r_r_r(dst, src, src2)) } +inst_sha1su1_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA1SU1, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_sha1su1_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha1su1_r_r(dst, src)) } +inst_sha256h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha256h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h_r_r_r(dst, src, src2)) } +inst_sha256h2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha256h2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256h2_r_r_r(dst, src, src2)) } +inst_sha256su0_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU0, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_sha256su0_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha256su0_r_r(dst, src)) } +inst_sha256su1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA256SU1, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sha256su1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha256su1_r_r_r(dst, src, src2)) } +inst_sha512h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(u8(reg_hw(src2))), {}}} } +emit_sha512h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h_r_r_r(dst, src, src2)) } +inst_sha512h2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512H2, operand_count = 3, length = 4, ops = {op_reg(dst), op_reg(src), op_v_2d(u8(reg_hw(src2))), {}}} } +emit_sha512h2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512h2_r_r_r(dst, src, src2)) } +inst_sha512su0_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU0, operand_count = 2, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), {}, {}}} } +emit_sha512su0_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sha512su0_r_r(dst, src)) } +inst_sha512su1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SHA512SU1, operand_count = 3, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), {}}} } +emit_sha512su1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sha512su1_r_r_r(dst, src, src2)) } +inst_eor3_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .EOR3, operand_count = 4, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), op_v_16b(u8(reg_hw(src3)))}} } +emit_eor3_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_eor3_r_r_r_r(dst, src, src2, src3)) } +inst_bcax_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .BCAX, operand_count = 4, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), op_v_16b(u8(reg_hw(src3)))}} } +emit_bcax_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_bcax_r_r_r_r(dst, src, src2, src3)) } +inst_rax1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RAX1, operand_count = 3, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), {}}} } +emit_rax1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rax1_r_r_r(dst, src, src2)) } +inst_xar_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .XAR, operand_count = 4, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), op_imm(imm, 1)}} } +emit_xar_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_xar_r_r_r_i(dst, src, src2, imm)) } +inst_sm3partw1_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW1, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sm3partw1_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw1_r_r_r(dst, src, src2)) } +inst_sm3partw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3PARTW2, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sm3partw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3partw2_r_r_r(dst, src, src2)) } +inst_sm3ss1_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return Instruction{mnemonic = .SM3SS1, operand_count = 4, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), op_v_4s(u8(reg_hw(src3)))}} } +emit_sm3ss1_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_sm3ss1_r_r_r_r(dst, src, src2, src3)) } +inst_sm3tt1a_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1A, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_reg(src2), {}}} } +emit_sm3tt1a_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1a_r_r_r(dst, src, src2)) } +inst_sm3tt1b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT1B, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_reg(src2), {}}} } +emit_sm3tt1b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt1b_r_r_r(dst, src, src2)) } +inst_sm3tt2a_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2A, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_reg(src2), {}}} } +emit_sm3tt2a_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2a_r_r_r(dst, src, src2)) } +inst_sm3tt2b_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM3TT2B, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_reg(src2), {}}} } +emit_sm3tt2b_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm3tt2b_r_r_r(dst, src, src2)) } +inst_sm4e_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SM4E, operand_count = 2, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_sm4e_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sm4e_r_r(dst, src)) } +inst_sm4ekey_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SM4EKEY, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_sm4ekey_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sm4ekey_r_r_r(dst, src, src2)) } +inst_pmull_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_pmull_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull_r_r_r(dst, src, src2)) } +inst_pmull2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .PMULL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_pmull2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_pmull2_r_r_r(dst, src, src2)) } +inst_fabs_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FABS_H, dst, src) } +emit_fabs_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fabs_h_r_r(dst, src)) } +inst_fneg_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FNEG_H, dst, src) } +emit_fneg_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fneg_h_r_r(dst, src)) } +inst_fsqrt_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FSQRT_H, dst, src) } +emit_fsqrt_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fsqrt_h_r_r(dst, src)) } +inst_fadd_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FADD_H, dst, src, src2) } +emit_fadd_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_h_r_r_r(dst, src, src2)) } +inst_fsub_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FSUB_H, dst, src, src2) } +emit_fsub_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_h_r_r_r(dst, src, src2)) } +inst_fmul_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMUL_H, dst, src, src2) } +emit_fmul_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_h_r_r_r(dst, src, src2)) } +inst_fdiv_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FDIV_H, dst, src, src2) } +emit_fdiv_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_h_r_r_r(dst, src, src2)) } +inst_fnmul_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FNMUL_H, dst, src, src2) } +emit_fnmul_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fnmul_h_r_r_r(dst, src, src2)) } +inst_fmadd_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMADD_H, dst, src, src2, src3) } +emit_fmadd_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmadd_h_r_r_r_r(dst, src, src2, src3)) } +inst_fmsub_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FMSUB_H, dst, src, src2, src3) } +emit_fmsub_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fmsub_h_r_r_r_r(dst, src, src2, src3)) } +inst_fnmadd_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMADD_H, dst, src, src2, src3) } +emit_fnmadd_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmadd_h_r_r_r_r(dst, src, src2, src3)) } +inst_fnmsub_h_r_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, src3: Register) -> Instruction { return inst_r_r_r_r(.FNMSUB_H, dst, src, src2, src3) } +emit_fnmsub_h_r_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, src3: Register) { append(instructions, inst_fnmsub_h_r_r_r_r(dst, src, src2, src3)) } +inst_fcmp_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMP_H, dst, src) } +emit_fcmp_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmp_h_r_r(dst, src)) } +inst_fcmpe_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCMPE_H, dst, src) } +emit_fcmpe_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcmpe_h_r_r(dst, src)) } +inst_fcsel_h_r_r_r_c :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, cond: Cond) -> Instruction { return Instruction{mnemonic = .FCSEL_H, operand_count = 4, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), op_cond(cond)}} } +emit_fcsel_h_r_r_r_c :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, cond: Cond) { append(instructions, inst_fcsel_h_r_r_r_c(dst, src, src2, cond)) } +inst_fmax_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAX_H, dst, src, src2) } +emit_fmax_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmax_h_r_r_r(dst, src, src2)) } +inst_fmin_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMIN_H, dst, src, src2) } +emit_fmin_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmin_h_r_r_r(dst, src, src2)) } +inst_fmaxnm_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMAXNM_H, dst, src, src2) } +emit_fmaxnm_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmaxnm_h_r_r_r(dst, src, src2)) } +inst_fminnm_h_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.FMINNM_H, dst, src, src2) } +emit_fminnm_h_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fminnm_h_r_r_r(dst, src, src2)) } +inst_fcvt_h_s_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_H_S, dst, src) } +emit_fcvt_h_s_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_h_s_r_r(dst, src)) } +inst_fcvt_h_d_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_H_D, dst, src) } +emit_fcvt_h_d_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_h_d_r_r(dst, src)) } +inst_fcvt_s_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_S_H, dst, src) } +emit_fcvt_s_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_s_h_r_r(dst, src)) } +inst_fcvt_d_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVT_D_H, dst, src) } +emit_fcvt_d_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvt_d_h_r_r(dst, src)) } +inst_fmov_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FMOV_H, dst, src) } +emit_fmov_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fmov_h_r_r(dst, src)) } +inst_scvtf_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SCVTF_H, dst, src) } +emit_scvtf_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_scvtf_h_r_r(dst, src)) } +inst_ucvtf_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UCVTF_H, dst, src) } +emit_ucvtf_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ucvtf_h_r_r(dst, src)) } +inst_fcvtzs_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZS_H, dst, src) } +emit_fcvtzs_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzs_h_r_r(dst, src)) } +inst_fcvtzu_h_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.FCVTZU_H, dst, src) } +emit_fcvtzu_h_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_fcvtzu_h_r_r(dst, src)) } +inst_bfcvt_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.BFCVT, dst, src) } +emit_bfcvt_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvt_r_r(dst, src)) } +inst_bfdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFDOT, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_bfdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfdot_r_r_r(dst, src, src2)) } +inst_bfmmla_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMMLA, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_bfmmla_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmmla_r_r_r(dst, src, src2)) } +inst_bfmlalb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALB, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_bfmlalb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalb_r_r_r(dst, src, src2)) } +inst_bfmlalt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BFMLALT, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_bfmlalt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bfmlalt_r_r_r(dst, src, src2)) } +inst_bfcvtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_bfcvtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn_r_r(dst, src)) } +inst_bfcvtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .BFCVTN2, operand_count = 2, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), {}, {}}} } +emit_bfcvtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_bfcvtn2_r_r(dst, src)) } +inst_add_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADD_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_add_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_add_v_r_r_r(dst, src, src2)) } +inst_sub_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUB_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_sub_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sub_v_r_r_r(dst, src, src2)) } +inst_mul_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .MUL_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_mul_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_mul_v_r_r_r(dst, src, src2)) } +inst_sdot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_sdot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sdot_r_r_r(dst, src, src2)) } +inst_udot_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UDOT, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_udot_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_udot_r_r_r(dst, src, src2)) } +inst_fadd_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FADD_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_fadd_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fadd_v_r_r_r(dst, src, src2)) } +inst_fsub_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FSUB_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_fsub_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fsub_v_r_r_r(dst, src, src2)) } +inst_fmul_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMUL_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_fmul_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmul_v_r_r_r(dst, src, src2)) } +inst_fdiv_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FDIV_V, operand_count = 3, length = 4, ops = {op_v_2s(u8(reg_hw(dst))), op_v_2s(u8(reg_hw(src))), op_v_2s(u8(reg_hw(src2))), {}}} } +emit_fdiv_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fdiv_v_r_r_r(dst, src, src2)) } +inst_fmla_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLA_V, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_fmla_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmla_v_r_r_r(dst, src, src2)) } +inst_fmls_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .FMLS_V, operand_count = 3, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), {}}} } +emit_fmls_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_fmls_v_r_r_r(dst, src, src2)) } +inst_cmeq_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMEQ, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_cmeq_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmeq_r_r_r(dst, src, src2)) } +inst_cmgt_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMGT, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_cmgt_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmgt_r_r_r(dst, src, src2)) } +inst_cmhi_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CMHI, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_cmhi_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cmhi_r_r_r(dst, src, src2)) } +inst_and_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .AND_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_and_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_and_v_r_r_r(dst, src, src2)) } +inst_orr_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORR_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_orr_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orr_v_r_r_r(dst, src, src2)) } +inst_eor_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .EOR_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_eor_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_eor_v_r_r_r(dst, src, src2)) } +inst_bic_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIC_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_bic_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bic_v_r_r_r(dst, src, src2)) } +inst_orn_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ORN_V, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_orn_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_orn_v_r_r_r(dst, src, src2)) } +inst_bit_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIT, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_bit_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bit_r_r_r(dst, src, src2)) } +inst_bif_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BIF, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_bif_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bif_r_r_r(dst, src, src2)) } +inst_bsl_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .BSL, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_bsl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_bsl_r_r_r(dst, src, src2)) } +inst_ld1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .LD1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +emit_ld1_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ld1_r_m(dst, mem)) } +inst_st1_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return Instruction{mnemonic = .ST1, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_mem(mem), {}, {}}} } +emit_st1_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_st1_r_m(dst, mem)) } +inst_ldr_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDR_V, dst, mem) } +emit_ldr_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldr_v_r_m(dst, mem)) } +inst_str_v_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STR_V, dst, mem) } +emit_str_v_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_str_v_r_m(dst, mem)) } +inst_sve_add_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADD_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_add_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_add_z_z_z_z(rz, rz2, rz3)) } +inst_sve_sub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SUB_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_sub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sub_z_z_z_z(rz, rz2, rz3)) } +inst_sve_sqadd_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQADD_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_sqadd_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqadd_z_z_z_z(rz, rz2, rz3)) } +inst_sve_uqadd_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UQADD_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_uqadd_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uqadd_z_z_z_z(rz, rz2, rz3)) } +inst_sve_sqsub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQSUB_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_sqsub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqsub_z_z_z_z(rz, rz2, rz3)) } +inst_sve_uqsub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UQSUB_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_uqsub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uqsub_z_z_z_z(rz, rz2, rz3)) } +inst_sve_add_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADD_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_add_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_add_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_sub_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SUB_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_sub_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sub_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_subr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SUBR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_subr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_subr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_mul_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_MUL_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_mul_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_mul_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_smulh_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SMULH_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_smulh_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_smulh_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_umulh_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UMULH_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_umulh_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_umulh_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_sdiv_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SDIV_PRED, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_sve_sdiv_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sdiv_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_udiv_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UDIV_PRED, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_sve_udiv_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_udiv_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_smax_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SMAX_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_smax_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_smax_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_umax_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UMAX_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_umax_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_umax_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_smin_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SMIN_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_smin_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_smin_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_umin_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UMIN_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_umin_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_umin_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_sabd_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SABD_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_sabd_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sabd_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_uabd_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_UABD_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_uabd_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_uabd_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_and_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_AND_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_sve_and_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_and_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_orr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORR_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_sve_orr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_eor_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EOR_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_sve_eor_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eor_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_bic_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BIC_PRED, operand_count = 4, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_d(rz3), op_z_d(rz4)}} } +emit_sve_bic_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bic_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_asr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ASR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_asr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_asr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_lsl_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSL_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_lsl_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsl_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_lsr_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_LSR_PRED, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_lsr_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_lsr_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_abs_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ABS_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_sve_abs_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_abs_pred_z_p_z(rz, rz2, rz3)) } +inst_sve_neg_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_NEG_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_sve_neg_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_neg_pred_z_p_z(rz, rz2, rz3)) } +inst_sve_cls_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_CLS_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_sve_cls_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_cls_pred_z_p_z(rz, rz2, rz3)) } +inst_sve_clz_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_CLZ_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_sve_clz_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_clz_pred_z_p_z(rz, rz2, rz3)) } +inst_sve_cnt_pred_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_CNT_PRED, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), {}}} } +emit_sve_cnt_pred_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_cnt_pred_z_p_z(rz, rz2, rz3)) } +inst_sve_fadd_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FADD_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_sve_fadd_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fadd_z_z_z_z(rz, rz2, rz3)) } +inst_sve_fsub_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUB_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_sve_fsub_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fsub_z_z_z_z(rz, rz2, rz3)) } +inst_sve_fmul_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMUL_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_sve_fmul_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fmul_z_z_z_z(rz, rz2, rz3)) } +inst_sve_frecps_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRECPS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_sve_frecps_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frecps_z_z_z(rz, rz2, rz3)) } +inst_sve_frsqrts_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FRSQRTS, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_sve_frsqrts_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_frsqrts_z_z_z(rz, rz2, rz3)) } +inst_sve_ftsmul_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FTSMUL, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_sve_ftsmul_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_ftsmul_z_z_z(rz, rz2, rz3)) } +inst_sve_fadd_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FADD_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fadd_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fadd_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fsub_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSUB_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fsub_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fsub_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fmul_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMUL_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fmul_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmul_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fdiv_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FDIV_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fdiv_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fdiv_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fmax_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMAX_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fmax_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmax_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fmin_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMIN_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fmin_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmin_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fmaxnm_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMAXNM_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fmaxnm_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmaxnm_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fminnm_pred_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMINNM_PRED, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fminnm_pred_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fminnm_pred_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fabs_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FABS_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_fabs_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fabs_z_z_p_z(rz, rz2, rz3)) } +inst_sve_fneg_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FNEG_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_fneg_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fneg_z_z_p_z(rz, rz2, rz3)) } +inst_sve_fsqrt_z_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_FSQRT_Z, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), {}}} } +emit_sve_fsqrt_z_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_fsqrt_z_z_p_z(rz, rz2, rz3)) } +inst_sve_fmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmla_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fmls_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fnmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FNMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fnmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fnmla_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_fnmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_FNMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_fnmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_fnmls_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_and_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_AND_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_and_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_and_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_bic_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BIC_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_bic_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bic_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_orr_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORR_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_orr_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orr_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_eor_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EOR_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_eor_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eor_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_nand_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NAND_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_nand_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nand_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_nor_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NOR_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_nor_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nor_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_orn_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORN_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_orn_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orn_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_sel_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SEL_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_sel_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_sel_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_ands_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ANDS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_ands_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_ands_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_bics_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BICS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_bics_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bics_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_orrs_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_ORRS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_orrs_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_orrs_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_eors_p_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_EORS_P, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), op_reg(Register(REG_P | (u16(rz4) & 0xF)))}} } +emit_sve_eors_p_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_eors_p_p_p_p_p(rz, rz2, rz3, rz4)) } +inst_sve_ptrue_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_PTRUE, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +emit_sve_ptrue_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_sve_ptrue_p_i(rz, imm)) } +inst_sve_ptrues_p_i :: #force_inline proc "contextless" (rz: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_PTRUES, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_imm(imm, 4), {}, {}}} } +emit_sve_ptrues_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64) { append(instructions, inst_sve_ptrues_p_i(rz, imm)) } +inst_sve_pfalse_p :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_PFALSE, operand_count = 1, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), {}, {}, {}}} } +emit_sve_pfalse_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_pfalse_p(rz)) } +inst_sve_pfirst_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PFIRST, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_pfirst_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pfirst_p_p_p(rz, rz2, rz3)) } +inst_sve_pnext_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PNEXT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_pnext_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pnext_p_p_p(rz, rz2, rz3)) } +inst_sve_cmpeq_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPEQ, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_cmpeq_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpeq_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_cmpne_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPNE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_cmpne_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpne_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_cmpge_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPGE, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_cmpge_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpge_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_cmpgt_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPGT, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_cmpgt_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmpgt_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_cmphi_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPHI, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_cmphi_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmphi_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_cmphs_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_CMPHS, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_cmphs_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_cmphs_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_dup_z_z_r :: #force_inline proc "contextless" (rz: u8, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_DUP_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_reg(src), {}, {}}} } +emit_sve_dup_z_z_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register) { append(instructions, inst_sve_dup_z_z_r(rz, src)) } +inst_sve_rev_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_REV_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +emit_sve_rev_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_rev_z_z_z(rz, rz2)) } +inst_sve_rev_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_REV_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), {}, {}}} } +emit_sve_rev_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_rev_p_p_p(rz, rz2)) } +inst_sve_tbl_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TBL, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_tbl_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_tbl_z_z_z(rz, rz2, rz3)) } +inst_sve_zip1_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP1_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_zip1_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip1_z_z_z_z(rz, rz2, rz3)) } +inst_sve_zip2_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP2_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_zip2_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip2_z_z_z_z(rz, rz2, rz3)) } +inst_sve_uzp1_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP1_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_uzp1_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp1_z_z_z_z(rz, rz2, rz3)) } +inst_sve_uzp2_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP2_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_uzp2_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp2_z_z_z_z(rz, rz2, rz3)) } +inst_sve_trn1_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN1_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_trn1_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn1_z_z_z_z(rz, rz2, rz3)) } +inst_sve_trn2_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN2_Z, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_trn2_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn2_z_z_z_z(rz, rz2, rz3)) } +inst_sve_zip1_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP1_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_zip1_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip1_p_p_p_p(rz, rz2, rz3)) } +inst_sve_zip2_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ZIP2_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_zip2_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_zip2_p_p_p_p(rz, rz2, rz3)) } +inst_sve_uzp1_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP1_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_uzp1_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp1_p_p_p_p(rz, rz2, rz3)) } +inst_sve_uzp2_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_UZP2_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_uzp2_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_uzp2_p_p_p_p(rz, rz2, rz3)) } +inst_sve_trn1_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN1_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_trn1_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn1_p_p_p_p(rz, rz2, rz3)) } +inst_sve_trn2_p_p_p_p :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TRN2_P, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_reg(Register(REG_P | (u16(rz3) & 0xF))), {}}} } +emit_sve_trn2_p_p_p_p :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_trn2_p_p_p_p(rz, rz2, rz3)) } +inst_sve_ld1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1b_z_p_m(rz, rz2, mem)) } +inst_sve_ld1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1h_z_p_m(rz, rz2, mem)) } +inst_sve_ld1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1w_z_p_m(rz, rz2, mem)) } +inst_sve_ld1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1d_z_p_m(rz, rz2, mem)) } +inst_sve_ld1sb_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SB, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1sb_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sb_z_p_m(rz, rz2, mem)) } +inst_sve_ld1sh_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SH, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1sh_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sh_z_p_m(rz, rz2, mem)) } +inst_sve_ld1sw_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SW, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1sw_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sw_z_p_m(rz, rz2, mem)) } +inst_sve_st1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_st1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1b_z_p_m(rz, rz2, mem)) } +inst_sve_st1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_st1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1h_z_p_m(rz, rz2, mem)) } +inst_sve_st1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_st1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1w_z_p_m(rz, rz2, mem)) } +inst_sve_st1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_st1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1d_z_p_m(rz, rz2, mem)) } +inst_sve_ldr_z_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDR_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } +emit_sve_ldr_z_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_ldr_z_z_m(rz, mem)) } +inst_sve_str_z_z_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STR_Z, operand_count = 2, length = 4, ops = {op_z_b(rz), op_mem(mem), {}, {}}} } +emit_sve_str_z_z_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_str_z_z_m(rz, mem)) } +inst_sve_ldr_p_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDR_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +emit_sve_ldr_p_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_ldr_p_p_m(rz, mem)) } +inst_sve_str_p_p_m :: #force_inline proc "contextless" (rz: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STR_P, operand_count = 2, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_mem(mem), {}, {}}} } +emit_sve_str_p_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, mem: Memory) { append(instructions, inst_sve_str_p_p_m(rz, mem)) } +inst_sve_ldff1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ldff1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1b_z_p_m(rz, rz2, mem)) } +inst_sve_ldff1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ldff1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1h_z_p_m(rz, rz2, mem)) } +inst_sve_ldff1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ldff1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1w_z_p_m(rz, rz2, mem)) } +inst_sve_ldff1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDFF1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ldff1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldff1d_z_p_m(rz, rz2, mem)) } +inst_sve_whilege_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEGE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_sve_whilege_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilege_p_r_r(rz, src, src2)) } +inst_sve_whilegt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEGT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_sve_whilegt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilegt_p_r_r(rz, src, src2)) } +inst_sve_whilele_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELE, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_sve_whilele_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilele_p_r_r(rz, src, src2)) } +inst_sve_whilelt_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELT, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_sve_whilelt_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilelt_p_r_r(rz, src, src2)) } +inst_sve_whilehi_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEHI, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_sve_whilehi_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilehi_p_r_r(rz, src, src2)) } +inst_sve_whilehs_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILEHS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_sve_whilehs_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilehs_p_r_r(rz, src, src2)) } +inst_sve_whilelo_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELO, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_sve_whilelo_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilelo_p_r_r(rz, src, src2)) } +inst_sve_whilels_p_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_WHILELS, operand_count = 3, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(src), op_reg(src2), {}}} } +emit_sve_whilels_p_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_whilels_p_r_r(rz, src, src2)) } +inst_sve_sqrdmlah_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQRDMLAH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_sqrdmlah_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqrdmlah_z_z_z(rz, rz2, rz3)) } +inst_sve_sqrdmlsh_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SQRDMLSH, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_sqrdmlsh_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sqrdmlsh_z_z_z(rz, rz2, rz3)) } +inst_sve_adclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_sve_adclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_adclb_z_z_z(rz, rz2, rz3)) } +inst_sve_adclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_ADCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_sve_adclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_adclt_z_z_z(rz, rz2, rz3)) } +inst_sve_sbclb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SBCLB, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_sve_sbclb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sbclb_z_z_z(rz, rz2, rz3)) } +inst_sve_sbclt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_SBCLT, operand_count = 3, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_sve_sbclt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_sbclt_z_z_z(rz, rz2, rz3)) } +inst_sve_tbl2_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TBL2, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_tbl2_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_tbl2_z_z_z(rz, rz2, rz3)) } +inst_sve_tbx_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_TBX, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_tbx_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_tbx_z_z_z(rz, rz2, rz3)) } +inst_sve_aese_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESE, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +emit_sve_aese_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_aese_z_z(rz, rz2)) } +inst_sve_aesd_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESD, operand_count = 2, length = 4, ops = {op_z_b(rz), op_z_b(rz2), {}, {}}} } +emit_sve_aesd_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sve_aesd_z_z(rz, rz2)) } +inst_sve_aesmc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } +emit_sve_aesmc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_aesmc_z(rz)) } +inst_sve_aesimc_z :: #force_inline proc "contextless" (rz: u8) -> Instruction { return Instruction{mnemonic = .SVE_AESIMC, operand_count = 1, length = 4, ops = {op_z_b(rz), {}, {}, {}}} } +emit_sve_aesimc_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8) { append(instructions, inst_sve_aesimc_z(rz)) } +inst_sve_match_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_MATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_match_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_match_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_nmatch_p_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NMATCH, operand_count = 4, length = 4, ops = {op_reg(Register(REG_P | (u16(rz) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_nmatch_p_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nmatch_p_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_histcnt_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_HISTCNT, operand_count = 4, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), op_z_s(rz4)}} } +emit_sve_histcnt_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_histcnt_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_histseg_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_HISTSEG, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_histseg_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_histseg_z_z_z(rz, rz2, rz3)) } +inst_sme_smstart_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SME_SMSTART) } +emit_sme_smstart_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sme_smstart_none()) } +inst_sme_smstop_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SME_SMSTOP) } +emit_sme_smstop_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sme_smstop_none()) } +inst_sme_rdsvl_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.SME_RDSVL, dst, imm) } +emit_sme_rdsvl_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_sme_rdsvl_r_i(dst, imm)) } +inst_sme_zero_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SME_ZERO, operand_count = 1, length = 4, ops = {op_imm(imm, 4), {}, {}, {}}} } +emit_sme_zero_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_sme_zero_i(imm)) } +inst_sme_fmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_FMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_sme_fmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_fmopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sme_fmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_FMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3)}} } +emit_sme_fmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_fmops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sme_bfmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_BFMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_sme_bfmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_bfmopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sme_bfmops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_BFMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3)}} } +emit_sme_bfmops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_bfmops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sme_smopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_SMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_sme_smopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_smopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sme_smops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_SMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_sme_smops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_smops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sme_umopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_UMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_sme_umopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_umopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sme_umops_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_UMOPS, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_sme_umops_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_umops_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sme_usmopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_USMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_sme_usmopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_usmopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sme_sumopa_i_p_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME_SUMOPA, operand_count = 4, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3)}} } +emit_sme_sumopa_i_p_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme_sumopa_i_p_p_z(imm, rz1, rz2, rz3)) } +inst_sme_ldr_za_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LDR_ZA, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +emit_sme_ldr_za_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_sme_ldr_za_i_m(imm, mem)) } +inst_sme_str_za_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_STR_ZA, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +emit_sme_str_za_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_sme_str_za_i_m(imm, mem)) } +inst_sve_fmla_idx_h_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLA_IDX_H, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } +emit_sve_fmla_idx_h_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmla_idx_h_z_z_z_i(rz, rz2, rz3, imm)) } +inst_sve_fmla_idx_s_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLA_IDX_S, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_imm(imm, 1)}} } +emit_sve_fmla_idx_s_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmla_idx_s_z_z_z_i(rz, rz2, rz3, imm)) } +inst_sve_fmla_idx_d_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLA_IDX_D, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_imm(imm, 1)}} } +emit_sve_fmla_idx_d_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmla_idx_d_z_z_z_i(rz, rz2, rz3, imm)) } +inst_sve_fmls_idx_h_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLS_IDX_H, operand_count = 4, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), op_imm(imm, 1)}} } +emit_sve_fmls_idx_h_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmls_idx_h_z_z_z_i(rz, rz2, rz3, imm)) } +inst_sve_fmls_idx_s_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLS_IDX_S, operand_count = 4, length = 4, ops = {op_z_s(rz), op_z_s(rz2), op_z_s(rz3), op_imm(imm, 1)}} } +emit_sve_fmls_idx_s_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmls_idx_s_z_z_z_i(rz, rz2, rz3, imm)) } +inst_sve_fmls_idx_d_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_FMLS_IDX_D, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_imm(imm, 1)}} } +emit_sve_fmls_idx_d_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_fmls_idx_d_z_z_z_i(rz, rz2, rz3, imm)) } +inst_sve_ld1b_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1B_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1b_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1b_gather_s_z_p_m(rz, rz2, mem)) } +inst_sve_ld1b_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1B_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1b_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1b_gather_d_z_p_m(rz, rz2, mem)) } +inst_sve_ld1h_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1H_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1h_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1h_gather_s_z_p_m(rz, rz2, mem)) } +inst_sve_ld1h_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1H_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1h_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1h_gather_d_z_p_m(rz, rz2, mem)) } +inst_sve_ld1w_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1W_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1w_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1w_gather_s_z_p_m(rz, rz2, mem)) } +inst_sve_ld1w_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1W_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1w_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1w_gather_d_z_p_m(rz, rz2, mem)) } +inst_sve_ld1d_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1D_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1d_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1d_gather_d_z_p_m(rz, rz2, mem)) } +inst_sve_ld1sb_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SB_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1sb_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sb_gather_s_z_p_m(rz, rz2, mem)) } +inst_sve_ld1sb_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SB_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1sb_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sb_gather_d_z_p_m(rz, rz2, mem)) } +inst_sve_ld1sh_gather_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SH_GATHER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1sh_gather_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sh_gather_s_z_p_m(rz, rz2, mem)) } +inst_sve_ld1sh_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SH_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1sh_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sh_gather_d_z_p_m(rz, rz2, mem)) } +inst_sve_ld1sw_gather_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LD1SW_GATHER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ld1sw_gather_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ld1sw_gather_d_z_p_m(rz, rz2, mem)) } +inst_sve_st1b_scatter_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1B_SCATTER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_st1b_scatter_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1b_scatter_s_z_p_m(rz, rz2, mem)) } +inst_sve_st1b_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1B_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_st1b_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1b_scatter_d_z_p_m(rz, rz2, mem)) } +inst_sve_st1h_scatter_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1H_SCATTER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_st1h_scatter_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1h_scatter_s_z_p_m(rz, rz2, mem)) } +inst_sve_st1h_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1H_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_st1h_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1h_scatter_d_z_p_m(rz, rz2, mem)) } +inst_sve_st1w_scatter_s_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1W_SCATTER_S, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_st1w_scatter_s_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1w_scatter_s_z_p_m(rz, rz2, mem)) } +inst_sve_st1w_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1W_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_st1w_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1w_scatter_d_z_p_m(rz, rz2, mem)) } +inst_sve_st1d_scatter_d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_ST1D_SCATTER_D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_st1d_scatter_d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_st1d_scatter_d_z_p_m(rz, rz2, mem)) } +inst_sme_ld1b_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1B_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sme_ld1b_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1b_tile_i_p_m(imm, rz1, mem)) } +inst_sme_ld1h_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1H_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sme_ld1h_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1h_tile_i_p_m(imm, rz1, mem)) } +inst_sme_ld1w_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1W_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sme_ld1w_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1w_tile_i_p_m(imm, rz1, mem)) } +inst_sme_ld1d_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1D_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sme_ld1d_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1d_tile_i_p_m(imm, rz1, mem)) } +inst_sme_ld1q_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_LD1Q_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sme_ld1q_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_ld1q_tile_i_p_m(imm, rz1, mem)) } +inst_sme_st1b_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1B_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sme_st1b_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1b_tile_i_p_m(imm, rz1, mem)) } +inst_sme_st1h_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1H_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sme_st1h_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1h_tile_i_p_m(imm, rz1, mem)) } +inst_sme_st1w_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1W_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sme_st1w_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1w_tile_i_p_m(imm, rz1, mem)) } +inst_sme_st1d_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1D_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sme_st1d_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1d_tile_i_p_m(imm, rz1, mem)) } +inst_sme_st1q_tile_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME_ST1Q_TILE, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sme_st1q_tile_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sme_st1q_tile_i_p_m(imm, rz1, mem)) } +inst_sme_mova_z_from_tile_z_p_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SME_MOVA_Z_FROM_TILE, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_imm(imm, 4), {}}} } +emit_sme_mova_z_from_tile_z_p_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, imm: i64) { append(instructions, inst_sme_mova_z_from_tile_z_p_i(rz, rz2, imm)) } +inst_sme_mova_tile_from_z_i_p_z :: #force_inline proc "contextless" (imm: i64, rz1: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SME_MOVA_TILE_FROM_Z, operand_count = 3, length = 4, ops = {op_imm(imm, 4), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_z_b(rz2), {}}} } +emit_sme_mova_tile_from_z_i_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, rz2: u8) { append(instructions, inst_sme_mova_tile_from_z_i_p_z(imm, rz1, rz2)) } +inst_fcmla_4h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_4H, operand_count = 4, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), op_imm(imm, 1)}} } +emit_fcmla_4h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_4h_r_r_r_i(dst, src, src2, imm)) } +inst_fcmla_8h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_8H, operand_count = 4, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), op_imm(imm, 1)}} } +emit_fcmla_8h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_8h_r_r_r_i(dst, src, src2, imm)) } +inst_fcmla_4s_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_4S, operand_count = 4, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), op_imm(imm, 1)}} } +emit_fcmla_4s_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_4s_r_r_r_i(dst, src, src2, imm)) } +inst_fcmla_2d_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCMLA_2D, operand_count = 4, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), op_imm(imm, 1)}} } +emit_fcmla_2d_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcmla_2d_r_r_r_i(dst, src, src2, imm)) } +inst_fcadd_4h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_4H, operand_count = 4, length = 4, ops = {op_v_4h(u8(reg_hw(dst))), op_v_4h(u8(reg_hw(src))), op_v_4h(u8(reg_hw(src2))), op_imm(imm, 1)}} } +emit_fcadd_4h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_4h_r_r_r_i(dst, src, src2, imm)) } +inst_fcadd_8h_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_8H, operand_count = 4, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), op_imm(imm, 1)}} } +emit_fcadd_8h_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_8h_r_r_r_i(dst, src, src2, imm)) } +inst_fcadd_4s_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_4S, operand_count = 4, length = 4, ops = {op_v_4s(u8(reg_hw(dst))), op_v_4s(u8(reg_hw(src))), op_v_4s(u8(reg_hw(src2))), op_imm(imm, 1)}} } +emit_fcadd_4s_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_4s_r_r_r_i(dst, src, src2, imm)) } +inst_fcadd_2d_r_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .FCADD_2D, operand_count = 4, length = 4, ops = {op_v_2d(u8(reg_hw(dst))), op_v_2d(u8(reg_hw(src))), op_v_2d(u8(reg_hw(src2))), op_imm(imm, 1)}} } +emit_fcadd_2d_r_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, imm: i64) { append(instructions, inst_fcadd_2d_r_r_r_i(dst, src, src2, imm)) } +inst_sve_prfb_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFB, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sve_prfb_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfb_i_p_m(imm, rz1, mem)) } +inst_sve_prfh_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFH, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sve_prfh_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfh_i_p_m(imm, rz1, mem)) } +inst_sve_prfw_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFW, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sve_prfw_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfw_i_p_m(imm, rz1, mem)) } +inst_sve_prfd_i_p_m :: #force_inline proc "contextless" (imm: i64, rz1: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_PRFD, operand_count = 3, length = 4, ops = {op_imm(imm, 1), op_reg(Register(REG_P | (u16(rz1) & 0xF))), op_mem(mem), {}}} } +emit_sve_prfd_i_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, rz1: u8, mem: Memory) { append(instructions, inst_sve_prfd_i_p_m(imm, rz1, mem)) } +inst_sve_ldnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ldnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1b_z_p_m(rz, rz2, mem)) } +inst_sve_ldnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ldnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1h_z_p_m(rz, rz2, mem)) } +inst_sve_ldnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ldnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1w_z_p_m(rz, rz2, mem)) } +inst_sve_ldnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_LDNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_ldnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_ldnt1d_z_p_m(rz, rz2, mem)) } +inst_sve_stnt1b_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1B, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_stnt1b_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1b_z_p_m(rz, rz2, mem)) } +inst_sve_stnt1h_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1H, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_stnt1h_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1h_z_p_m(rz, rz2, mem)) } +inst_sve_stnt1w_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1W, operand_count = 3, length = 4, ops = {op_z_s(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_stnt1w_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1w_z_p_m(rz, rz2, mem)) } +inst_sve_stnt1d_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SVE_STNT1D, operand_count = 3, length = 4, ops = {op_z_d(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sve_stnt1d_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sve_stnt1d_z_p_m(rz, rz2, mem)) } +inst_sve_ext_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_EXT, operand_count = 4, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), op_imm(imm, 1)}} } +emit_sve_ext_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sve_ext_z_z_z_i(rz, rz2, rz3, imm)) } +inst_sve_splice_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_SPLICE, operand_count = 4, length = 4, ops = {op_z_b(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_b(rz3), op_z_b(rz4)}} } +emit_sve_splice_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_splice_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_index_ii_z_i_i :: #force_inline proc "contextless" (rz: u8, imm: i64, imm2: i64) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_II, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_imm(imm2, 1), {}}} } +emit_sve_index_ii_z_i_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, imm2: i64) { append(instructions, inst_sve_index_ii_z_i_i(rz, imm, imm2)) } +inst_sve_index_ir_z_i_r :: #force_inline proc "contextless" (rz: u8, imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_IR, operand_count = 3, length = 4, ops = {op_z_b(rz), op_imm(imm, 1), op_reg(src), {}}} } +emit_sve_index_ir_z_i_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, imm: i64, src: Register) { append(instructions, inst_sve_index_ir_z_i_r(rz, imm, src)) } +inst_sve_index_ri_z_r_i :: #force_inline proc "contextless" (rz: u8, src: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_RI, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_imm(imm, 1), {}}} } +emit_sve_index_ri_z_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, imm: i64) { append(instructions, inst_sve_index_ri_z_r_i(rz, src, imm)) } +inst_sve_index_rr_z_r_r :: #force_inline proc "contextless" (rz: u8, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SVE_INDEX_RR, operand_count = 3, length = 4, ops = {op_z_b(rz), op_reg(src), op_reg(src2), {}}} } +emit_sve_index_rr_z_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, src: Register, src2: Register) { append(instructions, inst_sve_index_rr_z_r_r(rz, src, src2)) } +inst_sve_bsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_sve_bsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bsl_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_sve_bsl1n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BSL1N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_sve_bsl1n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bsl1n_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_sve_bsl2n_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BSL2N, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_sve_bsl2n_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bsl2n_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_sve_nbsl_z_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_NBSL, operand_count = 4, length = 4, ops = {op_z_d(rz), op_z_d(rz2), op_z_d(rz3), op_z_d(rz4)}} } +emit_sve_nbsl_z_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_nbsl_z_z_z_z(rz, rz2, rz3, rz4)) } +inst_sve_pmul_vec_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PMUL_VEC, operand_count = 3, length = 4, ops = {op_z_b(rz), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sve_pmul_vec_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pmul_vec_z_z_z(rz, rz2, rz3)) } +inst_sve_pmullb_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PMULLB, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_sve_pmullb_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pmullb_z_z_z(rz, rz2, rz3)) } +inst_sve_pmullt_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_PMULLT, operand_count = 3, length = 4, ops = {op_z_d(rz), op_z_s(rz2), op_z_s(rz3), {}}} } +emit_sve_pmullt_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_pmullt_z_z_z(rz, rz2, rz3)) } +inst_sve_bfcvt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFCVT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +emit_sve_bfcvt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfcvt_z_p_z(rz, rz2, rz3)) } +inst_sve_bfcvtnt_z_p_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFCVTNT, operand_count = 3, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_s(rz3), {}}} } +emit_sve_bfcvtnt_z_p_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfcvtnt_z_p_z(rz, rz2, rz3)) } +inst_ldraa_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA, dst, mem) } +emit_ldraa_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_r_m(dst, mem)) } +inst_ldrab_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB, dst, mem) } +emit_ldrab_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrab_r_m(dst, mem)) } +inst_ldraa_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAA_PRE, dst, mem) } +emit_ldraa_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldraa_pre_r_m(dst, mem)) } +inst_ldrab_pre_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDRAB_PRE, dst, mem) } +emit_ldrab_pre_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldrab_pre_r_m(dst, mem)) } +inst_tstart_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TSTART, dst) } +emit_tstart_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tstart_r(dst)) } +inst_tcommit_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TCOMMIT) } +emit_tcommit_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tcommit_none()) } +inst_tcancel_i :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .TCANCEL, operand_count = 1, length = 4, ops = {op_imm(imm, 2), {}, {}, {}}} } +emit_tcancel_i :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_tcancel_i(imm)) } +inst_ttest_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TTEST, dst) } +emit_ttest_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ttest_r(dst)) } +inst_wfet_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFET, dst) } +emit_wfet_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfet_r(dst)) } +inst_wfit_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.WFIT, dst) } +emit_wfit_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_wfit_r(dst)) } +inst_bc_cond_c_l :: #force_inline proc "contextless" (cond: Cond, label: u32) -> Instruction { return Instruction{mnemonic = .BC_COND, operand_count = 2, length = 4, ops = {op_cond(cond), op_label(label, 4), {}, {}}} } +emit_bc_cond_c_l :: #force_inline proc(instructions: ^[dynamic]Instruction, cond: Cond, label: u32) { append(instructions, inst_bc_cond_c_l(cond, label)) } +inst_uxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTB, dst, src) } +emit_uxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtb_r_r(dst, src)) } +inst_uxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTH, dst, src) } +emit_uxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxth_r_r(dst, src)) } +inst_uxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.UXTW, dst, src) } +emit_uxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uxtw_r_r(dst, src)) } +inst_sxtb_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTB, dst, src) } +emit_sxtb_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtb_r_r(dst, src)) } +inst_sxth_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTH, dst, src) } +emit_sxth_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxth_r_r(dst, src)) } +inst_sxtw_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.SXTW, dst, src) } +emit_sxtw_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sxtw_r_r(dst, src)) } +inst_adc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADC, dst, src, src2) } +emit_adc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adc_r_r_r(dst, src, src2)) } +inst_adcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.ADCS, dst, src, src2) } +emit_adcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_adcs_r_r_r(dst, src, src2)) } +inst_sbc_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBC, dst, src, src2) } +emit_sbc_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbc_r_r_r(dst, src, src2)) } +inst_sbcs_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SBCS, dst, src, src2) } +emit_sbcs_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sbcs_r_r_r(dst, src, src2)) } +inst_ngc_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGC, dst, src) } +emit_ngc_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngc_r_r(dst, src)) } +inst_ngcs_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.NGCS, dst, src) } +emit_ngcs_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_ngcs_r_r(dst, src)) } +inst_ldapur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPUR, dst, mem) } +emit_ldapur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapur_r_m(dst, mem)) } +inst_stlur_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLUR, dst, mem) } +emit_stlur_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlur_r_m(dst, mem)) } +inst_ldapurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURB, dst, mem) } +emit_ldapurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurb_r_m(dst, mem)) } +inst_stlurb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURB, dst, mem) } +emit_stlurb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurb_r_m(dst, mem)) } +inst_ldapurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURH, dst, mem) } +emit_ldapurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapurh_r_m(dst, mem)) } +inst_stlurh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.STLURH, dst, mem) } +emit_stlurh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_stlurh_r_m(dst, mem)) } +inst_ldapursb_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSB, dst, mem) } +emit_ldapursb_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursb_r_m(dst, mem)) } +inst_ldapursh_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSH, dst, mem) } +emit_ldapursh_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursh_r_m(dst, mem)) } +inst_ldapursw_r_m :: #force_inline proc "contextless" (dst: Register, mem: Memory) -> Instruction { return inst_ldst(.LDAPURSW, dst, mem) } +emit_ldapursw_r_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, mem: Memory) { append(instructions, inst_ldapursw_r_m(dst, mem)) } +inst_sve_bfadd_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFADD, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_bfadd_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfadd_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_bfsub_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFSUB, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_bfsub_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfsub_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_bfmul_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMUL, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_bfmul_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmul_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_bfmla_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMLA, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_bfmla_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmla_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_bfmls_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMLS, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_bfmls_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmls_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.SB) } +emit_sb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_sb_none()) } +inst_csdb_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.CSDB) } +emit_csdb_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_csdb_none()) } +inst_dgh_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.DGH) } +emit_dgh_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_dgh_none()) } +inst_psb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.PSB_CSYNC) } +emit_psb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_psb_csync_none()) } +inst_tsb_csync_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TSB_CSYNC) } +emit_tsb_csync_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tsb_csync_none()) } +inst_bti_j_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_J) } +emit_bti_j_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_j_none()) } +inst_bti_c_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_C) } +emit_bti_c_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_c_none()) } +inst_bti_jc_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.BTI_JC) } +emit_bti_jc_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_bti_jc_none()) } +inst_mov_v_alias_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .MOV_V_ALIAS, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_mov_v_alias_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_v_alias_r_r(dst, src)) } +inst_not_v_alias_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .NOT_V_ALIAS, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), {}, {}}} } +emit_not_v_alias_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_not_v_alias_r_r(dst, src)) } +inst_lsl_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSL_IMM, dst, src, imm) } +emit_lsl_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsl_imm_r_r_i(dst, src, imm)) } +inst_lsr_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.LSR_IMM, dst, src, imm) } +emit_lsr_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_lsr_imm_r_r_i(dst, src, imm)) } +inst_asr_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ASR_IMM, dst, src, imm) } +emit_asr_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_asr_imm_r_r_i(dst, src, imm)) } +inst_ror_imm_r_r_i :: #force_inline proc "contextless" (dst: Register, src: Register, imm: i64) -> Instruction { return inst_r_r_i(.ROR_IMM, dst, src, imm) } +emit_ror_imm_r_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, imm: i64) { append(instructions, inst_ror_imm_r_r_i(dst, src, imm)) } +inst_sve_bfadd_unpred_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFADD_UNPRED, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_sve_bfadd_unpred_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfadd_unpred_z_z_z(rz, rz2, rz3)) } +inst_sve_bfsub_unpred_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFSUB_UNPRED, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_sve_bfsub_unpred_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfsub_unpred_z_z_z(rz, rz2, rz3)) } +inst_sve_bfmul_unpred_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMUL_UNPRED, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_sve_bfmul_unpred_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfmul_unpred_z_z_z(rz, rz2, rz3)) } +inst_sve_bfclamp_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFCLAMP, operand_count = 3, length = 4, ops = {op_z_h(rz), op_z_h(rz2), op_z_h(rz3), {}}} } +emit_sve_bfclamp_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sve_bfclamp_z_z_z(rz, rz2, rz3)) } +inst_sve_bfmaxnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMAXNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_bfmaxnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfmaxnm_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sve_bfminnm_z_p_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, rz4: u8) -> Instruction { return Instruction{mnemonic = .SVE_BFMINNM, operand_count = 4, length = 4, ops = {op_z_h(rz), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_z_h(rz3), op_z_h(rz4)}} } +emit_sve_bfminnm_z_p_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, rz4: u8) { append(instructions, inst_sve_bfminnm_z_p_z_z(rz, rz2, rz3, rz4)) } +inst_sme2_luti2_b_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SME2_LUTI2_B, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } +emit_sme2_luti2_b_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sme2_luti2_b_z_z_z_i(rz, rz2, rz3, imm)) } +inst_sme2_luti4_b_z_z_z_i :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8, imm: i64) -> Instruction { return Instruction{mnemonic = .SME2_LUTI4_B, operand_count = 4, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), op_z_b(rz3), op_imm(imm, 1)}} } +emit_sme2_luti4_b_z_z_z_i :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8, imm: i64) { append(instructions, inst_sme2_luti4_b_z_z_z_i(rz, rz2, rz3, imm)) } +inst_sme2_ld1b_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1B_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_ld1b_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1b_x2_z_p_m(rz, rz2, mem)) } +inst_sme2_ld1h_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1H_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_ld1h_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1h_x2_z_p_m(rz, rz2, mem)) } +inst_sme2_ld1w_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1W_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_ld1w_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1w_x2_z_p_m(rz, rz2, mem)) } +inst_sme2_ld1d_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1D_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_ld1d_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1d_x2_z_p_m(rz, rz2, mem)) } +inst_sme2_ld1b_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1B_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_ld1b_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1b_x4_z_p_m(rz, rz2, mem)) } +inst_sme2_ld1h_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1H_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_ld1h_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1h_x4_z_p_m(rz, rz2, mem)) } +inst_sme2_ld1w_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1W_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_ld1w_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1w_x4_z_p_m(rz, rz2, mem)) } +inst_sme2_ld1d_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_LD1D_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_ld1d_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_ld1d_x4_z_p_m(rz, rz2, mem)) } +inst_sme2_st1b_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1B_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_st1b_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1b_x2_z_p_m(rz, rz2, mem)) } +inst_sme2_st1h_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1H_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_st1h_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1h_x2_z_p_m(rz, rz2, mem)) } +inst_sme2_st1w_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1W_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_st1w_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1w_x2_z_p_m(rz, rz2, mem)) } +inst_sme2_st1d_x2_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1D_X2, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_st1d_x2_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1d_x2_z_p_m(rz, rz2, mem)) } +inst_sme2_st1b_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1B_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_st1b_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1b_x4_z_p_m(rz, rz2, mem)) } +inst_sme2_st1h_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1H_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_st1h_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1h_x4_z_p_m(rz, rz2, mem)) } +inst_sme2_st1w_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1W_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_st1w_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1w_x4_z_p_m(rz, rz2, mem)) } +inst_sme2_st1d_x4_z_p_m :: #force_inline proc "contextless" (rz: u8, rz2: u8, mem: Memory) -> Instruction { return Instruction{mnemonic = .SME2_ST1D_X4, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_P | (u16(rz2) & 0xF))), op_mem(mem), {}}} } +emit_sme2_st1d_x4_z_p_m :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, mem: Memory) { append(instructions, inst_sme2_st1d_x4_z_p_m(rz, rz2, mem)) } +inst_sme2_zip_3_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME2_ZIP_3, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sme2_zip_3_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme2_zip_3_z_z_z(rz, rz2, rz3)) } +inst_sme2_zip_4_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SME2_ZIP_4, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } +emit_sme2_zip_4_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sme2_zip_4_z_z(rz, rz2)) } +inst_sme2_uzp_3_z_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8, rz3: u8) -> Instruction { return Instruction{mnemonic = .SME2_UZP_3, operand_count = 3, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_z_b(rz2), op_z_b(rz3), {}}} } +emit_sme2_uzp_3_z_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8, rz3: u8) { append(instructions, inst_sme2_uzp_3_z_z_z(rz, rz2, rz3)) } +inst_sme2_uzp_4_z_z :: #force_inline proc "contextless" (rz: u8, rz2: u8) -> Instruction { return Instruction{mnemonic = .SME2_UZP_4, operand_count = 2, length = 4, ops = {op_reg(Register(REG_Z | (u16(rz) & 0x1F))), op_reg(Register(REG_Z | (u16(rz2) & 0x1F))), {}, {}}} } +emit_sme2_uzp_4_z_z :: #force_inline proc(instructions: ^[dynamic]Instruction, rz: u8, rz2: u8) { append(instructions, inst_sme2_uzp_4_z_z(rz, rz2)) } +inst_tlbi_rpalos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPALOS, dst) } +emit_tlbi_rpalos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpalos_r(dst)) } +inst_tlbi_rpaos_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_RPAOS, dst) } +emit_tlbi_rpaos_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_rpaos_r(dst)) } +inst_at_s1e1a_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1A, dst) } +emit_at_s1e1a_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1a_r(dst)) } +inst_dc_cipapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIPAPA, dst) } +emit_dc_cipapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cipapa_r(dst)) } +inst_dc_cigdpapa_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIGDPAPA, dst) } +emit_dc_cigdpapa_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cigdpapa_r(dst)) } +inst_tlbi_paall_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALL) } +emit_tlbi_paall_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paall_none()) } +inst_tlbi_paallos_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_PAALLOS) } +emit_tlbi_paallos_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_paallos_none()) } +inst_amx_ldx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDX, dst) } +emit_amx_ldx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldx_r(dst)) } +inst_amx_ldy_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDY, dst) } +emit_amx_ldy_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldy_r(dst)) } +inst_amx_stx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STX, dst) } +emit_amx_stx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stx_r(dst)) } +inst_amx_sty_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STY, dst) } +emit_amx_sty_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_sty_r(dst)) } +inst_amx_ldz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZ, dst) } +emit_amx_ldz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldz_r(dst)) } +inst_amx_stz_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZ, dst) } +emit_amx_stz_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stz_r(dst)) } +inst_amx_ldzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_LDZI, dst) } +emit_amx_ldzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_ldzi_r(dst)) } +inst_amx_stzi_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_STZI, dst) } +emit_amx_stzi_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_stzi_r(dst)) } +inst_amx_extrx_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRX, dst) } +emit_amx_extrx_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extrx_r(dst)) } +inst_amx_extry_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_EXTRY, dst) } +emit_amx_extry_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_extry_r(dst)) } +inst_amx_fma64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA64, dst) } +emit_amx_fma64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma64_r(dst)) } +inst_amx_fms64_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS64, dst) } +emit_amx_fms64_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms64_r(dst)) } +inst_amx_fma32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA32, dst) } +emit_amx_fma32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma32_r(dst)) } +inst_amx_fms32_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS32, dst) } +emit_amx_fms32_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms32_r(dst)) } +inst_amx_mac16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MAC16, dst) } +emit_amx_mac16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_mac16_r(dst)) } +inst_amx_fma16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMA16, dst) } +emit_amx_fma16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fma16_r(dst)) } +inst_amx_fms16_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_FMS16, dst) } +emit_amx_fms16_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_fms16_r(dst)) } +inst_amx_set_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_SET) } +emit_amx_set_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_set_none()) } +inst_amx_clr_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.AMX_CLR) } +emit_amx_clr_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_amx_clr_none()) } +inst_amx_vecint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECINT, dst) } +emit_amx_vecint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecint_r(dst)) } +inst_amx_vecfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_VECFP, dst) } +emit_amx_vecfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_vecfp_r(dst)) } +inst_amx_matint_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATINT, dst) } +emit_amx_matint_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matint_r(dst)) } +inst_amx_matfp_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_MATFP, dst) } +emit_amx_matfp_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_matfp_r(dst)) } +inst_amx_genlut_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AMX_GENLUT, dst) } +emit_amx_genlut_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_amx_genlut_r(dst)) } +inst_cpyp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYP, dst, src, src2) } +emit_cpyp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyp_r_r_r(dst, src, src2)) } +inst_cpym_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYM, dst, src, src2) } +emit_cpym_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpym_r_r_r(dst, src, src2)) } +inst_cpye_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYE, dst, src, src2) } +emit_cpye_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpye_r_r_r(dst, src, src2)) } +inst_cpyfp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFP, dst, src, src2) } +emit_cpyfp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfp_r_r_r(dst, src, src2)) } +inst_cpyfm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFM, dst, src, src2) } +emit_cpyfm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfm_r_r_r(dst, src, src2)) } +inst_cpyfe_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.CPYFE, dst, src, src2) } +emit_cpyfe_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_cpyfe_r_r_r(dst, src, src2)) } +inst_setp_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETP, dst, src, src2) } +emit_setp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setp_r_r_r(dst, src, src2)) } +inst_setm_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETM, dst, src, src2) } +emit_setm_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_setm_r_r_r(dst, src, src2)) } +inst_sete_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return inst_r_r_r(.SETE, dst, src, src2) } +emit_sete_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_sete_r_r_r(dst, src, src2)) } +inst_dc_ivac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_IVAC, dst) } +emit_dc_ivac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_ivac_r(dst)) } +inst_dc_isw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ISW, dst) } +emit_dc_isw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_isw_r(dst)) } +inst_dc_csw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CSW, dst) } +emit_dc_csw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_csw_r(dst)) } +inst_dc_cisw_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CISW, dst) } +emit_dc_cisw_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cisw_r(dst)) } +inst_dc_zva_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_ZVA, dst) } +emit_dc_zva_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_zva_r(dst)) } +inst_dc_cvac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAC, dst) } +emit_dc_cvac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvac_r(dst)) } +inst_dc_cvau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CVAU, dst) } +emit_dc_cvau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_cvau_r(dst)) } +inst_dc_civac_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.DC_CIVAC, dst) } +emit_dc_civac_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_dc_civac_r(dst)) } +inst_ic_ialluis_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLUIS) } +emit_ic_ialluis_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_ialluis_none()) } +inst_ic_iallu_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.IC_IALLU) } +emit_ic_iallu_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_ic_iallu_none()) } +inst_ic_ivau_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.IC_IVAU, dst) } +emit_ic_ivau_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_ic_ivau_r(dst)) } +inst_at_s1e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1R, dst) } +emit_at_s1e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1r_r(dst)) } +inst_at_s1e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E1W, dst) } +emit_at_s1e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e1w_r(dst)) } +inst_at_s1e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0R, dst) } +emit_at_s1e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0r_r(dst)) } +inst_at_s1e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E0W, dst) } +emit_at_s1e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e0w_r(dst)) } +inst_at_s1e2r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2R, dst) } +emit_at_s1e2r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2r_r(dst)) } +inst_at_s1e2w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E2W, dst) } +emit_at_s1e2w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e2w_r(dst)) } +inst_at_s1e3r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3R, dst) } +emit_at_s1e3r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3r_r(dst)) } +inst_at_s1e3w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S1E3W, dst) } +emit_at_s1e3w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s1e3w_r(dst)) } +inst_at_s12e1r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1R, dst) } +emit_at_s12e1r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1r_r(dst)) } +inst_at_s12e1w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E1W, dst) } +emit_at_s12e1w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e1w_r(dst)) } +inst_at_s12e0r_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0R, dst) } +emit_at_s12e0r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0r_r(dst)) } +inst_at_s12e0w_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.AT_S12E0W, dst) } +emit_at_s12e0w_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_at_s12e0w_r(dst)) } +inst_tlbi_vmalle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1) } +emit_tlbi_vmalle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1_none()) } +inst_tlbi_vmalle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_VMALLE1IS) } +emit_tlbi_vmalle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_vmalle1is_none()) } +inst_tlbi_vae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1, dst) } +emit_tlbi_vae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1_r(dst)) } +inst_tlbi_vae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAE1IS, dst) } +emit_tlbi_vae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vae1is_r(dst)) } +inst_tlbi_aside1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1, dst) } +emit_tlbi_aside1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1_r(dst)) } +inst_tlbi_aside1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_ASIDE1IS, dst) } +emit_tlbi_aside1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_aside1is_r(dst)) } +inst_tlbi_vaae1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1, dst) } +emit_tlbi_vaae1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1_r(dst)) } +inst_tlbi_vaae1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAAE1IS, dst) } +emit_tlbi_vaae1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaae1is_r(dst)) } +inst_tlbi_vale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1, dst) } +emit_tlbi_vale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1_r(dst)) } +inst_tlbi_vale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VALE1IS, dst) } +emit_tlbi_vale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vale1is_r(dst)) } +inst_tlbi_vaale1_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1, dst) } +emit_tlbi_vaale1_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1_r(dst)) } +inst_tlbi_vaale1is_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return inst_r(.TLBI_VAALE1IS, dst) } +emit_tlbi_vaale1is_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_tlbi_vaale1is_r(dst)) } +inst_tlbi_alle1_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1) } +emit_tlbi_alle1_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1_none()) } +inst_tlbi_alle1is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE1IS) } +emit_tlbi_alle1is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle1is_none()) } +inst_tlbi_alle2_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2) } +emit_tlbi_alle2_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2_none()) } +inst_tlbi_alle2is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE2IS) } +emit_tlbi_alle2is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle2is_none()) } +inst_tlbi_alle3_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3) } +emit_tlbi_alle3_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3_none()) } +inst_tlbi_alle3is_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.TLBI_ALLE3IS) } +emit_tlbi_alle3is_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_tlbi_alle3is_none()) } +inst_prfm_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +emit_prfm_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfm_i_m(imm, mem)) } +inst_prfum_i_m :: #force_inline proc "contextless" (imm: i64, mem: Memory) -> Instruction { return Instruction{mnemonic = .PRFUM, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_mem(mem), {}, {}}} } +emit_prfum_i_m :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, mem: Memory) { append(instructions, inst_prfum_i_m(imm, mem)) } +inst_prfm_lit_i_l :: #force_inline proc "contextless" (imm: i64, label: u32) -> Instruction { return Instruction{mnemonic = .PRFM_LIT, operand_count = 2, length = 4, ops = {op_imm(imm, 1), op_label(label, 4), {}, {}}} } +emit_prfm_lit_i_l :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, label: u32) { append(instructions, inst_prfm_lit_i_l(imm, label)) } +inst_mov_reg_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MOV_REG, dst, src) } +emit_mov_reg_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mov_reg_r_r(dst, src)) } +inst_mov_bitmask_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.MOV_BITMASK, dst, imm) } +emit_mov_bitmask_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_mov_bitmask_r_i(dst, imm)) } +inst_mvn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return inst_r_r(.MVN, dst, src) } +emit_mvn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_mvn_r_r(dst, src)) } +inst_neg_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEG_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +emit_neg_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_neg_sr_r_sh(dst, src, src_shift, src_amount)) } +inst_negs_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .NEGS, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +emit_negs_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_negs_r_sh(dst, src, src_shift, src_amount)) } +inst_cmp_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +emit_cmp_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmp_sr_r_sh(dst, src, src_shift, src_amount)) } +inst_cmp_er_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMP_ER, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } +emit_cmp_er_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmp_er_r_ex(dst, src, src_ext, src_amount)) } +inst_cmp_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMP_IMM, dst, imm) } +emit_cmp_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmp_imm_r_i(dst, imm)) } +inst_cmn_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +emit_cmn_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_cmn_sr_r_sh(dst, src, src_shift, src_amount)) } +inst_cmn_er_r_ex :: #force_inline proc "contextless" (dst: Register, src: Register, src_ext: Extend, src_amount: u8) -> Instruction { return Instruction{mnemonic = .CMN_ER, operand_count = 2, length = 4, ops = {op_reg(dst), op_extended(src, src_ext, src_amount), {}, {}}} } +emit_cmn_er_r_ex :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_ext: Extend, src_amount: u8) { append(instructions, inst_cmn_er_r_ex(dst, src, src_ext, src_amount)) } +inst_cmn_imm_r_i :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return inst_r_i(.CMN_IMM, dst, imm) } +emit_cmn_imm_r_i :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_cmn_imm_r_i(dst, imm)) } +inst_tst_sr_r_sh :: #force_inline proc "contextless" (dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) -> Instruction { return Instruction{mnemonic = .TST_SR, operand_count = 2, length = 4, ops = {op_reg(dst), op_shifted(src, src_shift, src_amount), {}, {}}} } +emit_tst_sr_r_sh :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src_shift: Shift_Type, src_amount: u8) { append(instructions, inst_tst_sr_r_sh(dst, src, src_shift, src_amount)) } // ============================================================================= // Overload Groups // ============================================================================= -inst_add_imm :: inst_add_imm_r_r_i -emit_add_imm :: emit_add_imm_r_r_i -inst_adds_imm :: inst_adds_imm_r_r_i -emit_adds_imm :: emit_adds_imm_r_r_i -inst_sub_imm :: inst_sub_imm_r_r_i -emit_sub_imm :: emit_sub_imm_r_r_i -inst_subs_imm :: inst_subs_imm_r_r_i -emit_subs_imm :: emit_subs_imm_r_r_i -inst_movz :: inst_movz_r_i_i -emit_movz :: emit_movz_r_i_i -inst_movn :: inst_movn_r_i_i -emit_movn :: emit_movn_r_i_i -inst_movk :: inst_movk_r_i_i -emit_movk :: emit_movk_r_i_i -inst_adr :: inst_adr_r_l -emit_adr :: emit_adr_r_l -inst_adrp :: inst_adrp_r_l -emit_adrp :: emit_adrp_r_l -inst_lslv :: inst_lslv_r_r_r -emit_lslv :: emit_lslv_r_r_r -inst_lsrv :: inst_lsrv_r_r_r -emit_lsrv :: emit_lsrv_r_r_r -inst_asrv :: inst_asrv_r_r_r -emit_asrv :: emit_asrv_r_r_r -inst_rorv :: inst_rorv_r_r_r -emit_rorv :: emit_rorv_r_r_r -inst_udiv :: inst_udiv_r_r_r -emit_udiv :: emit_udiv_r_r_r -inst_sdiv :: inst_sdiv_r_r_r -emit_sdiv :: emit_sdiv_r_r_r -inst_madd :: inst_madd_r_r_r_r -emit_madd :: emit_madd_r_r_r_r -inst_msub :: inst_msub_r_r_r_r -emit_msub :: emit_msub_r_r_r_r -inst_smaddl :: inst_smaddl_r_r_r_r -emit_smaddl :: emit_smaddl_r_r_r_r -inst_smsubl :: inst_smsubl_r_r_r_r -emit_smsubl :: emit_smsubl_r_r_r_r -inst_umaddl :: inst_umaddl_r_r_r_r -emit_umaddl :: emit_umaddl_r_r_r_r -inst_umsubl :: inst_umsubl_r_r_r_r -emit_umsubl :: emit_umsubl_r_r_r_r -inst_smulh :: inst_smulh_r_r_r -emit_smulh :: emit_smulh_r_r_r -inst_umulh :: inst_umulh_r_r_r -emit_umulh :: emit_umulh_r_r_r -inst_clz :: inst_clz_r_r -emit_clz :: emit_clz_r_r -inst_cls :: inst_cls_r_r -emit_cls :: emit_cls_r_r -inst_rbit :: inst_rbit_r_r -emit_rbit :: emit_rbit_r_r -inst_rev :: inst_rev_r_r -emit_rev :: emit_rev_r_r -inst_rev16 :: inst_rev16_r_r -emit_rev16 :: emit_rev16_r_r -inst_rev32 :: inst_rev32_r_r -emit_rev32 :: emit_rev32_r_r -inst_csinc :: inst_csinc_r_r_r_c -emit_csinc :: emit_csinc_r_r_r_c -inst_csinv :: inst_csinv_r_r_r_c -emit_csinv :: emit_csinv_r_r_r_c -inst_csneg :: inst_csneg_r_r_r_c -emit_csneg :: emit_csneg_r_r_r_c -inst_extr :: inst_extr_r_r_r_i -emit_extr :: emit_extr_r_r_r_i -inst_b :: inst_b_l -emit_b :: emit_b_l -inst_bl :: inst_bl_l -emit_bl :: emit_bl_l -inst_br :: inst_br_r -emit_br :: emit_br_r -inst_blr :: inst_blr_r -emit_blr :: emit_blr_r -inst_ret :: proc{ inst_ret_r, inst_ret_none } -emit_ret :: proc{ emit_ret_r, emit_ret_none } -inst_cbnz :: inst_cbnz_r_l -emit_cbnz :: emit_cbnz_r_l -inst_tbnz :: inst_tbnz_r_i_l -emit_tbnz :: emit_tbnz_r_i_l -inst_ldr :: inst_ldr_r_m -emit_ldr :: emit_ldr_r_m -inst_str :: inst_str_r_m -emit_str :: emit_str_r_m -inst_ldrb :: inst_ldrb_r_m -emit_ldrb :: emit_ldrb_r_m -inst_strb :: inst_strb_r_m -emit_strb :: emit_strb_r_m -inst_ldrsb :: inst_ldrsb_r_m -emit_ldrsb :: emit_ldrsb_r_m -inst_ldrh :: inst_ldrh_r_m -emit_ldrh :: emit_ldrh_r_m -inst_strh :: inst_strh_r_m -emit_strh :: emit_strh_r_m -inst_ldrsh :: inst_ldrsh_r_m -emit_ldrsh :: emit_ldrsh_r_m -inst_ldrsw :: inst_ldrsw_r_m -emit_ldrsw :: emit_ldrsw_r_m -inst_ldp :: inst_ldp_r_r_m -emit_ldp :: emit_ldp_r_r_m -inst_stp :: inst_stp_r_r_m -emit_stp :: emit_stp_r_r_m -inst_ldpsw :: inst_ldpsw_r_r_m -emit_ldpsw :: emit_ldpsw_r_r_m -inst_ldr_lit :: inst_ldr_lit_r_l -emit_ldr_lit :: emit_ldr_lit_r_l -inst_ldar :: inst_ldar_r_m -emit_ldar :: emit_ldar_r_m -inst_stlr :: inst_stlr_r_m -emit_stlr :: emit_stlr_r_m -inst_ldarb :: inst_ldarb_r_m -emit_ldarb :: emit_ldarb_r_m -inst_stlrb :: inst_stlrb_r_m -emit_stlrb :: emit_stlrb_r_m -inst_ldarh :: inst_ldarh_r_m -emit_ldarh :: emit_ldarh_r_m -inst_stlrh :: inst_stlrh_r_m -emit_stlrh :: emit_stlrh_r_m -inst_ldxr :: inst_ldxr_r_m -emit_ldxr :: emit_ldxr_r_m -inst_stxr :: inst_stxr_r_r_m -emit_stxr :: emit_stxr_r_r_m -inst_ldaxr :: inst_ldaxr_r_m -emit_ldaxr :: emit_ldaxr_r_m -inst_stlxr :: inst_stlxr_r_r_m -emit_stlxr :: emit_stlxr_r_r_m -inst_nop :: inst_nop_none -emit_nop :: emit_nop_none -inst_yield :: inst_yield_none -emit_yield :: emit_yield_none -inst_wfe :: inst_wfe_none -emit_wfe :: emit_wfe_none -inst_wfi :: inst_wfi_none -emit_wfi :: emit_wfi_none -inst_sev :: inst_sev_none -emit_sev :: emit_sev_none -inst_sevl :: inst_sevl_none -emit_sevl :: emit_sevl_none -inst_isb :: inst_isb_i -emit_isb :: emit_isb_i -inst_dsb :: inst_dsb_i -emit_dsb :: emit_dsb_i -inst_dmb :: inst_dmb_i -emit_dmb :: emit_dmb_i -inst_svc :: inst_svc_i -emit_svc :: emit_svc_i -inst_hvc :: inst_hvc_i -emit_hvc :: emit_hvc_i -inst_smc :: inst_smc_i -emit_smc :: emit_smc_i -inst_brk :: inst_brk_i -emit_brk :: emit_brk_i -inst_hlt :: inst_hlt_i -emit_hlt :: emit_hlt_i -inst_eret :: inst_eret_none -emit_eret :: emit_eret_none -inst_fmov_reg :: inst_fmov_reg_r_r -emit_fmov_reg :: emit_fmov_reg_r_r -inst_fmov_gen :: inst_fmov_gen_r_r -emit_fmov_gen :: emit_fmov_gen_r_r -inst_fabs :: inst_fabs_r_r -emit_fabs :: emit_fabs_r_r -inst_fneg :: inst_fneg_r_r -emit_fneg :: emit_fneg_r_r -inst_fsqrt :: inst_fsqrt_r_r -emit_fsqrt :: emit_fsqrt_r_r -inst_fadd :: inst_fadd_r_r_r -emit_fadd :: emit_fadd_r_r_r -inst_fsub :: inst_fsub_r_r_r -emit_fsub :: emit_fsub_r_r_r -inst_fmul :: inst_fmul_r_r_r -emit_fmul :: emit_fmul_r_r_r -inst_fdiv :: inst_fdiv_r_r_r -emit_fdiv :: emit_fdiv_r_r_r -inst_fnmul :: inst_fnmul_r_r_r -emit_fnmul :: emit_fnmul_r_r_r -inst_fmadd :: inst_fmadd_r_r_r_r -emit_fmadd :: emit_fmadd_r_r_r_r -inst_fmsub :: inst_fmsub_r_r_r_r -emit_fmsub :: emit_fmsub_r_r_r_r -inst_fnmadd :: inst_fnmadd_r_r_r_r -emit_fnmadd :: emit_fnmadd_r_r_r_r -inst_fnmsub :: inst_fnmsub_r_r_r_r -emit_fnmsub :: emit_fnmsub_r_r_r_r -inst_fcmp :: inst_fcmp_r_r -emit_fcmp :: emit_fcmp_r_r -inst_fcmpe :: inst_fcmpe_r_r -emit_fcmpe :: emit_fcmpe_r_r -inst_fcsel :: inst_fcsel_r_r_r_c -emit_fcsel :: emit_fcsel_r_r_r_c -inst_fmax :: inst_fmax_r_r_r -emit_fmax :: emit_fmax_r_r_r -inst_fmin :: inst_fmin_r_r_r -emit_fmin :: emit_fmin_r_r_r -inst_fmaxnm :: inst_fmaxnm_r_r_r -emit_fmaxnm :: emit_fmaxnm_r_r_r -inst_fminnm :: inst_fminnm_r_r_r -emit_fminnm :: emit_fminnm_r_r_r -inst_fcvt :: inst_fcvt_r_r -emit_fcvt :: emit_fcvt_r_r -inst_scvtf :: inst_scvtf_r_r -emit_scvtf :: emit_scvtf_r_r -inst_ucvtf :: inst_ucvtf_r_r -emit_ucvtf :: emit_ucvtf_r_r -inst_fcvtzs :: inst_fcvtzs_r_r -emit_fcvtzs :: emit_fcvtzs_r_r -inst_fcvtzu :: inst_fcvtzu_r_r -emit_fcvtzu :: emit_fcvtzu_r_r -inst_ldur :: inst_ldur_r_m -emit_ldur :: emit_ldur_r_m -inst_stur :: inst_stur_r_m -emit_stur :: emit_stur_r_m -inst_ldurb :: inst_ldurb_r_m -emit_ldurb :: emit_ldurb_r_m -inst_sturb :: inst_sturb_r_m -emit_sturb :: emit_sturb_r_m -inst_ldursb :: inst_ldursb_r_m -emit_ldursb :: emit_ldursb_r_m -inst_ldurh :: inst_ldurh_r_m -emit_ldurh :: emit_ldurh_r_m -inst_sturh :: inst_sturh_r_m -emit_sturh :: emit_sturh_r_m -inst_ldursh :: inst_ldursh_r_m -emit_ldursh :: emit_ldursh_r_m -inst_ldursw :: inst_ldursw_r_m -emit_ldursw :: emit_ldursw_r_m -inst_ldr_pre :: inst_ldr_pre_r_m -emit_ldr_pre :: emit_ldr_pre_r_m -inst_str_pre :: inst_str_pre_r_m -emit_str_pre :: emit_str_pre_r_m -inst_ldr_post :: inst_ldr_post_r_m -emit_ldr_post :: emit_ldr_post_r_m -inst_str_post :: inst_str_post_r_m -emit_str_post :: emit_str_post_r_m -inst_ldr_reg :: inst_ldr_reg_r_m -emit_ldr_reg :: emit_ldr_reg_r_m -inst_str_reg :: inst_str_reg_r_m -emit_str_reg :: emit_str_reg_r_m -inst_ldp_pre :: inst_ldp_pre_r_r_m -emit_ldp_pre :: emit_ldp_pre_r_r_m -inst_stp_pre :: inst_stp_pre_r_r_m -emit_stp_pre :: emit_stp_pre_r_r_m -inst_ldp_post :: inst_ldp_post_r_r_m -emit_ldp_post :: emit_ldp_post_r_r_m -inst_stp_post :: inst_stp_post_r_r_m -emit_stp_post :: emit_stp_post_r_r_m -inst_ldpsw_pre :: inst_ldpsw_pre_r_r_m -emit_ldpsw_pre :: emit_ldpsw_pre_r_r_m -inst_ldpsw_post :: inst_ldpsw_post_r_r_m -emit_ldpsw_post :: emit_ldpsw_post_r_r_m -inst_ldnp :: inst_ldnp_r_r_m -emit_ldnp :: emit_ldnp_r_r_m -inst_stnp :: inst_stnp_r_r_m -emit_stnp :: emit_stnp_r_r_m -inst_ldxp :: inst_ldxp_r_r_m -emit_ldxp :: emit_ldxp_r_r_m -inst_stxp :: inst_stxp_r_r_r_m -emit_stxp :: emit_stxp_r_r_r_m -inst_ldaxp :: inst_ldaxp_r_r_m -emit_ldaxp :: emit_ldaxp_r_r_m -inst_stlxp :: inst_stlxp_r_r_r_m -emit_stlxp :: emit_stlxp_r_r_r_m -inst_ldxrb :: inst_ldxrb_r_m -emit_ldxrb :: emit_ldxrb_r_m -inst_stxrb :: inst_stxrb_r_r_m -emit_stxrb :: emit_stxrb_r_r_m -inst_ldaxrb :: inst_ldaxrb_r_m -emit_ldaxrb :: emit_ldaxrb_r_m -inst_stlxrb :: inst_stlxrb_r_r_m -emit_stlxrb :: emit_stlxrb_r_r_m -inst_ldxrh :: inst_ldxrh_r_m -emit_ldxrh :: emit_ldxrh_r_m -inst_stxrh :: inst_stxrh_r_r_m -emit_stxrh :: emit_stxrh_r_r_m -inst_ldaxrh :: inst_ldaxrh_r_m -emit_ldaxrh :: emit_ldaxrh_r_m -inst_stlxrh :: inst_stlxrh_r_r_m -emit_stlxrh :: emit_stlxrh_r_r_m -inst_ldapr :: inst_ldapr_r_m -emit_ldapr :: emit_ldapr_r_m -inst_ldaprb :: inst_ldaprb_r_m -emit_ldaprb :: emit_ldaprb_r_m -inst_ldaprh :: inst_ldaprh_r_m -emit_ldaprh :: emit_ldaprh_r_m -inst_ldadd :: inst_ldadd_r_r_m -emit_ldadd :: emit_ldadd_r_r_m -inst_ldadda :: inst_ldadda_r_r_m -emit_ldadda :: emit_ldadda_r_r_m -inst_ldaddl :: inst_ldaddl_r_r_m -emit_ldaddl :: emit_ldaddl_r_r_m -inst_ldaddal :: inst_ldaddal_r_r_m -emit_ldaddal :: emit_ldaddal_r_r_m -inst_ldclr :: inst_ldclr_r_r_m -emit_ldclr :: emit_ldclr_r_r_m -inst_ldclra :: inst_ldclra_r_r_m -emit_ldclra :: emit_ldclra_r_r_m -inst_ldclrl :: inst_ldclrl_r_r_m -emit_ldclrl :: emit_ldclrl_r_r_m -inst_ldclral :: inst_ldclral_r_r_m -emit_ldclral :: emit_ldclral_r_r_m -inst_ldeor :: inst_ldeor_r_r_m -emit_ldeor :: emit_ldeor_r_r_m -inst_ldeora :: inst_ldeora_r_r_m -emit_ldeora :: emit_ldeora_r_r_m -inst_ldeorl :: inst_ldeorl_r_r_m -emit_ldeorl :: emit_ldeorl_r_r_m -inst_ldeoral :: inst_ldeoral_r_r_m -emit_ldeoral :: emit_ldeoral_r_r_m -inst_ldset :: inst_ldset_r_r_m -emit_ldset :: emit_ldset_r_r_m -inst_ldseta :: inst_ldseta_r_r_m -emit_ldseta :: emit_ldseta_r_r_m -inst_ldsetl :: inst_ldsetl_r_r_m -emit_ldsetl :: emit_ldsetl_r_r_m -inst_ldsetal :: inst_ldsetal_r_r_m -emit_ldsetal :: emit_ldsetal_r_r_m -inst_ldsmax :: inst_ldsmax_r_r_m -emit_ldsmax :: emit_ldsmax_r_r_m -inst_ldsmaxa :: inst_ldsmaxa_r_r_m -emit_ldsmaxa :: emit_ldsmaxa_r_r_m -inst_ldsmaxl :: inst_ldsmaxl_r_r_m -emit_ldsmaxl :: emit_ldsmaxl_r_r_m -inst_ldsmaxal :: inst_ldsmaxal_r_r_m -emit_ldsmaxal :: emit_ldsmaxal_r_r_m -inst_ldsmin :: inst_ldsmin_r_r_m -emit_ldsmin :: emit_ldsmin_r_r_m -inst_ldsmina :: inst_ldsmina_r_r_m -emit_ldsmina :: emit_ldsmina_r_r_m -inst_ldsminl :: inst_ldsminl_r_r_m -emit_ldsminl :: emit_ldsminl_r_r_m -inst_ldsminal :: inst_ldsminal_r_r_m -emit_ldsminal :: emit_ldsminal_r_r_m -inst_ldumax :: inst_ldumax_r_r_m -emit_ldumax :: emit_ldumax_r_r_m -inst_ldumaxa :: inst_ldumaxa_r_r_m -emit_ldumaxa :: emit_ldumaxa_r_r_m -inst_ldumaxl :: inst_ldumaxl_r_r_m -emit_ldumaxl :: emit_ldumaxl_r_r_m -inst_ldumaxal :: inst_ldumaxal_r_r_m -emit_ldumaxal :: emit_ldumaxal_r_r_m -inst_ldumin :: inst_ldumin_r_r_m -emit_ldumin :: emit_ldumin_r_r_m -inst_ldumina :: inst_ldumina_r_r_m -emit_ldumina :: emit_ldumina_r_r_m -inst_lduminl :: inst_lduminl_r_r_m -emit_lduminl :: emit_lduminl_r_r_m -inst_lduminal :: inst_lduminal_r_r_m -emit_lduminal :: emit_lduminal_r_r_m -inst_swp :: inst_swp_r_r_m -emit_swp :: emit_swp_r_r_m -inst_swpa :: inst_swpa_r_r_m -emit_swpa :: emit_swpa_r_r_m -inst_swpl :: inst_swpl_r_r_m -emit_swpl :: emit_swpl_r_r_m -inst_swpal :: inst_swpal_r_r_m -emit_swpal :: emit_swpal_r_r_m -inst_cas :: inst_cas_r_r_m -emit_cas :: emit_cas_r_r_m -inst_casa :: inst_casa_r_r_m -emit_casa :: emit_casa_r_r_m -inst_casl :: inst_casl_r_r_m -emit_casl :: emit_casl_r_r_m -inst_casal :: inst_casal_r_r_m -emit_casal :: emit_casal_r_r_m -inst_casb :: inst_casb_r_r_m -emit_casb :: emit_casb_r_r_m -inst_casab :: inst_casab_r_r_m -emit_casab :: emit_casab_r_r_m -inst_caslb :: inst_caslb_r_r_m -emit_caslb :: emit_caslb_r_r_m -inst_casalb :: inst_casalb_r_r_m -emit_casalb :: emit_casalb_r_r_m -inst_cash :: inst_cash_r_r_m -emit_cash :: emit_cash_r_r_m -inst_casah :: inst_casah_r_r_m -emit_casah :: emit_casah_r_r_m -inst_caslh :: inst_caslh_r_r_m -emit_caslh :: emit_caslh_r_r_m -inst_casalh :: inst_casalh_r_r_m -emit_casalh :: emit_casalh_r_r_m -inst_casp :: inst_casp_r_r_m -emit_casp :: emit_casp_r_r_m -inst_caspa :: inst_caspa_r_r_m -emit_caspa :: emit_caspa_r_r_m -inst_caspl :: inst_caspl_r_r_m -emit_caspl :: emit_caspl_r_r_m -inst_caspal :: inst_caspal_r_r_m -emit_caspal :: emit_caspal_r_r_m -inst_pacia :: inst_pacia_r_r -emit_pacia :: emit_pacia_r_r -inst_pacib :: inst_pacib_r_r -emit_pacib :: emit_pacib_r_r -inst_pacda :: inst_pacda_r_r -emit_pacda :: emit_pacda_r_r -inst_pacdb :: inst_pacdb_r_r -emit_pacdb :: emit_pacdb_r_r -inst_paciza :: inst_paciza_r -emit_paciza :: emit_paciza_r -inst_pacizb :: inst_pacizb_r -emit_pacizb :: emit_pacizb_r -inst_pacdza :: inst_pacdza_r -emit_pacdza :: emit_pacdza_r -inst_pacdzb :: inst_pacdzb_r -emit_pacdzb :: emit_pacdzb_r -inst_autia :: inst_autia_r_r -emit_autia :: emit_autia_r_r -inst_autib :: inst_autib_r_r -emit_autib :: emit_autib_r_r -inst_autda :: inst_autda_r_r -emit_autda :: emit_autda_r_r -inst_autdb :: inst_autdb_r_r -emit_autdb :: emit_autdb_r_r -inst_autiza :: inst_autiza_r -emit_autiza :: emit_autiza_r -inst_autizb :: inst_autizb_r -emit_autizb :: emit_autizb_r -inst_autdza :: inst_autdza_r -emit_autdza :: emit_autdza_r -inst_autdzb :: inst_autdzb_r -emit_autdzb :: emit_autdzb_r -inst_paciasp :: inst_paciasp_none -emit_paciasp :: emit_paciasp_none -inst_pacibsp :: inst_pacibsp_none -emit_pacibsp :: emit_pacibsp_none -inst_autiasp :: inst_autiasp_none -emit_autiasp :: emit_autiasp_none -inst_autibsp :: inst_autibsp_none -emit_autibsp :: emit_autibsp_none -inst_pacia1716 :: inst_pacia1716_none -emit_pacia1716 :: emit_pacia1716_none -inst_pacib1716 :: inst_pacib1716_none -emit_pacib1716 :: emit_pacib1716_none -inst_autia1716 :: inst_autia1716_none -emit_autia1716 :: emit_autia1716_none -inst_autib1716 :: inst_autib1716_none -emit_autib1716 :: emit_autib1716_none -inst_pacga :: inst_pacga_r_r_r -emit_pacga :: emit_pacga_r_r_r -inst_xpaci :: inst_xpaci_r -emit_xpaci :: emit_xpaci_r -inst_xpacd :: inst_xpacd_r -emit_xpacd :: emit_xpacd_r -inst_xpaclri :: inst_xpaclri_none -emit_xpaclri :: emit_xpaclri_none -inst_retaa :: inst_retaa_none -emit_retaa :: emit_retaa_none -inst_retab :: inst_retab_none -emit_retab :: emit_retab_none -inst_braa :: inst_braa_r_r -emit_braa :: emit_braa_r_r -inst_brab :: inst_brab_r_r -emit_brab :: emit_brab_r_r -inst_braaz :: inst_braaz_r -emit_braaz :: emit_braaz_r -inst_brabz :: inst_brabz_r -emit_brabz :: emit_brabz_r -inst_blraa :: inst_blraa_r_r -emit_blraa :: emit_blraa_r_r -inst_blrab :: inst_blrab_r_r -emit_blrab :: emit_blrab_r_r -inst_blraaz :: inst_blraaz_r -emit_blraaz :: emit_blraaz_r -inst_blrabz :: inst_blrabz_r -emit_blrabz :: emit_blrabz_r -inst_eretaa :: inst_eretaa_none -emit_eretaa :: emit_eretaa_none -inst_eretab :: inst_eretab_none -emit_eretab :: emit_eretab_none -inst_bti :: inst_bti_i -emit_bti :: emit_bti_i -inst_irg :: inst_irg_r_r_r -emit_irg :: emit_irg_r_r_r -inst_addg :: inst_addg_r_r_i_i -emit_addg :: emit_addg_r_r_i_i -inst_subg :: inst_subg_r_r_i_i -emit_subg :: emit_subg_r_r_i_i -inst_gmi :: inst_gmi_r_r_r -emit_gmi :: emit_gmi_r_r_r -inst_subp :: inst_subp_r_r_r -emit_subp :: emit_subp_r_r_r -inst_subps :: inst_subps_r_r_r -emit_subps :: emit_subps_r_r_r -inst_ldg :: inst_ldg_r_m -emit_ldg :: emit_ldg_r_m -inst_stg :: inst_stg_r_m -emit_stg :: emit_stg_r_m -inst_st2g :: inst_st2g_r_m -emit_st2g :: emit_st2g_r_m -inst_stzg :: inst_stzg_r_m -emit_stzg :: emit_stzg_r_m -inst_stz2g :: inst_stz2g_r_m -emit_stz2g :: emit_stz2g_r_m -inst_stgp :: inst_stgp_r_r_m -emit_stgp :: emit_stgp_r_r_m -inst_ldgm :: inst_ldgm_r_m -emit_ldgm :: emit_ldgm_r_m -inst_stgm :: inst_stgm_r_m -emit_stgm :: emit_stgm_r_m -inst_stzgm :: inst_stzgm_r_m -emit_stzgm :: emit_stzgm_r_m -inst_crc32b :: inst_crc32b_r_r_r -emit_crc32b :: emit_crc32b_r_r_r -inst_crc32h :: inst_crc32h_r_r_r -emit_crc32h :: emit_crc32h_r_r_r -inst_crc32w :: inst_crc32w_r_r_r -emit_crc32w :: emit_crc32w_r_r_r -inst_crc32x :: inst_crc32x_r_r_r -emit_crc32x :: emit_crc32x_r_r_r -inst_crc32cb :: inst_crc32cb_r_r_r -emit_crc32cb :: emit_crc32cb_r_r_r -inst_crc32ch :: inst_crc32ch_r_r_r -emit_crc32ch :: emit_crc32ch_r_r_r -inst_crc32cw :: inst_crc32cw_r_r_r -emit_crc32cw :: emit_crc32cw_r_r_r -inst_crc32cx :: inst_crc32cx_r_r_r -emit_crc32cx :: emit_crc32cx_r_r_r -inst_sha1h :: inst_sha1h_r_r -emit_sha1h :: emit_sha1h_r_r -inst_fabs_h :: inst_fabs_h_r_r -emit_fabs_h :: emit_fabs_h_r_r -inst_fneg_h :: inst_fneg_h_r_r -emit_fneg_h :: emit_fneg_h_r_r -inst_fsqrt_h :: inst_fsqrt_h_r_r -emit_fsqrt_h :: emit_fsqrt_h_r_r -inst_fadd_h :: inst_fadd_h_r_r_r -emit_fadd_h :: emit_fadd_h_r_r_r -inst_fsub_h :: inst_fsub_h_r_r_r -emit_fsub_h :: emit_fsub_h_r_r_r -inst_fmul_h :: inst_fmul_h_r_r_r -emit_fmul_h :: emit_fmul_h_r_r_r -inst_fdiv_h :: inst_fdiv_h_r_r_r -emit_fdiv_h :: emit_fdiv_h_r_r_r -inst_fnmul_h :: inst_fnmul_h_r_r_r -emit_fnmul_h :: emit_fnmul_h_r_r_r -inst_fmadd_h :: inst_fmadd_h_r_r_r_r -emit_fmadd_h :: emit_fmadd_h_r_r_r_r -inst_fmsub_h :: inst_fmsub_h_r_r_r_r -emit_fmsub_h :: emit_fmsub_h_r_r_r_r -inst_fnmadd_h :: inst_fnmadd_h_r_r_r_r -emit_fnmadd_h :: emit_fnmadd_h_r_r_r_r -inst_fnmsub_h :: inst_fnmsub_h_r_r_r_r -emit_fnmsub_h :: emit_fnmsub_h_r_r_r_r -inst_fcmp_h :: inst_fcmp_h_r_r -emit_fcmp_h :: emit_fcmp_h_r_r -inst_fcmpe_h :: inst_fcmpe_h_r_r -emit_fcmpe_h :: emit_fcmpe_h_r_r -inst_fcsel_h :: inst_fcsel_h_r_r_r_c -emit_fcsel_h :: emit_fcsel_h_r_r_r_c -inst_fmax_h :: inst_fmax_h_r_r_r -emit_fmax_h :: emit_fmax_h_r_r_r -inst_fmin_h :: inst_fmin_h_r_r_r -emit_fmin_h :: emit_fmin_h_r_r_r -inst_fmaxnm_h :: inst_fmaxnm_h_r_r_r -emit_fmaxnm_h :: emit_fmaxnm_h_r_r_r -inst_fminnm_h :: inst_fminnm_h_r_r_r -emit_fminnm_h :: emit_fminnm_h_r_r_r -inst_fcvt_h_s :: inst_fcvt_h_s_r_r -emit_fcvt_h_s :: emit_fcvt_h_s_r_r -inst_fcvt_h_d :: inst_fcvt_h_d_r_r -emit_fcvt_h_d :: emit_fcvt_h_d_r_r -inst_fcvt_s_h :: inst_fcvt_s_h_r_r -emit_fcvt_s_h :: emit_fcvt_s_h_r_r -inst_fcvt_d_h :: inst_fcvt_d_h_r_r -emit_fcvt_d_h :: emit_fcvt_d_h_r_r -inst_fmov_h :: inst_fmov_h_r_r -emit_fmov_h :: emit_fmov_h_r_r -inst_scvtf_h :: inst_scvtf_h_r_r -emit_scvtf_h :: emit_scvtf_h_r_r -inst_ucvtf_h :: inst_ucvtf_h_r_r -emit_ucvtf_h :: emit_ucvtf_h_r_r -inst_fcvtzs_h :: inst_fcvtzs_h_r_r -emit_fcvtzs_h :: emit_fcvtzs_h_r_r -inst_fcvtzu_h :: inst_fcvtzu_h_r_r -emit_fcvtzu_h :: emit_fcvtzu_h_r_r -inst_bfcvt :: inst_bfcvt_r_r -emit_bfcvt :: emit_bfcvt_r_r -inst_ldr_v :: inst_ldr_v_r_m -emit_ldr_v :: emit_ldr_v_r_m -inst_str_v :: inst_str_v_r_m -emit_str_v :: emit_str_v_r_m -inst_sme_smstart :: inst_sme_smstart_none -emit_sme_smstart :: emit_sme_smstart_none -inst_sme_smstop :: inst_sme_smstop_none -emit_sme_smstop :: emit_sme_smstop_none -inst_sme_rdsvl :: inst_sme_rdsvl_r_i -emit_sme_rdsvl :: emit_sme_rdsvl_r_i -inst_sme_ldr_za :: inst_sme_ldr_za_i_m -emit_sme_ldr_za :: emit_sme_ldr_za_i_m -inst_sme_str_za :: inst_sme_str_za_i_m -emit_sme_str_za :: emit_sme_str_za_i_m -inst_ldraa :: inst_ldraa_r_m -emit_ldraa :: emit_ldraa_r_m -inst_ldrab :: inst_ldrab_r_m -emit_ldrab :: emit_ldrab_r_m -inst_ldraa_pre :: inst_ldraa_pre_r_m -emit_ldraa_pre :: emit_ldraa_pre_r_m -inst_ldrab_pre :: inst_ldrab_pre_r_m -emit_ldrab_pre :: emit_ldrab_pre_r_m -inst_tstart :: inst_tstart_r -emit_tstart :: emit_tstart_r -inst_tcommit :: inst_tcommit_none -emit_tcommit :: emit_tcommit_none -inst_tcancel :: inst_tcancel_i -emit_tcancel :: emit_tcancel_i -inst_ttest :: inst_ttest_r -emit_ttest :: emit_ttest_r -inst_wfet :: inst_wfet_r -emit_wfet :: emit_wfet_r -inst_wfit :: inst_wfit_r -emit_wfit :: emit_wfit_r -inst_bc_cond :: inst_bc_cond_c_l -emit_bc_cond :: emit_bc_cond_c_l -inst_uxtb :: inst_uxtb_r_r -emit_uxtb :: emit_uxtb_r_r -inst_uxth :: inst_uxth_r_r -emit_uxth :: emit_uxth_r_r -inst_uxtw :: inst_uxtw_r_r -emit_uxtw :: emit_uxtw_r_r -inst_sxtb :: inst_sxtb_r_r -emit_sxtb :: emit_sxtb_r_r -inst_sxth :: inst_sxth_r_r -emit_sxth :: emit_sxth_r_r -inst_sxtw :: inst_sxtw_r_r -emit_sxtw :: emit_sxtw_r_r -inst_adc :: inst_adc_r_r_r -emit_adc :: emit_adc_r_r_r -inst_adcs :: inst_adcs_r_r_r -emit_adcs :: emit_adcs_r_r_r -inst_sbc :: inst_sbc_r_r_r -emit_sbc :: emit_sbc_r_r_r -inst_sbcs :: inst_sbcs_r_r_r -emit_sbcs :: emit_sbcs_r_r_r -inst_ngc :: inst_ngc_r_r -emit_ngc :: emit_ngc_r_r -inst_ngcs :: inst_ngcs_r_r -emit_ngcs :: emit_ngcs_r_r -inst_ldapur :: inst_ldapur_r_m -emit_ldapur :: emit_ldapur_r_m -inst_stlur :: inst_stlur_r_m -emit_stlur :: emit_stlur_r_m -inst_ldapurb :: inst_ldapurb_r_m -emit_ldapurb :: emit_ldapurb_r_m -inst_stlurb :: inst_stlurb_r_m -emit_stlurb :: emit_stlurb_r_m -inst_ldapurh :: inst_ldapurh_r_m -emit_ldapurh :: emit_ldapurh_r_m -inst_stlurh :: inst_stlurh_r_m -emit_stlurh :: emit_stlurh_r_m -inst_ldapursb :: inst_ldapursb_r_m -emit_ldapursb :: emit_ldapursb_r_m -inst_ldapursh :: inst_ldapursh_r_m -emit_ldapursh :: emit_ldapursh_r_m -inst_ldapursw :: inst_ldapursw_r_m -emit_ldapursw :: emit_ldapursw_r_m -inst_sb :: inst_sb_none -emit_sb :: emit_sb_none -inst_csdb :: inst_csdb_none -emit_csdb :: emit_csdb_none -inst_dgh :: inst_dgh_none -emit_dgh :: emit_dgh_none -inst_psb_csync :: inst_psb_csync_none -emit_psb_csync :: emit_psb_csync_none -inst_tsb_csync :: inst_tsb_csync_none -emit_tsb_csync :: emit_tsb_csync_none -inst_bti_j :: inst_bti_j_none -emit_bti_j :: emit_bti_j_none -inst_bti_c :: inst_bti_c_none -emit_bti_c :: emit_bti_c_none -inst_bti_jc :: inst_bti_jc_none -emit_bti_jc :: emit_bti_jc_none -inst_lsl_imm :: inst_lsl_imm_r_r_i -emit_lsl_imm :: emit_lsl_imm_r_r_i -inst_lsr_imm :: inst_lsr_imm_r_r_i -emit_lsr_imm :: emit_lsr_imm_r_r_i -inst_asr_imm :: inst_asr_imm_r_r_i -emit_asr_imm :: emit_asr_imm_r_r_i -inst_ror_imm :: inst_ror_imm_r_r_i -emit_ror_imm :: emit_ror_imm_r_r_i -inst_tlbi_rpalos :: inst_tlbi_rpalos_r -emit_tlbi_rpalos :: emit_tlbi_rpalos_r -inst_tlbi_rpaos :: inst_tlbi_rpaos_r -emit_tlbi_rpaos :: emit_tlbi_rpaos_r -inst_at_s1e1a :: inst_at_s1e1a_r -emit_at_s1e1a :: emit_at_s1e1a_r -inst_dc_cipapa :: inst_dc_cipapa_r -emit_dc_cipapa :: emit_dc_cipapa_r -inst_dc_cigdpapa :: inst_dc_cigdpapa_r -emit_dc_cigdpapa :: emit_dc_cigdpapa_r -inst_tlbi_paall :: inst_tlbi_paall_none -emit_tlbi_paall :: emit_tlbi_paall_none -inst_tlbi_paallos :: inst_tlbi_paallos_none -emit_tlbi_paallos :: emit_tlbi_paallos_none -inst_amx_ldx :: inst_amx_ldx_r -emit_amx_ldx :: emit_amx_ldx_r -inst_amx_ldy :: inst_amx_ldy_r -emit_amx_ldy :: emit_amx_ldy_r -inst_amx_stx :: inst_amx_stx_r -emit_amx_stx :: emit_amx_stx_r -inst_amx_sty :: inst_amx_sty_r -emit_amx_sty :: emit_amx_sty_r -inst_amx_ldz :: inst_amx_ldz_r -emit_amx_ldz :: emit_amx_ldz_r -inst_amx_stz :: inst_amx_stz_r -emit_amx_stz :: emit_amx_stz_r -inst_amx_ldzi :: inst_amx_ldzi_r -emit_amx_ldzi :: emit_amx_ldzi_r -inst_amx_stzi :: inst_amx_stzi_r -emit_amx_stzi :: emit_amx_stzi_r -inst_amx_extrx :: inst_amx_extrx_r -emit_amx_extrx :: emit_amx_extrx_r -inst_amx_extry :: inst_amx_extry_r -emit_amx_extry :: emit_amx_extry_r -inst_amx_fma64 :: inst_amx_fma64_r -emit_amx_fma64 :: emit_amx_fma64_r -inst_amx_fms64 :: inst_amx_fms64_r -emit_amx_fms64 :: emit_amx_fms64_r -inst_amx_fma32 :: inst_amx_fma32_r -emit_amx_fma32 :: emit_amx_fma32_r -inst_amx_fms32 :: inst_amx_fms32_r -emit_amx_fms32 :: emit_amx_fms32_r -inst_amx_mac16 :: inst_amx_mac16_r -emit_amx_mac16 :: emit_amx_mac16_r -inst_amx_fma16 :: inst_amx_fma16_r -emit_amx_fma16 :: emit_amx_fma16_r -inst_amx_fms16 :: inst_amx_fms16_r -emit_amx_fms16 :: emit_amx_fms16_r -inst_amx_set :: inst_amx_set_none -emit_amx_set :: emit_amx_set_none -inst_amx_clr :: inst_amx_clr_none -emit_amx_clr :: emit_amx_clr_none -inst_amx_vecint :: inst_amx_vecint_r -emit_amx_vecint :: emit_amx_vecint_r -inst_amx_vecfp :: inst_amx_vecfp_r -emit_amx_vecfp :: emit_amx_vecfp_r -inst_amx_matint :: inst_amx_matint_r -emit_amx_matint :: emit_amx_matint_r -inst_amx_matfp :: inst_amx_matfp_r -emit_amx_matfp :: emit_amx_matfp_r -inst_amx_genlut :: inst_amx_genlut_r -emit_amx_genlut :: emit_amx_genlut_r -inst_cpyp :: inst_cpyp_r_r_r -emit_cpyp :: emit_cpyp_r_r_r -inst_cpym :: inst_cpym_r_r_r -emit_cpym :: emit_cpym_r_r_r -inst_cpye :: inst_cpye_r_r_r -emit_cpye :: emit_cpye_r_r_r -inst_cpyfp :: inst_cpyfp_r_r_r -emit_cpyfp :: emit_cpyfp_r_r_r -inst_cpyfm :: inst_cpyfm_r_r_r -emit_cpyfm :: emit_cpyfm_r_r_r -inst_cpyfe :: inst_cpyfe_r_r_r -emit_cpyfe :: emit_cpyfe_r_r_r -inst_setp :: inst_setp_r_r_r -emit_setp :: emit_setp_r_r_r -inst_setm :: inst_setm_r_r_r -emit_setm :: emit_setm_r_r_r -inst_sete :: inst_sete_r_r_r -emit_sete :: emit_sete_r_r_r -inst_dc_ivac :: inst_dc_ivac_r -emit_dc_ivac :: emit_dc_ivac_r -inst_dc_isw :: inst_dc_isw_r -emit_dc_isw :: emit_dc_isw_r -inst_dc_csw :: inst_dc_csw_r -emit_dc_csw :: emit_dc_csw_r -inst_dc_cisw :: inst_dc_cisw_r -emit_dc_cisw :: emit_dc_cisw_r -inst_dc_zva :: inst_dc_zva_r -emit_dc_zva :: emit_dc_zva_r -inst_dc_cvac :: inst_dc_cvac_r -emit_dc_cvac :: emit_dc_cvac_r -inst_dc_cvau :: inst_dc_cvau_r -emit_dc_cvau :: emit_dc_cvau_r -inst_dc_civac :: inst_dc_civac_r -emit_dc_civac :: emit_dc_civac_r -inst_ic_ialluis :: inst_ic_ialluis_none -emit_ic_ialluis :: emit_ic_ialluis_none -inst_ic_iallu :: inst_ic_iallu_none -emit_ic_iallu :: emit_ic_iallu_none -inst_ic_ivau :: inst_ic_ivau_r -emit_ic_ivau :: emit_ic_ivau_r -inst_at_s1e1r :: inst_at_s1e1r_r -emit_at_s1e1r :: emit_at_s1e1r_r -inst_at_s1e1w :: inst_at_s1e1w_r -emit_at_s1e1w :: emit_at_s1e1w_r -inst_at_s1e0r :: inst_at_s1e0r_r -emit_at_s1e0r :: emit_at_s1e0r_r -inst_at_s1e0w :: inst_at_s1e0w_r -emit_at_s1e0w :: emit_at_s1e0w_r -inst_at_s1e2r :: inst_at_s1e2r_r -emit_at_s1e2r :: emit_at_s1e2r_r -inst_at_s1e2w :: inst_at_s1e2w_r -emit_at_s1e2w :: emit_at_s1e2w_r -inst_at_s1e3r :: inst_at_s1e3r_r -emit_at_s1e3r :: emit_at_s1e3r_r -inst_at_s1e3w :: inst_at_s1e3w_r -emit_at_s1e3w :: emit_at_s1e3w_r -inst_at_s12e1r :: inst_at_s12e1r_r -emit_at_s12e1r :: emit_at_s12e1r_r -inst_at_s12e1w :: inst_at_s12e1w_r -emit_at_s12e1w :: emit_at_s12e1w_r -inst_at_s12e0r :: inst_at_s12e0r_r -emit_at_s12e0r :: emit_at_s12e0r_r -inst_at_s12e0w :: inst_at_s12e0w_r -emit_at_s12e0w :: emit_at_s12e0w_r -inst_tlbi_vmalle1 :: inst_tlbi_vmalle1_none -emit_tlbi_vmalle1 :: emit_tlbi_vmalle1_none -inst_tlbi_vmalle1is :: inst_tlbi_vmalle1is_none -emit_tlbi_vmalle1is :: emit_tlbi_vmalle1is_none -inst_tlbi_vae1 :: inst_tlbi_vae1_r -emit_tlbi_vae1 :: emit_tlbi_vae1_r -inst_tlbi_vae1is :: inst_tlbi_vae1is_r -emit_tlbi_vae1is :: emit_tlbi_vae1is_r -inst_tlbi_aside1 :: inst_tlbi_aside1_r -emit_tlbi_aside1 :: emit_tlbi_aside1_r -inst_tlbi_aside1is :: inst_tlbi_aside1is_r -emit_tlbi_aside1is :: emit_tlbi_aside1is_r -inst_tlbi_vaae1 :: inst_tlbi_vaae1_r -emit_tlbi_vaae1 :: emit_tlbi_vaae1_r -inst_tlbi_vaae1is :: inst_tlbi_vaae1is_r -emit_tlbi_vaae1is :: emit_tlbi_vaae1is_r -inst_tlbi_vale1 :: inst_tlbi_vale1_r -emit_tlbi_vale1 :: emit_tlbi_vale1_r -inst_tlbi_vale1is :: inst_tlbi_vale1is_r -emit_tlbi_vale1is :: emit_tlbi_vale1is_r -inst_tlbi_vaale1 :: inst_tlbi_vaale1_r -emit_tlbi_vaale1 :: emit_tlbi_vaale1_r -inst_tlbi_vaale1is :: inst_tlbi_vaale1is_r -emit_tlbi_vaale1is :: emit_tlbi_vaale1is_r -inst_tlbi_alle1 :: inst_tlbi_alle1_none -emit_tlbi_alle1 :: emit_tlbi_alle1_none -inst_tlbi_alle1is :: inst_tlbi_alle1is_none -emit_tlbi_alle1is :: emit_tlbi_alle1is_none -inst_tlbi_alle2 :: inst_tlbi_alle2_none -emit_tlbi_alle2 :: emit_tlbi_alle2_none -inst_tlbi_alle2is :: inst_tlbi_alle2is_none -emit_tlbi_alle2is :: emit_tlbi_alle2is_none -inst_tlbi_alle3 :: inst_tlbi_alle3_none -emit_tlbi_alle3 :: emit_tlbi_alle3_none -inst_tlbi_alle3is :: inst_tlbi_alle3is_none -emit_tlbi_alle3is :: emit_tlbi_alle3is_none -inst_prfm :: inst_prfm_i_m -emit_prfm :: emit_prfm_i_m -inst_prfum :: inst_prfum_i_m -emit_prfum :: emit_prfum_i_m -inst_prfm_lit :: inst_prfm_lit_i_l -emit_prfm_lit :: emit_prfm_lit_i_l -inst_mov_reg :: inst_mov_reg_r_r -emit_mov_reg :: emit_mov_reg_r_r -inst_mvn :: inst_mvn_r_r -emit_mvn :: emit_mvn_r_r -inst_cmp_imm :: inst_cmp_imm_r_i -emit_cmp_imm :: emit_cmp_imm_r_i -inst_cmn_imm :: inst_cmn_imm_r_i -emit_cmn_imm :: emit_cmn_imm_r_i +inst_add_imm :: inst_add_imm_r_r_i +emit_add_imm :: emit_add_imm_r_r_i +inst_adds_imm :: inst_adds_imm_r_r_i +emit_adds_imm :: emit_adds_imm_r_r_i +inst_sub_imm :: inst_sub_imm_r_r_i +emit_sub_imm :: emit_sub_imm_r_r_i +inst_subs_imm :: inst_subs_imm_r_r_i +emit_subs_imm :: emit_subs_imm_r_r_i +inst_movz :: inst_movz_r_i_i +emit_movz :: emit_movz_r_i_i +inst_movn :: inst_movn_r_i_i +emit_movn :: emit_movn_r_i_i +inst_movk :: inst_movk_r_i_i +emit_movk :: emit_movk_r_i_i +inst_adr :: inst_adr_r_l +emit_adr :: emit_adr_r_l +inst_adrp :: inst_adrp_r_l +emit_adrp :: emit_adrp_r_l +inst_add_sr :: inst_add_sr_r_r_sh +emit_add_sr :: emit_add_sr_r_r_sh +inst_adds_sr :: inst_adds_sr_r_r_sh +emit_adds_sr :: emit_adds_sr_r_r_sh +inst_sub_sr :: inst_sub_sr_r_r_sh +emit_sub_sr :: emit_sub_sr_r_r_sh +inst_subs_sr :: inst_subs_sr_r_r_sh +emit_subs_sr :: emit_subs_sr_r_r_sh +inst_and_sr :: inst_and_sr_r_r_sh +emit_and_sr :: emit_and_sr_r_r_sh +inst_ands_sr :: inst_ands_sr_r_r_sh +emit_ands_sr :: emit_ands_sr_r_r_sh +inst_orr_sr :: inst_orr_sr_r_r_sh +emit_orr_sr :: emit_orr_sr_r_r_sh +inst_eor_sr :: inst_eor_sr_r_r_sh +emit_eor_sr :: emit_eor_sr_r_r_sh +inst_bic_sr :: inst_bic_sr_r_r_sh +emit_bic_sr :: emit_bic_sr_r_r_sh +inst_bics_sr :: inst_bics_sr_r_r_sh +emit_bics_sr :: emit_bics_sr_r_r_sh +inst_orn_sr :: inst_orn_sr_r_r_sh +emit_orn_sr :: emit_orn_sr_r_r_sh +inst_eon_sr :: inst_eon_sr_r_r_sh +emit_eon_sr :: emit_eon_sr_r_r_sh +inst_add_er :: inst_add_er_r_r_ex +emit_add_er :: emit_add_er_r_r_ex +inst_adds_er :: inst_adds_er_r_r_ex +emit_adds_er :: emit_adds_er_r_r_ex +inst_sub_er :: inst_sub_er_r_r_ex +emit_sub_er :: emit_sub_er_r_r_ex +inst_subs_er :: inst_subs_er_r_r_ex +emit_subs_er :: emit_subs_er_r_r_ex +inst_lslv :: inst_lslv_r_r_r +emit_lslv :: emit_lslv_r_r_r +inst_lsrv :: inst_lsrv_r_r_r +emit_lsrv :: emit_lsrv_r_r_r +inst_asrv :: inst_asrv_r_r_r +emit_asrv :: emit_asrv_r_r_r +inst_rorv :: inst_rorv_r_r_r +emit_rorv :: emit_rorv_r_r_r +inst_udiv :: inst_udiv_r_r_r +emit_udiv :: emit_udiv_r_r_r +inst_sdiv :: inst_sdiv_r_r_r +emit_sdiv :: emit_sdiv_r_r_r +inst_madd :: inst_madd_r_r_r_r +emit_madd :: emit_madd_r_r_r_r +inst_msub :: inst_msub_r_r_r_r +emit_msub :: emit_msub_r_r_r_r +inst_smaddl :: inst_smaddl_r_r_r_r +emit_smaddl :: emit_smaddl_r_r_r_r +inst_smsubl :: inst_smsubl_r_r_r_r +emit_smsubl :: emit_smsubl_r_r_r_r +inst_umaddl :: inst_umaddl_r_r_r_r +emit_umaddl :: emit_umaddl_r_r_r_r +inst_umsubl :: inst_umsubl_r_r_r_r +emit_umsubl :: emit_umsubl_r_r_r_r +inst_smulh :: inst_smulh_r_r_r +emit_smulh :: emit_smulh_r_r_r +inst_umulh :: inst_umulh_r_r_r +emit_umulh :: emit_umulh_r_r_r +inst_clz :: inst_clz_r_r +emit_clz :: emit_clz_r_r +inst_cls :: inst_cls_r_r +emit_cls :: emit_cls_r_r +inst_rbit :: inst_rbit_r_r +emit_rbit :: emit_rbit_r_r +inst_rev :: inst_rev_r_r +emit_rev :: emit_rev_r_r +inst_rev16 :: inst_rev16_r_r +emit_rev16 :: emit_rev16_r_r +inst_rev32 :: inst_rev32_r_r +emit_rev32 :: emit_rev32_r_r +inst_csel :: inst_csel_r_r_r_c +emit_csel :: emit_csel_r_r_r_c +inst_csinc :: inst_csinc_r_r_r_c +emit_csinc :: emit_csinc_r_r_r_c +inst_csinv :: inst_csinv_r_r_r_c +emit_csinv :: emit_csinv_r_r_r_c +inst_csneg :: inst_csneg_r_r_r_c +emit_csneg :: emit_csneg_r_r_r_c +inst_extr :: inst_extr_r_r_r_i +emit_extr :: emit_extr_r_r_r_i +inst_b :: inst_b_l +emit_b :: emit_b_l +inst_bl :: inst_bl_l +emit_bl :: emit_bl_l +inst_br :: inst_br_r +emit_br :: emit_br_r +inst_blr :: inst_blr_r +emit_blr :: emit_blr_r +inst_ret :: proc{ inst_ret_r, inst_ret_none } +emit_ret :: proc{ emit_ret_r, emit_ret_none } +inst_b_cond :: inst_b_cond_c_l +emit_b_cond :: emit_b_cond_c_l +inst_cbz :: inst_cbz_r_l +emit_cbz :: emit_cbz_r_l +inst_cbnz :: inst_cbnz_r_l +emit_cbnz :: emit_cbnz_r_l +inst_tbz :: inst_tbz_r_i_l +emit_tbz :: emit_tbz_r_i_l +inst_tbnz :: inst_tbnz_r_i_l +emit_tbnz :: emit_tbnz_r_i_l +inst_ldr :: inst_ldr_r_m +emit_ldr :: emit_ldr_r_m +inst_str :: inst_str_r_m +emit_str :: emit_str_r_m +inst_ldrb :: inst_ldrb_r_m +emit_ldrb :: emit_ldrb_r_m +inst_strb :: inst_strb_r_m +emit_strb :: emit_strb_r_m +inst_ldrsb :: inst_ldrsb_r_m +emit_ldrsb :: emit_ldrsb_r_m +inst_ldrh :: inst_ldrh_r_m +emit_ldrh :: emit_ldrh_r_m +inst_strh :: inst_strh_r_m +emit_strh :: emit_strh_r_m +inst_ldrsh :: inst_ldrsh_r_m +emit_ldrsh :: emit_ldrsh_r_m +inst_ldrsw :: inst_ldrsw_r_m +emit_ldrsw :: emit_ldrsw_r_m +inst_ldp :: inst_ldp_r_r_m +emit_ldp :: emit_ldp_r_r_m +inst_stp :: inst_stp_r_r_m +emit_stp :: emit_stp_r_r_m +inst_ldpsw :: inst_ldpsw_r_r_m +emit_ldpsw :: emit_ldpsw_r_r_m +inst_ldr_lit :: inst_ldr_lit_r_l +emit_ldr_lit :: emit_ldr_lit_r_l +inst_ldar :: inst_ldar_r_m +emit_ldar :: emit_ldar_r_m +inst_stlr :: inst_stlr_r_m +emit_stlr :: emit_stlr_r_m +inst_ldarb :: inst_ldarb_r_m +emit_ldarb :: emit_ldarb_r_m +inst_stlrb :: inst_stlrb_r_m +emit_stlrb :: emit_stlrb_r_m +inst_ldarh :: inst_ldarh_r_m +emit_ldarh :: emit_ldarh_r_m +inst_stlrh :: inst_stlrh_r_m +emit_stlrh :: emit_stlrh_r_m +inst_ldxr :: inst_ldxr_r_m +emit_ldxr :: emit_ldxr_r_m +inst_stxr :: inst_stxr_r_r_m +emit_stxr :: emit_stxr_r_r_m +inst_ldaxr :: inst_ldaxr_r_m +emit_ldaxr :: emit_ldaxr_r_m +inst_stlxr :: inst_stlxr_r_r_m +emit_stlxr :: emit_stlxr_r_r_m +inst_nop :: inst_nop_none +emit_nop :: emit_nop_none +inst_yield :: inst_yield_none +emit_yield :: emit_yield_none +inst_wfe :: inst_wfe_none +emit_wfe :: emit_wfe_none +inst_wfi :: inst_wfi_none +emit_wfi :: emit_wfi_none +inst_sev :: inst_sev_none +emit_sev :: emit_sev_none +inst_sevl :: inst_sevl_none +emit_sevl :: emit_sevl_none +inst_mrs :: inst_mrs_r_i +emit_mrs :: emit_mrs_r_i +inst_msr_reg :: inst_msr_reg_i_r +emit_msr_reg :: emit_msr_reg_i_r +inst_isb :: inst_isb_i +emit_isb :: emit_isb_i +inst_dsb :: inst_dsb_i +emit_dsb :: emit_dsb_i +inst_dmb :: inst_dmb_i +emit_dmb :: emit_dmb_i +inst_svc :: inst_svc_i +emit_svc :: emit_svc_i +inst_hvc :: inst_hvc_i +emit_hvc :: emit_hvc_i +inst_smc :: inst_smc_i +emit_smc :: emit_smc_i +inst_brk :: inst_brk_i +emit_brk :: emit_brk_i +inst_hlt :: inst_hlt_i +emit_hlt :: emit_hlt_i +inst_eret :: inst_eret_none +emit_eret :: emit_eret_none +inst_fmov_reg :: inst_fmov_reg_r_r +emit_fmov_reg :: emit_fmov_reg_r_r +inst_fmov_gen :: inst_fmov_gen_r_r +emit_fmov_gen :: emit_fmov_gen_r_r +inst_fabs :: inst_fabs_r_r +emit_fabs :: emit_fabs_r_r +inst_fneg :: inst_fneg_r_r +emit_fneg :: emit_fneg_r_r +inst_fsqrt :: inst_fsqrt_r_r +emit_fsqrt :: emit_fsqrt_r_r +inst_fadd :: inst_fadd_r_r_r +emit_fadd :: emit_fadd_r_r_r +inst_fsub :: inst_fsub_r_r_r +emit_fsub :: emit_fsub_r_r_r +inst_fmul :: inst_fmul_r_r_r +emit_fmul :: emit_fmul_r_r_r +inst_fdiv :: inst_fdiv_r_r_r +emit_fdiv :: emit_fdiv_r_r_r +inst_fnmul :: inst_fnmul_r_r_r +emit_fnmul :: emit_fnmul_r_r_r +inst_fmadd :: inst_fmadd_r_r_r_r +emit_fmadd :: emit_fmadd_r_r_r_r +inst_fmsub :: inst_fmsub_r_r_r_r +emit_fmsub :: emit_fmsub_r_r_r_r +inst_fnmadd :: inst_fnmadd_r_r_r_r +emit_fnmadd :: emit_fnmadd_r_r_r_r +inst_fnmsub :: inst_fnmsub_r_r_r_r +emit_fnmsub :: emit_fnmsub_r_r_r_r +inst_fcmp :: inst_fcmp_r_r +emit_fcmp :: emit_fcmp_r_r +inst_fcmpe :: inst_fcmpe_r_r +emit_fcmpe :: emit_fcmpe_r_r +inst_fcsel :: inst_fcsel_r_r_r_c +emit_fcsel :: emit_fcsel_r_r_r_c +inst_fmax :: inst_fmax_r_r_r +emit_fmax :: emit_fmax_r_r_r +inst_fmin :: inst_fmin_r_r_r +emit_fmin :: emit_fmin_r_r_r +inst_fmaxnm :: inst_fmaxnm_r_r_r +emit_fmaxnm :: emit_fmaxnm_r_r_r +inst_fminnm :: inst_fminnm_r_r_r +emit_fminnm :: emit_fminnm_r_r_r +inst_fcvt :: inst_fcvt_r_r +emit_fcvt :: emit_fcvt_r_r +inst_scvtf :: inst_scvtf_r_r +emit_scvtf :: emit_scvtf_r_r +inst_ucvtf :: inst_ucvtf_r_r +emit_ucvtf :: emit_ucvtf_r_r +inst_fcvtzs :: inst_fcvtzs_r_r +emit_fcvtzs :: emit_fcvtzs_r_r +inst_fcvtzu :: inst_fcvtzu_r_r +emit_fcvtzu :: emit_fcvtzu_r_r +inst_and_imm :: inst_and_imm_r_r_i +emit_and_imm :: emit_and_imm_r_r_i +inst_ands_imm :: inst_ands_imm_r_r_i +emit_ands_imm :: emit_ands_imm_r_r_i +inst_orr_imm :: inst_orr_imm_r_r_i +emit_orr_imm :: emit_orr_imm_r_r_i +inst_eor_imm :: inst_eor_imm_r_r_i +emit_eor_imm :: emit_eor_imm_r_r_i +inst_tst_imm :: inst_tst_imm_r_i +emit_tst_imm :: emit_tst_imm_r_i +inst_ldur :: inst_ldur_r_m +emit_ldur :: emit_ldur_r_m +inst_stur :: inst_stur_r_m +emit_stur :: emit_stur_r_m +inst_ldurb :: inst_ldurb_r_m +emit_ldurb :: emit_ldurb_r_m +inst_sturb :: inst_sturb_r_m +emit_sturb :: emit_sturb_r_m +inst_ldursb :: inst_ldursb_r_m +emit_ldursb :: emit_ldursb_r_m +inst_ldurh :: inst_ldurh_r_m +emit_ldurh :: emit_ldurh_r_m +inst_sturh :: inst_sturh_r_m +emit_sturh :: emit_sturh_r_m +inst_ldursh :: inst_ldursh_r_m +emit_ldursh :: emit_ldursh_r_m +inst_ldursw :: inst_ldursw_r_m +emit_ldursw :: emit_ldursw_r_m +inst_ldr_pre :: inst_ldr_pre_r_m +emit_ldr_pre :: emit_ldr_pre_r_m +inst_str_pre :: inst_str_pre_r_m +emit_str_pre :: emit_str_pre_r_m +inst_ldr_post :: inst_ldr_post_r_m +emit_ldr_post :: emit_ldr_post_r_m +inst_str_post :: inst_str_post_r_m +emit_str_post :: emit_str_post_r_m +inst_ldr_reg :: inst_ldr_reg_r_m +emit_ldr_reg :: emit_ldr_reg_r_m +inst_str_reg :: inst_str_reg_r_m +emit_str_reg :: emit_str_reg_r_m +inst_ldp_pre :: inst_ldp_pre_r_r_m +emit_ldp_pre :: emit_ldp_pre_r_r_m +inst_stp_pre :: inst_stp_pre_r_r_m +emit_stp_pre :: emit_stp_pre_r_r_m +inst_ldp_post :: inst_ldp_post_r_r_m +emit_ldp_post :: emit_ldp_post_r_r_m +inst_stp_post :: inst_stp_post_r_r_m +emit_stp_post :: emit_stp_post_r_r_m +inst_ldpsw_pre :: inst_ldpsw_pre_r_r_m +emit_ldpsw_pre :: emit_ldpsw_pre_r_r_m +inst_ldpsw_post :: inst_ldpsw_post_r_r_m +emit_ldpsw_post :: emit_ldpsw_post_r_r_m +inst_ldnp :: inst_ldnp_r_r_m +emit_ldnp :: emit_ldnp_r_r_m +inst_stnp :: inst_stnp_r_r_m +emit_stnp :: emit_stnp_r_r_m +inst_ldxp :: inst_ldxp_r_r_m +emit_ldxp :: emit_ldxp_r_r_m +inst_stxp :: inst_stxp_r_r_r_m +emit_stxp :: emit_stxp_r_r_r_m +inst_ldaxp :: inst_ldaxp_r_r_m +emit_ldaxp :: emit_ldaxp_r_r_m +inst_stlxp :: inst_stlxp_r_r_r_m +emit_stlxp :: emit_stlxp_r_r_r_m +inst_ldxrb :: inst_ldxrb_r_m +emit_ldxrb :: emit_ldxrb_r_m +inst_stxrb :: inst_stxrb_r_r_m +emit_stxrb :: emit_stxrb_r_r_m +inst_ldaxrb :: inst_ldaxrb_r_m +emit_ldaxrb :: emit_ldaxrb_r_m +inst_stlxrb :: inst_stlxrb_r_r_m +emit_stlxrb :: emit_stlxrb_r_r_m +inst_ldxrh :: inst_ldxrh_r_m +emit_ldxrh :: emit_ldxrh_r_m +inst_stxrh :: inst_stxrh_r_r_m +emit_stxrh :: emit_stxrh_r_r_m +inst_ldaxrh :: inst_ldaxrh_r_m +emit_ldaxrh :: emit_ldaxrh_r_m +inst_stlxrh :: inst_stlxrh_r_r_m +emit_stlxrh :: emit_stlxrh_r_r_m +inst_ldapr :: inst_ldapr_r_m +emit_ldapr :: emit_ldapr_r_m +inst_ldaprb :: inst_ldaprb_r_m +emit_ldaprb :: emit_ldaprb_r_m +inst_ldaprh :: inst_ldaprh_r_m +emit_ldaprh :: emit_ldaprh_r_m +inst_ldadd :: inst_ldadd_r_r_m +emit_ldadd :: emit_ldadd_r_r_m +inst_ldadda :: inst_ldadda_r_r_m +emit_ldadda :: emit_ldadda_r_r_m +inst_ldaddl :: inst_ldaddl_r_r_m +emit_ldaddl :: emit_ldaddl_r_r_m +inst_ldaddal :: inst_ldaddal_r_r_m +emit_ldaddal :: emit_ldaddal_r_r_m +inst_ldclr :: inst_ldclr_r_r_m +emit_ldclr :: emit_ldclr_r_r_m +inst_ldclra :: inst_ldclra_r_r_m +emit_ldclra :: emit_ldclra_r_r_m +inst_ldclrl :: inst_ldclrl_r_r_m +emit_ldclrl :: emit_ldclrl_r_r_m +inst_ldclral :: inst_ldclral_r_r_m +emit_ldclral :: emit_ldclral_r_r_m +inst_ldeor :: inst_ldeor_r_r_m +emit_ldeor :: emit_ldeor_r_r_m +inst_ldeora :: inst_ldeora_r_r_m +emit_ldeora :: emit_ldeora_r_r_m +inst_ldeorl :: inst_ldeorl_r_r_m +emit_ldeorl :: emit_ldeorl_r_r_m +inst_ldeoral :: inst_ldeoral_r_r_m +emit_ldeoral :: emit_ldeoral_r_r_m +inst_ldset :: inst_ldset_r_r_m +emit_ldset :: emit_ldset_r_r_m +inst_ldseta :: inst_ldseta_r_r_m +emit_ldseta :: emit_ldseta_r_r_m +inst_ldsetl :: inst_ldsetl_r_r_m +emit_ldsetl :: emit_ldsetl_r_r_m +inst_ldsetal :: inst_ldsetal_r_r_m +emit_ldsetal :: emit_ldsetal_r_r_m +inst_ldsmax :: inst_ldsmax_r_r_m +emit_ldsmax :: emit_ldsmax_r_r_m +inst_ldsmaxa :: inst_ldsmaxa_r_r_m +emit_ldsmaxa :: emit_ldsmaxa_r_r_m +inst_ldsmaxl :: inst_ldsmaxl_r_r_m +emit_ldsmaxl :: emit_ldsmaxl_r_r_m +inst_ldsmaxal :: inst_ldsmaxal_r_r_m +emit_ldsmaxal :: emit_ldsmaxal_r_r_m +inst_ldsmin :: inst_ldsmin_r_r_m +emit_ldsmin :: emit_ldsmin_r_r_m +inst_ldsmina :: inst_ldsmina_r_r_m +emit_ldsmina :: emit_ldsmina_r_r_m +inst_ldsminl :: inst_ldsminl_r_r_m +emit_ldsminl :: emit_ldsminl_r_r_m +inst_ldsminal :: inst_ldsminal_r_r_m +emit_ldsminal :: emit_ldsminal_r_r_m +inst_ldumax :: inst_ldumax_r_r_m +emit_ldumax :: emit_ldumax_r_r_m +inst_ldumaxa :: inst_ldumaxa_r_r_m +emit_ldumaxa :: emit_ldumaxa_r_r_m +inst_ldumaxl :: inst_ldumaxl_r_r_m +emit_ldumaxl :: emit_ldumaxl_r_r_m +inst_ldumaxal :: inst_ldumaxal_r_r_m +emit_ldumaxal :: emit_ldumaxal_r_r_m +inst_ldumin :: inst_ldumin_r_r_m +emit_ldumin :: emit_ldumin_r_r_m +inst_ldumina :: inst_ldumina_r_r_m +emit_ldumina :: emit_ldumina_r_r_m +inst_lduminl :: inst_lduminl_r_r_m +emit_lduminl :: emit_lduminl_r_r_m +inst_lduminal :: inst_lduminal_r_r_m +emit_lduminal :: emit_lduminal_r_r_m +inst_swp :: inst_swp_r_r_m +emit_swp :: emit_swp_r_r_m +inst_swpa :: inst_swpa_r_r_m +emit_swpa :: emit_swpa_r_r_m +inst_swpl :: inst_swpl_r_r_m +emit_swpl :: emit_swpl_r_r_m +inst_swpal :: inst_swpal_r_r_m +emit_swpal :: emit_swpal_r_r_m +inst_cas :: inst_cas_r_r_m +emit_cas :: emit_cas_r_r_m +inst_casa :: inst_casa_r_r_m +emit_casa :: emit_casa_r_r_m +inst_casl :: inst_casl_r_r_m +emit_casl :: emit_casl_r_r_m +inst_casal :: inst_casal_r_r_m +emit_casal :: emit_casal_r_r_m +inst_casb :: inst_casb_r_r_m +emit_casb :: emit_casb_r_r_m +inst_casab :: inst_casab_r_r_m +emit_casab :: emit_casab_r_r_m +inst_caslb :: inst_caslb_r_r_m +emit_caslb :: emit_caslb_r_r_m +inst_casalb :: inst_casalb_r_r_m +emit_casalb :: emit_casalb_r_r_m +inst_cash :: inst_cash_r_r_m +emit_cash :: emit_cash_r_r_m +inst_casah :: inst_casah_r_r_m +emit_casah :: emit_casah_r_r_m +inst_caslh :: inst_caslh_r_r_m +emit_caslh :: emit_caslh_r_r_m +inst_casalh :: inst_casalh_r_r_m +emit_casalh :: emit_casalh_r_r_m +inst_casp :: inst_casp_r_r_m +emit_casp :: emit_casp_r_r_m +inst_caspa :: inst_caspa_r_r_m +emit_caspa :: emit_caspa_r_r_m +inst_caspl :: inst_caspl_r_r_m +emit_caspl :: emit_caspl_r_r_m +inst_caspal :: inst_caspal_r_r_m +emit_caspal :: emit_caspal_r_r_m +inst_pacia :: inst_pacia_r_r +emit_pacia :: emit_pacia_r_r +inst_pacib :: inst_pacib_r_r +emit_pacib :: emit_pacib_r_r +inst_pacda :: inst_pacda_r_r +emit_pacda :: emit_pacda_r_r +inst_pacdb :: inst_pacdb_r_r +emit_pacdb :: emit_pacdb_r_r +inst_paciza :: inst_paciza_r +emit_paciza :: emit_paciza_r +inst_pacizb :: inst_pacizb_r +emit_pacizb :: emit_pacizb_r +inst_pacdza :: inst_pacdza_r +emit_pacdza :: emit_pacdza_r +inst_pacdzb :: inst_pacdzb_r +emit_pacdzb :: emit_pacdzb_r +inst_autia :: inst_autia_r_r +emit_autia :: emit_autia_r_r +inst_autib :: inst_autib_r_r +emit_autib :: emit_autib_r_r +inst_autda :: inst_autda_r_r +emit_autda :: emit_autda_r_r +inst_autdb :: inst_autdb_r_r +emit_autdb :: emit_autdb_r_r +inst_autiza :: inst_autiza_r +emit_autiza :: emit_autiza_r +inst_autizb :: inst_autizb_r +emit_autizb :: emit_autizb_r +inst_autdza :: inst_autdza_r +emit_autdza :: emit_autdza_r +inst_autdzb :: inst_autdzb_r +emit_autdzb :: emit_autdzb_r +inst_paciasp :: inst_paciasp_none +emit_paciasp :: emit_paciasp_none +inst_pacibsp :: inst_pacibsp_none +emit_pacibsp :: emit_pacibsp_none +inst_autiasp :: inst_autiasp_none +emit_autiasp :: emit_autiasp_none +inst_autibsp :: inst_autibsp_none +emit_autibsp :: emit_autibsp_none +inst_pacia1716 :: inst_pacia1716_none +emit_pacia1716 :: emit_pacia1716_none +inst_pacib1716 :: inst_pacib1716_none +emit_pacib1716 :: emit_pacib1716_none +inst_autia1716 :: inst_autia1716_none +emit_autia1716 :: emit_autia1716_none +inst_autib1716 :: inst_autib1716_none +emit_autib1716 :: emit_autib1716_none +inst_pacga :: inst_pacga_r_r_r +emit_pacga :: emit_pacga_r_r_r +inst_xpaci :: inst_xpaci_r +emit_xpaci :: emit_xpaci_r +inst_xpacd :: inst_xpacd_r +emit_xpacd :: emit_xpacd_r +inst_xpaclri :: inst_xpaclri_none +emit_xpaclri :: emit_xpaclri_none +inst_retaa :: inst_retaa_none +emit_retaa :: emit_retaa_none +inst_retab :: inst_retab_none +emit_retab :: emit_retab_none +inst_braa :: inst_braa_r_r +emit_braa :: emit_braa_r_r +inst_brab :: inst_brab_r_r +emit_brab :: emit_brab_r_r +inst_braaz :: inst_braaz_r +emit_braaz :: emit_braaz_r +inst_brabz :: inst_brabz_r +emit_brabz :: emit_brabz_r +inst_blraa :: inst_blraa_r_r +emit_blraa :: emit_blraa_r_r +inst_blrab :: inst_blrab_r_r +emit_blrab :: emit_blrab_r_r +inst_blraaz :: inst_blraaz_r +emit_blraaz :: emit_blraaz_r +inst_blrabz :: inst_blrabz_r +emit_blrabz :: emit_blrabz_r +inst_eretaa :: inst_eretaa_none +emit_eretaa :: emit_eretaa_none +inst_eretab :: inst_eretab_none +emit_eretab :: emit_eretab_none +inst_bti :: inst_bti_i +emit_bti :: emit_bti_i +inst_irg :: inst_irg_r_r_r +emit_irg :: emit_irg_r_r_r +inst_addg :: inst_addg_r_r_i_i +emit_addg :: emit_addg_r_r_i_i +inst_subg :: inst_subg_r_r_i_i +emit_subg :: emit_subg_r_r_i_i +inst_gmi :: inst_gmi_r_r_r +emit_gmi :: emit_gmi_r_r_r +inst_subp :: inst_subp_r_r_r +emit_subp :: emit_subp_r_r_r +inst_subps :: inst_subps_r_r_r +emit_subps :: emit_subps_r_r_r +inst_ldg :: inst_ldg_r_m +emit_ldg :: emit_ldg_r_m +inst_stg :: inst_stg_r_m +emit_stg :: emit_stg_r_m +inst_st2g :: inst_st2g_r_m +emit_st2g :: emit_st2g_r_m +inst_stzg :: inst_stzg_r_m +emit_stzg :: emit_stzg_r_m +inst_stz2g :: inst_stz2g_r_m +emit_stz2g :: emit_stz2g_r_m +inst_stgp :: inst_stgp_r_r_m +emit_stgp :: emit_stgp_r_r_m +inst_ldgm :: inst_ldgm_r_m +emit_ldgm :: emit_ldgm_r_m +inst_stgm :: inst_stgm_r_m +emit_stgm :: emit_stgm_r_m +inst_stzgm :: inst_stzgm_r_m +emit_stzgm :: emit_stzgm_r_m +inst_crc32b :: inst_crc32b_r_r_r +emit_crc32b :: emit_crc32b_r_r_r +inst_crc32h :: inst_crc32h_r_r_r +emit_crc32h :: emit_crc32h_r_r_r +inst_crc32w :: inst_crc32w_r_r_r +emit_crc32w :: emit_crc32w_r_r_r +inst_crc32x :: inst_crc32x_r_r_r +emit_crc32x :: emit_crc32x_r_r_r +inst_crc32cb :: inst_crc32cb_r_r_r +emit_crc32cb :: emit_crc32cb_r_r_r +inst_crc32ch :: inst_crc32ch_r_r_r +emit_crc32ch :: emit_crc32ch_r_r_r +inst_crc32cw :: inst_crc32cw_r_r_r +emit_crc32cw :: emit_crc32cw_r_r_r +inst_crc32cx :: inst_crc32cx_r_r_r +emit_crc32cx :: emit_crc32cx_r_r_r +inst_aese :: inst_aese_r_r +emit_aese :: emit_aese_r_r +inst_aesd :: inst_aesd_r_r +emit_aesd :: emit_aesd_r_r +inst_aesmc :: inst_aesmc_r_r +emit_aesmc :: emit_aesmc_r_r +inst_aesimc :: inst_aesimc_r_r +emit_aesimc :: emit_aesimc_r_r +inst_sha1h :: inst_sha1h_r_r +emit_sha1h :: emit_sha1h_r_r +inst_sha1c :: inst_sha1c_r_r_r +emit_sha1c :: emit_sha1c_r_r_r +inst_sha1p :: inst_sha1p_r_r_r +emit_sha1p :: emit_sha1p_r_r_r +inst_sha1m :: inst_sha1m_r_r_r +emit_sha1m :: emit_sha1m_r_r_r +inst_sha1su0 :: inst_sha1su0_r_r_r +emit_sha1su0 :: emit_sha1su0_r_r_r +inst_sha1su1 :: inst_sha1su1_r_r +emit_sha1su1 :: emit_sha1su1_r_r +inst_sha256h :: inst_sha256h_r_r_r +emit_sha256h :: emit_sha256h_r_r_r +inst_sha256h2 :: inst_sha256h2_r_r_r +emit_sha256h2 :: emit_sha256h2_r_r_r +inst_sha256su0 :: inst_sha256su0_r_r +emit_sha256su0 :: emit_sha256su0_r_r +inst_sha256su1 :: inst_sha256su1_r_r_r +emit_sha256su1 :: emit_sha256su1_r_r_r +inst_sha512h :: inst_sha512h_r_r_r +emit_sha512h :: emit_sha512h_r_r_r +inst_sha512h2 :: inst_sha512h2_r_r_r +emit_sha512h2 :: emit_sha512h2_r_r_r +inst_sha512su0 :: inst_sha512su0_r_r +emit_sha512su0 :: emit_sha512su0_r_r +inst_sha512su1 :: inst_sha512su1_r_r_r +emit_sha512su1 :: emit_sha512su1_r_r_r +inst_eor3 :: inst_eor3_r_r_r_r +emit_eor3 :: emit_eor3_r_r_r_r +inst_bcax :: inst_bcax_r_r_r_r +emit_bcax :: emit_bcax_r_r_r_r +inst_rax1 :: inst_rax1_r_r_r +emit_rax1 :: emit_rax1_r_r_r +inst_xar :: inst_xar_r_r_r_i +emit_xar :: emit_xar_r_r_r_i +inst_sm3partw1 :: inst_sm3partw1_r_r_r +emit_sm3partw1 :: emit_sm3partw1_r_r_r +inst_sm3partw2 :: inst_sm3partw2_r_r_r +emit_sm3partw2 :: emit_sm3partw2_r_r_r +inst_sm3ss1 :: inst_sm3ss1_r_r_r_r +emit_sm3ss1 :: emit_sm3ss1_r_r_r_r +inst_sm3tt1a :: inst_sm3tt1a_r_r_r +emit_sm3tt1a :: emit_sm3tt1a_r_r_r +inst_sm3tt1b :: inst_sm3tt1b_r_r_r +emit_sm3tt1b :: emit_sm3tt1b_r_r_r +inst_sm3tt2a :: inst_sm3tt2a_r_r_r +emit_sm3tt2a :: emit_sm3tt2a_r_r_r +inst_sm3tt2b :: inst_sm3tt2b_r_r_r +emit_sm3tt2b :: emit_sm3tt2b_r_r_r +inst_sm4e :: inst_sm4e_r_r +emit_sm4e :: emit_sm4e_r_r +inst_sm4ekey :: inst_sm4ekey_r_r_r +emit_sm4ekey :: emit_sm4ekey_r_r_r +inst_pmull :: inst_pmull_r_r_r +emit_pmull :: emit_pmull_r_r_r +inst_pmull2 :: inst_pmull2_r_r_r +emit_pmull2 :: emit_pmull2_r_r_r +inst_fabs_h :: inst_fabs_h_r_r +emit_fabs_h :: emit_fabs_h_r_r +inst_fneg_h :: inst_fneg_h_r_r +emit_fneg_h :: emit_fneg_h_r_r +inst_fsqrt_h :: inst_fsqrt_h_r_r +emit_fsqrt_h :: emit_fsqrt_h_r_r +inst_fadd_h :: inst_fadd_h_r_r_r +emit_fadd_h :: emit_fadd_h_r_r_r +inst_fsub_h :: inst_fsub_h_r_r_r +emit_fsub_h :: emit_fsub_h_r_r_r +inst_fmul_h :: inst_fmul_h_r_r_r +emit_fmul_h :: emit_fmul_h_r_r_r +inst_fdiv_h :: inst_fdiv_h_r_r_r +emit_fdiv_h :: emit_fdiv_h_r_r_r +inst_fnmul_h :: inst_fnmul_h_r_r_r +emit_fnmul_h :: emit_fnmul_h_r_r_r +inst_fmadd_h :: inst_fmadd_h_r_r_r_r +emit_fmadd_h :: emit_fmadd_h_r_r_r_r +inst_fmsub_h :: inst_fmsub_h_r_r_r_r +emit_fmsub_h :: emit_fmsub_h_r_r_r_r +inst_fnmadd_h :: inst_fnmadd_h_r_r_r_r +emit_fnmadd_h :: emit_fnmadd_h_r_r_r_r +inst_fnmsub_h :: inst_fnmsub_h_r_r_r_r +emit_fnmsub_h :: emit_fnmsub_h_r_r_r_r +inst_fcmp_h :: inst_fcmp_h_r_r +emit_fcmp_h :: emit_fcmp_h_r_r +inst_fcmpe_h :: inst_fcmpe_h_r_r +emit_fcmpe_h :: emit_fcmpe_h_r_r +inst_fcsel_h :: inst_fcsel_h_r_r_r_c +emit_fcsel_h :: emit_fcsel_h_r_r_r_c +inst_fmax_h :: inst_fmax_h_r_r_r +emit_fmax_h :: emit_fmax_h_r_r_r +inst_fmin_h :: inst_fmin_h_r_r_r +emit_fmin_h :: emit_fmin_h_r_r_r +inst_fmaxnm_h :: inst_fmaxnm_h_r_r_r +emit_fmaxnm_h :: emit_fmaxnm_h_r_r_r +inst_fminnm_h :: inst_fminnm_h_r_r_r +emit_fminnm_h :: emit_fminnm_h_r_r_r +inst_fcvt_h_s :: inst_fcvt_h_s_r_r +emit_fcvt_h_s :: emit_fcvt_h_s_r_r +inst_fcvt_h_d :: inst_fcvt_h_d_r_r +emit_fcvt_h_d :: emit_fcvt_h_d_r_r +inst_fcvt_s_h :: inst_fcvt_s_h_r_r +emit_fcvt_s_h :: emit_fcvt_s_h_r_r +inst_fcvt_d_h :: inst_fcvt_d_h_r_r +emit_fcvt_d_h :: emit_fcvt_d_h_r_r +inst_fmov_h :: inst_fmov_h_r_r +emit_fmov_h :: emit_fmov_h_r_r +inst_scvtf_h :: inst_scvtf_h_r_r +emit_scvtf_h :: emit_scvtf_h_r_r +inst_ucvtf_h :: inst_ucvtf_h_r_r +emit_ucvtf_h :: emit_ucvtf_h_r_r +inst_fcvtzs_h :: inst_fcvtzs_h_r_r +emit_fcvtzs_h :: emit_fcvtzs_h_r_r +inst_fcvtzu_h :: inst_fcvtzu_h_r_r +emit_fcvtzu_h :: emit_fcvtzu_h_r_r +inst_bfcvt :: inst_bfcvt_r_r +emit_bfcvt :: emit_bfcvt_r_r +inst_bfdot :: inst_bfdot_r_r_r +emit_bfdot :: emit_bfdot_r_r_r +inst_bfmmla :: inst_bfmmla_r_r_r +emit_bfmmla :: emit_bfmmla_r_r_r +inst_bfmlalb :: inst_bfmlalb_r_r_r +emit_bfmlalb :: emit_bfmlalb_r_r_r +inst_bfmlalt :: inst_bfmlalt_r_r_r +emit_bfmlalt :: emit_bfmlalt_r_r_r +inst_bfcvtn :: inst_bfcvtn_r_r +emit_bfcvtn :: emit_bfcvtn_r_r +inst_bfcvtn2 :: inst_bfcvtn2_r_r +emit_bfcvtn2 :: emit_bfcvtn2_r_r +inst_add_v :: inst_add_v_r_r_r +emit_add_v :: emit_add_v_r_r_r +inst_sub_v :: inst_sub_v_r_r_r +emit_sub_v :: emit_sub_v_r_r_r +inst_mul_v :: inst_mul_v_r_r_r +emit_mul_v :: emit_mul_v_r_r_r +inst_sdot :: inst_sdot_r_r_r +emit_sdot :: emit_sdot_r_r_r +inst_udot :: inst_udot_r_r_r +emit_udot :: emit_udot_r_r_r +inst_fadd_v :: inst_fadd_v_r_r_r +emit_fadd_v :: emit_fadd_v_r_r_r +inst_fsub_v :: inst_fsub_v_r_r_r +emit_fsub_v :: emit_fsub_v_r_r_r +inst_fmul_v :: inst_fmul_v_r_r_r +emit_fmul_v :: emit_fmul_v_r_r_r +inst_fdiv_v :: inst_fdiv_v_r_r_r +emit_fdiv_v :: emit_fdiv_v_r_r_r +inst_fmla_v :: inst_fmla_v_r_r_r +emit_fmla_v :: emit_fmla_v_r_r_r +inst_fmls_v :: inst_fmls_v_r_r_r +emit_fmls_v :: emit_fmls_v_r_r_r +inst_cmeq :: inst_cmeq_r_r_r +emit_cmeq :: emit_cmeq_r_r_r +inst_cmgt :: inst_cmgt_r_r_r +emit_cmgt :: emit_cmgt_r_r_r +inst_cmhi :: inst_cmhi_r_r_r +emit_cmhi :: emit_cmhi_r_r_r +inst_and_v :: inst_and_v_r_r_r +emit_and_v :: emit_and_v_r_r_r +inst_orr_v :: inst_orr_v_r_r_r +emit_orr_v :: emit_orr_v_r_r_r +inst_eor_v :: inst_eor_v_r_r_r +emit_eor_v :: emit_eor_v_r_r_r +inst_bic_v :: inst_bic_v_r_r_r +emit_bic_v :: emit_bic_v_r_r_r +inst_orn_v :: inst_orn_v_r_r_r +emit_orn_v :: emit_orn_v_r_r_r +inst_bit :: inst_bit_r_r_r +emit_bit :: emit_bit_r_r_r +inst_bif :: inst_bif_r_r_r +emit_bif :: emit_bif_r_r_r +inst_bsl :: inst_bsl_r_r_r +emit_bsl :: emit_bsl_r_r_r +inst_ld1 :: inst_ld1_r_m +emit_ld1 :: emit_ld1_r_m +inst_st1 :: inst_st1_r_m +emit_st1 :: emit_st1_r_m +inst_ldr_v :: inst_ldr_v_r_m +emit_ldr_v :: emit_ldr_v_r_m +inst_str_v :: inst_str_v_r_m +emit_str_v :: emit_str_v_r_m +inst_sve_add_z :: inst_sve_add_z_z_z_z +emit_sve_add_z :: emit_sve_add_z_z_z_z +inst_sve_sub_z :: inst_sve_sub_z_z_z_z +emit_sve_sub_z :: emit_sve_sub_z_z_z_z +inst_sve_sqadd_z :: inst_sve_sqadd_z_z_z_z +emit_sve_sqadd_z :: emit_sve_sqadd_z_z_z_z +inst_sve_uqadd_z :: inst_sve_uqadd_z_z_z_z +emit_sve_uqadd_z :: emit_sve_uqadd_z_z_z_z +inst_sve_sqsub_z :: inst_sve_sqsub_z_z_z_z +emit_sve_sqsub_z :: emit_sve_sqsub_z_z_z_z +inst_sve_uqsub_z :: inst_sve_uqsub_z_z_z_z +emit_sve_uqsub_z :: emit_sve_uqsub_z_z_z_z +inst_sve_add_pred :: inst_sve_add_pred_z_p_z_z +emit_sve_add_pred :: emit_sve_add_pred_z_p_z_z +inst_sve_sub_pred :: inst_sve_sub_pred_z_p_z_z +emit_sve_sub_pred :: emit_sve_sub_pred_z_p_z_z +inst_sve_subr_pred :: inst_sve_subr_pred_z_p_z_z +emit_sve_subr_pred :: emit_sve_subr_pred_z_p_z_z +inst_sve_mul_pred :: inst_sve_mul_pred_z_p_z_z +emit_sve_mul_pred :: emit_sve_mul_pred_z_p_z_z +inst_sve_smulh_pred :: inst_sve_smulh_pred_z_p_z_z +emit_sve_smulh_pred :: emit_sve_smulh_pred_z_p_z_z +inst_sve_umulh_pred :: inst_sve_umulh_pred_z_p_z_z +emit_sve_umulh_pred :: emit_sve_umulh_pred_z_p_z_z +inst_sve_sdiv_pred :: inst_sve_sdiv_pred_z_p_z_z +emit_sve_sdiv_pred :: emit_sve_sdiv_pred_z_p_z_z +inst_sve_udiv_pred :: inst_sve_udiv_pred_z_p_z_z +emit_sve_udiv_pred :: emit_sve_udiv_pred_z_p_z_z +inst_sve_smax_pred :: inst_sve_smax_pred_z_p_z_z +emit_sve_smax_pred :: emit_sve_smax_pred_z_p_z_z +inst_sve_umax_pred :: inst_sve_umax_pred_z_p_z_z +emit_sve_umax_pred :: emit_sve_umax_pred_z_p_z_z +inst_sve_smin_pred :: inst_sve_smin_pred_z_p_z_z +emit_sve_smin_pred :: emit_sve_smin_pred_z_p_z_z +inst_sve_umin_pred :: inst_sve_umin_pred_z_p_z_z +emit_sve_umin_pred :: emit_sve_umin_pred_z_p_z_z +inst_sve_sabd_pred :: inst_sve_sabd_pred_z_p_z_z +emit_sve_sabd_pred :: emit_sve_sabd_pred_z_p_z_z +inst_sve_uabd_pred :: inst_sve_uabd_pred_z_p_z_z +emit_sve_uabd_pred :: emit_sve_uabd_pred_z_p_z_z +inst_sve_and_pred :: inst_sve_and_pred_z_p_z_z +emit_sve_and_pred :: emit_sve_and_pred_z_p_z_z +inst_sve_orr_pred :: inst_sve_orr_pred_z_p_z_z +emit_sve_orr_pred :: emit_sve_orr_pred_z_p_z_z +inst_sve_eor_pred :: inst_sve_eor_pred_z_p_z_z +emit_sve_eor_pred :: emit_sve_eor_pred_z_p_z_z +inst_sve_bic_pred :: inst_sve_bic_pred_z_p_z_z +emit_sve_bic_pred :: emit_sve_bic_pred_z_p_z_z +inst_sve_asr_pred :: inst_sve_asr_pred_z_p_z_z +emit_sve_asr_pred :: emit_sve_asr_pred_z_p_z_z +inst_sve_lsl_pred :: inst_sve_lsl_pred_z_p_z_z +emit_sve_lsl_pred :: emit_sve_lsl_pred_z_p_z_z +inst_sve_lsr_pred :: inst_sve_lsr_pred_z_p_z_z +emit_sve_lsr_pred :: emit_sve_lsr_pred_z_p_z_z +inst_sve_abs_pred :: inst_sve_abs_pred_z_p_z +emit_sve_abs_pred :: emit_sve_abs_pred_z_p_z +inst_sve_neg_pred :: inst_sve_neg_pred_z_p_z +emit_sve_neg_pred :: emit_sve_neg_pred_z_p_z +inst_sve_cls_pred :: inst_sve_cls_pred_z_p_z +emit_sve_cls_pred :: emit_sve_cls_pred_z_p_z +inst_sve_clz_pred :: inst_sve_clz_pred_z_p_z +emit_sve_clz_pred :: emit_sve_clz_pred_z_p_z +inst_sve_cnt_pred :: inst_sve_cnt_pred_z_p_z +emit_sve_cnt_pred :: emit_sve_cnt_pred_z_p_z +inst_sve_fadd_z :: inst_sve_fadd_z_z_z_z +emit_sve_fadd_z :: emit_sve_fadd_z_z_z_z +inst_sve_fsub_z :: inst_sve_fsub_z_z_z_z +emit_sve_fsub_z :: emit_sve_fsub_z_z_z_z +inst_sve_fmul_z :: inst_sve_fmul_z_z_z_z +emit_sve_fmul_z :: emit_sve_fmul_z_z_z_z +inst_sve_frecps :: inst_sve_frecps_z_z_z +emit_sve_frecps :: emit_sve_frecps_z_z_z +inst_sve_frsqrts :: inst_sve_frsqrts_z_z_z +emit_sve_frsqrts :: emit_sve_frsqrts_z_z_z +inst_sve_ftsmul :: inst_sve_ftsmul_z_z_z +emit_sve_ftsmul :: emit_sve_ftsmul_z_z_z +inst_sve_fadd_pred :: inst_sve_fadd_pred_z_p_z_z +emit_sve_fadd_pred :: emit_sve_fadd_pred_z_p_z_z +inst_sve_fsub_pred :: inst_sve_fsub_pred_z_p_z_z +emit_sve_fsub_pred :: emit_sve_fsub_pred_z_p_z_z +inst_sve_fmul_pred :: inst_sve_fmul_pred_z_p_z_z +emit_sve_fmul_pred :: emit_sve_fmul_pred_z_p_z_z +inst_sve_fdiv_pred :: inst_sve_fdiv_pred_z_p_z_z +emit_sve_fdiv_pred :: emit_sve_fdiv_pred_z_p_z_z +inst_sve_fmax_pred :: inst_sve_fmax_pred_z_p_z_z +emit_sve_fmax_pred :: emit_sve_fmax_pred_z_p_z_z +inst_sve_fmin_pred :: inst_sve_fmin_pred_z_p_z_z +emit_sve_fmin_pred :: emit_sve_fmin_pred_z_p_z_z +inst_sve_fmaxnm_pred :: inst_sve_fmaxnm_pred_z_p_z_z +emit_sve_fmaxnm_pred :: emit_sve_fmaxnm_pred_z_p_z_z +inst_sve_fminnm_pred :: inst_sve_fminnm_pred_z_p_z_z +emit_sve_fminnm_pred :: emit_sve_fminnm_pred_z_p_z_z +inst_sve_fabs_z :: inst_sve_fabs_z_z_p_z +emit_sve_fabs_z :: emit_sve_fabs_z_z_p_z +inst_sve_fneg_z :: inst_sve_fneg_z_z_p_z +emit_sve_fneg_z :: emit_sve_fneg_z_z_p_z +inst_sve_fsqrt_z :: inst_sve_fsqrt_z_z_p_z +emit_sve_fsqrt_z :: emit_sve_fsqrt_z_z_p_z +inst_sve_fmla :: inst_sve_fmla_z_p_z_z +emit_sve_fmla :: emit_sve_fmla_z_p_z_z +inst_sve_fmls :: inst_sve_fmls_z_p_z_z +emit_sve_fmls :: emit_sve_fmls_z_p_z_z +inst_sve_fnmla :: inst_sve_fnmla_z_p_z_z +emit_sve_fnmla :: emit_sve_fnmla_z_p_z_z +inst_sve_fnmls :: inst_sve_fnmls_z_p_z_z +emit_sve_fnmls :: emit_sve_fnmls_z_p_z_z +inst_sve_and_p :: inst_sve_and_p_p_p_p_p +emit_sve_and_p :: emit_sve_and_p_p_p_p_p +inst_sve_bic_p :: inst_sve_bic_p_p_p_p_p +emit_sve_bic_p :: emit_sve_bic_p_p_p_p_p +inst_sve_orr_p :: inst_sve_orr_p_p_p_p_p +emit_sve_orr_p :: emit_sve_orr_p_p_p_p_p +inst_sve_eor_p :: inst_sve_eor_p_p_p_p_p +emit_sve_eor_p :: emit_sve_eor_p_p_p_p_p +inst_sve_nand_p :: inst_sve_nand_p_p_p_p_p +emit_sve_nand_p :: emit_sve_nand_p_p_p_p_p +inst_sve_nor_p :: inst_sve_nor_p_p_p_p_p +emit_sve_nor_p :: emit_sve_nor_p_p_p_p_p +inst_sve_orn_p :: inst_sve_orn_p_p_p_p_p +emit_sve_orn_p :: emit_sve_orn_p_p_p_p_p +inst_sve_sel_p :: inst_sve_sel_p_p_p_p_p +emit_sve_sel_p :: emit_sve_sel_p_p_p_p_p +inst_sve_ands_p :: inst_sve_ands_p_p_p_p_p +emit_sve_ands_p :: emit_sve_ands_p_p_p_p_p +inst_sve_bics_p :: inst_sve_bics_p_p_p_p_p +emit_sve_bics_p :: emit_sve_bics_p_p_p_p_p +inst_sve_orrs_p :: inst_sve_orrs_p_p_p_p_p +emit_sve_orrs_p :: emit_sve_orrs_p_p_p_p_p +inst_sve_eors_p :: inst_sve_eors_p_p_p_p_p +emit_sve_eors_p :: emit_sve_eors_p_p_p_p_p +inst_sve_ptrue :: inst_sve_ptrue_p_i +emit_sve_ptrue :: emit_sve_ptrue_p_i +inst_sve_ptrues :: inst_sve_ptrues_p_i +emit_sve_ptrues :: emit_sve_ptrues_p_i +inst_sve_pfalse :: inst_sve_pfalse_p +emit_sve_pfalse :: emit_sve_pfalse_p +inst_sve_pfirst :: inst_sve_pfirst_p_p_p +emit_sve_pfirst :: emit_sve_pfirst_p_p_p +inst_sve_pnext :: inst_sve_pnext_p_p_p +emit_sve_pnext :: emit_sve_pnext_p_p_p +inst_sve_cmpeq :: inst_sve_cmpeq_p_p_z_z +emit_sve_cmpeq :: emit_sve_cmpeq_p_p_z_z +inst_sve_cmpne :: inst_sve_cmpne_p_p_z_z +emit_sve_cmpne :: emit_sve_cmpne_p_p_z_z +inst_sve_cmpge :: inst_sve_cmpge_p_p_z_z +emit_sve_cmpge :: emit_sve_cmpge_p_p_z_z +inst_sve_cmpgt :: inst_sve_cmpgt_p_p_z_z +emit_sve_cmpgt :: emit_sve_cmpgt_p_p_z_z +inst_sve_cmphi :: inst_sve_cmphi_p_p_z_z +emit_sve_cmphi :: emit_sve_cmphi_p_p_z_z +inst_sve_cmphs :: inst_sve_cmphs_p_p_z_z +emit_sve_cmphs :: emit_sve_cmphs_p_p_z_z +inst_sve_dup_z :: inst_sve_dup_z_z_r +emit_sve_dup_z :: emit_sve_dup_z_z_r +inst_sve_rev_z :: inst_sve_rev_z_z_z +emit_sve_rev_z :: emit_sve_rev_z_z_z +inst_sve_rev_p :: inst_sve_rev_p_p_p +emit_sve_rev_p :: emit_sve_rev_p_p_p +inst_sve_tbl :: inst_sve_tbl_z_z_z +emit_sve_tbl :: emit_sve_tbl_z_z_z +inst_sve_zip1_z :: inst_sve_zip1_z_z_z_z +emit_sve_zip1_z :: emit_sve_zip1_z_z_z_z +inst_sve_zip2_z :: inst_sve_zip2_z_z_z_z +emit_sve_zip2_z :: emit_sve_zip2_z_z_z_z +inst_sve_uzp1_z :: inst_sve_uzp1_z_z_z_z +emit_sve_uzp1_z :: emit_sve_uzp1_z_z_z_z +inst_sve_uzp2_z :: inst_sve_uzp2_z_z_z_z +emit_sve_uzp2_z :: emit_sve_uzp2_z_z_z_z +inst_sve_trn1_z :: inst_sve_trn1_z_z_z_z +emit_sve_trn1_z :: emit_sve_trn1_z_z_z_z +inst_sve_trn2_z :: inst_sve_trn2_z_z_z_z +emit_sve_trn2_z :: emit_sve_trn2_z_z_z_z +inst_sve_zip1_p :: inst_sve_zip1_p_p_p_p +emit_sve_zip1_p :: emit_sve_zip1_p_p_p_p +inst_sve_zip2_p :: inst_sve_zip2_p_p_p_p +emit_sve_zip2_p :: emit_sve_zip2_p_p_p_p +inst_sve_uzp1_p :: inst_sve_uzp1_p_p_p_p +emit_sve_uzp1_p :: emit_sve_uzp1_p_p_p_p +inst_sve_uzp2_p :: inst_sve_uzp2_p_p_p_p +emit_sve_uzp2_p :: emit_sve_uzp2_p_p_p_p +inst_sve_trn1_p :: inst_sve_trn1_p_p_p_p +emit_sve_trn1_p :: emit_sve_trn1_p_p_p_p +inst_sve_trn2_p :: inst_sve_trn2_p_p_p_p +emit_sve_trn2_p :: emit_sve_trn2_p_p_p_p +inst_sve_ld1b :: inst_sve_ld1b_z_p_m +emit_sve_ld1b :: emit_sve_ld1b_z_p_m +inst_sve_ld1h :: inst_sve_ld1h_z_p_m +emit_sve_ld1h :: emit_sve_ld1h_z_p_m +inst_sve_ld1w :: inst_sve_ld1w_z_p_m +emit_sve_ld1w :: emit_sve_ld1w_z_p_m +inst_sve_ld1d :: inst_sve_ld1d_z_p_m +emit_sve_ld1d :: emit_sve_ld1d_z_p_m +inst_sve_ld1sb :: inst_sve_ld1sb_z_p_m +emit_sve_ld1sb :: emit_sve_ld1sb_z_p_m +inst_sve_ld1sh :: inst_sve_ld1sh_z_p_m +emit_sve_ld1sh :: emit_sve_ld1sh_z_p_m +inst_sve_ld1sw :: inst_sve_ld1sw_z_p_m +emit_sve_ld1sw :: emit_sve_ld1sw_z_p_m +inst_sve_st1b :: inst_sve_st1b_z_p_m +emit_sve_st1b :: emit_sve_st1b_z_p_m +inst_sve_st1h :: inst_sve_st1h_z_p_m +emit_sve_st1h :: emit_sve_st1h_z_p_m +inst_sve_st1w :: inst_sve_st1w_z_p_m +emit_sve_st1w :: emit_sve_st1w_z_p_m +inst_sve_st1d :: inst_sve_st1d_z_p_m +emit_sve_st1d :: emit_sve_st1d_z_p_m +inst_sve_ldr_z :: inst_sve_ldr_z_z_m +emit_sve_ldr_z :: emit_sve_ldr_z_z_m +inst_sve_str_z :: inst_sve_str_z_z_m +emit_sve_str_z :: emit_sve_str_z_z_m +inst_sve_ldr_p :: inst_sve_ldr_p_p_m +emit_sve_ldr_p :: emit_sve_ldr_p_p_m +inst_sve_str_p :: inst_sve_str_p_p_m +emit_sve_str_p :: emit_sve_str_p_p_m +inst_sve_ldff1b :: inst_sve_ldff1b_z_p_m +emit_sve_ldff1b :: emit_sve_ldff1b_z_p_m +inst_sve_ldff1h :: inst_sve_ldff1h_z_p_m +emit_sve_ldff1h :: emit_sve_ldff1h_z_p_m +inst_sve_ldff1w :: inst_sve_ldff1w_z_p_m +emit_sve_ldff1w :: emit_sve_ldff1w_z_p_m +inst_sve_ldff1d :: inst_sve_ldff1d_z_p_m +emit_sve_ldff1d :: emit_sve_ldff1d_z_p_m +inst_sve_whilege :: inst_sve_whilege_p_r_r +emit_sve_whilege :: emit_sve_whilege_p_r_r +inst_sve_whilegt :: inst_sve_whilegt_p_r_r +emit_sve_whilegt :: emit_sve_whilegt_p_r_r +inst_sve_whilele :: inst_sve_whilele_p_r_r +emit_sve_whilele :: emit_sve_whilele_p_r_r +inst_sve_whilelt :: inst_sve_whilelt_p_r_r +emit_sve_whilelt :: emit_sve_whilelt_p_r_r +inst_sve_whilehi :: inst_sve_whilehi_p_r_r +emit_sve_whilehi :: emit_sve_whilehi_p_r_r +inst_sve_whilehs :: inst_sve_whilehs_p_r_r +emit_sve_whilehs :: emit_sve_whilehs_p_r_r +inst_sve_whilelo :: inst_sve_whilelo_p_r_r +emit_sve_whilelo :: emit_sve_whilelo_p_r_r +inst_sve_whilels :: inst_sve_whilels_p_r_r +emit_sve_whilels :: emit_sve_whilels_p_r_r +inst_sve_sqrdmlah :: inst_sve_sqrdmlah_z_z_z +emit_sve_sqrdmlah :: emit_sve_sqrdmlah_z_z_z +inst_sve_sqrdmlsh :: inst_sve_sqrdmlsh_z_z_z +emit_sve_sqrdmlsh :: emit_sve_sqrdmlsh_z_z_z +inst_sve_adclb :: inst_sve_adclb_z_z_z +emit_sve_adclb :: emit_sve_adclb_z_z_z +inst_sve_adclt :: inst_sve_adclt_z_z_z +emit_sve_adclt :: emit_sve_adclt_z_z_z +inst_sve_sbclb :: inst_sve_sbclb_z_z_z +emit_sve_sbclb :: emit_sve_sbclb_z_z_z +inst_sve_sbclt :: inst_sve_sbclt_z_z_z +emit_sve_sbclt :: emit_sve_sbclt_z_z_z +inst_sve_tbl2 :: inst_sve_tbl2_z_z_z +emit_sve_tbl2 :: emit_sve_tbl2_z_z_z +inst_sve_tbx :: inst_sve_tbx_z_z_z +emit_sve_tbx :: emit_sve_tbx_z_z_z +inst_sve_aese :: inst_sve_aese_z_z +emit_sve_aese :: emit_sve_aese_z_z +inst_sve_aesd :: inst_sve_aesd_z_z +emit_sve_aesd :: emit_sve_aesd_z_z +inst_sve_aesmc :: inst_sve_aesmc_z +emit_sve_aesmc :: emit_sve_aesmc_z +inst_sve_aesimc :: inst_sve_aesimc_z +emit_sve_aesimc :: emit_sve_aesimc_z +inst_sve_match :: inst_sve_match_p_p_z_z +emit_sve_match :: emit_sve_match_p_p_z_z +inst_sve_nmatch :: inst_sve_nmatch_p_p_z_z +emit_sve_nmatch :: emit_sve_nmatch_p_p_z_z +inst_sve_histcnt :: inst_sve_histcnt_z_p_z_z +emit_sve_histcnt :: emit_sve_histcnt_z_p_z_z +inst_sve_histseg :: inst_sve_histseg_z_z_z +emit_sve_histseg :: emit_sve_histseg_z_z_z +inst_sme_smstart :: inst_sme_smstart_none +emit_sme_smstart :: emit_sme_smstart_none +inst_sme_smstop :: inst_sme_smstop_none +emit_sme_smstop :: emit_sme_smstop_none +inst_sme_rdsvl :: inst_sme_rdsvl_r_i +emit_sme_rdsvl :: emit_sme_rdsvl_r_i +inst_sme_zero :: inst_sme_zero_i +emit_sme_zero :: emit_sme_zero_i +inst_sme_fmopa :: inst_sme_fmopa_i_p_p_z +emit_sme_fmopa :: emit_sme_fmopa_i_p_p_z +inst_sme_fmops :: inst_sme_fmops_i_p_p_z +emit_sme_fmops :: emit_sme_fmops_i_p_p_z +inst_sme_bfmopa :: inst_sme_bfmopa_i_p_p_z +emit_sme_bfmopa :: emit_sme_bfmopa_i_p_p_z +inst_sme_bfmops :: inst_sme_bfmops_i_p_p_z +emit_sme_bfmops :: emit_sme_bfmops_i_p_p_z +inst_sme_smopa :: inst_sme_smopa_i_p_p_z +emit_sme_smopa :: emit_sme_smopa_i_p_p_z +inst_sme_smops :: inst_sme_smops_i_p_p_z +emit_sme_smops :: emit_sme_smops_i_p_p_z +inst_sme_umopa :: inst_sme_umopa_i_p_p_z +emit_sme_umopa :: emit_sme_umopa_i_p_p_z +inst_sme_umops :: inst_sme_umops_i_p_p_z +emit_sme_umops :: emit_sme_umops_i_p_p_z +inst_sme_usmopa :: inst_sme_usmopa_i_p_p_z +emit_sme_usmopa :: emit_sme_usmopa_i_p_p_z +inst_sme_sumopa :: inst_sme_sumopa_i_p_p_z +emit_sme_sumopa :: emit_sme_sumopa_i_p_p_z +inst_sme_ldr_za :: inst_sme_ldr_za_i_m +emit_sme_ldr_za :: emit_sme_ldr_za_i_m +inst_sme_str_za :: inst_sme_str_za_i_m +emit_sme_str_za :: emit_sme_str_za_i_m +inst_sve_fmla_idx_h :: inst_sve_fmla_idx_h_z_z_z_i +emit_sve_fmla_idx_h :: emit_sve_fmla_idx_h_z_z_z_i +inst_sve_fmla_idx_s :: inst_sve_fmla_idx_s_z_z_z_i +emit_sve_fmla_idx_s :: emit_sve_fmla_idx_s_z_z_z_i +inst_sve_fmla_idx_d :: inst_sve_fmla_idx_d_z_z_z_i +emit_sve_fmla_idx_d :: emit_sve_fmla_idx_d_z_z_z_i +inst_sve_fmls_idx_h :: inst_sve_fmls_idx_h_z_z_z_i +emit_sve_fmls_idx_h :: emit_sve_fmls_idx_h_z_z_z_i +inst_sve_fmls_idx_s :: inst_sve_fmls_idx_s_z_z_z_i +emit_sve_fmls_idx_s :: emit_sve_fmls_idx_s_z_z_z_i +inst_sve_fmls_idx_d :: inst_sve_fmls_idx_d_z_z_z_i +emit_sve_fmls_idx_d :: emit_sve_fmls_idx_d_z_z_z_i +inst_sve_ld1b_gather_s :: inst_sve_ld1b_gather_s_z_p_m +emit_sve_ld1b_gather_s :: emit_sve_ld1b_gather_s_z_p_m +inst_sve_ld1b_gather_d :: inst_sve_ld1b_gather_d_z_p_m +emit_sve_ld1b_gather_d :: emit_sve_ld1b_gather_d_z_p_m +inst_sve_ld1h_gather_s :: inst_sve_ld1h_gather_s_z_p_m +emit_sve_ld1h_gather_s :: emit_sve_ld1h_gather_s_z_p_m +inst_sve_ld1h_gather_d :: inst_sve_ld1h_gather_d_z_p_m +emit_sve_ld1h_gather_d :: emit_sve_ld1h_gather_d_z_p_m +inst_sve_ld1w_gather_s :: inst_sve_ld1w_gather_s_z_p_m +emit_sve_ld1w_gather_s :: emit_sve_ld1w_gather_s_z_p_m +inst_sve_ld1w_gather_d :: inst_sve_ld1w_gather_d_z_p_m +emit_sve_ld1w_gather_d :: emit_sve_ld1w_gather_d_z_p_m +inst_sve_ld1d_gather_d :: inst_sve_ld1d_gather_d_z_p_m +emit_sve_ld1d_gather_d :: emit_sve_ld1d_gather_d_z_p_m +inst_sve_ld1sb_gather_s :: inst_sve_ld1sb_gather_s_z_p_m +emit_sve_ld1sb_gather_s :: emit_sve_ld1sb_gather_s_z_p_m +inst_sve_ld1sb_gather_d :: inst_sve_ld1sb_gather_d_z_p_m +emit_sve_ld1sb_gather_d :: emit_sve_ld1sb_gather_d_z_p_m +inst_sve_ld1sh_gather_s :: inst_sve_ld1sh_gather_s_z_p_m +emit_sve_ld1sh_gather_s :: emit_sve_ld1sh_gather_s_z_p_m +inst_sve_ld1sh_gather_d :: inst_sve_ld1sh_gather_d_z_p_m +emit_sve_ld1sh_gather_d :: emit_sve_ld1sh_gather_d_z_p_m +inst_sve_ld1sw_gather_d :: inst_sve_ld1sw_gather_d_z_p_m +emit_sve_ld1sw_gather_d :: emit_sve_ld1sw_gather_d_z_p_m +inst_sve_st1b_scatter_s :: inst_sve_st1b_scatter_s_z_p_m +emit_sve_st1b_scatter_s :: emit_sve_st1b_scatter_s_z_p_m +inst_sve_st1b_scatter_d :: inst_sve_st1b_scatter_d_z_p_m +emit_sve_st1b_scatter_d :: emit_sve_st1b_scatter_d_z_p_m +inst_sve_st1h_scatter_s :: inst_sve_st1h_scatter_s_z_p_m +emit_sve_st1h_scatter_s :: emit_sve_st1h_scatter_s_z_p_m +inst_sve_st1h_scatter_d :: inst_sve_st1h_scatter_d_z_p_m +emit_sve_st1h_scatter_d :: emit_sve_st1h_scatter_d_z_p_m +inst_sve_st1w_scatter_s :: inst_sve_st1w_scatter_s_z_p_m +emit_sve_st1w_scatter_s :: emit_sve_st1w_scatter_s_z_p_m +inst_sve_st1w_scatter_d :: inst_sve_st1w_scatter_d_z_p_m +emit_sve_st1w_scatter_d :: emit_sve_st1w_scatter_d_z_p_m +inst_sve_st1d_scatter_d :: inst_sve_st1d_scatter_d_z_p_m +emit_sve_st1d_scatter_d :: emit_sve_st1d_scatter_d_z_p_m +inst_sme_ld1b_tile :: inst_sme_ld1b_tile_i_p_m +emit_sme_ld1b_tile :: emit_sme_ld1b_tile_i_p_m +inst_sme_ld1h_tile :: inst_sme_ld1h_tile_i_p_m +emit_sme_ld1h_tile :: emit_sme_ld1h_tile_i_p_m +inst_sme_ld1w_tile :: inst_sme_ld1w_tile_i_p_m +emit_sme_ld1w_tile :: emit_sme_ld1w_tile_i_p_m +inst_sme_ld1d_tile :: inst_sme_ld1d_tile_i_p_m +emit_sme_ld1d_tile :: emit_sme_ld1d_tile_i_p_m +inst_sme_ld1q_tile :: inst_sme_ld1q_tile_i_p_m +emit_sme_ld1q_tile :: emit_sme_ld1q_tile_i_p_m +inst_sme_st1b_tile :: inst_sme_st1b_tile_i_p_m +emit_sme_st1b_tile :: emit_sme_st1b_tile_i_p_m +inst_sme_st1h_tile :: inst_sme_st1h_tile_i_p_m +emit_sme_st1h_tile :: emit_sme_st1h_tile_i_p_m +inst_sme_st1w_tile :: inst_sme_st1w_tile_i_p_m +emit_sme_st1w_tile :: emit_sme_st1w_tile_i_p_m +inst_sme_st1d_tile :: inst_sme_st1d_tile_i_p_m +emit_sme_st1d_tile :: emit_sme_st1d_tile_i_p_m +inst_sme_st1q_tile :: inst_sme_st1q_tile_i_p_m +emit_sme_st1q_tile :: emit_sme_st1q_tile_i_p_m +inst_sme_mova_z_from_tile :: inst_sme_mova_z_from_tile_z_p_i +emit_sme_mova_z_from_tile :: emit_sme_mova_z_from_tile_z_p_i +inst_sme_mova_tile_from_z :: inst_sme_mova_tile_from_z_i_p_z +emit_sme_mova_tile_from_z :: emit_sme_mova_tile_from_z_i_p_z +inst_fcmla_4h :: inst_fcmla_4h_r_r_r_i +emit_fcmla_4h :: emit_fcmla_4h_r_r_r_i +inst_fcmla_8h :: inst_fcmla_8h_r_r_r_i +emit_fcmla_8h :: emit_fcmla_8h_r_r_r_i +inst_fcmla_4s :: inst_fcmla_4s_r_r_r_i +emit_fcmla_4s :: emit_fcmla_4s_r_r_r_i +inst_fcmla_2d :: inst_fcmla_2d_r_r_r_i +emit_fcmla_2d :: emit_fcmla_2d_r_r_r_i +inst_fcadd_4h :: inst_fcadd_4h_r_r_r_i +emit_fcadd_4h :: emit_fcadd_4h_r_r_r_i +inst_fcadd_8h :: inst_fcadd_8h_r_r_r_i +emit_fcadd_8h :: emit_fcadd_8h_r_r_r_i +inst_fcadd_4s :: inst_fcadd_4s_r_r_r_i +emit_fcadd_4s :: emit_fcadd_4s_r_r_r_i +inst_fcadd_2d :: inst_fcadd_2d_r_r_r_i +emit_fcadd_2d :: emit_fcadd_2d_r_r_r_i +inst_sve_prfb :: inst_sve_prfb_i_p_m +emit_sve_prfb :: emit_sve_prfb_i_p_m +inst_sve_prfh :: inst_sve_prfh_i_p_m +emit_sve_prfh :: emit_sve_prfh_i_p_m +inst_sve_prfw :: inst_sve_prfw_i_p_m +emit_sve_prfw :: emit_sve_prfw_i_p_m +inst_sve_prfd :: inst_sve_prfd_i_p_m +emit_sve_prfd :: emit_sve_prfd_i_p_m +inst_sve_ldnt1b :: inst_sve_ldnt1b_z_p_m +emit_sve_ldnt1b :: emit_sve_ldnt1b_z_p_m +inst_sve_ldnt1h :: inst_sve_ldnt1h_z_p_m +emit_sve_ldnt1h :: emit_sve_ldnt1h_z_p_m +inst_sve_ldnt1w :: inst_sve_ldnt1w_z_p_m +emit_sve_ldnt1w :: emit_sve_ldnt1w_z_p_m +inst_sve_ldnt1d :: inst_sve_ldnt1d_z_p_m +emit_sve_ldnt1d :: emit_sve_ldnt1d_z_p_m +inst_sve_stnt1b :: inst_sve_stnt1b_z_p_m +emit_sve_stnt1b :: emit_sve_stnt1b_z_p_m +inst_sve_stnt1h :: inst_sve_stnt1h_z_p_m +emit_sve_stnt1h :: emit_sve_stnt1h_z_p_m +inst_sve_stnt1w :: inst_sve_stnt1w_z_p_m +emit_sve_stnt1w :: emit_sve_stnt1w_z_p_m +inst_sve_stnt1d :: inst_sve_stnt1d_z_p_m +emit_sve_stnt1d :: emit_sve_stnt1d_z_p_m +inst_sve_ext :: inst_sve_ext_z_z_z_i +emit_sve_ext :: emit_sve_ext_z_z_z_i +inst_sve_splice :: inst_sve_splice_z_p_z_z +emit_sve_splice :: emit_sve_splice_z_p_z_z +inst_sve_index_ii :: inst_sve_index_ii_z_i_i +emit_sve_index_ii :: emit_sve_index_ii_z_i_i +inst_sve_index_ir :: inst_sve_index_ir_z_i_r +emit_sve_index_ir :: emit_sve_index_ir_z_i_r +inst_sve_index_ri :: inst_sve_index_ri_z_r_i +emit_sve_index_ri :: emit_sve_index_ri_z_r_i +inst_sve_index_rr :: inst_sve_index_rr_z_r_r +emit_sve_index_rr :: emit_sve_index_rr_z_r_r +inst_sve_bsl :: inst_sve_bsl_z_z_z_z +emit_sve_bsl :: emit_sve_bsl_z_z_z_z +inst_sve_bsl1n :: inst_sve_bsl1n_z_z_z_z +emit_sve_bsl1n :: emit_sve_bsl1n_z_z_z_z +inst_sve_bsl2n :: inst_sve_bsl2n_z_z_z_z +emit_sve_bsl2n :: emit_sve_bsl2n_z_z_z_z +inst_sve_nbsl :: inst_sve_nbsl_z_z_z_z +emit_sve_nbsl :: emit_sve_nbsl_z_z_z_z +inst_sve_pmul_vec :: inst_sve_pmul_vec_z_z_z +emit_sve_pmul_vec :: emit_sve_pmul_vec_z_z_z +inst_sve_pmullb :: inst_sve_pmullb_z_z_z +emit_sve_pmullb :: emit_sve_pmullb_z_z_z +inst_sve_pmullt :: inst_sve_pmullt_z_z_z +emit_sve_pmullt :: emit_sve_pmullt_z_z_z +inst_sve_bfcvt :: inst_sve_bfcvt_z_p_z +emit_sve_bfcvt :: emit_sve_bfcvt_z_p_z +inst_sve_bfcvtnt :: inst_sve_bfcvtnt_z_p_z +emit_sve_bfcvtnt :: emit_sve_bfcvtnt_z_p_z +inst_ldraa :: inst_ldraa_r_m +emit_ldraa :: emit_ldraa_r_m +inst_ldrab :: inst_ldrab_r_m +emit_ldrab :: emit_ldrab_r_m +inst_ldraa_pre :: inst_ldraa_pre_r_m +emit_ldraa_pre :: emit_ldraa_pre_r_m +inst_ldrab_pre :: inst_ldrab_pre_r_m +emit_ldrab_pre :: emit_ldrab_pre_r_m +inst_tstart :: inst_tstart_r +emit_tstart :: emit_tstart_r +inst_tcommit :: inst_tcommit_none +emit_tcommit :: emit_tcommit_none +inst_tcancel :: inst_tcancel_i +emit_tcancel :: emit_tcancel_i +inst_ttest :: inst_ttest_r +emit_ttest :: emit_ttest_r +inst_wfet :: inst_wfet_r +emit_wfet :: emit_wfet_r +inst_wfit :: inst_wfit_r +emit_wfit :: emit_wfit_r +inst_bc_cond :: inst_bc_cond_c_l +emit_bc_cond :: emit_bc_cond_c_l +inst_uxtb :: inst_uxtb_r_r +emit_uxtb :: emit_uxtb_r_r +inst_uxth :: inst_uxth_r_r +emit_uxth :: emit_uxth_r_r +inst_uxtw :: inst_uxtw_r_r +emit_uxtw :: emit_uxtw_r_r +inst_sxtb :: inst_sxtb_r_r +emit_sxtb :: emit_sxtb_r_r +inst_sxth :: inst_sxth_r_r +emit_sxth :: emit_sxth_r_r +inst_sxtw :: inst_sxtw_r_r +emit_sxtw :: emit_sxtw_r_r +inst_adc :: inst_adc_r_r_r +emit_adc :: emit_adc_r_r_r +inst_adcs :: inst_adcs_r_r_r +emit_adcs :: emit_adcs_r_r_r +inst_sbc :: inst_sbc_r_r_r +emit_sbc :: emit_sbc_r_r_r +inst_sbcs :: inst_sbcs_r_r_r +emit_sbcs :: emit_sbcs_r_r_r +inst_ngc :: inst_ngc_r_r +emit_ngc :: emit_ngc_r_r +inst_ngcs :: inst_ngcs_r_r +emit_ngcs :: emit_ngcs_r_r +inst_ldapur :: inst_ldapur_r_m +emit_ldapur :: emit_ldapur_r_m +inst_stlur :: inst_stlur_r_m +emit_stlur :: emit_stlur_r_m +inst_ldapurb :: inst_ldapurb_r_m +emit_ldapurb :: emit_ldapurb_r_m +inst_stlurb :: inst_stlurb_r_m +emit_stlurb :: emit_stlurb_r_m +inst_ldapurh :: inst_ldapurh_r_m +emit_ldapurh :: emit_ldapurh_r_m +inst_stlurh :: inst_stlurh_r_m +emit_stlurh :: emit_stlurh_r_m +inst_ldapursb :: inst_ldapursb_r_m +emit_ldapursb :: emit_ldapursb_r_m +inst_ldapursh :: inst_ldapursh_r_m +emit_ldapursh :: emit_ldapursh_r_m +inst_ldapursw :: inst_ldapursw_r_m +emit_ldapursw :: emit_ldapursw_r_m +inst_sve_bfadd :: inst_sve_bfadd_z_p_z_z +emit_sve_bfadd :: emit_sve_bfadd_z_p_z_z +inst_sve_bfsub :: inst_sve_bfsub_z_p_z_z +emit_sve_bfsub :: emit_sve_bfsub_z_p_z_z +inst_sve_bfmul :: inst_sve_bfmul_z_p_z_z +emit_sve_bfmul :: emit_sve_bfmul_z_p_z_z +inst_sve_bfmla :: inst_sve_bfmla_z_p_z_z +emit_sve_bfmla :: emit_sve_bfmla_z_p_z_z +inst_sve_bfmls :: inst_sve_bfmls_z_p_z_z +emit_sve_bfmls :: emit_sve_bfmls_z_p_z_z +inst_sb :: inst_sb_none +emit_sb :: emit_sb_none +inst_csdb :: inst_csdb_none +emit_csdb :: emit_csdb_none +inst_dgh :: inst_dgh_none +emit_dgh :: emit_dgh_none +inst_psb_csync :: inst_psb_csync_none +emit_psb_csync :: emit_psb_csync_none +inst_tsb_csync :: inst_tsb_csync_none +emit_tsb_csync :: emit_tsb_csync_none +inst_bti_j :: inst_bti_j_none +emit_bti_j :: emit_bti_j_none +inst_bti_c :: inst_bti_c_none +emit_bti_c :: emit_bti_c_none +inst_bti_jc :: inst_bti_jc_none +emit_bti_jc :: emit_bti_jc_none +inst_mov_v_alias :: inst_mov_v_alias_r_r +emit_mov_v_alias :: emit_mov_v_alias_r_r +inst_not_v_alias :: inst_not_v_alias_r_r +emit_not_v_alias :: emit_not_v_alias_r_r +inst_lsl_imm :: inst_lsl_imm_r_r_i +emit_lsl_imm :: emit_lsl_imm_r_r_i +inst_lsr_imm :: inst_lsr_imm_r_r_i +emit_lsr_imm :: emit_lsr_imm_r_r_i +inst_asr_imm :: inst_asr_imm_r_r_i +emit_asr_imm :: emit_asr_imm_r_r_i +inst_ror_imm :: inst_ror_imm_r_r_i +emit_ror_imm :: emit_ror_imm_r_r_i +inst_sve_bfadd_unpred :: inst_sve_bfadd_unpred_z_z_z +emit_sve_bfadd_unpred :: emit_sve_bfadd_unpred_z_z_z +inst_sve_bfsub_unpred :: inst_sve_bfsub_unpred_z_z_z +emit_sve_bfsub_unpred :: emit_sve_bfsub_unpred_z_z_z +inst_sve_bfmul_unpred :: inst_sve_bfmul_unpred_z_z_z +emit_sve_bfmul_unpred :: emit_sve_bfmul_unpred_z_z_z +inst_sve_bfclamp :: inst_sve_bfclamp_z_z_z +emit_sve_bfclamp :: emit_sve_bfclamp_z_z_z +inst_sve_bfmaxnm :: inst_sve_bfmaxnm_z_p_z_z +emit_sve_bfmaxnm :: emit_sve_bfmaxnm_z_p_z_z +inst_sve_bfminnm :: inst_sve_bfminnm_z_p_z_z +emit_sve_bfminnm :: emit_sve_bfminnm_z_p_z_z +inst_sme2_luti2_b :: inst_sme2_luti2_b_z_z_z_i +emit_sme2_luti2_b :: emit_sme2_luti2_b_z_z_z_i +inst_sme2_luti4_b :: inst_sme2_luti4_b_z_z_z_i +emit_sme2_luti4_b :: emit_sme2_luti4_b_z_z_z_i +inst_sme2_ld1b_x2 :: inst_sme2_ld1b_x2_z_p_m +emit_sme2_ld1b_x2 :: emit_sme2_ld1b_x2_z_p_m +inst_sme2_ld1h_x2 :: inst_sme2_ld1h_x2_z_p_m +emit_sme2_ld1h_x2 :: emit_sme2_ld1h_x2_z_p_m +inst_sme2_ld1w_x2 :: inst_sme2_ld1w_x2_z_p_m +emit_sme2_ld1w_x2 :: emit_sme2_ld1w_x2_z_p_m +inst_sme2_ld1d_x2 :: inst_sme2_ld1d_x2_z_p_m +emit_sme2_ld1d_x2 :: emit_sme2_ld1d_x2_z_p_m +inst_sme2_ld1b_x4 :: inst_sme2_ld1b_x4_z_p_m +emit_sme2_ld1b_x4 :: emit_sme2_ld1b_x4_z_p_m +inst_sme2_ld1h_x4 :: inst_sme2_ld1h_x4_z_p_m +emit_sme2_ld1h_x4 :: emit_sme2_ld1h_x4_z_p_m +inst_sme2_ld1w_x4 :: inst_sme2_ld1w_x4_z_p_m +emit_sme2_ld1w_x4 :: emit_sme2_ld1w_x4_z_p_m +inst_sme2_ld1d_x4 :: inst_sme2_ld1d_x4_z_p_m +emit_sme2_ld1d_x4 :: emit_sme2_ld1d_x4_z_p_m +inst_sme2_st1b_x2 :: inst_sme2_st1b_x2_z_p_m +emit_sme2_st1b_x2 :: emit_sme2_st1b_x2_z_p_m +inst_sme2_st1h_x2 :: inst_sme2_st1h_x2_z_p_m +emit_sme2_st1h_x2 :: emit_sme2_st1h_x2_z_p_m +inst_sme2_st1w_x2 :: inst_sme2_st1w_x2_z_p_m +emit_sme2_st1w_x2 :: emit_sme2_st1w_x2_z_p_m +inst_sme2_st1d_x2 :: inst_sme2_st1d_x2_z_p_m +emit_sme2_st1d_x2 :: emit_sme2_st1d_x2_z_p_m +inst_sme2_st1b_x4 :: inst_sme2_st1b_x4_z_p_m +emit_sme2_st1b_x4 :: emit_sme2_st1b_x4_z_p_m +inst_sme2_st1h_x4 :: inst_sme2_st1h_x4_z_p_m +emit_sme2_st1h_x4 :: emit_sme2_st1h_x4_z_p_m +inst_sme2_st1w_x4 :: inst_sme2_st1w_x4_z_p_m +emit_sme2_st1w_x4 :: emit_sme2_st1w_x4_z_p_m +inst_sme2_st1d_x4 :: inst_sme2_st1d_x4_z_p_m +emit_sme2_st1d_x4 :: emit_sme2_st1d_x4_z_p_m +inst_sme2_zip_3 :: inst_sme2_zip_3_z_z_z +emit_sme2_zip_3 :: emit_sme2_zip_3_z_z_z +inst_sme2_zip_4 :: inst_sme2_zip_4_z_z +emit_sme2_zip_4 :: emit_sme2_zip_4_z_z +inst_sme2_uzp_3 :: inst_sme2_uzp_3_z_z_z +emit_sme2_uzp_3 :: emit_sme2_uzp_3_z_z_z +inst_sme2_uzp_4 :: inst_sme2_uzp_4_z_z +emit_sme2_uzp_4 :: emit_sme2_uzp_4_z_z +inst_tlbi_rpalos :: inst_tlbi_rpalos_r +emit_tlbi_rpalos :: emit_tlbi_rpalos_r +inst_tlbi_rpaos :: inst_tlbi_rpaos_r +emit_tlbi_rpaos :: emit_tlbi_rpaos_r +inst_at_s1e1a :: inst_at_s1e1a_r +emit_at_s1e1a :: emit_at_s1e1a_r +inst_dc_cipapa :: inst_dc_cipapa_r +emit_dc_cipapa :: emit_dc_cipapa_r +inst_dc_cigdpapa :: inst_dc_cigdpapa_r +emit_dc_cigdpapa :: emit_dc_cigdpapa_r +inst_tlbi_paall :: inst_tlbi_paall_none +emit_tlbi_paall :: emit_tlbi_paall_none +inst_tlbi_paallos :: inst_tlbi_paallos_none +emit_tlbi_paallos :: emit_tlbi_paallos_none +inst_amx_ldx :: inst_amx_ldx_r +emit_amx_ldx :: emit_amx_ldx_r +inst_amx_ldy :: inst_amx_ldy_r +emit_amx_ldy :: emit_amx_ldy_r +inst_amx_stx :: inst_amx_stx_r +emit_amx_stx :: emit_amx_stx_r +inst_amx_sty :: inst_amx_sty_r +emit_amx_sty :: emit_amx_sty_r +inst_amx_ldz :: inst_amx_ldz_r +emit_amx_ldz :: emit_amx_ldz_r +inst_amx_stz :: inst_amx_stz_r +emit_amx_stz :: emit_amx_stz_r +inst_amx_ldzi :: inst_amx_ldzi_r +emit_amx_ldzi :: emit_amx_ldzi_r +inst_amx_stzi :: inst_amx_stzi_r +emit_amx_stzi :: emit_amx_stzi_r +inst_amx_extrx :: inst_amx_extrx_r +emit_amx_extrx :: emit_amx_extrx_r +inst_amx_extry :: inst_amx_extry_r +emit_amx_extry :: emit_amx_extry_r +inst_amx_fma64 :: inst_amx_fma64_r +emit_amx_fma64 :: emit_amx_fma64_r +inst_amx_fms64 :: inst_amx_fms64_r +emit_amx_fms64 :: emit_amx_fms64_r +inst_amx_fma32 :: inst_amx_fma32_r +emit_amx_fma32 :: emit_amx_fma32_r +inst_amx_fms32 :: inst_amx_fms32_r +emit_amx_fms32 :: emit_amx_fms32_r +inst_amx_mac16 :: inst_amx_mac16_r +emit_amx_mac16 :: emit_amx_mac16_r +inst_amx_fma16 :: inst_amx_fma16_r +emit_amx_fma16 :: emit_amx_fma16_r +inst_amx_fms16 :: inst_amx_fms16_r +emit_amx_fms16 :: emit_amx_fms16_r +inst_amx_set :: inst_amx_set_none +emit_amx_set :: emit_amx_set_none +inst_amx_clr :: inst_amx_clr_none +emit_amx_clr :: emit_amx_clr_none +inst_amx_vecint :: inst_amx_vecint_r +emit_amx_vecint :: emit_amx_vecint_r +inst_amx_vecfp :: inst_amx_vecfp_r +emit_amx_vecfp :: emit_amx_vecfp_r +inst_amx_matint :: inst_amx_matint_r +emit_amx_matint :: emit_amx_matint_r +inst_amx_matfp :: inst_amx_matfp_r +emit_amx_matfp :: emit_amx_matfp_r +inst_amx_genlut :: inst_amx_genlut_r +emit_amx_genlut :: emit_amx_genlut_r +inst_cpyp :: inst_cpyp_r_r_r +emit_cpyp :: emit_cpyp_r_r_r +inst_cpym :: inst_cpym_r_r_r +emit_cpym :: emit_cpym_r_r_r +inst_cpye :: inst_cpye_r_r_r +emit_cpye :: emit_cpye_r_r_r +inst_cpyfp :: inst_cpyfp_r_r_r +emit_cpyfp :: emit_cpyfp_r_r_r +inst_cpyfm :: inst_cpyfm_r_r_r +emit_cpyfm :: emit_cpyfm_r_r_r +inst_cpyfe :: inst_cpyfe_r_r_r +emit_cpyfe :: emit_cpyfe_r_r_r +inst_setp :: inst_setp_r_r_r +emit_setp :: emit_setp_r_r_r +inst_setm :: inst_setm_r_r_r +emit_setm :: emit_setm_r_r_r +inst_sete :: inst_sete_r_r_r +emit_sete :: emit_sete_r_r_r +inst_dc_ivac :: inst_dc_ivac_r +emit_dc_ivac :: emit_dc_ivac_r +inst_dc_isw :: inst_dc_isw_r +emit_dc_isw :: emit_dc_isw_r +inst_dc_csw :: inst_dc_csw_r +emit_dc_csw :: emit_dc_csw_r +inst_dc_cisw :: inst_dc_cisw_r +emit_dc_cisw :: emit_dc_cisw_r +inst_dc_zva :: inst_dc_zva_r +emit_dc_zva :: emit_dc_zva_r +inst_dc_cvac :: inst_dc_cvac_r +emit_dc_cvac :: emit_dc_cvac_r +inst_dc_cvau :: inst_dc_cvau_r +emit_dc_cvau :: emit_dc_cvau_r +inst_dc_civac :: inst_dc_civac_r +emit_dc_civac :: emit_dc_civac_r +inst_ic_ialluis :: inst_ic_ialluis_none +emit_ic_ialluis :: emit_ic_ialluis_none +inst_ic_iallu :: inst_ic_iallu_none +emit_ic_iallu :: emit_ic_iallu_none +inst_ic_ivau :: inst_ic_ivau_r +emit_ic_ivau :: emit_ic_ivau_r +inst_at_s1e1r :: inst_at_s1e1r_r +emit_at_s1e1r :: emit_at_s1e1r_r +inst_at_s1e1w :: inst_at_s1e1w_r +emit_at_s1e1w :: emit_at_s1e1w_r +inst_at_s1e0r :: inst_at_s1e0r_r +emit_at_s1e0r :: emit_at_s1e0r_r +inst_at_s1e0w :: inst_at_s1e0w_r +emit_at_s1e0w :: emit_at_s1e0w_r +inst_at_s1e2r :: inst_at_s1e2r_r +emit_at_s1e2r :: emit_at_s1e2r_r +inst_at_s1e2w :: inst_at_s1e2w_r +emit_at_s1e2w :: emit_at_s1e2w_r +inst_at_s1e3r :: inst_at_s1e3r_r +emit_at_s1e3r :: emit_at_s1e3r_r +inst_at_s1e3w :: inst_at_s1e3w_r +emit_at_s1e3w :: emit_at_s1e3w_r +inst_at_s12e1r :: inst_at_s12e1r_r +emit_at_s12e1r :: emit_at_s12e1r_r +inst_at_s12e1w :: inst_at_s12e1w_r +emit_at_s12e1w :: emit_at_s12e1w_r +inst_at_s12e0r :: inst_at_s12e0r_r +emit_at_s12e0r :: emit_at_s12e0r_r +inst_at_s12e0w :: inst_at_s12e0w_r +emit_at_s12e0w :: emit_at_s12e0w_r +inst_tlbi_vmalle1 :: inst_tlbi_vmalle1_none +emit_tlbi_vmalle1 :: emit_tlbi_vmalle1_none +inst_tlbi_vmalle1is :: inst_tlbi_vmalle1is_none +emit_tlbi_vmalle1is :: emit_tlbi_vmalle1is_none +inst_tlbi_vae1 :: inst_tlbi_vae1_r +emit_tlbi_vae1 :: emit_tlbi_vae1_r +inst_tlbi_vae1is :: inst_tlbi_vae1is_r +emit_tlbi_vae1is :: emit_tlbi_vae1is_r +inst_tlbi_aside1 :: inst_tlbi_aside1_r +emit_tlbi_aside1 :: emit_tlbi_aside1_r +inst_tlbi_aside1is :: inst_tlbi_aside1is_r +emit_tlbi_aside1is :: emit_tlbi_aside1is_r +inst_tlbi_vaae1 :: inst_tlbi_vaae1_r +emit_tlbi_vaae1 :: emit_tlbi_vaae1_r +inst_tlbi_vaae1is :: inst_tlbi_vaae1is_r +emit_tlbi_vaae1is :: emit_tlbi_vaae1is_r +inst_tlbi_vale1 :: inst_tlbi_vale1_r +emit_tlbi_vale1 :: emit_tlbi_vale1_r +inst_tlbi_vale1is :: inst_tlbi_vale1is_r +emit_tlbi_vale1is :: emit_tlbi_vale1is_r +inst_tlbi_vaale1 :: inst_tlbi_vaale1_r +emit_tlbi_vaale1 :: emit_tlbi_vaale1_r +inst_tlbi_vaale1is :: inst_tlbi_vaale1is_r +emit_tlbi_vaale1is :: emit_tlbi_vaale1is_r +inst_tlbi_alle1 :: inst_tlbi_alle1_none +emit_tlbi_alle1 :: emit_tlbi_alle1_none +inst_tlbi_alle1is :: inst_tlbi_alle1is_none +emit_tlbi_alle1is :: emit_tlbi_alle1is_none +inst_tlbi_alle2 :: inst_tlbi_alle2_none +emit_tlbi_alle2 :: emit_tlbi_alle2_none +inst_tlbi_alle2is :: inst_tlbi_alle2is_none +emit_tlbi_alle2is :: emit_tlbi_alle2is_none +inst_tlbi_alle3 :: inst_tlbi_alle3_none +emit_tlbi_alle3 :: emit_tlbi_alle3_none +inst_tlbi_alle3is :: inst_tlbi_alle3is_none +emit_tlbi_alle3is :: emit_tlbi_alle3is_none +inst_prfm :: inst_prfm_i_m +emit_prfm :: emit_prfm_i_m +inst_prfum :: inst_prfum_i_m +emit_prfum :: emit_prfum_i_m +inst_prfm_lit :: inst_prfm_lit_i_l +emit_prfm_lit :: emit_prfm_lit_i_l +inst_mov_reg :: inst_mov_reg_r_r +emit_mov_reg :: emit_mov_reg_r_r +inst_mov_bitmask :: inst_mov_bitmask_r_i +emit_mov_bitmask :: emit_mov_bitmask_r_i +inst_mvn :: inst_mvn_r_r +emit_mvn :: emit_mvn_r_r +inst_neg_sr :: inst_neg_sr_r_sh +emit_neg_sr :: emit_neg_sr_r_sh +inst_negs :: inst_negs_r_sh +emit_negs :: emit_negs_r_sh +inst_cmp_sr :: inst_cmp_sr_r_sh +emit_cmp_sr :: emit_cmp_sr_r_sh +inst_cmp_er :: inst_cmp_er_r_ex +emit_cmp_er :: emit_cmp_er_r_ex +inst_cmp_imm :: inst_cmp_imm_r_i +emit_cmp_imm :: emit_cmp_imm_r_i +inst_cmn_sr :: inst_cmn_sr_r_sh +emit_cmn_sr :: emit_cmn_sr_r_sh +inst_cmn_er :: inst_cmn_er_r_ex +emit_cmn_er :: emit_cmn_er_r_ex +inst_cmn_imm :: inst_cmn_imm_r_i +emit_cmn_imm :: emit_cmn_imm_r_i +inst_tst_sr :: inst_tst_sr_r_sh +emit_tst_sr :: emit_tst_sr_r_sh diff --git a/core/rexcode/arm64/tests/pipeline_smoke.odin b/core/rexcode/arm64/tests/pipeline_smoke.odin index 432539ad1..98ee73b10 100644 --- a/core/rexcode/arm64/tests/pipeline_smoke.odin +++ b/core/rexcode/arm64/tests/pipeline_smoke.odin @@ -171,7 +171,7 @@ run_pipeline_tests :: proc() { { clear(&relocs); clear(&errors) for i in 0.. / emit_ overload group. // -// COVERED (param type / op_ expr): -// W_REG X_REG WSP_REG XSP_REG -> Register / op_reg -// B_REG H_REG S_REG D_REG Q_REG V_REG -> Register / op_reg -// IMM_12 IMM_16 IMM_8 IMM_6 IMM_5 IMM_4 IMM_3 IMM_2 -> i64 / op_imm -// HW_SHIFT NZCV_IMM -> i64 / op_imm -// REL_26 REL_19 REL_14 REL_PG21 -> u32 (label id) / op_label -// MEM -> Memory / op_mem -// COND -> Cond / op_cond +// PARAM-TYPE per operand category (the suffix token is a function of the +// Odin parameter TYPE only, so two builders with the same generated name +// necessarily have the same Odin signature -- which is exactly what Odin +// requires for legal overload sets, and lets name-dedup == signature-dedup): // -// SKIPPED (no clean single-value constructor): -// W_SHIFTED X_SHIFTED W_EXTENDED X_EXTENDED BITMASK_IMM SYS_REG -// LSE_SIZE LDRAA_IMM10 LSL_SHIFT_W LSL_SHIFT_X ROR_SHIFT -// FCMLA_ROT FCADD_ROT SVE_PRFOP SME_PATTERN SVE_PATTERN -// all SVE : Z_REG_B/H/S/D P_REG P_REG_MERGE P_REG_ZERO P_REG_GOV Z_PAIR Z_QUAD -// all SME : ZA_TILE_B/H/S/D/Q SME_SLICE_B/H/W/D/Q -// all NEON arrangement/lane: V_8B V_16B V_4H V_8H V_2S V_4S V_1D V_2D -// V_4H_FP16 V_8H_FP16 V_ELEM_B/H/S/D +// integer/SIMD scalar/NEON-vector register -> Register / op_reg, op_v_* (suffix r) +// SVE Z register / Z pair / Z quad -> u8 / op_z_* (suffix z) +// SVE predicate (P_REG / merge / zero / gov) -> u8 / Register(REG_P|..) (suffix p) +// all immediates (incl ZA tile, SME slice, -> i64 / op_imm (suffix i) +// patterns, bitmask, sysreg, HW, NZCV, ...) +// PC-relative label -> u32 / op_label (suffix l) +// memory -> Memory / op_mem (suffix m) +// condition code -> Cond / op_cond (suffix c) +// shifted register (W/X_SHIFTED) -> (Register, Shift_Type, u8) / op_shifted (suffix sh) +// extended register (W/X_EXTENDED) -> (Register, Extend, u8) / op_extended (suffix ex) +// +// Because Register is `distinct u16` and the SVE-register / predicate params +// are `u8`, suffix `r` (one Register), `z`/`p` (one u8) are distinct Odin +// signatures and may coexist. Two forms of one mnemonic that collapse to the +// same Odin signature (e.g. the W and X variants, or the .8B and .16B +// arrangement variants which are all `Register`) are deduplicated to a single +// builder -- the first form wins and the encoder's matcher disambiguates the +// rest at encode time by register class / size. This mirrors the original +// W/X collapse and keeps every overload group legal. // // Run with: odin run tools/gen_mnemonic_builders.odin -file // -// Output: mnemonic_builders.odin (written to current directory; move to package root) +// Output: mnemonic_builders.odin (written next to the package via #directory). import "core:fmt" import "core:os" @@ -50,13 +58,19 @@ GEN_ATTRIB :: "// rexcode · Brendan Punsky (dotbmp@github), original author\n // Operand model // ----------------------------------------------------------------------------- -// Category drives both the param type and the op_ expression. +// Category drives the param shape (count + Odin types) and the constructor +// expression. The suffix token is derived from the Odin param TYPE so that +// equal generated names imply equal Odin signatures. Operand_Category :: enum { - REG, // Register -> op_reg - IMM, // i64 -> op_imm - REL, // u32 label -> op_label - MEM, // Memory -> op_mem - COND, // Cond -> op_cond + REG, // Register -> op_reg / op_v_* (1 param, suffix r) + ZREG, // u8 -> op_z_* / Register(REG_Z) (1 param, suffix z) + PREG, // u8 -> Register(REG_P) (1 param, suffix p) + IMM, // i64 -> op_imm (1 param, suffix i) + REL, // u32 label -> op_label (1 param, suffix l) + MEM, // Memory -> op_mem (1 param, suffix m) + COND, // Cond -> op_cond (1 param, suffix c) + SHIFTED, // Register + Shift_Type + u8 -> op_shifted (3 params, suffix sh) + EXTENDED, // Register + Extend + u8 -> op_extended (3 params, suffix ex) } Operand_Signature :: struct { @@ -75,55 +89,46 @@ mnemonic_to_lower :: proc(m: a.Mnemonic) -> string { return strings.to_lower(name) } -// Is this operand type one we can build a clean single-value param for? -is_supported_operand :: proc(t: a.Operand_Type) -> bool { - #partial switch t { - case .W_REG, .X_REG, .WSP_REG, .XSP_REG, - .B_REG, .H_REG, .S_REG, .D_REG, .Q_REG, .V_REG: - return true - case .IMM_12, .IMM_16, .IMM_8, .IMM_6, .IMM_5, .IMM_4, .IMM_3, .IMM_2, - .HW_SHIFT, .NZCV_IMM: - return true - case .REL_26, .REL_19, .REL_14, .REL_PG21: - return true - case .MEM: - return true - case .COND: - return true - } - return false -} - +// Every operand type now maps to a category -- nothing is unsupported, so no +// form is ever skipped. operand_category :: proc(t: a.Operand_Type) -> Operand_Category { #partial switch t { case .W_REG, .X_REG, .WSP_REG, .XSP_REG, - .B_REG, .H_REG, .S_REG, .D_REG, .Q_REG, .V_REG: + .B_REG, .H_REG, .S_REG, .D_REG, .Q_REG, .V_REG, + .V_8B, .V_16B, .V_4H, .V_8H, .V_2S, .V_4S, .V_1D, .V_2D, + .V_4H_FP16, .V_8H_FP16, + .V_ELEM_B, .V_ELEM_H, .V_ELEM_S, .V_ELEM_D: return .REG + case .Z_REG_B, .Z_REG_H, .Z_REG_S, .Z_REG_D, .Z_PAIR, .Z_QUAD: + return .ZREG + case .P_REG, .P_REG_MERGE, .P_REG_ZERO, .P_REG_GOV: + return .PREG case .REL_26, .REL_19, .REL_14, .REL_PG21: return .REL case .MEM: return .MEM case .COND: return .COND + case .W_SHIFTED, .X_SHIFTED: + return .SHIFTED + case .W_EXTENDED, .X_EXTENDED: + return .EXTENDED case: return .IMM } } -// Odin parameter type for an operand. -operand_param_type :: proc(t: a.Operand_Type) -> string { - switch operand_category(t) { - case .REG: return "Register" - case .IMM: return "i64" - case .REL: return "u32" - case .MEM: return "Memory" - case .COND: return "Cond" +// Number of Odin parameters this operand contributes. +operand_param_count :: proc(t: a.Operand_Type) -> int { + #partial switch operand_category(t) { + case .SHIFTED, .EXTENDED: + return 3 } - return "i64" + return 1 } // Width byte for op_imm / op_label (informational only; the matcher checks -// only operand kind, not size, so this never affects correctness). +// operand kind, not size, so this never affects correctness). operand_imm_size :: proc(t: a.Operand_Type) -> u8 { #partial switch t { case .IMM_16: return 2 @@ -135,20 +140,21 @@ operand_imm_size :: proc(t: a.Operand_Type) -> u8 { return 4 } -// Procedure-name suffix token for an operand. -// Procedure-name suffix token. Because AArch64 has no typed register enums, -// every register operand maps to the same Odin param type (`Register`) and -// every plain immediate to `i64`. We therefore name by PARAM-TYPE CATEGORY -// (r/i/l/m/c), not by operand subtype. This makes name-based dedup exactly -// equivalent to Odin-type dedup: two forms that produce the same name also -// produce the same proc signature (which Odin forbids in one overload group). +// Procedure-name suffix token for an operand -- a function of the Odin param +// TYPE only (see header). This makes name-based dedup exactly equivalent to +// Odin-type dedup: two forms producing the same name also produce the same +// proc signature (which Odin forbids twice in one overload group). operand_suffix :: proc(t: a.Operand_Type) -> string { switch operand_category(t) { - case .REG: return "r" - case .IMM: return "i" - case .REL: return "l" - case .MEM: return "m" - case .COND: return "c" + case .REG: return "r" + case .ZREG: return "z" + case .PREG: return "p" + case .IMM: return "i" + case .REL: return "l" + case .MEM: return "m" + case .COND: return "c" + case .SHIFTED: return "sh" + case .EXTENDED: return "ex" } return "x" } @@ -157,8 +163,9 @@ operand_suffix :: proc(t: a.Operand_Type) -> string { // Signature building // ----------------------------------------------------------------------------- -// Build the explicit-operand signature for a form, returning ok=false when any -// non-NONE operand is unsupported (the whole form is then skipped). +// Build the explicit-operand signature for a form. Every non-NONE operand is +// included; only truly implicit operands (enc == .IMPL, which AArch64's tables +// never actually use) carry no param. build_signature :: proc(form: a.Encoding) -> (sig: Operand_Signature, ok: bool) { for i in 0..<4 { op := form.ops[i] @@ -167,53 +174,111 @@ build_signature :: proc(form: a.Encoding) -> (sig: Operand_Signature, ok: bool) // Implicit operands carry no bits and take no param. if form.enc[i] == .IMPL { continue } - if !is_supported_operand(op) { - return {}, false - } - sig.types[sig.count] = op sig.count += 1 } return sig, true } -// Unique, descriptive parameter names per operand. -param_names :: proc(sig: Operand_Signature) -> [4]string { - result: [4]string +// Unique, descriptive parameter NAME(S) per operand. SHIFTED / EXTENDED +// expand to three (reg, shift/ext, amount). Returns a flat list of +// "name: type" param fragments plus, separately, the argument expressions for +// emit_ forwarding. +Param :: struct { + decl: string, // e.g. "dst: Register" + name: string, // e.g. "dst" (for emit forwarding) +} + +// Names of just the per-operand "primary" identifiers, indexed by operand +// slot. names[i][0] is the main identifier; for SHIFTED/EXTENDED, [1]/[2] are +// the shift/extend kind and amount. This is the single source of truth for +// parameter names; param_list derives the typed declarations from it so the +// declared params always match the expressions that reference them. +operand_primary_names :: proc(sig: Operand_Signature) -> [4][3]string { + result: [4][3]string reg_count := 0 imm_count := 0 + zp_count := 0 + + reg_name :: proc(i: int, reg_count: ^int) -> string { + if i == 0 { + return "dst" + } else if reg_count^ == 0 { + reg_count^ += 1 + return "src" + } + n := reg_count^ + 1 + reg_count^ += 1 + return fmt.tprintf("src%d", n) + } for i in 0.. u8 hardware number. + base := "rz" if i == 0 else fmt.tprintf("rz%d", zp_count + 1) + zp_count += 1 + result[i][0] = base case .IMM: - if imm_count == 0 { - result[i] = "imm" - } else { - result[i] = fmt.tprintf("imm%d", imm_count + 1) - } + result[i][0] = "imm" if imm_count == 0 else fmt.tprintf("imm%d", imm_count + 1) imm_count += 1 case .REL: - result[i] = "label" + result[i][0] = "label" case .MEM: - result[i] = "mem" + result[i][0] = "mem" case .COND: - result[i] = "cond" + result[i][0] = "cond" + case .SHIFTED: + rn := reg_name(i, ®_count) + result[i][0] = rn + result[i][1] = fmt.tprintf("%s_shift", rn) + result[i][2] = fmt.tprintf("%s_amount", rn) + case .EXTENDED: + rn := reg_name(i, ®_count) + result[i][0] = rn + result[i][1] = fmt.tprintf("%s_ext", rn) + result[i][2] = fmt.tprintf("%s_amount", rn) } } return result } +// Typed parameter declarations, derived from operand_primary_names so the +// names match exactly what the op_ expressions reference. +param_list :: proc(sig: Operand_Signature) -> [dynamic]Param { + params: [dynamic]Param + names := operand_primary_names(sig) + for i in 0.. string { sb := strings.builder_make() @@ -234,88 +299,132 @@ generate_proc_name :: proc(mnemonic: a.Mnemonic, sig: Operand_Signature) -> stri } // ----------------------------------------------------------------------------- -// op_ expression for a single operand +// op_ expression for a single operand (uses the form's exact operand type so +// the produced encoding is valid for the kept form). // ----------------------------------------------------------------------------- -write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, name: string) { - switch operand_category(t) { +write_operand_expr :: proc(sb: ^strings.Builder, t: a.Operand_Type, names: [3]string) { + #partial switch operand_category(t) { case .REG: - fmt.sbprintf(sb, "op_reg(%s)", name) + #partial switch t { + case .V_8B: fmt.sbprintf(sb, "op_v_8b(u8(reg_hw(%s)))", names[0]) + case .V_16B: fmt.sbprintf(sb, "op_v_16b(u8(reg_hw(%s)))", names[0]) + case .V_4H, .V_4H_FP16: fmt.sbprintf(sb, "op_v_4h(u8(reg_hw(%s)))", names[0]) + case .V_8H, .V_8H_FP16: fmt.sbprintf(sb, "op_v_8h(u8(reg_hw(%s)))", names[0]) + case .V_2S: fmt.sbprintf(sb, "op_v_2s(u8(reg_hw(%s)))", names[0]) + case .V_4S: fmt.sbprintf(sb, "op_v_4s(u8(reg_hw(%s)))", names[0]) + case .V_1D: fmt.sbprintf(sb, "op_v_1d(u8(reg_hw(%s)))", names[0]) + case .V_2D: fmt.sbprintf(sb, "op_v_2d(u8(reg_hw(%s)))", names[0]) + case: fmt.sbprintf(sb, "op_reg(%s)", names[0]) + } + case .ZREG: + #partial switch t { + case .Z_REG_B: fmt.sbprintf(sb, "op_z_b(%s)", names[0]) + case .Z_REG_H: fmt.sbprintf(sb, "op_z_h(%s)", names[0]) + case .Z_REG_S: fmt.sbprintf(sb, "op_z_s(%s)", names[0]) + case .Z_REG_D: fmt.sbprintf(sb, "op_z_d(%s)", names[0]) + case: fmt.sbprintf(sb, "op_reg(Register(REG_Z | (u16(%s) & 0x1F)))", names[0]) // Z_PAIR / Z_QUAD + } + case .PREG: + fmt.sbprintf(sb, "op_reg(Register(REG_P | (u16(%s) & 0xF)))", names[0]) case .IMM: - fmt.sbprintf(sb, "op_imm(%s, %d)", name, operand_imm_size(t)) + fmt.sbprintf(sb, "op_imm(%s, %d)", names[0], operand_imm_size(t)) case .REL: - fmt.sbprintf(sb, "op_label(%s, 4)", name) + fmt.sbprintf(sb, "op_label(%s, 4)", names[0]) case .MEM: - fmt.sbprintf(sb, "op_mem(%s)", name) + fmt.sbprintf(sb, "op_mem(%s)", names[0]) case .COND: - fmt.sbprintf(sb, "op_cond(%s)", name) + fmt.sbprintf(sb, "op_cond(%s)", names[0]) + case .SHIFTED: + fmt.sbprintf(sb, "op_shifted(%s, %s, %s)", names[0], names[1], names[2]) + case .EXTENDED: + fmt.sbprintf(sb, "op_extended(%s, %s, %s)", names[0], names[1], names[2]) } } -// Pattern string of operand categories, e.g. "r_r_i", used to pick a shape -// helper from instructions.odin where one fits cleanly. +// Pattern string of operand categories (one token each), used to pick a shape +// helper from instructions.odin where one fits cleanly. Shifted/extended use +// multi-char tokens so they never collide with the simple ones. pattern_string :: proc(sig: Operand_Signature) -> string { if sig.count == 0 { return "none" } sb := strings.builder_make() for i in 0.. 0 { strings.write_byte(&sb, '_') } - switch operand_category(sig.types[i]) { - case .REG: strings.write_byte(&sb, 'r') - case .IMM: strings.write_byte(&sb, 'i') - case .REL: strings.write_byte(&sb, 'l') - case .MEM: strings.write_byte(&sb, 'm') - case .COND: strings.write_byte(&sb, 'c') - } + strings.write_string(&sb, operand_suffix(sig.types[i])) } return strings.to_string(sb) } +// True when every operand maps to one of the plain constructors +// (op_reg/op_imm/op_mem/op_label) that the hand-written shape helpers use. +// V-arrangement / Z / P / shifted / extended forms must use the direct +// Instruction{} fallback instead, since the helpers would build the wrong +// constructor. +uses_plain_constructors :: proc(sig: Operand_Signature) -> bool { + for i in 0.. 0 { strings.write_string(sb, ", ") } if i < sig.count { - write_operand_expr(sb, sig.types[i], names[i]) + write_operand_expr(sb, sig.types[i], pnames[i]) } else { strings.write_string(sb, "{}") } @@ -345,57 +454,54 @@ write_inst_fallback :: proc(sb: ^strings.Builder, entry: Proc_Entry) { // ----------------------------------------------------------------------------- write_proc :: proc(sb: ^strings.Builder, entry: Proc_Entry, pad: int) { - sig := entry.sig - names := param_names(sig) + params := param_list(entry.sig) + defer delete(params) - // params - params := strings.builder_make() - defer strings.builder_destroy(¶ms) - for i in 0.. 0 { strings.write_string(¶ms, ", ") } - fmt.sbprintf(¶ms, "%s: %s", names[i], operand_param_type(sig.types[i])) + pstr := strings.builder_make() + defer strings.builder_destroy(&pstr) + for p, i in params { + if i > 0 { strings.write_string(&pstr, ", ") } + strings.write_string(&pstr, p.decl) } strings.write_string(sb, entry.proc_name) for n := pad - len(entry.proc_name); n > 0; n -= 1 { strings.write_byte(sb, ' ') } strings.write_string(sb, " :: #force_inline proc \"contextless\" (") - strings.write_string(sb, strings.to_string(params)) + strings.write_string(sb, strings.to_string(pstr)) strings.write_string(sb, ") -> Instruction { return ") write_inst_body(sb, entry) strings.write_string(sb, " }\n") } write_emit_proc :: proc(sb: ^strings.Builder, entry: Proc_Entry, pad: int) { - sig := entry.sig - names := param_names(sig) + params := param_list(entry.sig) + defer delete(params) emit_name := strings.concatenate({"emit_", entry.proc_name[5:]}) defer delete(emit_name) - // params (instructions + originals) - params := strings.builder_make() - defer strings.builder_destroy(¶ms) - strings.write_string(¶ms, "instructions: ^[dynamic]Instruction") - for i in 0.. 0 { strings.write_string(&args, ", ") } - strings.write_string(&args, names[i]) + astr := strings.builder_make() + defer strings.builder_destroy(&astr) + for p, i in params { + if i > 0 { strings.write_string(&astr, ", ") } + strings.write_string(&astr, p.name) } strings.write_string(sb, emit_name) for n := pad - len(entry.proc_name); n > 0; n -= 1 { strings.write_byte(sb, ' ') } strings.write_string(sb, " :: #force_inline proc(") - strings.write_string(sb, strings.to_string(params)) + strings.write_string(sb, strings.to_string(pstr)) strings.write_string(sb, ") { append(instructions, ") strings.write_string(sb, entry.proc_name) strings.write_byte(sb, '(') - strings.write_string(sb, strings.to_string(args)) + strings.write_string(sb, strings.to_string(astr)) strings.write_string(sb, ")) }\n") } @@ -403,13 +509,12 @@ write_emit_proc :: proc(sb: ^strings.Builder, entry: Proc_Entry, pad: int) { // Driver // ----------------------------------------------------------------------------- -// Lowercased mnemonic names whose generated overload group (inst_ / -// emit_) would collide with a hand-written shape helper already defined -// in instructions.odin. Those mnemonics already have dedicated typed builders, -// so we skip generating overloads for them entirely. +// Lowercased mnemonic names whose generated overload group would collide with +// a generic shape helper already defined in instructions.odin. Those helpers +// are not per-mnemonic (they take the Mnemonic as a parameter), so the +// generator must not also define a group of the same name. RESERVED_MNEMONIC_NAMES :: []string{ - "none", "r", "branch", "ldst", "mov_imm", // inst_none/inst_r/inst_branch/inst_ldst/inst_mov_imm - "b_cond", "cbz", "tbz", "csel", // inst_b_cond/inst_cbz/inst_tbz/inst_csel + "none", "r", "branch", "ldst", "mov_imm", } is_reserved_mnemonic :: proc(name: string) -> bool { @@ -431,30 +536,39 @@ main :: proc() { delete(procs_by_mnemonic) } + zero_form_mnemonics: [dynamic]a.Mnemonic + defer delete(zero_form_mnemonics) + + form_bearing := 0 + seen_proc_names: map[string]bool defer delete(seen_proc_names) for mnemonic in a.Mnemonic { if mnemonic == .INVALID { continue } - // Skip mnemonics whose overload-group name collides with a hand-written - // helper in instructions.odin (they already have typed builders). - if is_reserved_mnemonic(mnemonic_to_lower(mnemonic)) { continue } - _run := a.ENCODE_RUNS[u16(mnemonic)] forms := a.ENCODE_FORMS[_run.start:][:_run.count] - if len(forms) == 0 { continue } + if len(forms) == 0 { + append(&zero_form_mnemonics, mnemonic) + continue + } + form_bearing += 1 + + // Skip mnemonics whose overload-group name collides with a generic + // hand-written helper in instructions.odin. + if is_reserved_mnemonic(mnemonic_to_lower(mnemonic)) { continue } for form in forms { sig, ok := build_signature(form) if !ok { continue } proc_name := generate_proc_name(mnemonic, sig) - // Dedup by generated name. Because suffixes are param-type - // categories, equal names mean equal Odin signatures, so this - // collapses W/X (and other same-shape) variants into one generic- - // Register builder; the encoder's matcher disambiguates at encode - // time by register class. (Two same-typed procs in one overload + // Dedup by generated name. Because the suffix is a function of the + // Odin param TYPE, equal names mean equal Odin signatures, so this + // collapses W/X (and same-shape arrangement) variants into one + // builder; the encoder's matcher disambiguates at encode time by + // register class / size. (Two same-typed procs in one overload // group is also a hard Odin error, so this dedup is required.) if proc_name in seen_proc_names { continue } seen_proc_names[proc_name] = true @@ -545,10 +659,16 @@ main :: proc() { err := os.write_entire_file(#directory + "/../mnemonic_builders.odin", transmute([]u8)strings.concatenate({GEN_ATTRIB, output})) if err == nil { fmt.println("Generated mnemonic_builders.odin successfully!") - fmt.printf("Total mnemonics with builders: %d\n", len(mnemonic_list)) + fmt.printf("Form-bearing mnemonics: %d\n", form_bearing) + fmt.printf("Mnemonics with builder groups: %d\n", len(mnemonic_list)) + fmt.printf("Reserved (generic helper) skip:%d\n", form_bearing - len(mnemonic_list)) total := 0 for m in mnemonic_list { total += len(procs_by_mnemonic[m]) } - fmt.printf("Total procedures generated: %d\n", total) + fmt.printf("Total inst_ procedures: %d\n", total) + fmt.printf("Zero-form (decode-only) mnemonics: %d\n", len(zero_form_mnemonics)) + for m in zero_form_mnemonics { + fmt.printf(" %v\n", m) + } } else { fmt.eprintln("Failed to write mnemonic_builders.odin") } @@ -564,10 +684,13 @@ generate_header :: proc(sb: ^strings.Builder) { // Generated by tools/gen_mnemonic_builders.odin from ENCODE_FORMS. // Regenerate with: odin run arm64/tools/gen_mnemonic_builders.odin -file // -// Typed mnemonic builder procedures with overloading. Each supported mnemonic -// form gets an inst_* (returns Instruction) and emit_* (appends to a -// [dynamic]Instruction). Forms touching exotic operand types -// (SVE/SME/NEON-arrangement/shifted/extended/bitmask/sysreg/...) are skipped. +// Typed mnemonic builder procedures with overloading. Every mnemonic that has +// at least one encode form gets an inst_* (returns Instruction) and emit_* +// (appends to a [dynamic]Instruction) overload group covering all of its +// distinct operand SHAPES. Forms that share an Odin signature (e.g. the W/X +// variants, or NEON arrangement / SVE element-size variants which are all +// passed as a Register/u8) collapse to one builder; the encoder's matcher +// disambiguates by register class / size at encode time. `) } diff --git a/core/rexcode/mos6502/instructions.odin b/core/rexcode/mos6502/instructions.odin index 74e6d7f7a..9115c832f 100644 --- a/core/rexcode/mos6502/instructions.odin +++ b/core/rexcode/mos6502/instructions.odin @@ -75,15 +75,6 @@ inst_zp_rel :: #force_inline proc "contextless" (m: Mnemonic, zp: u8, label_id: } } -// HuC6280 TST # imm, addr (3 or 4 bytes depending on addressing mode). -@(require_results) -inst_tst :: #force_inline proc "contextless" (m: Mnemonic, imm: i64, mm: Memory) -> Instruction { - return Instruction{ - mnemonic = m, operand_count = 2, length = 0, - ops = {op_imm8(imm), op_mem(mm), {}}, - } -} - // HuC6280 block transfer: src, dst, length (7-byte encoding). @(require_results) inst_block :: #force_inline proc "contextless" (m: Mnemonic, src, dst, length_val: u16) -> Instruction { diff --git a/core/rexcode/mos6502/mnemonic_builders.odin b/core/rexcode/mos6502/mnemonic_builders.odin index abe454def..d8980e6f5 100644 --- a/core/rexcode/mos6502/mnemonic_builders.odin +++ b/core/rexcode/mos6502/mnemonic_builders.odin @@ -334,8 +334,8 @@ inst_tam_imm8 :: #force_inline proc "contextless" (imm: i64) -> Instruction { emit_tam_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_i(.TAM, imm)) } inst_tma_imm8 :: #force_inline proc "contextless" (imm: i64) -> Instruction { return inst_i(.TMA, imm) } emit_tma_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_i(.TMA, imm)) } -inst_tst_tst :: #force_inline proc "contextless" (imm: i64, m: Memory) -> Instruction { return inst_tst(.TST, imm, m) } -emit_tst_tst :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, m: Memory) { append(instructions, inst_tst(.TST, imm, m)) } +inst_tst_tst :: #force_inline proc "contextless" (imm: i64, m: Memory) -> Instruction { return Instruction{mnemonic = .TST, operand_count = 2, length = 0, ops = {op_imm8(imm), op_mem(m), {}}} } +emit_tst_tst :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, m: Memory) { append(instructions, Instruction{mnemonic = .TST, operand_count = 2, length = 0, ops = {op_imm8(imm), op_mem(m), {}}}) } inst_bsr_rel :: #force_inline proc "contextless" (label_id: u32) -> Instruction { return inst_rel(.BSR, label_id) } emit_bsr_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, label_id: u32) { append(instructions, inst_rel(.BSR, label_id)) } inst_tii_block :: #force_inline proc "contextless" (src, dst, length_val: u16) -> Instruction { return inst_block(.TII, src, dst, length_val) } @@ -627,7 +627,8 @@ inst_tam :: inst_tam_imm8 emit_tam :: emit_tam_imm8 inst_tma :: inst_tma_imm8 emit_tma :: emit_tma_imm8 -// inst_tst / emit_tst overload group omitted: name collides with base helper inst_tst. +inst_tst :: inst_tst_tst +emit_tst :: emit_tst_tst inst_bsr :: inst_bsr_rel emit_bsr :: emit_bsr_rel inst_tii :: inst_tii_block diff --git a/core/rexcode/mos6502/tests/pipeline_smoke.odin b/core/rexcode/mos6502/tests/pipeline_smoke.odin index 7e8b13e82..510d8d981 100644 --- a/core/rexcode/mos6502/tests/pipeline_smoke.odin +++ b/core/rexcode/mos6502/tests/pipeline_smoke.odin @@ -115,7 +115,7 @@ run_pipeline_tests :: proc() { eq_bytes("SAX (HuC)", encode_or_fail({m.inst_none(.SAX)}), {0x22}) eq_bytes("CLA", encode_or_fail({m.inst_none(.CLA)}), {0x62}) eq_bytes("ST0 #$05", encode_or_fail({m.inst_i(.ST0, 0x05)}), {0x03, 0x05}) - eq_bytes("TST #$10, $80", encode_or_fail({m.inst_tst(.TST, 0x10, m.mem_zp(0x80))}), {0x83, 0x10, 0x80}) + eq_bytes("TST #$10, $80", encode_or_fail({m.inst_tst(0x10, m.mem_zp(0x80))}), {0x83, 0x10, 0x80}) eq_bytes("TII", encode_or_fail({m.inst_block(.TII, 0x4000, 0x2000, 0x100)}), {0x73, 0x00, 0x40, 0x00, 0x20, 0x00, 0x01}) diff --git a/core/rexcode/mos6502/tools/gen_mnemonic_builders.odin b/core/rexcode/mos6502/tools/gen_mnemonic_builders.odin index 1cfeeb581..b8f28f784 100644 --- a/core/rexcode/mos6502/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/mos6502/tools/gen_mnemonic_builders.odin @@ -42,7 +42,7 @@ Shape :: enum { REL, // PC-relative branch target -> inst_rel(.M, label) MEM, // any addressing-mode mem -> inst_m(.M, mem) ZP_REL, // BBR/BBS: zp + rel branch -> inst_zp_rel(.M, zp, label) - TST, // HuC TST: imm + mem -> inst_tst(.M, imm, mem) + TST, // HuC TST: imm + mem -> Instruction{ op_imm8, op_mem } BLOCK, // HuC block xfer: 3x word16 -> inst_block(.M, src, dst, len) SKIP, // could not classify } @@ -57,18 +57,6 @@ mnemonic_to_lower :: proc(m: m6502.Mnemonic) -> string { return strings.to_lower(fmt.tprintf("%v", m)) } -// Base instruction helpers in instructions.odin are inst_ for these x. -// If a mnemonic lowercases to one of them, an overload group named inst_ -// would redeclare the helper -- so we suppress the group for that mnemonic. -BASE_HELPER_SUFFIXES :: []string{"none", "a", "i", "m", "rel", "zp_rel", "tst", "block"} - -collides_with_base_helper :: proc(lower: string) -> bool { - for s in BASE_HELPER_SUFFIXES { - if lower == s { return true } - } - return false -} - // Classify a single encoding form into a builder Shape. classify :: proc(form: m6502.Encoding) -> Shape { // Gather the explicit operand types (skip trailing NONEs). @@ -230,16 +218,6 @@ main :: proc() { for mnemonic in mnemonic_list { procs := procs_by_mnemonic[mnemonic] if len(procs) == 0 { continue } - // A mnemonic named the same as an existing base helper (e.g. TST -> the - // HuC `inst_tst` bit-test helper) would have its overload group shadow / - // redeclare that helper. Skip the group in that case; the per-shape - // members (inst__) remain the typed entry points. - lower := mnemonic_to_lower(mnemonic) - if collides_with_base_helper(lower) { - fmt.sbprintf(&sb, "// inst_%s / emit_%s overload group omitted: name collides with base helper inst_%s.\n", - lower, lower, lower) - continue - } generate_overload_group(&sb, mnemonic, procs[:], pad) } @@ -309,7 +287,9 @@ shape_inst_body :: proc(sb: ^strings.Builder, e: Proc_Entry) { case .REL: fmt.sbprintf(sb, "inst_rel(.%s, label_id)", mn) case .MEM: fmt.sbprintf(sb, "inst_m(.%s, m)", mn) case .ZP_REL: fmt.sbprintf(sb, "inst_zp_rel(.%s, zp, label_id)", mn) - case .TST: fmt.sbprintf(sb, "inst_tst(.%s, imm, m)", mn) + // HuC6280 TST # imm, addr (imm + memory). Built inline so the inst_tst + // overload-group alias is free to name this mnemonic's typed entry point. + case .TST: fmt.sbprintf(sb, "Instruction{{mnemonic = .%s, operand_count = 2, length = 0, ops = {{op_imm8(imm), op_mem(m), {{}}}}}}", mn) case .BLOCK: fmt.sbprintf(sb, "inst_block(.%s, src, dst, length_val)", mn) case .SKIP: strings.write_string(sb, "{}") } diff --git a/core/rexcode/riscv/instructions.odin b/core/rexcode/riscv/instructions.odin index 574d16256..a4a462c0a 100644 --- a/core/rexcode/riscv/instructions.odin +++ b/core/rexcode/riscv/instructions.odin @@ -75,13 +75,6 @@ inst_u :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, imm: i64) ops = {op_reg(rd), op_imm(imm, 4), {}, {}}} } -// J-type: rd, label -@(require_results) -inst_jal :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, label_id: u32) -> Instruction { - return Instruction{mnemonic = m, operand_count = 2, length = 4, - ops = {op_reg(rd), op_label(label_id, 4), {}, {}}} -} - // B-type branch: rs1, rs2, label @(require_results) inst_branch :: #force_inline proc "contextless" (m: Mnemonic, rs1, rs2: Register, label_id: u32) -> Instruction { @@ -89,13 +82,6 @@ inst_branch :: #force_inline proc "contextless" (m: Mnemonic, rs1, rs2: Register ops = {op_reg(rs1), op_reg(rs2), op_label(label_id, 2), {}}} } -// JALR: rd, rs1, imm12 (indirect jump with offset) -@(require_results) -inst_jalr :: #force_inline proc "contextless" (rd, rs1: Register, imm: i64) -> Instruction { - return Instruction{mnemonic = .JALR, operand_count = 3, length = 4, - ops = {op_reg(rd), op_reg(rs1), op_imm(imm, 2), {}}} -} - // CSR ops: rd, csr, rs1 @(require_results) inst_csr :: #force_inline proc "contextless" (m: Mnemonic, rd: Register, csr: u16, rs1: Register) -> Instruction { diff --git a/core/rexcode/riscv/mnemonic_builders.odin b/core/rexcode/riscv/mnemonic_builders.odin index c2d9d4bb5..c02e23bbb 100644 --- a/core/rexcode/riscv/mnemonic_builders.odin +++ b/core/rexcode/riscv/mnemonic_builders.odin @@ -417,9 +417,9 @@ inst_lui :: inst_lui_gpr_imm20 emit_lui :: emit_lui_gpr_imm20 inst_auipc :: inst_auipc_gpr_imm20 emit_auipc :: emit_auipc_gpr_imm20 -// inst_jal: overload alias omitted (name taken by hand-written helper in instructions.odin); use inst_jal_gpr_label +inst_jal :: inst_jal_gpr_label emit_jal :: emit_jal_gpr_label -// inst_jalr: overload alias omitted (name taken by hand-written helper in instructions.odin); use inst_jalr_gpr_gpr_imm12 +inst_jalr :: inst_jalr_gpr_gpr_imm12 emit_jalr :: emit_jalr_gpr_gpr_imm12 inst_beq :: inst_beq_gpr_gpr_label emit_beq :: emit_beq_gpr_gpr_label diff --git a/core/rexcode/riscv/tests/pipeline_smoke.odin b/core/rexcode/riscv/tests/pipeline_smoke.odin index 18434bc58..c5181e6c5 100644 --- a/core/rexcode/riscv/tests/pipeline_smoke.odin +++ b/core/rexcode/riscv/tests/pipeline_smoke.odin @@ -166,9 +166,9 @@ run_pipeline_tests :: proc() { append(&ld, rv.Label_Definition(2)) // target at inst 2 insts := []rv.Instruction{ - rv.inst_jal(.JAL, rv.RA, 0), + rv.inst_jal(rv.GPR.RA, 0), rv.inst_r_r_i(.ADDI, rv.SP, rv.SP, 0), - rv.inst_jalr(rv.ZERO, rv.RA, 0), + rv.inst_jalr(rv.GPR.ZERO, rv.GPR.RA, 0), } r := rv.encode(insts, ld[:], code[:], &relocs, &errors) ok("JAL: encode ok", r.success) diff --git a/core/rexcode/riscv/tools/gen_mnemonic_builders.odin b/core/rexcode/riscv/tools/gen_mnemonic_builders.odin index a3175d4ae..37aca6413 100644 --- a/core/rexcode/riscv/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/riscv/tools/gen_mnemonic_builders.odin @@ -467,21 +467,12 @@ main :: proc() { mlow := mnemonic_to_lower(m) - // inst_ overload group. If "inst_" would collide with a - // hand-written helper of the same name in instructions.odin (inst_jal, - // inst_jalr), the standalone group alias is suppressed -- the existing - // helper keeps that name and the typed builder stays reachable under its - // explicit per-variant name (e.g. inst_jal_gpr_label). + // inst_ overload group. inst_group := strings.concatenate({"inst_", mlow}) defer delete(inst_group) - if is_reserved_inst_group(inst_group) { - fmt.sbprintf(&sb, "// inst_%s: overload alias omitted (name taken by hand-written helper in instructions.odin); use %s\n", - mlow, procs[0].proc_name) - } else { - strings.write_string(&sb, inst_group) - for n := pad - len(mlow); n > 0; n -= 1 { strings.write_byte(&sb, ' ') } - write_group(&sb, procs, "inst_") - } + strings.write_string(&sb, inst_group) + for n := pad - len(mlow); n > 0; n -= 1 { strings.write_byte(&sb, ' ') } + write_group(&sb, procs, "inst_") // emit_ overload group. No hand-written emit_ helpers collide. strings.write_string(&sb, "emit_") @@ -511,18 +502,6 @@ main :: proc() { } } -// inst_ group names that coincide with a hand-written helper of the -// same name in instructions.odin. For these the standalone group alias is -// suppressed (the existing helper keeps the name); the typed builder stays -// reachable under its explicit per-variant name. -is_reserved_inst_group :: proc(name: string) -> bool { - switch name { - case "inst_jal": return true // inst_jal(m, rd, label_id) in instructions.odin - case "inst_jalr": return true // inst_jalr(rd, rs1, imm) in instructions.odin - } - return false -} - // Write the " :: proc{ ... }\n" overload group body (or single alias). // prefix is "inst_" or "emit_"; entry proc_names always carry the "inst_" // prefix, so for emit_ we swap the prefix. diff --git a/core/rexcode/x86/mnemonic_builders.odin b/core/rexcode/x86/mnemonic_builders.odin index e39548a21..620a6a06c 100644 --- a/core/rexcode/x86/mnemonic_builders.odin +++ b/core/rexcode/x86/mnemonic_builders.odin @@ -21,6 +21,7 @@ Mem8 :: distinct struct { mem: Memory } Mem16 :: distinct struct { mem: Memory } Mem32 :: distinct struct { mem: Memory } Mem64 :: distinct struct { mem: Memory } +Mem80 :: distinct struct { mem: Memory } Mem128 :: distinct struct { mem: Memory } Mem256 :: distinct struct { mem: Memory } Mem512 :: distinct struct { mem: Memory } @@ -46,6 +47,11 @@ mem64 :: #force_inline proc "contextless" (m: Memory) -> Mem64 { return Mem64{ mem = m } } +@(require_results) +mem80 :: #force_inline proc "contextless" (m: Memory) -> Mem80 { + return Mem80{ mem = m } +} + @(require_results) mem128 :: #force_inline proc "contextless" (m: Memory) -> Mem128 { return Mem128{ mem = m } @@ -1219,10 +1225,12 @@ inst_jmp_rel8 :: #force_inline proc "contextless" (offset: inst_jmp_rel32 :: #force_inline proc "contextless" (offset: i32) -> Instruction { return inst_rel_offset(.JMP, i64(offset), 4) } inst_jmp_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return inst_r(.JMP, Register(dst)) } inst_jmp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return inst_m(.JMP, dst.mem, 8) } +inst_jmp_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return inst_m(.JMP, dst, 0) } emit_jmp_rel8 :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i8) { emit_rel_offset(instructions, .JMP, i64(offset), 1) } emit_jmp_rel32 :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i32) { emit_rel_offset(instructions, .JMP, i64(offset), 4) } emit_jmp_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { emit_r(instructions, .JMP, Register(dst)) } emit_jmp_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { emit_m(instructions, .JMP, dst.mem, 8) } +emit_jmp_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { emit_m(instructions, .JMP, dst, 0) } inst_ja_rel8 :: #force_inline proc "contextless" (offset: i8) -> Instruction { return inst_rel_offset(.JA, i64(offset), 1) } inst_ja_rel32 :: #force_inline proc "contextless" (offset: i32) -> Instruction { return inst_rel_offset(.JA, i64(offset), 4) } emit_ja_rel8 :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i8) { emit_rel_offset(instructions, .JA, i64(offset), 1) } @@ -1358,9 +1366,11 @@ emit_loopne_rel8 :: #force_inline proc(instructions: ^[dynami inst_call_rel32 :: #force_inline proc "contextless" (offset: i32) -> Instruction { return inst_rel_offset(.CALL, i64(offset), 4) } inst_call_r64 :: #force_inline proc "contextless" (dst: GPR64) -> Instruction { return inst_r(.CALL, Register(dst)) } inst_call_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return inst_m(.CALL, dst.mem, 8) } +inst_call_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return inst_m(.CALL, dst, 0) } emit_call_rel32 :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i32) { emit_rel_offset(instructions, .CALL, i64(offset), 4) } emit_call_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64) { emit_r(instructions, .CALL, Register(dst)) } emit_call_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { emit_m(instructions, .CALL, dst.mem, 8) } +emit_call_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { emit_m(instructions, .CALL, dst, 0) } inst_ret_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.RET) } inst_ret_imm16 :: #force_inline proc "contextless" (imm: i16) -> Instruction { return inst_i(.RET, i64(imm), 2) } emit_ret_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { emit_none(instructions, .RET) } @@ -7077,9 +7087,11 @@ inst_fxam_none :: #force_inline proc "contextless" () -> In emit_fxam_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { emit_none(instructions, .FXAM) } inst_fld_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return inst_m(.FLD, dst.mem, 4) } inst_fld_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return inst_m(.FLD, dst.mem, 8) } +inst_fld_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return inst_m(.FLD, dst.mem, 10) } inst_fld_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return inst_r(.FLD, Register(dst)) } emit_fld_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { emit_m(instructions, .FLD, dst.mem, 4) } emit_fld_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { emit_m(instructions, .FLD, dst.mem, 8) } +emit_fld_m80 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem80) { emit_m(instructions, .FLD, dst.mem, 10) } emit_fld_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { emit_r(instructions, .FLD, Register(dst)) } inst_fild_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return inst_m(.FILD, dst.mem, 2) } inst_fild_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return inst_m(.FILD, dst.mem, 4) } @@ -7087,6 +7099,8 @@ inst_fild_m64 :: #force_inline proc "contextless" (dst: Me emit_fild_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { emit_m(instructions, .FILD, dst.mem, 2) } emit_fild_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { emit_m(instructions, .FILD, dst.mem, 4) } emit_fild_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { emit_m(instructions, .FILD, dst.mem, 8) } +inst_fbld_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return inst_m(.FBLD, dst.mem, 10) } +emit_fbld_m80 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem80) { emit_m(instructions, .FBLD, dst.mem, 10) } inst_fst_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return inst_m(.FST, dst.mem, 4) } inst_fst_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return inst_m(.FST, dst.mem, 8) } inst_fst_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return inst_r(.FST, Register(dst)) } @@ -7095,9 +7109,11 @@ emit_fst_m64 :: #force_inline proc(instructions: ^[dynami emit_fst_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { emit_r(instructions, .FST, Register(dst)) } inst_fstp_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return inst_m(.FSTP, dst.mem, 4) } inst_fstp_m64 :: #force_inline proc "contextless" (dst: Mem64) -> Instruction { return inst_m(.FSTP, dst.mem, 8) } +inst_fstp_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return inst_m(.FSTP, dst.mem, 10) } inst_fstp_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return inst_r(.FSTP, Register(dst)) } emit_fstp_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { emit_m(instructions, .FSTP, dst.mem, 4) } emit_fstp_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { emit_m(instructions, .FSTP, dst.mem, 8) } +emit_fstp_m80 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem80) { emit_m(instructions, .FSTP, dst.mem, 10) } emit_fstp_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { emit_r(instructions, .FSTP, Register(dst)) } inst_fist_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return inst_m(.FIST, dst.mem, 2) } inst_fist_m32 :: #force_inline proc "contextless" (dst: Mem32) -> Instruction { return inst_m(.FIST, dst.mem, 4) } @@ -7115,6 +7131,8 @@ inst_fisttp_m64 :: #force_inline proc "contextless" (dst: Me emit_fisttp_m16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem16) { emit_m(instructions, .FISTTP, dst.mem, 2) } emit_fisttp_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32) { emit_m(instructions, .FISTTP, dst.mem, 4) } emit_fisttp_m64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64) { emit_m(instructions, .FISTTP, dst.mem, 8) } +inst_fbstp_m80 :: #force_inline proc "contextless" (dst: Mem80) -> Instruction { return inst_m(.FBSTP, dst.mem, 10) } +emit_fbstp_m80 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem80) { emit_m(instructions, .FBSTP, dst.mem, 10) } inst_fxch_st :: #force_inline proc "contextless" (dst: ST) -> Instruction { return inst_r(.FXCH, Register(dst)) } inst_fxch_none :: #force_inline proc "contextless" () -> Instruction { return inst_none(.FXCH) } emit_fxch_st :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: ST) { emit_r(instructions, .FXCH, Register(dst)) } @@ -7261,6 +7279,14 @@ inst_fxrstor_m512 :: #force_inline proc "contextless" (dst: Me emit_fxrstor_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512) { emit_m(instructions, .FXRSTOR, dst.mem, 64) } inst_fxrstor64_m512 :: #force_inline proc "contextless" (dst: Mem512) -> Instruction { return inst_m(.FXRSTOR64, dst.mem, 64) } emit_fxrstor64_m512 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem512) { emit_m(instructions, .FXRSTOR64, dst.mem, 64) } +inst_lgdt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return inst_m(.LGDT, dst, 0) } +emit_lgdt_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { emit_m(instructions, .LGDT, dst, 0) } +inst_sgdt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return inst_m(.SGDT, dst, 0) } +emit_sgdt_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { emit_m(instructions, .SGDT, dst, 0) } +inst_lidt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return inst_m(.LIDT, dst, 0) } +emit_lidt_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { emit_m(instructions, .LIDT, dst, 0) } +inst_sidt_m :: #force_inline proc "contextless" (dst: Memory) -> Instruction { return inst_m(.SIDT, dst, 0) } +emit_sidt_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Memory) { emit_m(instructions, .SIDT, dst, 0) } inst_lldt_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return inst_r(.LLDT, Register(dst)) } inst_lldt_m16 :: #force_inline proc "contextless" (dst: Mem16) -> Instruction { return inst_m(.LLDT, dst.mem, 2) } emit_lldt_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { emit_r(instructions, .LLDT, Register(dst)) } @@ -7499,9 +7525,9 @@ emit_xadd_r32_r32 :: #force_inline proc(instructions: ^[dynami emit_xadd_m32_r32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem32, src: GPR32) { emit_mr(instructions, .XADD, dst.mem, 4, Register(src)) } emit_xadd_r64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR64, src: GPR64) { emit_rr(instructions, .XADD, Register(dst), Register(src)) } emit_xadd_m64_r64 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Mem64, src: GPR64) { emit_mr(instructions, .XADD, dst.mem, 8, Register(src)) } -inst_bound_r16 :: #force_inline proc "contextless" (dst: GPR16) -> Instruction { return inst_r(.BOUND, Register(dst)) } +inst_bound_r16_m :: #force_inline proc "contextless" (dst: GPR16, src: Memory) -> Instruction { return inst_r_m(.BOUND, Register(dst), src, 0) } inst_bound_r32_m32 :: #force_inline proc "contextless" (dst: GPR32, src: Mem32) -> Instruction { return inst_r_m(.BOUND, Register(dst), src.mem, 4) } -emit_bound_r16 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16) { emit_r(instructions, .BOUND, Register(dst)) } +emit_bound_r16_m :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR16, src: Memory) { emit_rm(instructions, .BOUND, Register(dst), src, 0) } emit_bound_r32_m32 :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: GPR32, src: Mem32) { emit_rm(instructions, .BOUND, Register(dst), src.mem, 4) } inst_enter_imm16_imm8 :: #force_inline proc "contextless" (imm: i16, imm2: i8) -> Instruction { return Instruction{ mnemonic = .ENTER, operand_count = 2, ops = {op_imm16(imm), op_imm8(imm2), {}, {}} } } emit_enter_imm16_imm8 :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i16, imm2: i8) { append(instructions, inst_enter_imm16_imm8(imm, imm2)) } @@ -7628,8 +7654,8 @@ inst_lzcnt :: proc{ inst_lzcnt_r16_r16, inst_lzcnt emit_lzcnt :: proc{ emit_lzcnt_r16_r16, emit_lzcnt_r16_m16, emit_lzcnt_r32_r32, emit_lzcnt_r32_m32, emit_lzcnt_r64_r64, emit_lzcnt_r64_m64 } inst_tzcnt :: proc{ inst_tzcnt_r16_r16, inst_tzcnt_r16_m16, inst_tzcnt_r32_r32, inst_tzcnt_r32_m32, inst_tzcnt_r64_r64, inst_tzcnt_r64_m64 } emit_tzcnt :: proc{ emit_tzcnt_r16_r16, emit_tzcnt_r16_m16, emit_tzcnt_r32_r32, emit_tzcnt_r32_m32, emit_tzcnt_r64_r64, emit_tzcnt_r64_m64 } -inst_jmp :: proc{ inst_jmp_rel8, inst_jmp_rel32, inst_jmp_r64, inst_jmp_m64 } -emit_jmp :: proc{ emit_jmp_rel8, emit_jmp_rel32, emit_jmp_r64, emit_jmp_m64 } +inst_jmp :: proc{ inst_jmp_rel8, inst_jmp_rel32, inst_jmp_r64, inst_jmp_m64, inst_jmp_m } +emit_jmp :: proc{ emit_jmp_rel8, emit_jmp_rel32, emit_jmp_r64, emit_jmp_m64, emit_jmp_m } inst_ja :: proc{ inst_ja_rel8, inst_ja_rel32 } emit_ja :: proc{ emit_ja_rel8, emit_ja_rel32 } inst_jae :: proc{ inst_jae_rel8, inst_jae_rel32 } @@ -7702,8 +7728,8 @@ inst_loope :: inst_loope_rel8 emit_loope :: emit_loope_rel8 inst_loopne :: inst_loopne_rel8 emit_loopne :: emit_loopne_rel8 -inst_call :: proc{ inst_call_rel32, inst_call_r64, inst_call_m64 } -emit_call :: proc{ emit_call_rel32, emit_call_r64, emit_call_m64 } +inst_call :: proc{ inst_call_rel32, inst_call_r64, inst_call_m64, inst_call_m } +emit_call :: proc{ emit_call_rel32, emit_call_r64, emit_call_m64, emit_call_m } inst_ret :: proc{ inst_ret_none, inst_ret_imm16 } emit_ret :: proc{ emit_ret_none, emit_ret_imm16 } inst_iret :: inst_iret_none @@ -9572,20 +9598,24 @@ inst_fxtract :: inst_fxtract_none emit_fxtract :: emit_fxtract_none inst_fxam :: inst_fxam_none emit_fxam :: emit_fxam_none -inst_fld :: proc{ inst_fld_m32, inst_fld_m64, inst_fld_st } -emit_fld :: proc{ emit_fld_m32, emit_fld_m64, emit_fld_st } +inst_fld :: proc{ inst_fld_m32, inst_fld_m64, inst_fld_m80, inst_fld_st } +emit_fld :: proc{ emit_fld_m32, emit_fld_m64, emit_fld_m80, emit_fld_st } inst_fild :: proc{ inst_fild_m16, inst_fild_m32, inst_fild_m64 } emit_fild :: proc{ emit_fild_m16, emit_fild_m32, emit_fild_m64 } +inst_fbld :: inst_fbld_m80 +emit_fbld :: emit_fbld_m80 inst_fst :: proc{ inst_fst_m32, inst_fst_m64, inst_fst_st } emit_fst :: proc{ emit_fst_m32, emit_fst_m64, emit_fst_st } -inst_fstp :: proc{ inst_fstp_m32, inst_fstp_m64, inst_fstp_st } -emit_fstp :: proc{ emit_fstp_m32, emit_fstp_m64, emit_fstp_st } +inst_fstp :: proc{ inst_fstp_m32, inst_fstp_m64, inst_fstp_m80, inst_fstp_st } +emit_fstp :: proc{ emit_fstp_m32, emit_fstp_m64, emit_fstp_m80, emit_fstp_st } inst_fist :: proc{ inst_fist_m16, inst_fist_m32 } emit_fist :: proc{ emit_fist_m16, emit_fist_m32 } inst_fistp :: proc{ inst_fistp_m16, inst_fistp_m32, inst_fistp_m64 } emit_fistp :: proc{ emit_fistp_m16, emit_fistp_m32, emit_fistp_m64 } inst_fisttp :: proc{ inst_fisttp_m16, inst_fisttp_m32, inst_fisttp_m64 } emit_fisttp :: proc{ emit_fisttp_m16, emit_fisttp_m32, emit_fisttp_m64 } +inst_fbstp :: inst_fbstp_m80 +emit_fbstp :: emit_fbstp_m80 inst_fxch :: proc{ inst_fxch_st, inst_fxch_none } emit_fxch :: proc{ emit_fxch_st, emit_fxch_none } inst_fcmovb :: inst_fcmovb_st @@ -9710,6 +9740,14 @@ inst_fxrstor :: inst_fxrstor_m512 emit_fxrstor :: emit_fxrstor_m512 inst_fxrstor64 :: inst_fxrstor64_m512 emit_fxrstor64 :: emit_fxrstor64_m512 +inst_lgdt :: inst_lgdt_m +emit_lgdt :: emit_lgdt_m +inst_sgdt :: inst_sgdt_m +emit_sgdt :: emit_sgdt_m +inst_lidt :: inst_lidt_m +emit_lidt :: emit_lidt_m +inst_sidt :: inst_sidt_m +emit_sidt :: emit_sidt_m inst_lldt :: proc{ inst_lldt_r16, inst_lldt_m16 } emit_lldt :: proc{ emit_lldt_r16, emit_lldt_m16 } inst_sldt :: proc{ inst_sldt_r16, inst_sldt_m16, inst_sldt_r32, inst_sldt_r64 } @@ -9862,8 +9900,8 @@ inst_cmpxchg16b :: inst_cmpxchg16b_m128 emit_cmpxchg16b :: emit_cmpxchg16b_m128 inst_xadd :: proc{ inst_xadd_r8_r8, inst_xadd_m8_r8, inst_xadd_r16_r16, inst_xadd_m16_r16, inst_xadd_r32_r32, inst_xadd_m32_r32, inst_xadd_r64_r64, inst_xadd_m64_r64 } emit_xadd :: proc{ emit_xadd_r8_r8, emit_xadd_m8_r8, emit_xadd_r16_r16, emit_xadd_m16_r16, emit_xadd_r32_r32, emit_xadd_m32_r32, emit_xadd_r64_r64, emit_xadd_m64_r64 } -inst_bound :: proc{ inst_bound_r16, inst_bound_r32_m32 } -emit_bound :: proc{ emit_bound_r16, emit_bound_r32_m32 } +inst_bound :: proc{ inst_bound_r16_m, inst_bound_r32_m32 } +emit_bound :: proc{ emit_bound_r16_m, emit_bound_r32_m32 } inst_enter :: inst_enter_imm16_imm8 emit_enter :: emit_enter_imm16_imm8 inst_leave :: inst_leave_none diff --git a/core/rexcode/x86/tools/gen_mnemonic_builders.odin b/core/rexcode/x86/tools/gen_mnemonic_builders.odin index f9cb042b3..df9a655bb 100644 --- a/core/rexcode/x86/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/x86/tools/gen_mnemonic_builders.odin @@ -244,6 +244,7 @@ Mem8 :: distinct struct { mem: Memory } Mem16 :: distinct struct { mem: Memory } Mem32 :: distinct struct { mem: Memory } Mem64 :: distinct struct { mem: Memory } +Mem80 :: distinct struct { mem: Memory } Mem128 :: distinct struct { mem: Memory } Mem256 :: distinct struct { mem: Memory } Mem512 :: distinct struct { mem: Memory } @@ -269,6 +270,11 @@ mem64 :: #force_inline proc "contextless" (m: Memory) -> Mem64 { return Mem64{ mem = m } } +@(require_results) +mem80 :: #force_inline proc "contextless" (m: Memory) -> Mem80 { + return Mem80{ mem = m } +} + @(require_results) mem128 :: #force_inline proc "contextless" (m: Memory) -> Mem128 { return Mem128{ mem = m } @@ -307,8 +313,8 @@ can_generate_builder :: proc(enc: x86.Encoding) -> bool { case .MOFFS8, .MOFFS16, .MOFFS32, .MOFFS64: // Skip moffs - special encoding continue - case .PTR16_16, .PTR16_32, .PTR16_64, .M16_16, .M16_32, .M16_64: - // Skip far pointers + case .PTR16_16, .PTR16_32, .PTR16_64: + // Skip far pointers (16:16 / 16:32 / 16:64 immediate ptr forms) continue case .IMM8SX: // Skip sign-extended immediates for now @@ -425,6 +431,10 @@ is_memory_only_operand :: proc(op: x86.Operand_Type) -> bool { #partial switch op { case .M, .M8, .M16, .M32, .M64, .M80, .M128, .M256, .M512: return true + // Descriptor-table memory operands (LGDT/SGDT/LIDT/SIDT). The encoder treats + // them as size-agnostic memory, so they map to a single Memory parameter. + case .M16_16, .M16_32, .M16_64: + return true } return false } @@ -435,7 +445,7 @@ is_implicit_operand :: proc(op: x86.Operand_Type) -> bool { return true case .MOFFS8, .MOFFS16, .MOFFS32, .MOFFS64: return true - case .PTR16_16, .PTR16_32, .PTR16_64, .M16_16, .M16_32, .M16_64: + case .PTR16_16, .PTR16_32, .PTR16_64: return true } return false @@ -452,7 +462,10 @@ can_generate_operand :: proc(info: Operand_Info) -> bool { case .RM8, .RM16, .RM32, .RM64: return true // Memory only - case .M, .M8, .M16, .M32, .M64, .M128, .M256, .M512: + case .M, .M8, .M16, .M32, .M64, .M80, .M128, .M256, .M512: + return true + // Descriptor-table memory (LGDT/SGDT/LIDT/SIDT) -> single Memory parameter + case .M16_16, .M16_32, .M16_64: return true // Immediates case .IMM8, .IMM16, .IMM32, .IMM64: @@ -549,9 +562,13 @@ operand_suffix :: proc(info: Operand_Info) -> string { case .M16: return "m16" case .M32: return "m32" case .M64: return "m64" + case .M80: return "m80" case .M128: return "m128" case .M256: return "m256" case .M512: return "m512" + // Descriptor-table memory: collapse 16:32 / 16:64 forms to a single + // generic memory builder (matches the encoder's size-agnostic handling). + case .M16_16, .M16_32, .M16_64: return "m" } } else { #partial switch op { @@ -620,9 +637,11 @@ operand_odin_type :: proc(info: Operand_Info) -> string { case .M16: return "Mem16" case .M32: return "Mem32" case .M64: return "Mem64" + case .M80: return "Mem80" case .M128: return "Mem128" case .M256: return "Mem256" case .M512: return "Mem512" + case .M16_16, .M16_32, .M16_64: return "Memory" } } else { #partial switch op { @@ -699,10 +718,10 @@ operand_size :: proc(info: Operand_Info) -> u8 { return 8 case .K: return 8 - case .STI: + case .STI, .M80: return 10 - case .M: - return 0 // Size not known for generic memory + case .M, .M16_16, .M16_32, .M16_64: + return 0 // Size not known for generic / descriptor-table memory } return 0 } @@ -714,10 +733,11 @@ generate_operand_expr :: proc(sb: ^strings.Builder, info: Operand_Info, param_na if info.is_memory { // Memory operands use op_mem with the inner memory and size size := operand_size(info) - if op == .M { - // Generic memory - size is 0 - fmt.sbprintf(sb, "op_mem(%s, 0)", param_name) - } else { + #partial switch op { + case .M, .M16_16, .M16_32, .M16_64: + // Generic / descriptor-table memory: typed as raw Memory, size unknown + fmt.sbprintf(sb, "op_mem(%s, %d)", param_name, size) + case: fmt.sbprintf(sb, "op_mem(%s.mem, %d)", param_name, size) } return