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Check for float register width exactly for risc-v frontend

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This commit is contained in:
gingerBill
2026-08-21 12:19:02 +01:00
parent a604ddceb1
commit 4a4a5045f8
5 changed files with 27 additions and 2 deletions
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3
core/rexcode/isa/riscv/tablegen/cpp-compiler/cpp-gen.odin
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@@ -551,6 +551,9 @@ main :: proc() {
bool integer_reg_width_is_exact() const {
return false;
}
bool float_reg_width_is_exact() const {
return false;
}
""")
strings.write_string(&sb, "\n\n")

3
core/rexcode/isa/x86/tablegen/cpp-compiler/cpp-gen.odin
View File

@@ -553,6 +553,9 @@ main :: proc() {
bool integer_reg_width_is_exact() const {
return true;
}
bool float_reg_width_is_exact() const {
return true;
}
""")
strings.write_string(&sb, "\n\n")