From 9ec6f3e378f0cfc01ce1afe0b510c1f54e0b7628 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 15 Jun 2026 14:50:55 +0100 Subject: [PATCH 01/27] Minimize Instruction and Operand across ISAs further with `struct #raw_union #packed` --- core/rexcode/arm32/instructions.odin | 6 +++--- core/rexcode/arm32/operands.odin | 6 ++---- core/rexcode/arm64/instructions.odin | 3 ++- core/rexcode/arm64/operands.odin | 6 +++--- core/rexcode/ppc/instructions.odin | 4 ++-- core/rexcode/ppc/operands.odin | 4 ++-- core/rexcode/ppc_vle/instructions.odin | 2 +- core/rexcode/ppc_vle/operands.odin | 4 ++-- 8 files changed, 17 insertions(+), 18 deletions(-) diff --git a/core/rexcode/arm32/instructions.odin b/core/rexcode/arm32/instructions.odin index 16d3f5761..1c343d583 100644 --- a/core/rexcode/arm32/instructions.odin +++ b/core/rexcode/arm32/instructions.odin @@ -21,7 +21,7 @@ Instruction_Flags :: bit_field u8 { } Instruction :: struct #packed { - ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 22 = 88 + ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 18 = 68 mnemonic: Mnemonic, // 2 cond: u8, // 0..15 (AL=14) operand_count: u8, // 0..4 @@ -35,9 +35,9 @@ Instruction :: struct #packed { // bits). User-constructed instructions leave it at 0; the encoder then // falls back to first-shape-match. Stored as u16 over the two padding bytes. form_id: u16, + _: [7]u8, } -#assert(size_of(Instruction) == 97) -// 88 + 9 = 97 bytes (packed) +#assert(size_of(Instruction) == 88) // ============================================================================= // Builders diff --git a/core/rexcode/arm32/operands.odin b/core/rexcode/arm32/operands.odin index 6cb81b6a3..1442183ff 100644 --- a/core/rexcode/arm32/operands.odin +++ b/core/rexcode/arm32/operands.odin @@ -94,7 +94,7 @@ mem_reg_shift :: #force_inline proc "contextless" ( // ---- Operand structure ----------------------------------------------------- Operand :: struct #packed { - using _: struct #raw_union { + using _: struct #raw_union #packed { reg: Register, mem: Memory, immediate: i64, @@ -107,9 +107,7 @@ Operand :: struct #packed { lane: u8, // SIMD lane index for DPR_ELEM / QPR_ELEM cond: u8, // condition code 0..15 (default = AL = 14) } -#assert(size_of(Operand) == 22) -// 16-byte raw_union (Memory is largest) + 6 bytes of trailing fields = 22 bytes -// (packed; no alignment padding). +#assert(size_of(Operand) == 18) // ---- Operand builders ------------------------------------------------------ diff --git a/core/rexcode/arm64/instructions.odin b/core/rexcode/arm64/instructions.odin index 6bef2dd58..68896b187 100644 --- a/core/rexcode/arm64/instructions.odin +++ b/core/rexcode/arm64/instructions.odin @@ -16,8 +16,9 @@ Instruction :: struct #packed { operand_count: u8, // 1 flags: Instruction_Flags, // 1 length: u8, // 1 -- always 4 + _: [3]u8, } -#assert(size_of(Instruction) == 77) +#assert(size_of(Instruction) == 64) // ============================================================================= // Builders -- the most common shapes; less-common forms can be built diff --git a/core/rexcode/arm64/operands.odin b/core/rexcode/arm64/operands.odin index 44f0f4331..8c519dfab 100644 --- a/core/rexcode/arm64/operands.odin +++ b/core/rexcode/arm64/operands.odin @@ -89,7 +89,7 @@ Extended_Reg :: struct #packed { // 16-byte tagged operand. The union holds whichever payload matches `kind`. Operand :: struct #packed { - using _: struct #raw_union { + using _: struct #raw_union #packed { reg: Register, // 2 mem: Memory, // 12 immediate: i64, // 8 @@ -97,11 +97,11 @@ Operand :: struct #packed { shifted: Shifted_Reg, // 8 extended: Extended_Reg, // 8 cond: u8, // 1 - }, // 16 total because of alignment + }, // 12 total because of alignment kind: Operand_Kind, // 1 size: u8, // 1 -- carried width info; meaning varies } -#assert(size_of(Operand) == 18) +#assert(size_of(Operand) == 14) // ----------------------------------------------------------------------------- // Constructors -- generic diff --git a/core/rexcode/ppc/instructions.odin b/core/rexcode/ppc/instructions.odin index ef44fb10c..e13c0d945 100644 --- a/core/rexcode/ppc/instructions.odin +++ b/core/rexcode/ppc/instructions.odin @@ -20,7 +20,7 @@ Instruction_Flags :: bit_field u8 { } Instruction :: struct #packed { - ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 18 = 68 + ops: [4]Operand `fmt:"v,operand_count"`, // 4 * 14 = 56 mnemonic: Mnemonic, // 2 operand_count: u8, // 0..4 flags: Instruction_Flags, // 1 @@ -28,7 +28,7 @@ Instruction :: struct #packed { length: u8, // 4 or 8 (prefixed) form_id: u16, // 0 = no hint; otherwise 1 + form index } -#assert(size_of(Instruction) == 80) +#assert(size_of(Instruction) == 64) // ============================================================================= // Builders diff --git a/core/rexcode/ppc/operands.odin b/core/rexcode/ppc/operands.odin index 17996e215..0c41cc518 100644 --- a/core/rexcode/ppc/operands.odin +++ b/core/rexcode/ppc/operands.odin @@ -46,7 +46,7 @@ mem_x :: #force_inline proc "contextless" (base, index: Register) -> Memory { } Operand :: struct #packed { - using _: struct #raw_union { + using _: struct #raw_union #packed { reg: Register, mem: Memory, immediate: i64, @@ -55,7 +55,7 @@ Operand :: struct #packed { kind: Operand_Kind, size: u8, // operand size in bytes (4 = word, 8 = dword) } -#assert(size_of(Operand) == 18) +#assert(size_of(Operand) == 14) @(require_results) op_reg :: #force_inline proc "contextless" (r: Register) -> Operand { diff --git a/core/rexcode/ppc_vle/instructions.odin b/core/rexcode/ppc_vle/instructions.odin index 5cce1a408..8a3a33228 100644 --- a/core/rexcode/ppc_vle/instructions.odin +++ b/core/rexcode/ppc_vle/instructions.odin @@ -26,7 +26,7 @@ Instruction :: struct #packed { length: u8, // 2 or 4 form_id: u16, } -#assert(size_of(Instruction) == 80) +#assert(size_of(Instruction) == 64) @(require_results) inst_none :: #force_inline proc "contextless" (m: Mnemonic) -> Instruction { diff --git a/core/rexcode/ppc_vle/operands.odin b/core/rexcode/ppc_vle/operands.odin index ecacb5df2..c105db99b 100644 --- a/core/rexcode/ppc_vle/operands.odin +++ b/core/rexcode/ppc_vle/operands.odin @@ -31,7 +31,7 @@ mem_x :: #force_inline proc "contextless" (base, index: Register) -> Memory { } Operand :: struct #packed { - using _: struct #raw_union { + using _: struct #raw_union #packed { reg: Register, mem: Memory, immediate: i64, @@ -40,7 +40,7 @@ Operand :: struct #packed { kind: Operand_Kind, size: u8, } -#assert(size_of(Operand) == 18) +#assert(size_of(Operand) == 14) @(require_results) op_reg :: #force_inline proc "contextless" (r: Register) -> Operand { From 6feb33a79b62bb7fae970e1fd64a5e7d1cf1c2bf Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 15 Jun 2026 16:53:15 +0100 Subject: [PATCH 02/27] Heavily improve reading and writing to bit fields --- base/runtime/internal.odin | 97 ++++++++++++----- src/llvm_backend_general.cpp | 203 +++++++++++++++++++++++++---------- 2 files changed, 217 insertions(+), 83 deletions(-) diff --git a/base/runtime/internal.odin b/base/runtime/internal.odin index bb9fc4b36..091feece7 100644 --- a/base/runtime/internal.odin +++ b/base/runtime/internal.odin @@ -8,10 +8,10 @@ IS_WASM :: ODIN_ARCH == .wasm32 || ODIN_ARCH == .wasm64p32 @(private) RUNTIME_LINKAGE :: "strong" when ODIN_USE_SEPARATE_MODULES else - "internal" when ODIN_NO_ENTRY_POINT && (ODIN_BUILD_MODE == .Static || ODIN_BUILD_MODE == .Dynamic || ODIN_BUILD_MODE == .Object) else - "strong" when ODIN_BUILD_MODE == .Dynamic else - "strong" when !ODIN_NO_CRT else - "internal" + "internal" when ODIN_NO_ENTRY_POINT && (ODIN_BUILD_MODE == .Static || ODIN_BUILD_MODE == .Dynamic || ODIN_BUILD_MODE == .Object) else + "strong" when ODIN_BUILD_MODE == .Dynamic else + "strong" when !ODIN_NO_CRT else + "internal" RUNTIME_REQUIRE :: false // !ODIN_TILDE @(private) @@ -24,7 +24,7 @@ HAS_HARDWARE_SIMD :: false when (ODIN_ARCH == .amd64 || ODIN_ARCH == .i386) && ! true // Size of a native SIMD register for the current compilation target -NATIVE_SIMD_BIT_WIDTH :: +NATIVE_SIMD_BIT_WIDTH :: 512 when (ODIN_ARCH == .amd64) && intrinsics.has_target_feature("avx512f") else 256 when (ODIN_ARCH == .amd64) && (intrinsics.has_target_feature("avx2") || intrinsics.has_target_feature("avx")) else // Fallback for no hardware SIMD, but also SSE, NEON, SVE, RVV and WASM SIMD128. @@ -1186,7 +1186,7 @@ floattidf :: proc "c" (a: i128) -> f64 { // okay case: a = i128(u128(a) >> u128(sd - (DBL_MANT_DIG+2))) | - i128(u128(a) & (~u128(0) >> u128(N + DBL_MANT_DIG+2 - sd)) != 0) + i128(u128(a) & (~u128(0) >> u128(N + DBL_MANT_DIG+2 - sd)) != 0) } a |= i128((a & 4) != 0) @@ -1202,8 +1202,8 @@ floattidf :: proc "c" (a: i128) -> f64 { } fb: [2]u32 fb[1] = (u32(s) & 0x80000000) | // sign - (u32(e + 1023) << 20) | // exponent - u32((u64(a) >> 32) & 0x000FFFFF) // mantissa-high + (u32(e + 1023) << 20) | // exponent + u32((u64(a) >> 32) & 0x000FFFFF) // mantissa-high fb[0] = u32(a) // mantissa-low return transmute(f64)fb } @@ -1243,8 +1243,8 @@ floattidf_unsigned :: proc "c" (a: u128) -> f64 { } fb: [2]u32 fb[1] = (0) | // sign - u32((e + 1023) << 20) | // exponent - u32((u64(a) >> 32) & 0x000FFFFF) // mantissa-high + u32((e + 1023) << 20) | // exponent + u32((u64(a) >> 32) & 0x000FFFFF) // mantissa-high fb[0] = u32(a) // mantissa-low return transmute(f64)fb } @@ -1374,24 +1374,71 @@ fixdfti :: proc "c" (a: u64) -> i128 { } - - -__write_bits :: proc "contextless" (dst, src: [^]byte, offset: uintptr, size: uintptr) { - for i in 0..>3]) & (1<<(i&7)) != 0) - dst[j>>3] &~= 1<<(j&7) - dst[j>>3] |= the_bit<<(j&7) +__copy_bits :: #force_inline proc "contextless" ( + dst: [^]byte, + src: [^]byte, + buf_bytes: uintptr, + dst_bit: uintptr, + src_bit: uintptr, + size_bits: uintptr, +) #no_bounds_check { + src_byte := src_bit >> 3 + dst_byte := dst_bit >> 3 + src_shift := src_bit & 7 + dst_shift := dst_bit & 7 + src_need_bytes := ((src_shift + size_bits + 7) >> 3) + a, b: u64 + if src_need_bytes <= 4 { + a = u64(intrinsics.unaligned_load((^u32)(&src[src_byte]))) + } else { + a = intrinsics.unaligned_load((^u64)(&src[src_byte])) + b = intrinsics.unaligned_load((^u64)(&src[src_byte + 8])) + } + bits := (a >> src_shift) | (b << (64 - src_shift)) + mask := ~u64(0) + if size_bits < 64 { + mask = (u64(1) << size_bits) - 1 + } + bits &= mask + dst_need_bytes := ((dst_shift + size_bits + 7) >> 3) + if dst_shift == 0 { + if dst_need_bytes <= 4 { + v := u64(intrinsics.unaligned_load((^u32)(&dst[dst_byte]))) + v = (v & ~mask) | bits + intrinsics.unaligned_store((^u32)(&dst[dst_byte]), u32(v)) + } else { + v := intrinsics.unaligned_load((^u64)(&dst[dst_byte])) + v = (v & ~mask) | bits + intrinsics.unaligned_store((^u64)(&dst[dst_byte]), v) + } + } else { + v0 := intrinsics.unaligned_load((^u64)(&dst[dst_byte])) + v1 := intrinsics.unaligned_load((^u64)(&dst[dst_byte + 8])) + v0 = (v0 & ~(mask << dst_shift)) | (bits << dst_shift) + v1 = (v1 & ~(mask >> (64 - dst_shift))) | (bits >> (64 - dst_shift)) + intrinsics.unaligned_store((^u64)(&dst[dst_byte]), v0) + intrinsics.unaligned_store((^u64)(&dst[dst_byte + 8]), v1) } } -__read_bits :: proc "contextless" (dst, src: [^]byte, offset: uintptr, size: uintptr) { - for j in 0..>3]) & (1<<(i&7)) != 0) - dst[j>>3] &~= 1<<(j&7) - dst[j>>3] |= the_bit<<(j&7) - } +__write_bits :: proc "contextless" (dst, src: [^]byte, dst_size_bytes: uintptr, offset_bits: uintptr, size_bits: uintptr) { + __copy_bits(dst, src, dst_size_bytes, offset_bits, 0, size_bits) + // for i in 0..>3]) & (1<<(i&7)) != 0) + // dst[j>>3] &~= 1<<(j&7) + // dst[j>>3] |= the_bit<<(j&7) + // } +} + +__read_bits :: proc "contextless" (dst, src: [^]byte, src_size_bytes: uintptr, offset_bits: uintptr, size_bits: uintptr) { + __copy_bits(dst, src, src_size_bytes, 0, offset_bits, size_bits) + // for j in 0..>3]) & (1<<(i&7)) != 0) + // dst[j>>3] &~= 1<<(j&7) + // dst[j>>3] |= the_bit<<(j&7) + // } } when .Address in ODIN_SANITIZER_FLAGS { diff --git a/src/llvm_backend_general.cpp b/src/llvm_backend_general.cpp index 27a8c66e3..d36dd002d 100644 --- a/src/llvm_backend_general.cpp +++ b/src/llvm_backend_general.cpp @@ -957,6 +957,133 @@ gb_internal LLVMValueRef OdinLLVMBuildLoadAligned(lbProcedure *p, LLVMTypeRef ty return result; } +// gb_internal void OdinLLVMBuildUnalignedStore(lbProcedure *p, LLVMValueRef dst, LLVMValueRef src, Type *ptr_type) { +// Type *t = type_deref(ptr_type); + +// if (is_type_simd_vector(t)) { +// LLVMValueRef store = LLVMBuildStore(p->builder, src, dst); +// LLVMSetAlignment(store, 1); +// } else { +// lb_mem_copy_non_overlapping(p, {dst, ptr_type}, {src, ptr_type}, lb_const_int(p->module, t_int, type_size_of(t)), false); +// } + +// } +gb_internal LLVMValueRef OdinLLVMBuildUnalignedLoad(lbProcedure *p, LLVMValueRef src, Type *ptr_type) { + LLVMTypeRef type = lb_type(p->module, type_deref(ptr_type)); + + src = LLVMBuildPointerCast(p->builder, src, lb_type(p->module, ptr_type), ""); + LLVMValueRef load = LLVMBuildLoad2(p->builder, type, src, ""); + LLVMSetAlignment(load, 1); + return load; +} + +gb_internal void lb_copy_bits(lbProcedure *p, + LLVMValueRef dst, + LLVMValueRef src, + u64 buf_bytes, + u64 dst_bit, + u64 src_bit, + u64 size_bits +) { + auto ptr_offset = [](lbProcedure *p, LLVMValueRef ptr, u64 offset) -> LLVMValueRef { + LLVMValueRef indices[1] = {LLVMConstInt(lb_type(p->module, t_u64), offset, false)}; + ptr = LLVMBuildPointerCast(p->builder, ptr, lb_type(p->module, t_u8_ptr), ""); + return LLVMBuildGEP2(p->builder, lb_type(p->module, t_u8), ptr, indices, 1, ""); + }; + + Type *t_u32_ptr = alloc_type_pointer(t_u32); + Type *t_u64_ptr = alloc_type_pointer(t_u64); + LLVMTypeRef llvm_u32 = lb_type(p->module, t_u32); + LLVMTypeRef llvm_u64 = lb_type(p->module, t_u64); + LLVMTypeRef llvm_u32_ptr = lb_type(p->module, t_u32_ptr); + LLVMTypeRef llvm_u64_ptr = lb_type(p->module, t_u64_ptr); + + dst = LLVMBuildPointerCast(p->builder, dst, lb_type(p->module, t_u8_ptr), ""); + src = LLVMBuildPointerCast(p->builder, src, lb_type(p->module, t_u8_ptr), ""); + + u64 src_byte = src_bit>>3; + u64 dst_byte = dst_bit>>3; + u64 src_shift = src_bit&7; + u64 dst_shift = dst_bit&7; + u64 src_need_bytes = (src_shift + size_bits + 7)>>3; + + LLVMValueRef a = LLVMConstInt(llvm_u64, 0, false); + LLVMValueRef b = LLVMConstInt(llvm_u64, 0, false); + if (src_need_bytes <= 4) { + // a = u64(intrinsics.unaligned_load((^u32)(&src[src_byte]))) + a = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, src, src_byte), t_u32_ptr); + a = LLVMBuildZExt(p->builder, a, llvm_u64, ""); + } else { + // a = intrinsics.unaligned_load((^u64)(&src[src_byte])) + a = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, src, src_byte), t_u64_ptr); + // b = intrinsics.unaligned_load((^u64)(&src[src_byte + 8])) + b = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, src, src_byte + 8), t_u64_ptr); + } + + // bits := (a >> src_shift) | (b << (64 - src_shift)) + LLVMValueRef bits = LLVMBuildOr(p->builder, + LLVMBuildLShr(p->builder, a, LLVMConstInt(llvm_u64, src_shift, false), ""), + LLVMBuildShl (p->builder, b, LLVMConstInt(llvm_u64, 64 - src_shift, false), ""), + "" + ); + u64 mask = ~cast(u64)0; + if (size_bits < 64) { + mask = ((cast(u64)1)<builder, bits, LLVMConstInt(llvm_u64, mask, false), ""); + + u64 dst_need_bytes = (dst_shift + size_bits + 7) >> 3; + if (dst_shift == 0) { + if (dst_need_bytes <= 4) { + // v := u64(intrinsics.unaligned_load((^u32)(&dst[dst_byte]))) + LLVMValueRef v = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, dst, dst_byte), t_u32_ptr); + v = LLVMBuildZExt(p->builder, v, llvm_u64, ""); + + // v = (v & ~mask) | bits + v = LLVMBuildAnd(p->builder, v, LLVMConstInt(llvm_u64, ~mask, false), ""); + v = LLVMBuildOr(p->builder, v, bits, ""); + + // intrinsics.unaligned_store((^u32)(&dst[dst_byte]), u32(v)) + v = LLVMBuildTrunc(p->builder, v, llvm_u32, ""); + LLVMValueRef store = LLVMBuildStore(p->builder, v, LLVMBuildPointerCast(p->builder, ptr_offset(p, dst, dst_byte), llvm_u32_ptr, "")); + LLVMSetAlignment(store, 1); + } else { + // v := intrinsics.unaligned_load((^u64)(&dst[dst_byte])) + LLVMValueRef v = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, dst, dst_byte), t_u64_ptr); + + // v = (v & ~mask) | bits + v = LLVMBuildAnd(p->builder, v, LLVMConstInt(llvm_u64, ~mask, false), ""); + v = LLVMBuildOr(p->builder, v, bits, ""); + + // intrinsics.unaligned_store((^u64)(&dst[dst_byte]), v) + LLVMValueRef store = LLVMBuildStore(p->builder, v, LLVMBuildPointerCast(p->builder, ptr_offset(p, dst, dst_byte), llvm_u64_ptr, "")); + LLVMSetAlignment(store, 1); + } + } else { + // v0 := intrinsics.unaligned_load((^u64)(&dst[dst_byte])) + // v1 := intrinsics.unaligned_load((^u64)(&dst[dst_byte + 8])) + LLVMValueRef v0 = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, dst, dst_byte+0), t_u64_ptr); + LLVMValueRef v1 = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, dst, dst_byte+8), t_u64_ptr); + + // v0 = (v0 & ~(mask << dst_shift)) | (bits << dst_shift) + v0 = LLVMBuildAnd(p->builder, v0, LLVMConstInt(llvm_u64, ~(mask << dst_shift), false), ""); + v0 = LLVMBuildOr (p->builder, v0, LLVMBuildShl(p->builder, bits, LLVMConstInt(llvm_u64, dst_shift, false), ""), ""); + + // v1 = (v1 & ~(mask >> (64 - dst_shift))) | (bits >> (64 - dst_shift)) + v1 = LLVMBuildAnd(p->builder, v1, LLVMConstInt(llvm_u64, ~(mask >> (64 - dst_shift)), false), ""); + v1 = LLVMBuildOr (p->builder, v1, LLVMBuildLShr(p->builder, bits, LLVMConstInt(llvm_u64, (64 - dst_shift), false), ""), ""); + + // intrinsics.unaligned_store((^u64)(&dst[dst_byte]), v0) + // intrinsics.unaligned_store((^u64)(&dst[dst_byte + 8]), v1) + LLVMValueRef s0 = LLVMBuildStore(p->builder, v0, LLVMBuildPointerCast(p->builder, ptr_offset(p, dst, dst_byte+0), llvm_u64_ptr, "")); + LLVMValueRef s1 = LLVMBuildStore(p->builder, v1, LLVMBuildPointerCast(p->builder, ptr_offset(p, dst, dst_byte+8), llvm_u64_ptr, "")); + LLVMSetAlignment(s0, 1); + LLVMSetAlignment(s1, 1); + } +} + + gb_internal void lb_addr_store(lbProcedure *p, lbAddr addr, lbValue value) { if (addr.addr.value == nullptr) { return; @@ -974,6 +1101,7 @@ gb_internal void lb_addr_store(lbProcedure *p, lbAddr addr, lbValue value) { if (addr.kind == lbAddr_BitField) { lbValue dst = addr.addr; + lbValue src = {}; if (is_type_endian_big(addr.bitfield.type)) { i64 shift_amount = 8*type_size_of(value.type) - addr.bitfield.bit_size; lbValue shifted_value = value; @@ -981,33 +1109,17 @@ gb_internal void lb_addr_store(lbProcedure *p, lbAddr addr, lbValue value) { shifted_value.value, LLVMConstInt(LLVMTypeOf(shifted_value.value), shift_amount, false), ""); - lbValue src = lb_address_from_load_or_generate_local(p, shifted_value); - - auto args = array_make(temporary_allocator(), 4); - args[0] = dst; - args[1] = src; - args[2] = lb_const_int(p->module, t_uintptr, addr.bitfield.bit_offset); - args[3] = lb_const_int(p->module, t_uintptr, addr.bitfield.bit_size); - lb_emit_runtime_call(p, "__write_bits", args); - } else if ((addr.bitfield.bit_offset % 8) == 0 && - (addr.bitfield.bit_size % 8) == 0) { - lbValue src = lb_address_from_load_or_generate_local(p, value); - - lbValue byte_offset = lb_const_int(p->module, t_uintptr, addr.bitfield.bit_offset/8); - lbValue byte_size = lb_const_int(p->module, t_uintptr, addr.bitfield.bit_size/8); - lbValue dst_offset = lb_emit_conv(p, dst, t_u8_ptr); - dst_offset = lb_emit_ptr_offset(p, dst_offset, byte_offset); - lb_mem_copy_non_overlapping(p, dst_offset, src, byte_size); + src = lb_address_from_load_or_generate_local(p, shifted_value); } else { - lbValue src = lb_address_from_load_or_generate_local(p, value); - - auto args = array_make(temporary_allocator(), 4); - args[0] = dst; - args[1] = src; - args[2] = lb_const_int(p->module, t_uintptr, addr.bitfield.bit_offset); - args[3] = lb_const_int(p->module, t_uintptr, addr.bitfield.bit_size); - lb_emit_runtime_call(p, "__write_bits", args); + src = lb_address_from_load_or_generate_local(p, value); } + + u64 buf_bytes = cast(u64)type_size_of(type_deref(dst.type)); + u64 dst_bit = cast(u64)addr.bitfield.bit_offset; + u64 src_bit = cast(u64)0; + u64 size_bits = cast(u64)addr.bitfield.bit_size; + + lb_copy_bits(p, dst.value, src.value, buf_bytes, dst_bit, src_bit, size_bits); return; } else if (addr.kind == lbAddr_Map) { lb_internal_dynamic_map_set(p, addr.addr, addr.map.type, addr.map.key, value, p->curr_stmt); @@ -1289,53 +1401,28 @@ gb_internal lbValue lb_addr_load(lbProcedure *p, lbAddr const &addr) { } } - i64 total_bitfield_bit_size = 8*type_size_of(lb_addr_type(addr)); i64 dst_byte_size = type_size_of(addr.bitfield.type); lbAddr dst = lb_add_local_generated(p, addr.bitfield.type, true); lbValue src = addr.addr; - lbValue bit_offset = lb_const_int(p->module, t_uintptr, addr.bitfield.bit_offset); - lbValue bit_size = lb_const_int(p->module, t_uintptr, addr.bitfield.bit_size); - lbValue byte_offset = lb_const_int(p->module, t_uintptr, (addr.bitfield.bit_offset+7)/8); - lbValue byte_size = lb_const_int(p->module, t_uintptr, (addr.bitfield.bit_size+7)/8); - GB_ASSERT(type_size_of(addr.bitfield.type) >= ((addr.bitfield.bit_size+7)/8)); lbValue r = {}; - if (is_type_endian_big(addr.bitfield.type)) { - auto args = array_make(temporary_allocator(), 4); - args[0] = dst.addr; - args[1] = src; - args[2] = bit_offset; - args[3] = bit_size; - lb_emit_runtime_call(p, "__read_bits", args); + u64 buf_bytes = cast(u64)type_size_of(type_deref(src.type)); + u64 dst_bit = cast(u64)0; + u64 src_bit = cast(u64)addr.bitfield.bit_offset; + u64 size_bits = cast(u64)addr.bitfield.bit_size; + + lb_copy_bits(p, dst.addr.value, src.value, buf_bytes, dst_bit, src_bit, size_bits); + r = lb_addr_load(p, dst); + if (is_type_endian_big(addr.bitfield.type)) { LLVMValueRef shift_amount = LLVMConstInt( lb_type(p->module, lb_addr_type(dst)), 8*dst_byte_size - addr.bitfield.bit_size, false ); - r = lb_addr_load(p, dst); r.value = LLVMBuildShl(p->builder, r.value, shift_amount, ""); - } else if ((addr.bitfield.bit_offset % 8) == 0) { - do_mask = 8*dst_byte_size != addr.bitfield.bit_size; - - lbValue copy_size = byte_size; - lbValue src_offset = lb_emit_conv(p, src, t_u8_ptr); - src_offset = lb_emit_ptr_offset(p, src_offset, byte_offset); - if (addr.bitfield.bit_offset + 8*dst_byte_size <= total_bitfield_bit_size) { - copy_size = lb_const_int(p->module, t_uintptr, dst_byte_size); - } - lb_mem_copy_non_overlapping(p, dst.addr, src_offset, copy_size, false); - r = lb_addr_load(p, dst); - } else { - auto args = array_make(temporary_allocator(), 4); - args[0] = dst.addr; - args[1] = src; - args[2] = bit_offset; - args[3] = bit_size; - lb_emit_runtime_call(p, "__read_bits", args); - r = lb_addr_load(p, dst); } Type *t = addr.bitfield.type; From ee5d5d68826a24011a0596f1586ffd73092db183 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 15 Jun 2026 16:57:27 +0100 Subject: [PATCH 03/27] Remove the now defunct `__write_bits` and `__read_bits` --- base/runtime/internal.odin | 21 +-------------------- src/check_expr.cpp | 5 ----- 2 files changed, 1 insertion(+), 25 deletions(-) diff --git a/base/runtime/internal.odin b/base/runtime/internal.odin index 091feece7..3847ce046 100644 --- a/base/runtime/internal.odin +++ b/base/runtime/internal.odin @@ -1374,7 +1374,7 @@ fixdfti :: proc "c" (a: u64) -> i128 { } -__copy_bits :: #force_inline proc "contextless" ( +__copy_bits :: proc "contextless" ( dst: [^]byte, src: [^]byte, buf_bytes: uintptr, @@ -1421,25 +1421,6 @@ __copy_bits :: #force_inline proc "contextless" ( } } -__write_bits :: proc "contextless" (dst, src: [^]byte, dst_size_bytes: uintptr, offset_bits: uintptr, size_bits: uintptr) { - __copy_bits(dst, src, dst_size_bytes, offset_bits, 0, size_bits) - // for i in 0..>3]) & (1<<(i&7)) != 0) - // dst[j>>3] &~= 1<<(j&7) - // dst[j>>3] |= the_bit<<(j&7) - // } -} - -__read_bits :: proc "contextless" (dst, src: [^]byte, src_size_bytes: uintptr, offset_bits: uintptr, size_bits: uintptr) { - __copy_bits(dst, src, src_size_bytes, 0, offset_bits, size_bits) - // for j in 0..>3]) & (1<<(i&7)) != 0) - // dst[j>>3] &~= 1<<(j&7) - // dst[j>>3] |= the_bit<<(j&7) - // } -} when .Address in ODIN_SANITIZER_FLAGS { foreign { diff --git a/src/check_expr.cpp b/src/check_expr.cpp index a28c6016b..a9c9f1fb0 100644 --- a/src/check_expr.cpp +++ b/src/check_expr.cpp @@ -6124,11 +6124,6 @@ gb_internal Entity *check_selector(CheckerContext *c, Operand *operand, Ast *nod operand->type = entity->type; operand->expr = node; - if (entity->flags & EntityFlag_BitFieldField) { - add_package_dependency(c, "runtime", "__write_bits"); - add_package_dependency(c, "runtime", "__read_bits"); - } - switch (entity->kind) { case Entity_Constant: operand->value = entity->Constant.value; From c91d3f120ccb1c74b5bfec269fcfd418cb834460 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 15 Jun 2026 17:13:33 +0100 Subject: [PATCH 04/27] Fix shifting buf in lb_copy_bits --- src/llvm_backend_general.cpp | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/src/llvm_backend_general.cpp b/src/llvm_backend_general.cpp index d36dd002d..e0eb3bd04 100644 --- a/src/llvm_backend_general.cpp +++ b/src/llvm_backend_general.cpp @@ -1016,16 +1016,28 @@ gb_internal void lb_copy_bits(lbProcedure *p, } else { // a = intrinsics.unaligned_load((^u64)(&src[src_byte])) a = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, src, src_byte), t_u64_ptr); - // b = intrinsics.unaligned_load((^u64)(&src[src_byte + 8])) - b = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, src, src_byte + 8), t_u64_ptr); + if (src_need_bytes > 8) { + // b = intrinsics.unaligned_load((^u64)(&src[src_byte + 8])) + b = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, src, src_byte + 8), t_u64_ptr); + } } - // bits := (a >> src_shift) | (b << (64 - src_shift)) + LLVMValueRef hi; + if (src_shift == 0) { + hi = LLVMConstInt(llvm_u64, 0, false); + } else { + hi = LLVMBuildShl(p->builder, b, LLVMConstInt(llvm_u64, 64 - src_shift, false), ""); + } LLVMValueRef bits = LLVMBuildOr(p->builder, - LLVMBuildLShr(p->builder, a, LLVMConstInt(llvm_u64, src_shift, false), ""), - LLVMBuildShl (p->builder, b, LLVMConstInt(llvm_u64, 64 - src_shift, false), ""), - "" - ); + LLVMBuildLShr(p->builder, a, LLVMConstInt(llvm_u64, src_shift, false), ""), + hi, ""); + + // // bits := (a >> src_shift) | (b << (64 - src_shift)) + // LLVMValueRef bits = LLVMBuildOr(p->builder, + // LLVMBuildLShr(p->builder, a, LLVMConstInt(llvm_u64, src_shift, false), ""), + // LLVMBuildShl (p->builder, b, LLVMConstInt(llvm_u64, 64 - src_shift, false), ""), + // "" + // ); u64 mask = ~cast(u64)0; if (size_bits < 64) { mask = ((cast(u64)1)< Date: Mon, 15 Jun 2026 17:46:54 +0100 Subject: [PATCH 05/27] Improve `lb_copy_bits` --- src/llvm_backend_general.cpp | 136 ++++++++++++++--------------------- 1 file changed, 52 insertions(+), 84 deletions(-) diff --git a/src/llvm_backend_general.cpp b/src/llvm_backend_general.cpp index e0eb3bd04..a3f3978e8 100644 --- a/src/llvm_backend_general.cpp +++ b/src/llvm_backend_general.cpp @@ -985,117 +985,85 @@ gb_internal void lb_copy_bits(lbProcedure *p, u64 src_bit, u64 size_bits ) { + if (size_bits == 0) { + return; + } + GB_ASSERT(size_bits <= 64); // this routine assembles the field in a single u64 + auto ptr_offset = [](lbProcedure *p, LLVMValueRef ptr, u64 offset) -> LLVMValueRef { LLVMValueRef indices[1] = {LLVMConstInt(lb_type(p->module, t_u64), offset, false)}; ptr = LLVMBuildPointerCast(p->builder, ptr, lb_type(p->module, t_u8_ptr), ""); return LLVMBuildGEP2(p->builder, lb_type(p->module, t_u8), ptr, indices, 1, ""); }; - Type *t_u32_ptr = alloc_type_pointer(t_u32); - Type *t_u64_ptr = alloc_type_pointer(t_u64); - LLVMTypeRef llvm_u32 = lb_type(p->module, t_u32); + LLVMTypeRef llvm_u8 = lb_type(p->module, t_u8); LLVMTypeRef llvm_u64 = lb_type(p->module, t_u64); - LLVMTypeRef llvm_u32_ptr = lb_type(p->module, t_u32_ptr); - LLVMTypeRef llvm_u64_ptr = lb_type(p->module, t_u64_ptr); dst = LLVMBuildPointerCast(p->builder, dst, lb_type(p->module, t_u8_ptr), ""); src = LLVMBuildPointerCast(p->builder, src, lb_type(p->module, t_u8_ptr), ""); - u64 src_byte = src_bit>>3; - u64 dst_byte = dst_bit>>3; - u64 src_shift = src_bit&7; - u64 dst_shift = dst_bit&7; - u64 src_need_bytes = (src_shift + size_bits + 7)>>3; + u64 src_byte = src_bit >> 3; + u64 dst_byte = dst_bit >> 3; + u64 src_shift = src_bit & 7; + u64 dst_shift = dst_bit & 7; - LLVMValueRef a = LLVMConstInt(llvm_u64, 0, false); - LLVMValueRef b = LLVMConstInt(llvm_u64, 0, false); - if (src_need_bytes <= 4) { - // a = u64(intrinsics.unaligned_load((^u32)(&src[src_byte]))) - a = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, src, src_byte), t_u32_ptr); - a = LLVMBuildZExt(p->builder, a, llvm_u64, ""); - } else { - // a = intrinsics.unaligned_load((^u64)(&src[src_byte])) - a = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, src, src_byte), t_u64_ptr); - if (src_need_bytes > 8) { - // b = intrinsics.unaligned_load((^u64)(&src[src_byte + 8])) - b = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, src, src_byte + 8), t_u64_ptr); - } - } + u64 src_need_bytes = (src_shift + size_bits + 7) >> 3; // 1..9, exact span of the field + u64 dst_need_bytes = (dst_shift + size_bits + 7) >> 3; // 1..9, exact span of the field - LLVMValueRef hi; - if (src_shift == 0) { - hi = LLVMConstInt(llvm_u64, 0, false); - } else { - hi = LLVMBuildShl(p->builder, b, LLVMConstInt(llvm_u64, 64 - src_shift, false), ""); - } - LLVMValueRef bits = LLVMBuildOr(p->builder, - LLVMBuildLShr(p->builder, a, LLVMConstInt(llvm_u64, src_shift, false), ""), - hi, ""); + // These spans are exactly the bytes the field occupies, so they are in bounds + // whenever the field is. (buf_bytes must bound the buffer each pointer refers to.) + GB_ASSERT(src_byte + src_need_bytes <= buf_bytes); + GB_ASSERT(dst_byte + dst_need_bytes <= buf_bytes); - // // bits := (a >> src_shift) | (b << (64 - src_shift)) - // LLVMValueRef bits = LLVMBuildOr(p->builder, - // LLVMBuildLShr(p->builder, a, LLVMConstInt(llvm_u64, src_shift, false), ""), - // LLVMBuildShl (p->builder, b, LLVMConstInt(llvm_u64, 64 - src_shift, false), ""), - // "" - // ); u64 mask = ~cast(u64)0; if (size_bits < 64) { - mask = ((cast(u64)1)<builder, byte, llvm_u64, ""); + + // byte i sits at frame bit i*8; the field starts at frame bit src_shift + if (i*8 >= src_shift) { + u64 sh = i*8 - src_shift; // 0..63 (sh==64 only needs i==8, which requires src_shift>=1) + byte = LLVMBuildShl (p->builder, byte, LLVMConstInt(llvm_u64, sh, false), ""); + } else { + u64 sh = src_shift - i*8; // 1..7 + byte = LLVMBuildLShr(p->builder, byte, LLVMConstInt(llvm_u64, sh, false), ""); + } + bits = LLVMBuildOr(p->builder, bits, byte, ""); } - // bits &= mask bits = LLVMBuildAnd(p->builder, bits, LLVMConstInt(llvm_u64, mask, false), ""); - u64 dst_need_bytes = (dst_shift + size_bits + 7) >> 3; - if (dst_shift == 0) { - if (dst_need_bytes <= 4) { - // v := u64(intrinsics.unaligned_load((^u32)(&dst[dst_byte]))) - LLVMValueRef v = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, dst, dst_byte), t_u32_ptr); - v = LLVMBuildZExt(p->builder, v, llvm_u64, ""); + // Scatter: write exactly dst_need_bytes bytes, each a masked read-modify-write --- + for (u64 i = 0; i < dst_need_bytes; i++) { + LLVMValueRef contrib = nullptr; + u64 byte_mask = 0; // which bits (0..7) of this byte belong to the field - // v = (v & ~mask) | bits - v = LLVMBuildAnd(p->builder, v, LLVMConstInt(llvm_u64, ~mask, false), ""); - v = LLVMBuildOr(p->builder, v, bits, ""); - - // intrinsics.unaligned_store((^u32)(&dst[dst_byte]), u32(v)) - v = LLVMBuildTrunc(p->builder, v, llvm_u32, ""); - LLVMValueRef store = LLVMBuildStore(p->builder, v, LLVMBuildPointerCast(p->builder, ptr_offset(p, dst, dst_byte), llvm_u32_ptr, "")); - LLVMSetAlignment(store, 1); + if (i*8 >= dst_shift) { + u64 sh = i*8 - dst_shift; + contrib = LLVMBuildLShr(p->builder, bits, LLVMConstInt(llvm_u64, sh, false), ""); + byte_mask = (mask >> sh) & 0xff; } else { - // v := intrinsics.unaligned_load((^u64)(&dst[dst_byte])) - LLVMValueRef v = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, dst, dst_byte), t_u64_ptr); - - // v = (v & ~mask) | bits - v = LLVMBuildAnd(p->builder, v, LLVMConstInt(llvm_u64, ~mask, false), ""); - v = LLVMBuildOr(p->builder, v, bits, ""); - - // intrinsics.unaligned_store((^u64)(&dst[dst_byte]), v) - LLVMValueRef store = LLVMBuildStore(p->builder, v, LLVMBuildPointerCast(p->builder, ptr_offset(p, dst, dst_byte), llvm_u64_ptr, "")); - LLVMSetAlignment(store, 1); + u64 sh = dst_shift - i*8; // 1..7 + contrib = LLVMBuildShl(p->builder, bits, LLVMConstInt(llvm_u64, sh, false), ""); + byte_mask = (mask << sh) & 0xff; } - } else { - // v0 := intrinsics.unaligned_load((^u64)(&dst[dst_byte])) - // v1 := intrinsics.unaligned_load((^u64)(&dst[dst_byte + 8])) - LLVMValueRef v0 = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, dst, dst_byte+0), t_u64_ptr); - LLVMValueRef v1 = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, dst, dst_byte+8), t_u64_ptr); + contrib = LLVMBuildTrunc(p->builder, contrib, llvm_u8, ""); + contrib = LLVMBuildAnd(p->builder, contrib, LLVMConstInt(llvm_u8, byte_mask, false), ""); - // v0 = (v0 & ~(mask << dst_shift)) | (bits << dst_shift) - v0 = LLVMBuildAnd(p->builder, v0, LLVMConstInt(llvm_u64, ~(mask << dst_shift), false), ""); - v0 = LLVMBuildOr (p->builder, v0, LLVMBuildShl(p->builder, bits, LLVMConstInt(llvm_u64, dst_shift, false), ""), ""); + LLVMValueRef old = OdinLLVMBuildUnalignedLoad(p, ptr_offset(p, dst, dst_byte + i), t_u8_ptr); + old = LLVMBuildAnd(p->builder, old, LLVMConstInt(llvm_u8, (~byte_mask) & 0xff, false), ""); - // v1 = (v1 & ~(mask >> (64 - dst_shift))) | (bits >> (64 - dst_shift)) - v1 = LLVMBuildAnd(p->builder, v1, LLVMConstInt(llvm_u64, ~(mask >> (64 - dst_shift)), false), ""); - v1 = LLVMBuildOr (p->builder, v1, LLVMBuildLShr(p->builder, bits, LLVMConstInt(llvm_u64, (64 - dst_shift), false), ""), ""); - - // intrinsics.unaligned_store((^u64)(&dst[dst_byte]), v0) - // intrinsics.unaligned_store((^u64)(&dst[dst_byte + 8]), v1) - LLVMValueRef s0 = LLVMBuildStore(p->builder, v0, LLVMBuildPointerCast(p->builder, ptr_offset(p, dst, dst_byte+0), llvm_u64_ptr, "")); - LLVMValueRef s1 = LLVMBuildStore(p->builder, v1, LLVMBuildPointerCast(p->builder, ptr_offset(p, dst, dst_byte+8), llvm_u64_ptr, "")); - LLVMSetAlignment(s0, 1); - LLVMSetAlignment(s1, 1); + LLVMValueRef merged = LLVMBuildOr(p->builder, old, contrib, ""); + LLVMValueRef store = LLVMBuildStore(p->builder, merged, ptr_offset(p, dst, dst_byte + i)); + LLVMSetAlignment(store, 1); } } - gb_internal void lb_addr_store(lbProcedure *p, lbAddr addr, lbValue value) { if (addr.addr.value == nullptr) { return; From 7ef82c367c9924f0d8f7100b83a6b5efcef09e25 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 15 Jun 2026 17:48:33 +0100 Subject: [PATCH 06/27] Remove `__copy_bits` --- base/runtime/internal.odin | 47 -------------------------------------- 1 file changed, 47 deletions(-) diff --git a/base/runtime/internal.odin b/base/runtime/internal.odin index 3847ce046..2b9cdae62 100644 --- a/base/runtime/internal.odin +++ b/base/runtime/internal.odin @@ -1374,53 +1374,6 @@ fixdfti :: proc "c" (a: u64) -> i128 { } -__copy_bits :: proc "contextless" ( - dst: [^]byte, - src: [^]byte, - buf_bytes: uintptr, - dst_bit: uintptr, - src_bit: uintptr, - size_bits: uintptr, -) #no_bounds_check { - src_byte := src_bit >> 3 - dst_byte := dst_bit >> 3 - src_shift := src_bit & 7 - dst_shift := dst_bit & 7 - src_need_bytes := ((src_shift + size_bits + 7) >> 3) - a, b: u64 - if src_need_bytes <= 4 { - a = u64(intrinsics.unaligned_load((^u32)(&src[src_byte]))) - } else { - a = intrinsics.unaligned_load((^u64)(&src[src_byte])) - b = intrinsics.unaligned_load((^u64)(&src[src_byte + 8])) - } - bits := (a >> src_shift) | (b << (64 - src_shift)) - mask := ~u64(0) - if size_bits < 64 { - mask = (u64(1) << size_bits) - 1 - } - bits &= mask - dst_need_bytes := ((dst_shift + size_bits + 7) >> 3) - if dst_shift == 0 { - if dst_need_bytes <= 4 { - v := u64(intrinsics.unaligned_load((^u32)(&dst[dst_byte]))) - v = (v & ~mask) | bits - intrinsics.unaligned_store((^u32)(&dst[dst_byte]), u32(v)) - } else { - v := intrinsics.unaligned_load((^u64)(&dst[dst_byte])) - v = (v & ~mask) | bits - intrinsics.unaligned_store((^u64)(&dst[dst_byte]), v) - } - } else { - v0 := intrinsics.unaligned_load((^u64)(&dst[dst_byte])) - v1 := intrinsics.unaligned_load((^u64)(&dst[dst_byte + 8])) - v0 = (v0 & ~(mask << dst_shift)) | (bits << dst_shift) - v1 = (v1 & ~(mask >> (64 - dst_shift))) | (bits >> (64 - dst_shift)) - intrinsics.unaligned_store((^u64)(&dst[dst_byte]), v0) - intrinsics.unaligned_store((^u64)(&dst[dst_byte + 8]), v1) - } -} - when .Address in ODIN_SANITIZER_FLAGS { foreign { From 202be0601bd88622f947f0fa711ac841ad4b9b4c Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 15 Jun 2026 20:36:11 +0100 Subject: [PATCH 07/27] Minor changes in performance --- core/rexcode/doc.odin | 9 --- core/rexcode/x86/decoder.odin | 111 +++++++++++++++---------------- core/rexcode/x86/encoder.odin | 14 ++-- core/rexcode/x86/registers.odin | 21 +++--- core/rexcode/x86/tests/test.odin | 46 +++++++------ 5 files changed, 98 insertions(+), 103 deletions(-) diff --git a/core/rexcode/doc.odin b/core/rexcode/doc.odin index d22442873..abc5e2d54 100644 --- a/core/rexcode/doc.odin +++ b/core/rexcode/doc.odin @@ -51,17 +51,8 @@ compile time — no table is built during a normal library build: odin run /tablegen # ENCODING_TABLE -> generated Odin + /tables.odin odin run /tablegen/generated # -> /tables/.*.bin ``` - Regenerate after editing `ENCODING_TABLE`. See `docs/table_migration.md`. -## Performance (x86) - -With `-o:speed -microarch:native -no-bounds-check`: -- Encoder: ~17 M instructions/sec (~56 MB/s) -- Decoder: ~16 M instructions/sec (~54 MB/s) - -Measured on AMD Ryzen 3950X. - ## Usage ```odin diff --git a/core/rexcode/x86/decoder.odin b/core/rexcode/x86/decoder.odin index fc797898f..b37bb611e 100644 --- a/core/rexcode/x86/decoder.odin +++ b/core/rexcode/x86/decoder.odin @@ -269,7 +269,7 @@ decode_opcode :: proc(state: ^Decoder_State) -> (entry: ^Decode_Entry, vex_entry } // Handle VEX/EVEX encoded instructions - if state.vex_type != .NONE { + if state.vex_type != nil { return decode_opcode_vex(state) } @@ -575,8 +575,7 @@ decode_operands :: proc(state: ^Decoder_State, entry: ^Decode_Entry) -> (inst: I // Check if we need ModR/M needs_modrm := false - for _, i in entry.enc { - enc := entry.enc[i] + for enc in entry.enc { if enc == .MR || enc == .REG || enc == .VVVV { needs_modrm = true break @@ -617,25 +616,20 @@ decode_operands :: proc(state: ^Decoder_State, entry: ^Decode_Entry) -> (inst: I } // Decode each operand - for _, i in entry.ops { - op_type := entry.ops[i] - op_enc := entry.enc[i] - + for op_type, i in entry.ops { if op_type == .NONE { break } + op_enc := entry.enc[i] // i386: default_64 entries have R64/RM64 operand types but // really mean R32/RM32 in 32-bit mode (same encoded bytes). effective := mode_rewrite_op_type(op_type, state.mode, entry.flags.default_64) - inst.ops[i], err = decode_single_operand(state, effective, op_enc, modrm_info, sib_info, has_sib) - if err != nil { - return {}, err - } + inst.ops[i] = decode_single_operand(state, effective, op_enc, modrm_info, sib_info, has_sib) or_return inst.operand_count += 1 } - return inst, .NONE + return } decode_operands_vex :: proc(state: ^Decoder_State, entry: ^VEX_Decode_Entry) -> (inst: Instruction, err: Error_Code) { @@ -664,30 +658,25 @@ decode_operands_vex :: proc(state: ^Decoder_State, entry: ^VEX_Decode_Entry) -> } // Decode each operand - for _, i in entry.ops { - op_type := entry.ops[i] - op_enc := entry.enc[i] - + for op_type, i in entry.ops { if op_type == .NONE { break } + op_enc := entry.enc[i] - inst.ops[i], err = decode_single_operand_vex(state, op_type, op_enc, modrm_info, sib_info, has_sib) - if err != nil { - return {}, err - } + inst.ops[i] = decode_single_operand_vex(state, op_type, op_enc, modrm_info, sib_info, has_sib) or_return inst.operand_count += 1 } - return inst, .NONE + return } decode_single_operand :: proc(state: ^Decoder_State, op_type: Operand_Type, op_enc: Operand_Encoding, - modrm_info: ModRM_Info, sib_info: SIB_Info, has_sib: bool) -> (op: Operand, err: Error_Code) { + modrm_info: ModRM_Info, sib_info: SIB_Info, has_sib: bool) -> (op: Operand, err: Error_Code) { switch op_enc { case .NONE: - return {}, .NONE + return case .REG: // Register encoded in ModR/M.reg @@ -696,7 +685,8 @@ decode_single_operand :: proc(state: ^Decoder_State, op_type: Operand_Type, op_e register_number += 8 } reg := decode_register(register_number, op_type, state.rex) - return op_reg(reg), .NONE + op = op_reg(reg) + return case .MR: // Register or memory in ModR/M.rm @@ -707,7 +697,8 @@ decode_single_operand :: proc(state: ^Decoder_State, op_type: Operand_Type, op_e register_number += 8 } reg := decode_register(register_number, op_type, state.rex) - return op_reg(reg), .NONE + op = op_reg(reg) + return } else { // Memory return decode_memory_operand(state, modrm_info, sib_info, has_sib, op_type) @@ -716,43 +707,44 @@ decode_single_operand :: proc(state: ^Decoder_State, op_type: Operand_Type, op_e case .IB: // 8-bit immediate or rel8 if state.position >= len(state.data) { - return {}, .BUFFER_TOO_SHORT + err = .BUFFER_TOO_SHORT + return } immediate_value := i64(i8(state.data[state.position])) state.position += 1 - if op_type == .REL8 { - return Operand{kind = .RELATIVE, relative = immediate_value, size = 1}, .NONE - } - return Operand{kind = .IMMEDIATE, immediate = immediate_value, size = 1}, .NONE + op = Operand{kind = (op_type == .REL8 ? .RELATIVE : .IMMEDIATE), relative = immediate_value, size = 1} + return case .IW: // 16-bit immediate if state.position + 2 > len(state.data) { - return {}, .BUFFER_TOO_SHORT + err = .BUFFER_TOO_SHORT + return } immediate_value := i64(i16(u16(state.data[state.position]) | u16(state.data[state.position+1]) << 8)) state.position += 2 - return Operand{kind = .IMMEDIATE, immediate = immediate_value, size = 2}, .NONE + op = Operand{kind = .IMMEDIATE, immediate = immediate_value, size = 2} + return case .ID: // 32-bit immediate or rel32 if state.position + 4 > len(state.data) { - return {}, .BUFFER_TOO_SHORT + err = .BUFFER_TOO_SHORT + return } immediate_value := i64(i32(u32(state.data[state.position]) | u32(state.data[state.position+1]) << 8 | u32(state.data[state.position+2]) << 16 | u32(state.data[state.position+3]) << 24)) state.position += 4 - if op_type == .REL32 { - return Operand{kind = .RELATIVE, relative = immediate_value, size = 4}, .NONE - } - return Operand{kind = .IMMEDIATE, immediate = immediate_value, size = 4}, .NONE + op = Operand{kind = (op_type == .REL32 ? .RELATIVE : .IMMEDIATE), relative = immediate_value, size = 4} + return case .IQ: // 64-bit immediate if state.position + 8 > len(state.data) { - return {}, .BUFFER_TOO_SHORT + err = .BUFFER_TOO_SHORT + return } immediate_value := i64(u64(state.data[state.position]) | u64(state.data[state.position+1]) << 8 | @@ -763,7 +755,8 @@ decode_single_operand :: proc(state: ^Decoder_State, op_type: Operand_Type, op_e u64(state.data[state.position+6]) << 48 | u64(state.data[state.position+7]) << 56) state.position += 8 - return Operand{kind = .IMMEDIATE, immediate = immediate_value, size = 8}, .NONE + op = Operand{kind = .IMMEDIATE, immediate = immediate_value, size = 8} + return case .IMPL: // Implicit register - decode from operand type @@ -776,7 +769,8 @@ decode_single_operand :: proc(state: ^Decoder_State, op_type: Operand_Type, op_e register_number += 8 } reg := decode_register(register_number, op_type, state.rex) - return op_reg(reg), .NONE + op = op_reg(reg) + return case .VVVV: // VEX.vvvv register @@ -785,25 +779,28 @@ decode_single_operand :: proc(state: ^Decoder_State, op_type: Operand_Type, op_e register_number += 16 } reg := decode_register(register_number, op_type, state.rex) - return op_reg(reg), .NONE + op = op_reg(reg) + return case .IS4: // Immediate byte with register in high 4 bits if state.position >= len(state.data) { - return {}, .BUFFER_TOO_SHORT + err = .BUFFER_TOO_SHORT + return } immediate_byte := state.data[state.position] state.position += 1 register_number := (immediate_byte >> 4) & 0x0F reg := decode_register(register_number, op_type, state.rex) - return op_reg(reg), .NONE + op = op_reg(reg) + return case .AAA: // EVEX opmask - already decoded in state - return {}, .NONE + return } - return {}, .NONE + return } decode_single_operand_vex :: proc(state: ^Decoder_State, op_type: Operand_Type, op_enc: Operand_Encoding, @@ -940,7 +937,7 @@ decode_memory_operand :: proc(state: ^Decoder_State, modrm_info: ModRM_Info, // 8.8 Register Decoding Helpers // ----------------------------------------------------------------------------- -decode_register :: proc(num: u8, op_type: Operand_Type, rex: u8) -> Register { +decode_register :: #force_inline proc "contextless" (num: u8, op_type: Operand_Type, rex: u8) -> Register { #partial switch op_type { case .R64, .RM64: return gpr64_from_num(num) @@ -1032,7 +1029,7 @@ decode :: proc( } data_length := len(data) - pos: u32 = 0 + pos := 0 has_errors := false // Track branch targets for label inference (resolved in pass 2 by isa). @@ -1043,12 +1040,12 @@ decode :: proc( // PASS 1: Decode all instructions, collect branch targets // ========================================================================= - for pos < u32(data_length) { + for pos < data_length { inst: Instruction info: Instruction_Info // Record offset - info.offset = pos + info.offset = u32(pos) // Initialize decoder state state := Decoder_State{ @@ -1080,7 +1077,7 @@ decode :: proc( is_dec := (b & 0x08) != 0 reg: Register = state.prefix_66 ? gpr16_from_num(reg_num) : gpr32_from_num(reg_num) - inst.mnemonic = is_dec ? Mnemonic.DEC : Mnemonic.INC + inst.mnemonic = is_dec ? .DEC : .INC inst.operand_count = 1 inst.ops[0] = op_reg(reg) inst.length = u8(state.position) @@ -1095,7 +1092,7 @@ decode :: proc( append(instructions, inst) append(inst_info, info) - pos += u32(state.position) + pos += state.position continue } } @@ -1140,7 +1137,7 @@ decode :: proc( info.rep = inst.flags.rep info.segment = state.segment info.vex_type = state.vex_type - if state.vex_type != .NONE && vex_entry != nil { + if state.vex_type != nil && vex_entry != nil { // Use encoding requirements to distinguish LIG/WIG from L0/W0 // If encoding says LIG, the actual L value doesn't matter for re-encoding // If encoding says L0/L1/L2, we should preserve the actual value @@ -1157,7 +1154,7 @@ decode :: proc( info.evex_b = state.evex_b info.evex_z = state.evex_z info.opmask = state.evex_aaa - } else if state.vex_type != .NONE { + } else if state.vex_type != nil { // Fallback when vex_entry is nil (shouldn't happen normally) info.vex_l = state.vex_l == 0 ? .L0 : (state.vex_l == 1 ? .L1 : .L2) info.vex_w = state.vex_w ? .W1 : .W0 @@ -1167,7 +1164,7 @@ decode :: proc( } // Check for relative operands and record pending branch targets - inst_end := pos + u32(state.position) + inst_end := pos + state.position for op_idx in 0.. bool { +encoding_matches_inline :: proc "contextless" (inst: ^Instruction, enc: ^Encoding, mode: Mode) -> bool { // Mode gate: skip i386-only encodings (short-form INC/DEC at 0x40-0x4F) // when not in Mode._32. if enc.flags.mode_32_only && mode != ._32 { return false } @@ -740,7 +740,7 @@ encoding_matches_inline :: #force_inline proc "contextless" (inst: ^Instruction, if user_idx >= inst.operand_count - 1 { return false } effective_op_type := mode_rewrite_op_type(op_type, mode, enc.flags.default_64) - if !operand_matches_inline(&inst.ops[user_idx], effective_op_type) { return false } + operand_matches_inline(&inst.ops[user_idx], effective_op_type) or_return user_idx += 1 } return user_idx == inst.operand_count - 1 @@ -757,7 +757,7 @@ encoding_matches_inline :: #force_inline proc "contextless" (inst: ^Instruction, if user_idx >= inst.operand_count { return false } effective_op_type := mode_rewrite_op_type(op_type, mode, enc.flags.default_64) - if !operand_matches_inline(&inst.ops[user_idx], effective_op_type) { return false } + operand_matches_inline(&inst.ops[user_idx], effective_op_type) or_return user_idx += 1 } @@ -861,16 +861,16 @@ imm_matches_inline :: #force_inline proc "contextless" (op: ^Operand, op_type: O #partial switch op_type { case .IMM8: // Full 8-bit range: signed [-128, 127] OR unsigned [0, 255] - return op.immediate >= -128 && op.immediate <= 255 + return -128 <= op.immediate && op.immediate <= 255 case .IMM8SX: // Sign-extended 8-bit: must be in signed 8-bit range - return op.immediate >= -128 && op.immediate <= 127 + return -128 <= op.immediate && op.immediate <= 127 case .IMM16: // Full 16-bit range: signed [-32768, 32767] OR unsigned [0, 65535] - return op.immediate >= -32768 && op.immediate <= 65535 + return -32768 <= op.immediate && op.immediate <= 65535 case .IMM32: // Full 32-bit range: signed [-2147483648, 2147483647] OR unsigned [0, 4294967295] - return op.immediate >= -2147483648 && op.immediate <= 4294967295 + return -2147483648 <= op.immediate && op.immediate <= 4294967295 case .IMM64: return true // Any i64 value fits } diff --git a/core/rexcode/x86/registers.odin b/core/rexcode/x86/registers.odin index b9f6eaa44..a3554f5ab 100644 --- a/core/rexcode/x86/registers.odin +++ b/core/rexcode/x86/registers.odin @@ -324,13 +324,13 @@ reg_needs_evex :: #force_inline proc "contextless" (r: Register) -> bool { @(require_results) reg_is_gpr :: #force_inline proc "contextless" (r: Register) -> bool { c := reg_class(r) - return c >= REG_GPR64 && c <= REG_GPR8H + return REG_GPR64 <= c && c <= REG_GPR8H } @(require_results) reg_is_vector :: #force_inline proc "contextless" (r: Register) -> bool { c := reg_class(r) - return c >= REG_XMM && c <= REG_ZMM + return REG_XMM <= c && c <= REG_ZMM } @(require_results) @@ -340,7 +340,7 @@ reg_is_high_byte :: #force_inline proc "contextless" (r: Register) -> bool { // Size in bits for register @(require_results) -reg_size :: proc "contextless" (r: Register) -> u16 { +reg_size :: #force_inline proc "contextless" (r: Register) -> u16 { switch reg_class(r) { case REG_GPR64: return 64 case REG_GPR32: return 32 @@ -382,19 +382,18 @@ gpr16_from_num :: #force_inline proc "contextless" (num: u8) -> Register { return num < 16 ? Register(REG_GPR16 | u16(num)) : NONE } -gpr8_from_num :: proc(num: u8, has_rex: bool) -> Register { +@(require_results) +gpr8_from_num :: #force_inline proc "contextless" (num: u8, has_rex: bool) -> Register { // Without REX prefix, nums 4-7 encode AH/CH/DH/BH (high byte legacy regs) // With REX prefix, nums 4-7 encode SPL/BPL/SIL/DIL (low byte regs) if has_rex { return num < 16 ? Register(REG_GPR8 | u16(num)) : NONE - } else { - if num < 4 { - return Register(REG_GPR8 | u16(num)) // AL, CL, DL, BL - } else if num < 8 { - return Register(REG_GPR8H | u16(num)) // AH, CH, DH, BH (hw num 4-7) - } - return NONE + } else if num < 4 { + return Register(REG_GPR8 | u16(num)) // AL, CL, DL, BL + } else if num < 8 { + return Register(REG_GPR8H | u16(num)) // AH, CH, DH, BH (hw num 4-7) } + return NONE } @(require_results) diff --git a/core/rexcode/x86/tests/test.odin b/core/rexcode/x86/tests/test.odin index f5c76623c..552d8ec01 100644 --- a/core/rexcode/x86/tests/test.odin +++ b/core/rexcode/x86/tests/test.odin @@ -6,7 +6,6 @@ import x86 "../" import "../../isa" import "core:fmt" import "core:time" -import "core:slice" import "core:strings" import "core:mem/virtual" import "core:math" @@ -3051,7 +3050,7 @@ run_benchmarks :: proc() { bench_insts := make([dynamic]x86.Instruction) defer delete(bench_insts) - for _ in 0..<1000 { + for _ in 0..<100 { insts := []x86.Instruction{ x86.inst_r(.PUSH, x86.RBP), x86.inst_r_r(.MOV, x86.RBP, x86.RSP), @@ -3071,25 +3070,34 @@ run_benchmarks :: proc() { append(&bench_insts, ..insts) } - code_buf: [16 * 1024]u8 + code_buf := make([]byte, 1<<16) + defer delete(code_buf) + labels: [4]x86.Label_Definition + relocs: [dynamic]x86.Relocation; defer delete(relocs) + errs: [dynamic]x86.Error; defer delete(relocs) + + insts: [dynamic]x86.Instruction; defer delete(insts) + info: [dynamic]x86.Instruction_Info; defer delete(info) + lbls: [dynamic]x86.Label_Definition; defer delete(lbls) + // Encode enc_start := time.now() enc_bytes := 0 for _ in 0.. Date: Mon, 15 Jun 2026 21:43:58 +0100 Subject: [PATCH 08/27] Replace `-> isa.Result` with `-> (byte_code: u32, ok: bool)` --- core/rexcode/arm32/decoder.odin | 26 +-- core/rexcode/arm32/encoder.odin | 27 +-- core/rexcode/arm32/encoding_types.odin | 1 - core/rexcode/arm32/tests/pipeline.odin | 22 +-- core/rexcode/arm32/tests/sweep.odin | 4 +- core/rexcode/arm64/decoder.odin | 20 +- core/rexcode/arm64/encoder.odin | 18 +- core/rexcode/arm64/encoding_types.odin | 1 - core/rexcode/arm64/tests/pipeline_smoke.odin | 184 +++++++++--------- core/rexcode/isa/status.odin | 4 - core/rexcode/mips/decoder.odin | 20 +- core/rexcode/mips/encoder.odin | 20 +- core/rexcode/mips/encoding_types.odin | 1 - core/rexcode/mips/tests/decode_smoke.odin | 54 ++--- core/rexcode/mips/tests/encode_smoke.odin | 42 ++-- core/rexcode/mips/tests/print_smoke.odin | 16 +- core/rexcode/mos6502/decoder.odin | 18 +- core/rexcode/mos6502/encoder.odin | 31 ++- core/rexcode/mos6502/encoding_types.odin | 1 - .../rexcode/mos6502/tests/pipeline_smoke.odin | 42 ++-- core/rexcode/mos65816/decoder.odin | 18 +- core/rexcode/mos65816/encoder.odin | 27 ++- core/rexcode/mos65816/encoding_types.odin | 1 - core/rexcode/mos65816/tests/smoke.odin | 30 +-- core/rexcode/ppc/decoder.odin | 26 +-- core/rexcode/ppc/encoder.odin | 20 +- core/rexcode/ppc/encoding_types.odin | 1 - core/rexcode/ppc/tests/branch_reloc.odin | 8 +- core/rexcode/ppc/tests/decode_sweep.odin | 4 +- core/rexcode/ppc/tests/full_sweep.odin | 18 +- core/rexcode/ppc/tests/roundtrip.odin | 12 +- core/rexcode/ppc_vle/decoder.odin | 28 +-- core/rexcode/ppc_vle/encoder.odin | 19 +- core/rexcode/ppc_vle/encoding_types.odin | 1 - core/rexcode/ppc_vle/tests/branch_test.odin | 24 +-- core/rexcode/ppc_vle/tests/cond_branch.odin | 14 +- core/rexcode/ppc_vle/tests/e2e.odin | 14 +- core/rexcode/ppc_vle/tests/extension.odin | 8 +- core/rexcode/ppc_vle/tests/full_sweep.odin | 18 +- core/rexcode/ppc_vle/tests/operand_test.odin | 8 +- core/rexcode/ppc_vle/tests/roundtrip.odin | 12 +- core/rexcode/riscv/decoder.odin | 24 +-- core/rexcode/riscv/encoder.odin | 22 +-- core/rexcode/riscv/encoding_types.odin | 1 - core/rexcode/riscv/tests/pipeline_smoke.odin | 86 ++++---- core/rexcode/rsp/decoder.odin | 20 +- core/rexcode/rsp/encoder.odin | 20 +- core/rexcode/rsp/encoding_types.odin | 1 - core/rexcode/rsp/tests/pipeline_smoke.odin | 46 ++--- core/rexcode/x86/decoder.odin | 40 ++-- core/rexcode/x86/encoder.odin | 36 ++-- core/rexcode/x86/encoding_types.odin | 1 - core/rexcode/x86/tests/test.odin | 31 ++- 53 files changed, 580 insertions(+), 611 deletions(-) diff --git a/core/rexcode/arm32/decoder.odin b/core/rexcode/arm32/decoder.odin index 9ee267889..ebc739157 100644 --- a/core/rexcode/arm32/decoder.odin +++ b/core/rexcode/arm32/decoder.odin @@ -40,7 +40,7 @@ decode :: proc( label_defs: ^[dynamic]Label_Definition, errors: ^[dynamic]Error, mode: Mode = .A32, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_bytes := u32(len(data)) if mode == .T32 { n_bytes = n_bytes & ~u32(1) } else { n_bytes = n_bytes & ~u32(3) } @@ -50,21 +50,20 @@ decode :: proc( pending_branches: [dynamic]isa.Branch_Target defer delete(pending_branches) - pc: u32 = 0 - for pc < n_bytes { + for byte_count < n_bytes { word: u32 ilen: u32 = 4 if mode == .A32 { - if pc + 4 > n_bytes { break } - word = read_u32_le(data, pc) + if byte_count + 4 > n_bytes { break } + word = read_u32_le(data, byte_count) } else { // T32: 16 or 32 bit - hword_hi := read_u16_le(data, pc) + hword_hi := read_u16_le(data, byte_count) top5 := (hword_hi >> 11) & 0x1F if top5 == 0x1D || top5 == 0x1E || top5 == 0x1F { - if pc + 4 > n_bytes { break } - hword_lo := read_u16_le(data, pc + 2) + if byte_count + 4 > n_bytes { break } + hword_lo := read_u16_le(data, byte_count + 2) // Pack: bits = low_halfword | (high_halfword << 16) word = u32(hword_lo) | (u32(hword_hi) << 16) ilen = 4 @@ -76,10 +75,10 @@ decode :: proc( inst: Instruction info: Instruction_Info - info.offset = pc + info.offset = byte_count if !find_and_decode(word, mode, ilen, &inst, &info) { - append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE}) + append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE}) inst = Instruction{mnemonic = .INVALID, length = u8(ilen), mode = mode} } else { inst.length = u8(ilen) @@ -103,11 +102,12 @@ decode :: proc( append(instructions, inst) append(inst_info, info) - pc += ilen + byte_count += ilen } - isa.infer_labels_from_branches(pending_branches[:], pc, label_defs, relocs) - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + isa.infer_labels_from_branches(pending_branches[:], byte_count, label_defs, relocs) + ok = u32(len(errors)) == errors_start + return } // ============================================================================= diff --git a/core/rexcode/arm32/encoder.odin b/core/rexcode/arm32/encoder.odin index 94dcf851b..031f7337d 100644 --- a/core/rexcode/arm32/encoder.odin +++ b/core/rexcode/arm32/encoder.odin @@ -34,38 +34,37 @@ encode :: proc( errors: ^[dynamic]Error, resolve: bool = true, base_address: u64 = 0, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_inst := len(instructions) if len(code) < n_inst * 4 { append(errors, Error{inst_idx = 0, code = .BUFFER_OVERFLOW}) - return Result{byte_count = 0, success = false} + return } errors_start := u32(len(errors)) pending_start := u32(len(relocs)) - pc: u32 = 0 inst_pc := make([]u32, n_inst, context.temp_allocator) // ---- PASS 1 ------------------------------------------------------------ for i in 0..> 16)) - write_u16_le(code, pc + 2, u16(word)) + write_u16_le(code, byte_count, u16(word >> 16)) + write_u16_le(code, byte_count + 2, u16(word)) } else { - write_u32_le(code, pc, word) + write_u32_le(code, byte_count, word) } } - pc += u32(ilen) + byte_count += u32(ilen) } // ---- PASS 1.5: label_def instruction-idx -> byte-offset ----------------- @@ -81,7 +80,8 @@ encode :: proc( } if !resolve { - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } // ---- PASS 2: resolve relocations ---------------------------------------- @@ -97,7 +97,8 @@ encode :: proc( } if write_idx != n_relocs { resize(relocs, int(write_idx)) } - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } // ============================================================================= diff --git a/core/rexcode/arm32/encoding_types.odin b/core/rexcode/arm32/encoding_types.odin index f8614cb88..cb0e89784 100644 --- a/core/rexcode/arm32/encoding_types.odin +++ b/core/rexcode/arm32/encoding_types.odin @@ -51,7 +51,6 @@ import "../isa" // All operand-driven fields live in the zeros of `mask`; the encoder ORs // them in. The matcher tests `(word & mask) == bits`. -Result :: isa.Result Error :: isa.Error Error_Code :: isa.Error_Code Label_Definition :: isa.Label_Definition diff --git a/core/rexcode/arm32/tests/pipeline.odin b/core/rexcode/arm32/tests/pipeline.odin index a83b1fa68..d1373f2e0 100644 --- a/core/rexcode/arm32/tests/pipeline.odin +++ b/core/rexcode/arm32/tests/pipeline.odin @@ -21,14 +21,14 @@ check_bytes :: proc(name: string, inst: a.Instruction, want: []u8) { errors: [dynamic]a.Error defer { delete(label_defs); delete(code); delete(relocs); delete(errors) } - res := a.encode(insts, label_defs[:], code, &relocs, &errors) - if !res.success { + byte_count, success := a.encode(insts, label_defs[:], code, &relocs, &errors) + if !success { fmt.printf(" [FAIL] %s: encode failed (errors=%d)\n", name, len(errors)) fail += 1 return } - if int(res.byte_count) != len(want) { - fmt.printf(" [FAIL] %s: got %d bytes, want %d\n", name, res.byte_count, len(want)) + if int(byte_count) != len(want) { + fmt.printf(" [FAIL] %s: got %d bytes, want %d\n", name, byte_count, len(want)) fail += 1 return } @@ -55,9 +55,9 @@ check_decode :: proc(name: string, bytes: []u8, want_mn: a.Mnemonic, mode: a.Mod labels: [dynamic]a.Label_Definition errors: [dynamic]a.Error defer { delete(insts); delete(info); delete(labels); delete(errors) } - res := a.decode(bytes, relocs, &insts, &info, &labels, &errors, mode) - if !res.success || len(insts) == 0 { - fmt.printf(" [FAIL] decode %s: success=%v len=%d\n", name, res.success, len(insts)) + byte_count, success := a.decode(bytes, relocs, &insts, &info, &labels, &errors, mode) + if !success || len(insts) == 0 { + fmt.printf(" [FAIL] decode %s: success=%v len=%d\n", name, success, len(insts)) fail += 1 return } @@ -160,8 +160,8 @@ check_roundtrip :: proc(name: string, inst: a.Instruction) { errors: [dynamic]a.Error defer { delete(label_defs); delete(code); delete(relocs); delete(errors) } - res := a.encode(insts, label_defs[:], code, &relocs, &errors) - if !res.success { + byte_count, success := a.encode(insts, label_defs[:], code, &relocs, &errors) + if !success { fmt.printf(" [FAIL] roundtrip %s: encode failed\n", name) fail += 1 return @@ -174,8 +174,8 @@ check_roundtrip :: proc(name: string, inst: a.Instruction) { dec_err: [dynamic]a.Error defer { delete(decoded); delete(info); delete(labels); delete(dec_err) } - dec_res := a.decode(code[:res.byte_count], dec_relocs, &decoded, &info, &labels, &dec_err, inst.mode) - if !dec_res.success || len(decoded) == 0 { + dec_byte_count, dec_success := a.decode(code[:byte_count], dec_relocs, &decoded, &info, &labels, &dec_err, inst.mode) + if !dec_success || len(decoded) == 0 { fmt.printf(" [FAIL] roundtrip %s: decode failed\n", name) fail += 1 return diff --git a/core/rexcode/arm32/tests/sweep.odin b/core/rexcode/arm32/tests/sweep.odin index cc52a971e..884410fcb 100644 --- a/core/rexcode/arm32/tests/sweep.odin +++ b/core/rexcode/arm32/tests/sweep.odin @@ -113,8 +113,8 @@ run_sweep_tests :: proc() { ren_errors: [dynamic]a.Error out: [4]u8 defer { delete(ren_relocs); delete(ren_errors) } - res := a.encode(insts[:], label_defs[:], out[:], &ren_relocs, &ren_errors, resolve=false) - if !res.success { + byte_count, success := a.encode(insts[:], label_defs[:], out[:], &ren_relocs, &ren_errors, resolve=false) + if !success { stats.fail_encode += 1 if failed_examples < max_fail_print && (only_print_kind == "" || only_print_kind == "re-enc") { fmt.printf(" [re-enc ] %v[%d] %08X re-encode failed\n", mn, idx, word) diff --git a/core/rexcode/arm64/decoder.odin b/core/rexcode/arm64/decoder.odin index 86992aa09..697ed2b4e 100644 --- a/core/rexcode/arm64/decoder.odin +++ b/core/rexcode/arm64/decoder.odin @@ -36,25 +36,24 @@ decode :: proc( label_defs: ^[dynamic]Label_Definition, errors: ^[dynamic]Error, endianness: Endianness = .LITTLE, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_bytes := u32(len(data)) & ~u32(3) errors_start := u32(len(errors)) pending_branches: [dynamic]isa.Branch_Target defer delete(pending_branches) - pc: u32 = 0 - for pc < n_bytes { - word := read_u32(data, pc, endianness) + for byte_count < n_bytes { + word := read_u32(data, byte_count, endianness) inst: Instruction info: Instruction_Info - entry_idx := decode_one_inline(word, pc, &inst, &info) + entry_idx := decode_one_inline(word, byte_count, &inst, &info) if entry_idx < 0 { - append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE}) + append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE}) inst = Instruction{mnemonic = .INVALID, length = 4} - info = Instruction_Info{offset = pc} + info = Instruction_Info{offset = byte_count} } else { inst_idx_for_branches := u32(len(instructions)) for slot in 0.. Result { +) -> (byte_count: u32, ok: bool) { n_inst := u32(len(instructions)) if u32(len(code)) < n_inst * 4 { append(errors, Error{inst_idx = 0, code = .BUFFER_OVERFLOW}) - return Result{byte_count = 0, success = false} + return } errors_start := u32(len(errors)) pending_start := u32(len(relocs)) - pc: u32 = 0 // ---- PASS 1 ----------------------------------------------------------- for i in 0.. *4 ------------------------------------- @@ -71,7 +69,8 @@ encode :: proc( } if !resolve { - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } // ---- PASS 2: resolve relocations ------------------------------------- @@ -87,7 +86,8 @@ encode :: proc( } if write_idx != n_relocs { resize(relocs, int(write_idx)) } - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } // ============================================================================= diff --git a/core/rexcode/arm64/encoding_types.odin b/core/rexcode/arm64/encoding_types.odin index 9f575f34d..a1fc646df 100644 --- a/core/rexcode/arm64/encoding_types.odin +++ b/core/rexcode/arm64/encoding_types.odin @@ -37,7 +37,6 @@ import "../isa" // option 13-15 extend type (data-proc extended register, LDR/STR EXT) // imm3 10-12 extend amount -Result :: isa.Result Error :: isa.Error Error_Code :: isa.Error_Code Label_Definition :: isa.Label_Definition diff --git a/core/rexcode/arm64/tests/pipeline_smoke.odin b/core/rexcode/arm64/tests/pipeline_smoke.odin index 432539ad1..0e43529d3 100644 --- a/core/rexcode/arm64/tests/pipeline_smoke.odin +++ b/core/rexcode/arm64/tests/pipeline_smoke.odin @@ -78,8 +78,8 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.inst_r_r_i(.ADD_IMM, a.X0, a.X1, 100), } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("ADD_IMM: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("ADD_IMM: encode", success) eq_word("ADD X0,X1,#100", load_le(code[:], 0), 0x91019020) } @@ -92,8 +92,8 @@ run_pipeline_tests :: proc() { clear(&relocs); clear(&errors) for i in 0..= 1 && d_insts[0].mnemonic == .AMX_SET) ok("AMX: LDX", len(d_insts) >= 2 && d_insts[1].mnemonic == .AMX_LDX) @@ -651,9 +651,9 @@ run_pipeline_tests :: proc() { isa.label_set_at(&labels, fwd, &insts) // .L1: at instruction 4 append(&insts, a.inst_none(.RET)) // [4] byte 16: RET - r := a.encode(insts[:], labels[:], code[:], &relocs, &errors) - ok("anon labels: encode", r.success) - ok("anon labels: byte_count = 20", r.byte_count == 20) + byte_count, success := a.encode(insts[:], labels[:], code[:], &relocs, &errors) + ok("anon labels: encode", success) + ok("anon labels: byte_count = 20", byte_count == 20) // B.LT at byte 8 -> .L1 at byte 16: offset = +8 = +2 words. // bits = 0x54000000 | (2<<5) | LT(0xB) = 0x5400004B @@ -670,7 +670,7 @@ run_pipeline_tests :: proc() { d_labels: [dynamic]a.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - a.decode(code[:r.byte_count], nil, &d_insts, &d_info, &d_labels, &errors) + a.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors) ok("anon labels: decode 5 insts", len(d_insts) == 5) have_back, have_fwd: bool for ld in d_labels { @@ -713,8 +713,8 @@ run_pipeline_tests :: proc() { ops = {a.op_reg(a.X3), a.op_imm(a.DCZID_EL0, 2), {}, {}}, }, } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("sysreg: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("sysreg: encode", success) eq_word("MRS X0,NZCV", load_le(code[:], 0), 0xD53B4200) eq_word("MRS X1,TPIDR_EL0", load_le(code[:], 4), 0xD53BD041) eq_word("MRS X2,CNTVCT_EL0", load_le(code[:], 8), 0xD53BE042) @@ -729,8 +729,8 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.inst_r(.DC_ZVA, a.X0), } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("DC ZVA: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("DC ZVA: encode", success) eq_word("DC ZVA X0", load_le(code[:], 0), 0xD50B7420) d_insts: [dynamic]a.Instruction @@ -738,7 +738,7 @@ run_pipeline_tests :: proc() { d_labels: [dynamic]a.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - a.decode(code[:r.byte_count], nil, &d_insts, &d_info, &d_labels, &errors) + a.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors) ok("DC ZVA: decode", len(d_insts) == 1 && d_insts[0].mnemonic == .DC_ZVA) ok("DC ZVA: Rt = X0", len(d_insts) == 1 && d_insts[0].ops[0].reg == a.X0) } @@ -756,8 +756,8 @@ run_pipeline_tests :: proc() { ops = {a.op_reg(a.X0), a.op_shifted(a.X1, .LSL, 0), {}, {}}, }, } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("CMP_SR: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("CMP_SR: encode", success) eq_word("CMP X0,X1", load_le(code[:], 0), 0xEB01001F) } @@ -786,8 +786,8 @@ run_pipeline_tests :: proc() { ops = {a.op_reg(a.X0), a.op_reg(a.X1), a.op_reg(a.X2), {}}, }, } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("MOPS CPY: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("MOPS CPY: encode", success) eq_word("CPYP X0,X1,X2", load_le(code[:], 0), 0x1D020420) eq_word("CPYM X0,X1,X2", load_le(code[:], 4), 0x1D420420) eq_word("CPYE X0,X1,X2", load_le(code[:], 8), 0x1D820420) @@ -808,8 +808,8 @@ run_pipeline_tests :: proc() { ops = {a.op_z_s(0), a.op_z_s(1), a.op_z_s(2), a.op_imm(2, 1)}, }, } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("SVE FMLA indexed: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("SVE FMLA indexed: encode", success) eq_word("SVE FMLA Z0.S, Z1.S, Z2.S[2]", load_le(code[:], 0), 0x64B20020) } @@ -835,8 +835,8 @@ run_pipeline_tests :: proc() { ops = {a.op_z_s(0), a.op_reg(p0), a.op_mem(mem), {}}, }, } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("SVE LD1W gather: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("SVE LD1W gather: encode", success) eq_word("SVE LD1W Z0.S,P0/Z,[X1,Z2.S,UXTW]", load_le(code[:], 0), 0x85024020) } @@ -864,8 +864,8 @@ run_pipeline_tests :: proc() { ops = {a.op_imm(slice_packed, 2), a.op_reg(p5), a.op_mem(mem), {}}, }, } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("SME LD1B tile vs LLVM: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("SME LD1B tile vs LLVM: encode", success) eq_word("SME LD1B ZA0V.B[W14,5],P5/Z,[X10,X21]", load_le(code[:], 0), 0xE015D545) d_insts: [dynamic]a.Instruction @@ -873,7 +873,7 @@ run_pipeline_tests :: proc() { d_labels: [dynamic]a.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - a.decode(code[:r.byte_count], nil, &d_insts, &d_info, &d_labels, &errors) + a.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors) ok("SME LD1B tile: decode 1 inst", len(d_insts) == 1) ok("SME LD1B tile: mnemonic", len(d_insts) == 1 && d_insts[0].mnemonic == .SME_LD1B_TILE) ok("SME LD1B tile: slice roundtrip", @@ -891,8 +891,8 @@ run_pipeline_tests :: proc() { ops = {a.op_v_4s(0), a.op_v_4s(1), a.op_v_4s(2), a.op_imm(0, 1)}, }, } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("FCMLA: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("FCMLA: encode", success) eq_word("FCMLA V0.4S,V1.4S,V2.4S,#0", load_le(code[:], 0), 0x6E82C420) } @@ -908,8 +908,8 @@ run_pipeline_tests :: proc() { a.inst_none(.TCOMMIT), a.inst_r(.TTEST, a.X1), } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("TME: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("TME: encode", success) eq_word("TSTART X0", load_le(code[:], 0), 0xD5233060) eq_word("TCOMMIT", load_le(code[:], 4), 0xD503307F) eq_word("TTEST X1", load_le(code[:], 8), 0xD5233161) @@ -925,8 +925,8 @@ run_pipeline_tests :: proc() { a.inst_r_r(.UXTB, a.W0, a.W1), a.inst_r_r(.SXTW, a.X0, a.W1), } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("extend aliases: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("extend aliases: encode", success) eq_word("UXTB W0,W1", load_le(code[:], 0), 0x53001C20) eq_word("SXTW X0,W1", load_le(code[:], 4), 0x93407C20) } @@ -942,8 +942,8 @@ run_pipeline_tests :: proc() { a.inst_r_r_r(.ADC, a.X0, a.X1, a.X2), a.inst_r_r_r(.SBCS, a.X3, a.X4, a.X5), } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("ADC/SBCS: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("ADC/SBCS: encode", success) eq_word("ADC X0,X1,X2", load_le(code[:], 0), 0x9A020020) eq_word("SBCS X3,X4,X5", load_le(code[:], 4), 0xFA050083) } @@ -961,8 +961,8 @@ run_pipeline_tests :: proc() { ops = {a.op_reg(a.X7), a.op_imm(a.RNDR, 2), {}, {}}, }, } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("MRS X7,RNDR: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("MRS X7,RNDR: encode", success) eq_word("MRS X7,RNDR", load_le(code[:], 0), 0xD53B2407) } @@ -979,8 +979,8 @@ run_pipeline_tests :: proc() { a.inst_ldst(.LDAPUR, a.X0, a.mem_offset(a.X1, 8)), a.inst_ldst(.STLUR, a.X2, a.mem_offset(a.SP, -8)), } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("RCpc unscaled: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("RCpc unscaled: encode", success) eq_word("LDAPUR X0,[X1,#8]", load_le(code[:], 0), 0xD9408020) eq_word("STLUR X2,[SP,#-8]", load_le(code[:], 4), 0xD91F83E2) } @@ -994,8 +994,8 @@ run_pipeline_tests :: proc() { a.inst_none(.BTI_J), a.inst_none(.PSB_CSYNC), } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("barriers/BTI: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("barriers/BTI: encode", success) eq_word("SB", load_le(code[:], 0), 0xD50330FF) eq_word("BTI j", load_le(code[:], 4), 0xD503245F) eq_word("PSB CSYNC", load_le(code[:], 8), 0xD503223F) @@ -1011,8 +1011,8 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.inst_r_r_i(.LSL_IMM, a.W0, a.W1, 4), } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("LSL_IMM 32: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("LSL_IMM 32: encode", success) eq_word("LSL W0,W1,#4", load_le(code[:], 0), 0x531C6C20) } @@ -1026,8 +1026,8 @@ run_pipeline_tests :: proc() { insts := []a.Instruction{ a.inst_r_r_i(.ROR_IMM, a.W0, a.W1, 4), } - r := a.encode(insts, nil, code[:], &relocs, &errors) - ok("ROR_IMM 32: encode", r.success) + byte_count, success := a.encode(insts, nil, code[:], &relocs, &errors) + ok("ROR_IMM 32: encode", success) eq_word("ROR W0,W1,#4", load_le(code[:], 0), 0x13811020) } diff --git a/core/rexcode/isa/status.odin b/core/rexcode/isa/status.odin index 9ccff1663..35ece81e0 100644 --- a/core/rexcode/isa/status.odin +++ b/core/rexcode/isa/status.odin @@ -43,7 +43,3 @@ Error :: struct #packed { } #assert(size_of(Error) == 8) -Result :: struct { - byte_count: u32, // Bytes written/read - success: bool, // True if no errors -} diff --git a/core/rexcode/mips/decoder.odin b/core/rexcode/mips/decoder.odin index 3210a512d..22b0e83cd 100644 --- a/core/rexcode/mips/decoder.odin +++ b/core/rexcode/mips/decoder.odin @@ -57,7 +57,7 @@ decode :: proc( label_defs: ^[dynamic]Label_Definition, errors: ^[dynamic]Error, endianness: Endianness = .BIG, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_bytes := u32(len(data)) if n_bytes & 3 != 0 { n_bytes &= ~u32(3) // ignore the dangling tail @@ -68,18 +68,17 @@ decode :: proc( defer delete(pending_branches) // ---- PASS 1 ----------------------------------------------------------- - pc: u32 = 0 - for pc < n_bytes { - word := read_u32(data, pc, endianness) + for byte_count < n_bytes { + word := read_u32(data, byte_count, endianness) inst: Instruction info: Instruction_Info - entry_idx := decode_one_inline(word, pc, &inst, &info) + entry_idx := decode_one_inline(word, byte_count, &inst, &info) if entry_idx < 0 { - append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE}) + append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE}) inst = Instruction{mnemonic = .INVALID, length = 4} - info = Instruction_Info{offset = pc} + info = Instruction_Info{offset = byte_count} } else { inst_idx_for_branches := u32(len(instructions)) for slot in 0.. Result { +) -> (byte_count: u32, ok: bool) { n_inst := u32(len(instructions)) if u32(len(code)) < n_inst * 4 { append(errors, Error{inst_idx = 0, code = .BUFFER_OVERFLOW}) - return Result{byte_count = 0, success = false} + return } errors_start := u32(len(errors)) pending_start := u32(len(relocs)) - pc: u32 = 0 // ---- PASS 1 ------------------------------------------------------------ for i in 0.. 0 && errors[0].code == .BUFFER_OVERFLOW, @@ -300,9 +300,9 @@ run_encoder_tests :: proc() { insts := []mips.Instruction{ mips.inst_r_r_r(.ADD_S, mips.F4, mips.F5, mips.F6), } - res := mips.encode(insts, nil, code[:], &relocs, &errors) + byte_count, success := mips.encode(insts, nil, code[:], &relocs, &errors) - check_bool("FPU: success", res.success, true) + check_bool("FPU: success", success, true) check_word("FPU: ADD.S", load_word_be(code[:], 0), 0x46062900) } @@ -316,9 +316,9 @@ run_encoder_tests :: proc() { insts := []mips.Instruction{ mips.inst_none(.RTPS), } - res := mips.encode(insts, nil, code[:], &relocs, &errors) + byte_count, success := mips.encode(insts, nil, code[:], &relocs, &errors) - check_bool("GTE: success", res.success, true) + check_bool("GTE: success", success, true) check_word("GTE: RTPS", load_word_be(code[:], 0), 0x4A000001) } diff --git a/core/rexcode/mips/tests/print_smoke.odin b/core/rexcode/mips/tests/print_smoke.odin index f346a38c6..336ae5fbb 100644 --- a/core/rexcode/mips/tests/print_smoke.odin +++ b/core/rexcode/mips/tests/print_smoke.odin @@ -38,8 +38,8 @@ encode_and_print :: proc( defer delete(relocs) defer delete(errors) - eres := mips.encode(insts, label_defs, code[:], &relocs, &errors) - if !eres.success { return "" } + byte_count, esuccess := mips.encode(insts, label_defs, code[:], &relocs, &errors) + if !esuccess { return "" } dec_insts: [dynamic]mips.Instruction dec_info: [dynamic]mips.Instruction_Info @@ -49,9 +49,9 @@ encode_and_print :: proc( defer delete(dec_labels) clear(&errors) - dres := mips.decode(code[:eres.byte_count], nil, + _, dsuccess := mips.decode(code[:byte_count], nil, &dec_insts, &dec_info, &dec_labels, &errors) - if !dres.success { return "" } + if !dsuccess { return "" } sb := strings.builder_make(context.temp_allocator) mips.sbprint(&sb, dec_insts[:], dec_info[:], dec_labels[:]) @@ -162,7 +162,7 @@ run_printer_tests :: proc() { mips.inst_none(.NOP), mips.inst_branch2(.BEQ, mips.T0, mips.T1, 0), } - eres := mips.encode(insts, ld[:], code[:], &relocs, &errors) + byte_count, _ := mips.encode(insts, ld[:], code[:], &relocs, &errors) dec_insts: [dynamic]mips.Instruction dec_info: [dynamic]mips.Instruction_Info @@ -171,7 +171,7 @@ run_printer_tests :: proc() { defer delete(dec_info) defer delete(dec_labels) clear(&errors) - mips.decode(code[:eres.byte_count], nil, &dec_insts, &dec_info, &dec_labels, &errors) + mips.decode(code[:byte_count], nil, &dec_insts, &dec_info, &dec_labels, &errors) names: map[u32]string defer delete(names) @@ -197,7 +197,7 @@ run_printer_tests :: proc() { errors: [dynamic]mips.Error defer delete(relocs) defer delete(errors) - eres := mips.encode(insts, nil, code[:], &relocs, &errors) + byte_count, _ := mips.encode(insts, nil, code[:], &relocs, &errors) dec_insts: [dynamic]mips.Instruction dec_info: [dynamic]mips.Instruction_Info @@ -206,7 +206,7 @@ run_printer_tests :: proc() { defer delete(dec_info) defer delete(dec_labels) clear(&errors) - mips.decode(code[:eres.byte_count], nil, &dec_insts, &dec_info, &dec_labels, &errors) + mips.decode(code[:byte_count], nil, &dec_insts, &dec_info, &dec_labels, &errors) out := mips.aprint(dec_insts[:], dec_info[:], dec_labels[:], nil, &opts, nil, context.temp_allocator) diff --git a/core/rexcode/mos6502/decoder.odin b/core/rexcode/mos6502/decoder.odin index 4e1327fe2..96515419d 100644 --- a/core/rexcode/mos6502/decoder.odin +++ b/core/rexcode/mos6502/decoder.odin @@ -44,23 +44,22 @@ decode :: proc( label_defs: ^[dynamic]Label_Definition, errors: ^[dynamic]Error, cpu: CPU = .NMOS, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_bytes := u32(len(data)) errors_start := u32(len(errors)) pending_branches: [dynamic]isa.Branch_Target defer delete(pending_branches) - pc: u32 = 0 - for pc < n_bytes { + for byte_count < n_bytes { inst: Instruction info: Instruction_Info - entry_idx, consumed := decode_one_inline(data, pc, n_bytes, cpu, &inst, &info) + entry_idx, consumed := decode_one_inline(data, byte_count, n_bytes, cpu, &inst, &info) if entry_idx < 0 { - append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE}) + append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE}) inst = Instruction{mnemonic = .INVALID, length = 1} - info = Instruction_Info{offset = pc} + info = Instruction_Info{offset = byte_count} consumed = 1 } else { inst_idx_for_branches := u32(len(instructions)) @@ -78,11 +77,12 @@ decode :: proc( append(instructions, inst) append(inst_info, info) - pc += consumed + byte_count += consumed } - isa.infer_labels_from_branches(pending_branches[:], pc, label_defs, relocs) - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + isa.infer_labels_from_branches(pending_branches[:], byte_count, label_defs, relocs) + ok = u32(len(errors)) == errors_start + return } // ============================================================================= diff --git a/core/rexcode/mos6502/encoder.odin b/core/rexcode/mos6502/encoder.odin index b8cd3deec..57f7ca31e 100644 --- a/core/rexcode/mos6502/encoder.odin +++ b/core/rexcode/mos6502/encoder.odin @@ -48,47 +48,43 @@ encode :: proc( errors: ^[dynamic]Error, resolve: bool = true, base_address: u64 = 0, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_inst := u32(len(instructions)) errors_start := u32(len(errors)) pending_start := u32(len(relocs)) inst_offsets := make([]u32, n_inst, context.temp_allocator) - pc: u32 = 0 - // ---- PASS 1 ----------------------------------------------------------- for i in 0.. u32(len(code)) { + if byte_count + u32(form.length) > u32(len(code)) { append(errors, Error{inst_idx = i, code = .BUFFER_OVERFLOW}) - return Result{byte_count = pc, success = false} + return } // Opcode byte - code[pc] = form.opcode + code[byte_count] = form.opcode // Operand bytes - if form.enc[0] != .NONE { pack_operand_inline(&inst.ops[0], form.enc[0], pc, u16(i), code, relocs) } - if form.enc[1] != .NONE { pack_operand_inline(&inst.ops[1], form.enc[1], pc, u16(i), code, relocs) } - if form.enc[2] != .NONE { pack_operand_inline(&inst.ops[2], form.enc[2], pc, u16(i), code, relocs) } + if form.enc[0] != .NONE { pack_operand_inline(&inst.ops[0], form.enc[0], byte_count, u16(i), code, relocs) } + if form.enc[1] != .NONE { pack_operand_inline(&inst.ops[1], form.enc[1], byte_count, u16(i), code, relocs) } + if form.enc[2] != .NONE { pack_operand_inline(&inst.ops[2], form.enc[2], byte_count, u16(i), code, relocs) } inst.length = form.length - pc += u32(form.length) + byte_count += u32(form.length) } // ---- PASS 1.5: inst-index -> byte-offset ----------------------------- isa.rewrite_label_defs_to_offsets(label_defs, inst_offsets) if !resolve { - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } // ---- PASS 2: resolve relocations -------------------------------------- @@ -108,7 +104,8 @@ encode :: proc( resize(relocs, int(write_idx)) } - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } // ============================================================================= diff --git a/core/rexcode/mos6502/encoding_types.odin b/core/rexcode/mos6502/encoding_types.odin index 504185655..334333bb0 100644 --- a/core/rexcode/mos6502/encoding_types.odin +++ b/core/rexcode/mos6502/encoding_types.odin @@ -27,7 +27,6 @@ import "../isa" // 65C816 (SNES, Apple IIgs) is a separate 16/24-bit ISA and lives in a // sibling subpackage if/when added. -Result :: isa.Result Error :: isa.Error Error_Code :: isa.Error_Code Label_Definition :: isa.Label_Definition diff --git a/core/rexcode/mos6502/tests/pipeline_smoke.odin b/core/rexcode/mos6502/tests/pipeline_smoke.odin index 7e8b13e82..573a2b0fc 100644 --- a/core/rexcode/mos6502/tests/pipeline_smoke.odin +++ b/core/rexcode/mos6502/tests/pipeline_smoke.odin @@ -69,8 +69,8 @@ encode_one :: proc(insts: []m.Instruction) -> ([]u8, bool) { @(static) errors: [dynamic]m.Error clear(&relocs); clear(&errors) for i in 0..= 1 && d_insts[0].mnemonic == .TII) ok("huc tii: 3 operands", d_insts[0].operand_count == 3) @@ -321,7 +321,7 @@ encode_or_fail :: proc(insts: []m.Instruction) -> []u8 { @(static) errors: [dynamic]m.Error clear(&relocs); clear(&errors) for i in 0.. Result { +) -> (byte_count: u32, ok: bool) { n_bytes := u32(len(data)) errors_start := u32(len(errors)) @@ -44,16 +44,15 @@ decode :: proc( eff := state if eff.e { eff.m = true; eff.x = true } - pc: u32 = 0 - for pc < n_bytes { + for byte_count < n_bytes { inst: Instruction info: Instruction_Info - entry_idx, consumed := decode_one_inline(data, pc, n_bytes, eff, &inst, &info) + entry_idx, consumed := decode_one_inline(data, byte_count, n_bytes, eff, &inst, &info) if entry_idx < 0 { - append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE}) + append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE}) inst = Instruction{mnemonic = .INVALID, length = 1} - info = Instruction_Info{offset = pc} + info = Instruction_Info{offset = byte_count} consumed = 1 } else { inst_idx_for_branches := u32(len(instructions)) @@ -71,11 +70,12 @@ decode :: proc( append(instructions, inst) append(inst_info, info) - pc += consumed + byte_count += consumed } - isa.infer_labels_from_branches(pending_branches[:], pc, label_defs, relocs) - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + isa.infer_labels_from_branches(pending_branches[:], byte_count, label_defs, relocs) + ok = u32(len(errors)) == errors_start + return } // ============================================================================= diff --git a/core/rexcode/mos65816/encoder.odin b/core/rexcode/mos65816/encoder.odin index 70379d8af..fb7b2dbbd 100644 --- a/core/rexcode/mos65816/encoder.odin +++ b/core/rexcode/mos65816/encoder.odin @@ -40,38 +40,36 @@ encode :: proc( errors: ^[dynamic]Error, resolve: bool = true, base_address: u64 = 0, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_inst := u32(len(instructions)) errors_start := u32(len(errors)) pending_start := u32(len(relocs)) inst_offsets := make([]u32, n_inst, context.temp_allocator) - pc: u32 = 0 - for i in 0.. u32(len(code)) { + if byte_count + u32(form.length) > u32(len(code)) { append(errors, Error{inst_idx = i, code = .BUFFER_OVERFLOW}) - return Result{byte_count = pc, success = false} + return } - code[pc] = form.opcode - if form.enc[0] != .NONE { pack_operand_inline(&inst.ops[0], form.enc[0], pc, u16(i), code, relocs) } - if form.enc[1] != .NONE { pack_operand_inline(&inst.ops[1], form.enc[1], pc, u16(i), code, relocs) } + code[byte_count] = form.opcode + if form.enc[0] != .NONE { pack_operand_inline(&inst.ops[0], form.enc[0], byte_count, u16(i), code, relocs) } + if form.enc[1] != .NONE { pack_operand_inline(&inst.ops[1], form.enc[1], byte_count, u16(i), code, relocs) } inst.length = form.length - pc += u32(form.length) + byte_count += u32(form.length) } isa.rewrite_label_defs_to_offsets(label_defs, inst_offsets) if !resolve { - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } n_relocs := u32(len(relocs)) @@ -90,7 +88,8 @@ encode :: proc( resize(relocs, int(write_idx)) } - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } // ============================================================================= diff --git a/core/rexcode/mos65816/encoding_types.odin b/core/rexcode/mos65816/encoding_types.odin index 37cd7b24e..a2bc957a1 100644 --- a/core/rexcode/mos65816/encoding_types.odin +++ b/core/rexcode/mos65816/encoding_types.odin @@ -30,7 +30,6 @@ import "../isa" // passes `e=true` in Assumed_State so the decoder picks the 8-bit immediate // forms. -Result :: isa.Result Error :: isa.Error Error_Code :: isa.Error_Code Label_Definition :: isa.Label_Definition diff --git a/core/rexcode/mos65816/tests/smoke.odin b/core/rexcode/mos65816/tests/smoke.odin index 706b7b8cd..7926a1e8c 100644 --- a/core/rexcode/mos65816/tests/smoke.odin +++ b/core/rexcode/mos65816/tests/smoke.odin @@ -68,9 +68,9 @@ enc :: proc(insts: []m.Instruction) -> []u8 { @(static) errors: [dynamic]m.Error clear(&relocs); clear(&errors) for i in 0.. decode in 16-bit native, print --------- @@ -186,18 +186,18 @@ main :: proc() { m.inst_m(.STA, m.mem_long(0x7E1000)), // 4 bytes m.inst_rel(.BRA, 0), // 2 bytes back to loop } - r := m.encode(src, ld[:], code[:], &relocs, &errors) - ok("rt: encode ok", r.success) + byte_count, success := m.encode(src, ld[:], code[:], &relocs, &errors) + ok("rt: encode ok", success) d_insts: [dynamic]m.Instruction d_info: [dynamic]m.Instruction_Info d_labels: [dynamic]m.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - d := m.decode(code[:r.byte_count], nil, + _, dsuccess := m.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors, state = m.NATIVE_16) - ok("rt: decode ok", d.success) + ok("rt: decode ok", dsuccess) ok("rt: 3 insts", len(d_insts) == 3) ok("rt: LDA", d_insts[0].mnemonic == .LDA) ok("rt: STA", d_insts[1].mnemonic == .STA) @@ -261,14 +261,14 @@ main :: proc() { m.inst_m(.JML, m.mem_abs_ind_long(0xFFFC)), m.inst_m(.LDA, m.mem_sr_ind_y(0x10)), } - r := m.encode(src, nil, code[:], &relocs, &errors) + byte_count, success := m.encode(src, nil, code[:], &relocs, &errors) d_insts: [dynamic]m.Instruction d_info: [dynamic]m.Instruction_Info d_labels: [dynamic]m.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - m.decode(code[:r.byte_count], nil, &d_insts, &d_info, &d_labels, &errors, + m.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors, state = m.NATIVE_16) text := m.aprint(d_insts[:], d_info[:], d_labels[:], diff --git a/core/rexcode/ppc/decoder.odin b/core/rexcode/ppc/decoder.odin index f0996f241..10f960e52 100644 --- a/core/rexcode/ppc/decoder.odin +++ b/core/rexcode/ppc/decoder.odin @@ -34,36 +34,35 @@ decode :: proc( label_defs: ^[dynamic]Label_Definition, errors: ^[dynamic]Error, mode: Mode = .PPC32, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_bytes := u32(len(data)) & ~u32(3) errors_start := u32(len(errors)) pending_branches: [dynamic]isa.Branch_Target defer delete(pending_branches) - pc: u32 = 0 - for pc < n_bytes { - if pc + 4 > n_bytes { break } - word := read_u32_be(data, pc) + for byte_count < n_bytes { + if byte_count + 4 > n_bytes { break } + word := read_u32_be(data, byte_count) // Detect prefixed instruction: primary opcode = 1. is_prefixed := (word >> 26) == 0x01 ilen: u32 = 4 suffix: u32 = 0 if is_prefixed { - if pc + 8 > n_bytes { break } - suffix = read_u32_be(data, pc + 4) + if byte_count + 8 > n_bytes { break } + suffix = read_u32_be(data, byte_count + 4) ilen = 8 } inst: Instruction info: Instruction_Info - info.offset = pc + info.offset = byte_count match_word := is_prefixed ? suffix : word prefix_word := is_prefixed ? word : 0 if !find_and_decode(match_word, prefix_word, is_prefixed, mode, &inst, &info) { - append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE}) + append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE}) inst = Instruction{mnemonic = .INVALID, length = u8(ilen), mode = mode} } else { inst.length = u8(ilen) @@ -74,7 +73,7 @@ decode :: proc( if op.kind == .RELATIVE && op.relative >= 0 { // The unpacker stores PC-relative byte offsets; convert // to absolute target = pc + relative. - target := u32(i32(pc) + i32(op.relative)) + target := u32(i32(byte_count) + i32(op.relative)) append(&pending_branches, isa.Branch_Target{ inst_idx = inst_idx, op_idx = slot, @@ -86,11 +85,12 @@ decode :: proc( append(instructions, inst) append(inst_info, info) - pc += ilen + byte_count += ilen } - isa.infer_labels_from_branches(pending_branches[:], pc, label_defs, relocs) - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + isa.infer_labels_from_branches(pending_branches[:], byte_count, label_defs, relocs) + ok = u32(len(errors)) == errors_start + return } // ============================================================================= diff --git a/core/rexcode/ppc/encoder.odin b/core/rexcode/ppc/encoder.odin index 583e89dd9..3ae82df23 100644 --- a/core/rexcode/ppc/encoder.odin +++ b/core/rexcode/ppc/encoder.odin @@ -34,28 +34,24 @@ encode :: proc( errors: ^[dynamic]Error, resolve: bool = true, base_address: u64 = 0, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_inst := u32(len(instructions)) if u32(len(code)) < n_inst * MAX_INST_SIZE { append(errors, Error{inst_idx = 0, code = .BUFFER_OVERFLOW}) - return Result{byte_count = 0, success = false} + return } errors_start := u32(len(errors)) pending_start := u32(len(relocs)) - pc: u32 = 0 inst_pc := make([]u32, n_inst, context.temp_allocator) // ---- PASS 1 ------------------------------------------------------------ for i in 0.. byte offset -------------------- @@ -71,7 +67,8 @@ encode :: proc( } if !resolve { - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } // ---- PASS 2: resolve relocations --------------------------------------- @@ -87,7 +84,8 @@ encode :: proc( } if write_idx != n_relocs { resize(relocs, int(write_idx)) } - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } // ============================================================================= diff --git a/core/rexcode/ppc/encoding_types.odin b/core/rexcode/ppc/encoding_types.odin index a654dd10a..c1cf03dfe 100644 --- a/core/rexcode/ppc/encoding_types.odin +++ b/core/rexcode/ppc/encoding_types.odin @@ -67,7 +67,6 @@ import "../isa" // XX4-form vsx 4-op (xxsel) -- + XT + XA + XB + XC + XO + CX + AX + BX + TX // MLS / MMIRR / 8RR / 8LS prefixed (ISA 3.1) -- 8-byte (4 prefix + 4 suffix) -Result :: isa.Result Error :: isa.Error Error_Code :: isa.Error_Code Label_Definition :: isa.Label_Definition diff --git a/core/rexcode/ppc/tests/branch_reloc.odin b/core/rexcode/ppc/tests/branch_reloc.odin index f04137d03..9bf991f33 100644 --- a/core/rexcode/ppc/tests/branch_reloc.odin +++ b/core/rexcode/ppc/tests/branch_reloc.odin @@ -16,15 +16,15 @@ check :: proc(name: string, instructions: []p.Instruction, label_defs: []isa.Lab errors: [dynamic]p.Error defer delete(relocs); defer delete(errors) - r := p.encode(instructions, label_defs, code, &relocs, &errors) - if !r.success { + byte_count, success := p.encode(instructions, label_defs, code, &relocs, &errors) + if !success { fmt.printf(" [FAIL] %s: encode failed, %d errors\n", name, len(errors)) for e in errors { fmt.printf(" code=%v inst_idx=%d\n", e.code, e.inst_idx) } fail += 1 return } - if int(r.byte_count) != len(want_bytes) { - fmt.printf(" [FAIL] %s: wrong byte count (got %d, want %d)\n", name, r.byte_count, len(want_bytes)) + if int(byte_count) != len(want_bytes) { + fmt.printf(" [FAIL] %s: wrong byte count (got %d, want %d)\n", name, byte_count, len(want_bytes)) fail += 1 return } diff --git a/core/rexcode/ppc/tests/decode_sweep.odin b/core/rexcode/ppc/tests/decode_sweep.odin index 7a7f2f526..005c3061d 100644 --- a/core/rexcode/ppc/tests/decode_sweep.odin +++ b/core/rexcode/ppc/tests/decode_sweep.odin @@ -47,8 +47,8 @@ run_decode_sweep :: proc() { errors: [dynamic]p.Error defer delete(decoded); defer delete(info); defer delete(labels); defer delete(errors) - r := p.decode(buf[:ilen], nil, &decoded, &info, &labels, &errors, .PPC64) - if !r.success || len(decoded) == 0 || (len(decoded) > 0 && decoded[0].mnemonic == .INVALID) { + byte_count, success := p.decode(buf[:ilen], nil, &decoded, &info, &labels, &errors, .PPC64) + if !success || len(decoded) == 0 || (len(decoded) > 0 && decoded[0].mnemonic == .INVALID) { if missing_mn_total < 20 { fmt.printf(" [UNDECODABLE] %v word=%08x prefixed=%v\n", mn, word, f.flags.prefixed) } diff --git a/core/rexcode/ppc/tests/full_sweep.odin b/core/rexcode/ppc/tests/full_sweep.odin index 455149e92..e73d90437 100644 --- a/core/rexcode/ppc/tests/full_sweep.odin +++ b/core/rexcode/ppc/tests/full_sweep.odin @@ -182,8 +182,8 @@ test_form :: proc(mn: p.Mnemonic, fi: int, f: ^p.Encoding, fails: ^[dynamic]stri instructions := []p.Instruction{inst} label_defs: []isa.Label_Definition - r := p.encode(instructions, label_defs, code, &relocs, &errors) - if !r.success { + byte_count, success := p.encode(instructions, label_defs, code, &relocs, &errors) + if !success { stats.encode_fail += 1 if len(fails) < 100 { append(fails, fmt.aprintf("ENCODE_FAIL %v[%d] errors=%d", mn, fi, len(errors))) } return @@ -196,8 +196,8 @@ test_form :: proc(mn: p.Mnemonic, fi: int, f: ^p.Encoding, fails: ^[dynamic]stri dec_errors: [dynamic]p.Error defer delete(decoded); defer delete(dec_info); defer delete(dec_labels); defer delete(dec_errors) - dr := p.decode(code[:r.byte_count], nil, &decoded, &dec_info, &dec_labels, &dec_errors, f.mode) - if !dr.success || len(decoded) == 0 || decoded[0].mnemonic == .INVALID { + dbyte_count, dsuccess := p.decode(code[:byte_count], nil, &decoded, &dec_info, &dec_labels, &dec_errors, f.mode) + if !dsuccess || len(decoded) == 0 || decoded[0].mnemonic == .INVALID { stats.decode_fail += 1 if len(fails) < 100 { append(fails, fmt.aprintf("DECODE_FAIL %v[%d] bytes=%02x%02x%02x%02x", @@ -213,8 +213,8 @@ test_form :: proc(mn: p.Mnemonic, fi: int, f: ^p.Encoding, fails: ^[dynamic]stri re_errors: [dynamic]p.Error defer delete(re_relocs); defer delete(re_errors) - rr := p.encode(decoded[:], dec_labels[:], code2, &re_relocs, &re_errors) - if !rr.success { + rrbyte_count, rrsuccess := p.encode(decoded[:], dec_labels[:], code2, &re_relocs, &re_errors) + if !rrsuccess { stats.reencode_fail += 1 if len(fails) < 100 { append(fails, fmt.aprintf("REENCODE_FAIL %v[%d] decoded_mn=%v", @@ -223,14 +223,14 @@ test_form :: proc(mn: p.Mnemonic, fi: int, f: ^p.Encoding, fails: ^[dynamic]stri return } - if rr.byte_count != r.byte_count { + if rrbyte_count != byte_count { stats.byte_mismatch += 1 if len(fails) < 100 { - append(fails, fmt.aprintf("LEN_MISMATCH %v[%d] orig=%d re=%d", mn, fi, r.byte_count, rr.byte_count)) + append(fails, fmt.aprintf("LEN_MISMATCH %v[%d] orig=%d re=%d", mn, fi, byte_count, rrbyte_count)) } return } - for i in 0.. Result { +) -> (byte_count: u32, ok: bool) { n_bytes := u32(len(data)) & ~u32(1) errors_start := u32(len(errors)) pending_branches: [dynamic]isa.Branch_Target defer delete(pending_branches) - pc: u32 = 0 - for pc < n_bytes { - if pc + 2 > n_bytes { break } - hw := u32(read_u16_be(data, pc)) + for byte_count < n_bytes { + if byte_count + 2 > n_bytes { break } + hw := u32(read_u16_be(data, byte_count)) inst: Instruction info: Instruction_Info - info.offset = pc + info.offset = byte_count matched := try_decode(hw, true, &inst, &info) ilen: u32 = 2 if !matched { - if pc + 4 > n_bytes { - append(errors, Error{inst_idx = pc, code = .BUFFER_TOO_SHORT}) + if byte_count + 4 > n_bytes { + append(errors, Error{inst_idx = byte_count, code = .BUFFER_TOO_SHORT}) break } - word := (hw << 16) | u32(read_u16_be(data, pc + 2)) + word := (hw << 16) | u32(read_u16_be(data, byte_count + 2)) matched = try_decode(word, false, &inst, &info) ilen = 4 } if !matched { - append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE}) + append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE}) inst = Instruction{mnemonic = .INVALID, length = 2, mode = .PPC32_VLE} ilen = 2 } else { @@ -70,7 +69,7 @@ decode :: proc( append(&pending_branches, isa.Branch_Target{ inst_idx = inst_idx, op_idx = slot, - target = u32(i32(pc) + i32(op.relative)), + target = u32(i32(byte_count) + i32(op.relative)), }) } } @@ -78,11 +77,12 @@ decode :: proc( append(instructions, inst) append(inst_info, info) - pc += ilen + byte_count += ilen } - isa.infer_labels_from_branches(pending_branches[:], pc, label_defs, relocs) - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + isa.infer_labels_from_branches(pending_branches[:], byte_count, label_defs, relocs) + ok = u32(len(errors)) == errors_start + return } @(private="file") diff --git a/core/rexcode/ppc_vle/encoder.odin b/core/rexcode/ppc_vle/encoder.odin index 2869e078a..3c6d0debd 100644 --- a/core/rexcode/ppc_vle/encoder.odin +++ b/core/rexcode/ppc_vle/encoder.odin @@ -25,24 +25,23 @@ encode :: proc( errors: ^[dynamic]Error, resolve: bool = true, base_address: u64 = 0, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_inst := u32(len(instructions)) if u32(len(code)) < n_inst * MAX_INST_SIZE { append(errors, Error{inst_idx = 0, code = .BUFFER_OVERFLOW}) - return Result{byte_count = 0, success = false} + return } errors_start := u32(len(errors)) pending_start := u32(len(relocs)) - pc: u32 = 0 + inst_pc := make([]u32, n_inst, context.temp_allocator) for i in 0.. Result { +) -> (byte_count: u32, ok: bool) { n_bytes := u32(len(data)) & ~u32(1) // align to halfword (RVC is 2-byte) errors_start := u32(len(errors)) pending_branches: [dynamic]isa.Branch_Target defer delete(pending_branches) - pc: u32 = 0 - for pc < n_bytes { + for byte_count < n_bytes { // Read the first halfword; bits[1:0] != 11 means compressed (2 bytes). - hword_lo := read_u16_le(data, pc) + hword_lo := read_u16_le(data, byte_count) ilen: u32 = 4 word: u32 if (hword_lo & 0x3) != 0x3 { ilen = 2 word = u32(hword_lo) } else { - if pc + 4 > n_bytes { break } - word = read_u32_le(data, pc) + if byte_count + 4 > n_bytes { break } + word = read_u32_le(data, byte_count) } inst: Instruction info: Instruction_Info - entry_idx := decode_one_inline(word, pc, xlen, ilen == 2, &inst, &info) + entry_idx := decode_one_inline(word, byte_count, xlen, ilen == 2, &inst, &info) if entry_idx < 0 { - append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE}) + append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE}) inst = Instruction{mnemonic = .INVALID, length = u8(ilen)} - info = Instruction_Info{offset = pc} + info = Instruction_Info{offset = byte_count} } else { inst.length = u8(ilen) inst_idx_for_branches := u32(len(instructions)) @@ -89,11 +88,12 @@ decode :: proc( append(instructions, inst) append(inst_info, info) - pc += ilen + byte_count += ilen } - isa.infer_labels_from_branches(pending_branches[:], pc, label_defs, relocs) - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + isa.infer_labels_from_branches(pending_branches[:], byte_count, label_defs, relocs) + ok = u32(len(errors)) == errors_start + return } // ============================================================================= diff --git a/core/rexcode/riscv/encoder.odin b/core/rexcode/riscv/encoder.odin index f0424d0ce..6ee9cc618 100644 --- a/core/rexcode/riscv/encoder.odin +++ b/core/rexcode/riscv/encoder.odin @@ -41,16 +41,15 @@ encode :: proc( errors: ^[dynamic]Error, resolve: bool = true, base_address: u64 = 0, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_inst := u32(len(instructions)) if u32(len(code)) < n_inst * 4 { append(errors, Error{inst_idx = 0, code = .BUFFER_OVERFLOW}) - return Result{byte_count = 0, success = false} + return } errors_start := u32(len(errors)) pending_start := u32(len(relocs)) - pc: u32 = 0 // Per-instruction byte offsets so label_defs (instruction-indexed) // can be rewritten to byte-offset after pass 1 in the presence of @@ -59,16 +58,15 @@ encode :: proc( // ---- PASS 1 ----------------------------------------------------------- for i in 0.. byte-offset) -- @@ -84,7 +82,8 @@ encode :: proc( } if !resolve { - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } // ---- PASS 2: resolve relocations -------------------------------------- @@ -100,7 +99,8 @@ encode :: proc( } if write_idx != n_relocs { resize(relocs, int(write_idx)) } - return Result{byte_count = pc, success = u32(len(errors)) == errors_start} + ok = u32(len(errors)) == errors_start + return } // ============================================================================= diff --git a/core/rexcode/riscv/encoding_types.odin b/core/rexcode/riscv/encoding_types.odin index bc8f04d24..5b93e3fc8 100644 --- a/core/rexcode/riscv/encoding_types.odin +++ b/core/rexcode/riscv/encoding_types.odin @@ -31,7 +31,6 @@ import "../isa" // pattern, `mask` flags which positions are static. Operand-driven bits // land in the zero positions of `bits`. -Result :: isa.Result Error :: isa.Error Error_Code :: isa.Error_Code Label_Definition :: isa.Label_Definition diff --git a/core/rexcode/riscv/tests/pipeline_smoke.odin b/core/rexcode/riscv/tests/pipeline_smoke.odin index 18434bc58..ba86ba77c 100644 --- a/core/rexcode/riscv/tests/pipeline_smoke.odin +++ b/core/rexcode/riscv/tests/pipeline_smoke.odin @@ -91,8 +91,8 @@ run_pipeline_tests :: proc() { rv.inst_u (.LUI, rv.T0, 0x12345), rv.inst_u (.AUIPC,rv.RA, 0x10), } - r := rv.encode(insts, nil, code[:], &relocs, &errors) - ok("R/I/U: encode ok", r.success) + byte_count, success := rv.encode(insts, nil, code[:], &relocs, &errors) + ok("R/I/U: encode ok", success) eq_word("R: ADD t0,a0,a1", load_le(code[:], 0), 0x00B502B3) eq_word("I: ADDI sp,sp,-16", load_le(code[:], 4), 0xFF010113) eq_word("U: LUI t0,0x12345", load_le(code[:], 8), 0x123452B7) @@ -114,8 +114,8 @@ run_pipeline_tests :: proc() { rv.inst_load (.LW, rv.T0, rv.mem(rv.SP, 100)), rv.inst_store(.SW, rv.A0, rv.mem(rv.SP, -8)), } - r := rv.encode(insts, nil, code[:], &relocs, &errors) - ok("LW/SW: encode ok", r.success) + byte_count, success := rv.encode(insts, nil, code[:], &relocs, &errors) + ok("LW/SW: encode ok", success) eq_word("LW t0,100(sp)", load_le(code[:], 0), 0x06412283) eq_word("SW a0,-8(sp)", load_le(code[:], 4), 0xFEA12C23) } @@ -144,8 +144,8 @@ run_pipeline_tests :: proc() { rv.inst_branch(.BNE, rv.T0, rv.ZERO, 0), rv.inst_r_r_i(.ADDI, rv.ZERO, rv.ZERO, 0), } - r := rv.encode(insts, ld[:], code[:], &relocs, &errors) - ok("br: encode ok", r.success) + byte_count, success := rv.encode(insts, ld[:], code[:], &relocs, &errors) + ok("br: encode ok", success) ok("br: no leftover relocs", len(relocs) == 0) eq_word("BNE rel=-8", load_le(code[:], 8), 0xFE029CE3) } @@ -170,9 +170,9 @@ run_pipeline_tests :: proc() { rv.inst_r_r_i(.ADDI, rv.SP, rv.SP, 0), rv.inst_jalr(rv.ZERO, rv.RA, 0), } - r := rv.encode(insts, ld[:], code[:], &relocs, &errors) - ok("JAL: encode ok", r.success) - eq_word("JAL ra,+8", load_le(code[:], 0), 0x008000EF) + byte_count, success := rv.encode(insts, ld[:], code[:], &relocs, &errors) + ok("JAL: encode ok", success) + eq_word("JAL ra,+8", load_le(code[:], 0), 0x008000EF) } // ---- 5. Round-trip: encode -> decode -> print ----------------------- @@ -189,16 +189,16 @@ run_pipeline_tests :: proc() { rv.inst_load (.LW, rv.A0, rv.mem(rv.SP, 0)), rv.inst_branch(.BNE, rv.T0, rv.ZERO, 0), } - r := rv.encode(src, ld[:], code[:], &relocs, &errors) - ok("rt: encode ok", r.success) + byte_count, success := rv.encode(src, ld[:], code[:], &relocs, &errors) + ok("rt: encode ok", success) d_insts: [dynamic]rv.Instruction d_info: [dynamic]rv.Instruction_Info d_labels: [dynamic]rv.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - d := rv.decode(code[:r.byte_count], nil, &d_insts, &d_info, &d_labels, &errors) - ok("rt: decode ok", d.success) + dbyte_count, dsuccess := rv.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors) + ok("rt: decode ok", dsuccess) ok("rt: 3 insts", len(d_insts) == 3) ok("rt: ADDI", d_insts[0].mnemonic == .ADDI) ok("rt: LW", d_insts[1].mnemonic == .LW) @@ -223,15 +223,15 @@ run_pipeline_tests :: proc() { rv.inst_r_r_r(.DIV, rv.T1, rv.A0, rv.A1), rv.inst_r_r_r(.REMU, rv.T2, rv.A0, rv.A1), } - r := rv.encode(src, nil, code[:], &relocs, &errors) - ok("M: encode ok", r.success) + byte_count, success := rv.encode(src, nil, code[:], &relocs, &errors) + ok("M: encode ok", success) d_insts: [dynamic]rv.Instruction d_info: [dynamic]rv.Instruction_Info d_labels: [dynamic]rv.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - rv.decode(code[:r.byte_count], nil, &d_insts, &d_info, &d_labels, &errors) + rv.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors) ok("M: MUL", d_insts[0].mnemonic == .MUL) ok("M: DIV", d_insts[1].mnemonic == .DIV) ok("M: REMU", d_insts[2].mnemonic == .REMU) @@ -258,8 +258,8 @@ run_pipeline_tests :: proc() { }, }, } - r := rv.encode(insts, nil, code[:], &relocs, &errors) - ok("A: encode ok", r.success) + byte_count, success := rv.encode(insts, nil, code[:], &relocs, &errors) + ok("A: encode ok", success) eq_word("A: AMOADD.W", load_le(code[:], 0), 0x00B522AF) } @@ -283,8 +283,8 @@ run_pipeline_tests :: proc() { }, }, } - r := rv.encode(insts, nil, code[:], &relocs, &errors) - ok("F: encode ok", r.success) + byte_count, success := rv.encode(insts, nil, code[:], &relocs, &errors) + ok("F: encode ok", success) eq_word("F: FADD.S", load_le(code[:], 0), 0x00C58553) d_insts: [dynamic]rv.Instruction @@ -292,7 +292,7 @@ run_pipeline_tests :: proc() { d_labels: [dynamic]rv.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - rv.decode(code[:r.byte_count], nil, &d_insts, &d_info, &d_labels, &errors) + rv.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors) text := rv.aprint(d_insts[:], d_info[:], d_labels[:], nil, nil, nil, context.temp_allocator) @@ -317,8 +317,8 @@ run_pipeline_tests :: proc() { rv.Register(rv.REG_FPR | 12), // fa2 rv.Register(rv.REG_FPR | 13)), // fa3 } - r := rv.encode(insts, nil, code[:], &relocs, &errors) - ok("D: encode ok", r.success) + byte_count, success := rv.encode(insts, nil, code[:], &relocs, &errors) + ok("D: encode ok", success) eq_word("D: FMADD.D", load_le(code[:], 0), 0x6AC58543) } @@ -333,8 +333,8 @@ run_pipeline_tests :: proc() { insts := []rv.Instruction{ rv.inst_csr(.CSRRW, rv.A0, 0xF14, rv.ZERO), } - r := rv.encode(insts, nil, code[:], &relocs, &errors) - ok("CSR: encode ok", r.success) + byte_count, success := rv.encode(insts, nil, code[:], &relocs, &errors) + ok("CSR: encode ok", success) eq_word("CSR: csrrw", load_le(code[:], 0), 0xF1401573) } @@ -382,9 +382,9 @@ run_pipeline_tests :: proc() { ops = {rv.op_reg(rv.A2), rv.op_reg(rv.A3), {}, {}}, }, } - r := rv.encode(insts, nil, code[:], &relocs, &errors) - ok("C: encode ok", r.success) - ok("C: byte count", r.byte_count == 8) + byte_count, success := rv.encode(insts, nil, code[:], &relocs, &errors) + ok("C: encode ok", success) + ok("C: byte count", byte_count == 8) get_hw := proc(buf: []u8, off: u32) -> u16 { return u16(buf[off]) | (u16(buf[off+1]) << 8) } @@ -402,7 +402,7 @@ run_pipeline_tests :: proc() { d_labels: [dynamic]rv.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - rv.decode(code[:r.byte_count], nil, &d_insts, &d_info, &d_labels, &errors) + rv.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors) ok("C: decode 4 insts", len(d_insts) == 4) ok("C: NOP", len(d_insts) >= 1 && d_insts[0].mnemonic == .C_NOP) ok("C: LI", len(d_insts) >= 2 && d_insts[1].mnemonic == .C_LI) @@ -429,16 +429,16 @@ run_pipeline_tests :: proc() { ops = {rv.op_reg(rv.A2), rv.op_reg(rv.A0), {}, {}}, }, } - r := rv.encode(insts, nil, code[:], &relocs, &errors) - ok("C: mixed encode", r.success) - ok("C: mixed bytes = 8", r.byte_count == 8) + byte_count, success := rv.encode(insts, nil, code[:], &relocs, &errors) + ok("C: mixed encode", success) + ok("C: mixed bytes = 8", byte_count == 8) d_insts: [dynamic]rv.Instruction d_info: [dynamic]rv.Instruction_Info d_labels: [dynamic]rv.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - rv.decode(code[:r.byte_count], nil, &d_insts, &d_info, &d_labels, &errors) + rv.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors) ok("C: mixed decode 3", len(d_insts) == 3) ok("C: [0]=C.LI len=2", len(d_insts) >= 1 && d_insts[0].mnemonic == .C_LI && d_insts[0].length == 2) ok("C: [1]=ADDI len=4", len(d_insts) >= 2 && d_insts[1].mnemonic == .ADDI && d_insts[1].length == 4) @@ -483,9 +483,9 @@ run_pipeline_tests :: proc() { }, rv.inst_none(.C_NOP), } - r := rv.encode(insts, ld[:], code[:], &relocs, &errors) - ok("C.BEQZ: encode", r.success) - ok("C.BEQZ: byte_count=8", r.byte_count == 8) + byte_count, success := rv.encode(insts, ld[:], code[:], &relocs, &errors) + ok("C.BEQZ: encode", success) + ok("C.BEQZ: byte_count=8", byte_count == 8) get_hw := proc(buf: []u8, off: u32) -> u16 { return u16(buf[off]) | (u16(buf[off+1]) << 8) @@ -502,7 +502,7 @@ run_pipeline_tests :: proc() { d_labels: [dynamic]rv.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - rv.decode(code[:r.byte_count], nil, &d_insts, &d_info, &d_labels, &errors) + rv.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors) ok("C.BEQZ: decode count", len(d_insts) == 4) ok("C.BEQZ: [0] mnemonic", len(d_insts) >= 1 && d_insts[0].mnemonic == .C_BEQZ) ok("C.BEQZ: target = 6", len(d_insts) >= 1 && d_insts[0].ops[1].kind == .RELATIVE && u32(d_insts[0].ops[0].relative + d_insts[0].ops[1].relative)*0+ u32(d_insts[0].ops[1].relative) == 6) @@ -552,9 +552,9 @@ run_pipeline_tests :: proc() { ops = {rv.op_label(0), {}, {}, {}}, }, } - r := rv.encode(insts, ld[:], code[:], &relocs, &errors) - ok("C.J: encode", r.success) - ok("C.J: byte_count=10", r.byte_count == 10) + byte_count, success := rv.encode(insts, ld[:], code[:], &relocs, &errors) + ok("C.J: encode", success) + ok("C.J: byte_count=10", byte_count == 10) get_hw := proc(buf: []u8, off: u32) -> u16 { return u16(buf[off]) | (u16(buf[off+1]) << 8) @@ -571,7 +571,7 @@ run_pipeline_tests :: proc() { d_labels: [dynamic]rv.Label_Definition defer delete(d_insts); defer delete(d_info); defer delete(d_labels) clear(&errors) - rv.decode(code[:r.byte_count], nil, &d_insts, &d_info, &d_labels, &errors) + rv.decode(code[:byte_count], nil, &d_insts, &d_info, &d_labels, &errors) ok("C.J: decode count", len(d_insts) == 4) ok("C.J: [3] mnemonic", len(d_insts) >= 4 && d_insts[3].mnemonic == .C_J) ok("C.J: target = 0", len(d_insts) >= 4 && d_insts[3].ops[0].kind == .RELATIVE && u32(d_insts[3].ops[0].relative) == 0) @@ -601,8 +601,8 @@ run_pipeline_tests :: proc() { // Target at byte 2 + 64*4 = 258 -- out of range for 9-bit signed (max 254) append(&long_insts, rv.inst_none(.C_NOP)) - r := rv.encode(long_insts[:], ld[:], big_code[:], &relocs, &errors) - ok("C.BEQZ out-of-range: error", !r.success && len(errors) > 0) + byte_count, success := rv.encode(long_insts[:], ld[:], big_code[:], &relocs, &errors) + ok("C.BEQZ out-of-range: error", !success && len(errors) > 0) if len(errors) > 0 { ok("C.BEQZ out-of-range: code", errors[0].code == .LABEL_OUT_OF_RANGE) } diff --git a/core/rexcode/rsp/decoder.odin b/core/rexcode/rsp/decoder.odin index 150717460..21a8864eb 100644 --- a/core/rexcode/rsp/decoder.odin +++ b/core/rexcode/rsp/decoder.odin @@ -29,25 +29,24 @@ decode :: proc( label_defs: ^[dynamic]Label_Definition, errors: ^[dynamic]Error, endianness: Endianness = .BIG, -) -> Result { +) -> (byte_count: u32, ok: bool) { n_bytes := u32(len(data)) & ~u32(3) // drop dangling tail errors_start := u32(len(errors)) pending_branches: [dynamic]isa.Branch_Target defer delete(pending_branches) - pc: u32 = 0 - for pc < n_bytes { - word := read_u32(data, pc, endianness) + for byte_count < n_bytes { + word := read_u32(data, byte_count, endianness) inst: Instruction info: Instruction_Info - entry_idx := decode_one_inline(word, pc, &inst, &info) + entry_idx := decode_one_inline(word, byte_count, &inst, &info) if entry_idx < 0 { - append(errors, Error{inst_idx = pc, code = .INVALID_OPCODE}) + append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE}) inst = Instruction{mnemonic = .INVALID, length = 4} - info = Instruction_Info{offset = pc} + info = Instruction_Info{offset = byte_count} } else { inst_idx_for_branches := u32(len(instructions)) for slot in 0.. Result { +) -> (byte_count: u32, ok: bool) { n_inst := u32(len(instructions)) if u32(len(code)) < n_inst * 4 { append(errors, Error{inst_idx = 0, code = .BUFFER_OVERFLOW}) - return Result{byte_count = 0, success = false} + return } errors_start := u32(len(errors)) pending_start := u32(len(relocs)) - pc: u32 = 0 for i in 0.. Result { +) -> (byte_count: u32, ok: bool) { if mode == ._16 { // Real-mode decoding is not implemented; the ModRM addressing // model differs from protected/long mode and needs a separate // decode path. See Mode enum comment in encoding_types.odin. fmt.panicf("x64.decode: Mode._16 (real mode) is not yet supported") } + ok = true if len(data) == 0 { - return Result{success = true} + return } - data_length := len(data) - pos := 0 - has_errors := false + data_length := u32(len(data)) // Track branch targets for label inference (resolved in pass 2 by isa). pending_branches: [dynamic]isa.Branch_Target @@ -1040,26 +1039,26 @@ decode :: proc( // PASS 1: Decode all instructions, collect branch targets // ========================================================================= - for pos < data_length { + for byte_count < data_length { inst: Instruction info: Instruction_Info // Record offset - info.offset = u32(pos) + info.offset = byte_count // Initialize decoder state state := Decoder_State{ - data = data[pos:], + data = data[byte_count:], position = 0, - mode = mode, - segment = NONE, + mode = mode, + segment = NONE, } // Phase 1: Parse prefixes err := decode_prefixes(&state) if err != nil { append(errors, Error{inst_idx = u32(len(instructions)), code = err}) - has_errors = true + ok = false break } @@ -1092,7 +1091,7 @@ decode :: proc( append(instructions, inst) append(inst_info, info) - pos += state.position + byte_count += u32(state.position) continue } } @@ -1103,7 +1102,7 @@ decode :: proc( entry, vex_entry, err = decode_opcode(&state) if err != nil { append(errors, Error{inst_idx = u32(len(instructions)), code = err}) - has_errors = true + ok = false break } @@ -1114,12 +1113,12 @@ decode :: proc( inst, err = decode_operands(&state, entry) } else { append(errors, Error{inst_idx = u32(len(instructions)), code = .INVALID_OPCODE}) - has_errors = true + ok = false break } if err != nil { append(errors, Error{inst_idx = u32(len(instructions)), code = err}) - has_errors = true + ok = false break } @@ -1164,7 +1163,7 @@ decode :: proc( } // Check for relative operands and record pending branch targets - inst_end := pos + state.position + inst_end := byte_count + u32(state.position) for op_idx in 0.. Result { +) -> (byte_count: u32, ok: bool) { if mode == ._16 { // Real-mode encoding is not implemented; the ModRM addressing // model differs from protected/long mode and needs a separate @@ -73,8 +73,7 @@ encode :: proc( fmt.panicf("x64.encode: Mode._16 (real mode) is not yet supported") } - code_pos: u32 = 0 - has_errors := false + ok = true // Temp storage for pending relocations (before resolution) pending_relocations: [dynamic]Relocation @@ -91,19 +90,19 @@ encode :: proc( for &inst, instruction_index in instructions { // Record this instruction's byte offset - inst_offsets[instruction_index] = code_pos + inst_offsets[instruction_index] = byte_count // Validate operand_count bounds if inst.operand_count > 4 { append(errors, Error{u32(instruction_index), .INVALID_OPERAND_COUNT, {}}) - has_errors = true + ok = false continue } // Check buffer space - if code_pos + MAX_INST_SIZE > u32(len(code)) { + if byte_count + MAX_INST_SIZE > u32(len(code)) { append(errors, Error{u32(instruction_index), .BUFFER_OVERFLOW, {}}) - has_errors = true + ok = false continue } @@ -136,7 +135,7 @@ encode :: proc( } if invalid { append(errors, Error{u32(instruction_index), .OPERAND_MISMATCH, {}}) - has_errors = true + ok = false continue } } @@ -145,7 +144,7 @@ encode :: proc( encodings := encoding_forms(inst.mnemonic) if len(encodings) == 0 { append(errors, Error{u32(instruction_index), .INVALID_MNEMONIC, {}}) - has_errors = true + ok = false continue } @@ -160,7 +159,7 @@ encode :: proc( if matched_enc == nil { append(errors, Error{u32(instruction_index), .NO_MATCHING_ENCODING, {}}) - has_errors = true + ok = false continue } @@ -169,7 +168,7 @@ encode :: proc( // ===================================================================== enc := matched_enc - out := code[code_pos:] + out := code[byte_count:] pos: u32 = 0 // --- Legacy Prefixes --- @@ -398,7 +397,7 @@ encode :: proc( // the instruction is not legal i386. if mode == ._32 && rex != 0 { append(errors, Error{u32(instruction_index), .OPERAND_MISMATCH, {}}) - has_errors = true + ok = false continue } @@ -598,7 +597,7 @@ encode :: proc( case .RELATIVE: // Relative reference - record relocation label_id := u32(user_op.relative) - append(&pending_relocations, Relocation{code_pos + pos, label_id, 0, .REL8, 1, u16(instruction_index)}) + append(&pending_relocations, Relocation{byte_count + pos, label_id, 0, .REL8, 1, u16(instruction_index)}) out[pos] = 0 pos += 1 } @@ -623,7 +622,7 @@ encode :: proc( pos += 4 case .RELATIVE: label_id := u32(user_op.relative) - append(&pending_relocations, Relocation{code_pos + pos, label_id, 0, .REL32, 4, u16(instruction_index)}) + append(&pending_relocations, Relocation{byte_count + pos, label_id, 0, .REL32, 4, u16(instruction_index)}) out[pos] = 0; out[pos+1] = 0; out[pos+2] = 0; out[pos+3] = 0 pos += 4 } @@ -639,7 +638,7 @@ encode :: proc( } } - code_pos += pos + byte_count += pos } // ========================================================================= @@ -677,7 +676,7 @@ encode :: proc( next_pc := patch_offset + 1 if !patch_pcrel_i8(code, patch_offset, target_offset, next_pc, relocation.addend) { append(errors, Error{u32(relocation.inst_idx), .LABEL_OUT_OF_RANGE, {}}) - has_errors = true + ok = false } case .REL32: @@ -692,10 +691,7 @@ encode :: proc( } } - return Result{ - byte_count = code_pos, - success = !has_errors, - } + return } // ----------------------------------------------------------------------------- diff --git a/core/rexcode/x86/encoding_types.odin b/core/rexcode/x86/encoding_types.odin index 62b1393df..db75512df 100644 --- a/core/rexcode/x86/encoding_types.odin +++ b/core/rexcode/x86/encoding_types.odin @@ -12,7 +12,6 @@ import "../isa" // SECTION: 6.0 Re-exports from isa (status, relocation) // ----------------------------------------------------------------------------- -Result :: isa.Result Error :: isa.Error Error_Code :: isa.Error_Code // Relocation and Relocation_Type live in reloc.odin (per-arch by design). diff --git a/core/rexcode/x86/tests/test.odin b/core/rexcode/x86/tests/test.odin index 552d8ec01..0879565c7 100644 --- a/core/rexcode/x86/tests/test.odin +++ b/core/rexcode/x86/tests/test.odin @@ -322,7 +322,7 @@ run_test :: proc(t: Test) -> bool { relocs: [dynamic]x86.Relocation defer delete(relocs) - encode_result := x86.encode( + byte_count, ok := x86.encode( t.instructions, labels_copy[:len(t.labels)], code_buf[:], @@ -333,11 +333,11 @@ run_test :: proc(t: Test) -> bool { ) // Copy encoded bytes - for i in 0.. bool { // Verify expected bytes if provided if len(t.expected_code) > 0 { - if int(encode_result.byte_count) != len(t.expected_code) { + if int(byte_count) != len(t.expected_code) { fmt.printf("%s[FAIL]%s %s - code size %d != expected %d\n", - RED, RESET, t.name, encode_result.byte_count, len(t.expected_code)) + RED, RESET, t.name, byte_count, len(t.expected_code)) g_stats.failed += 1 return false } - for i in 0.. bool { // ========================================================================= if len(code_to_decode) > 0 { - decode_result := x86.decode( + byte_count, ok := x86.decode( code_to_decode, nil, &decoded_insts, @@ -538,7 +538,7 @@ run_test :: proc(t: Test) -> bool { &decode_errors, ) - if !decode_result.success { + if !ok { fmt.printf("%s[FAIL]%s %s - decoding failed\n", RED, RESET, t.name) if len(decode_errors) > 0 { for err in decode_errors { @@ -2991,9 +2991,8 @@ run_label_map_tests :: proc() { defer delete(relocs) defer delete(errs) - result := x86.encode(instructions[:], lm.labels[:], code_buf[:], &relocs, &errs, true, 0) - - if !result.success { + byte_count, ok := x86.encode(instructions[:], lm.labels[:], code_buf[:], &relocs, &errs, true, 0) + if !ok { fmt.printf("%s[FAIL]%s Label_Map test - encoding failed\n", RED, RESET) g_stats.failed += 1 return @@ -3009,7 +3008,7 @@ run_label_map_tests :: proc() { defer delete(decoded_labels) defer delete(decode_errors) - x86.decode(code_buf[:result.byte_count], nil, &decoded_insts, &decoded_info, &decoded_labels, &decode_errors) + x86.decode(code_buf[:byte_count], nil, &decoded_insts, &decoded_info, &decoded_labels, &decode_errors) // Print with named labels (printer wants id→name; Label_Map stores name→id). id_to_name := make(map[u32]string, len(lm.names), context.temp_allocator) @@ -3088,8 +3087,8 @@ run_benchmarks :: proc() { for _ in 0.. Date: Mon, 15 Jun 2026 21:49:41 +0100 Subject: [PATCH 09/27] Minor style changes --- core/rexcode/arm64/bitmask.odin | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/core/rexcode/arm64/bitmask.odin b/core/rexcode/arm64/bitmask.odin index 601106675..ada4717f3 100644 --- a/core/rexcode/arm64/bitmask.odin +++ b/core/rexcode/arm64/bitmask.odin @@ -157,7 +157,7 @@ decode_bitmask_imm :: proc "contextless" (n, immr, imms: u8, is_64: bool) -> (va elem_size: u32 = 0 s_field: u8 = 0 if n == 1 { - if !is_64 { return 0, false } // N=1 only valid for 64-bit ops + if !is_64 { return } // N=1 only valid for 64-bit ops elem_size = 64 s_field = s } else { @@ -179,15 +179,15 @@ decode_bitmask_imm :: proc "contextless" (n, immr, imms: u8, is_64: bool) -> (va elem_size = 2 s_field = s & 0b000001 case: - return 0, false + return } } width: u32 = is_64 ? 64 : 32 - if elem_size > width { return 0, false } + if elem_size > width { return } ones := u32(s_field) + 1 - if ones == 0 || ones >= elem_size { return 0, false } + if ones == 0 || ones >= elem_size { return } rotation := u32(immr) & (elem_size - 1) @@ -199,10 +199,11 @@ decode_bitmask_imm :: proc "contextless" (n, immr, imms: u8, is_64: bool) -> (va rotated := rotate_right_u64(pattern, inv_rot, elem_size) & elem_mask // Replicate to fill width. - out: u64 = rotated + value = rotated for size: u32 = elem_size; size < width; size *= 2 { - out |= out << size + value |= value << size } - if width == 32 { out &= 0xFFFFFFFF } - return out, true + if width == 32 { value &= 0xFFFFFFFF } + ok = true + return } From 14fd4617f9627a4034948d138c209e98d5fb7d13 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 15 Jun 2026 21:54:15 +0100 Subject: [PATCH 10/27] spaces -> tabs --- core/rexcode/ppc_vle/tests/branch_test.odin | 176 ++++++++++---------- core/rexcode/ppc_vle/tests/full_sweep.odin | 140 ++++++++-------- 2 files changed, 158 insertions(+), 158 deletions(-) diff --git a/core/rexcode/ppc_vle/tests/branch_test.odin b/core/rexcode/ppc_vle/tests/branch_test.odin index ce86a0d9c..272ed7bea 100644 --- a/core/rexcode/ppc_vle/tests/branch_test.odin +++ b/core/rexcode/ppc_vle/tests/branch_test.odin @@ -9,99 +9,99 @@ import "../../isa" @(private="file") check :: proc(name: string, instructions: []v.Instruction, label_defs: []isa.Label_Definition, want: []u8) { - code := make([]u8, 64, context.temp_allocator) - relocs: [dynamic]v.Relocation - errors: [dynamic]v.Error - defer delete(relocs); defer delete(errors) + code := make([]u8, 64, context.temp_allocator) + relocs: [dynamic]v.Relocation + errors: [dynamic]v.Error + defer delete(relocs); defer delete(errors) - byte_count, success := v.encode(instructions, label_defs, code, &relocs, &errors) - if !success { - fmt.printf(" [FAIL] %s: encode failed\n", name) - for e in errors { fmt.printf(" code=%v inst_idx=%d\n", e.code, e.inst_idx) } - fail_count += 1 - return - } - if int(byte_count) != len(want) { - fmt.printf(" [FAIL] %s: byte_count %d (want %d)\n", name, byte_count, len(want)) - fail_count += 1 - return - } - for i in 0.. first inst: se_b with displacement 4 (encoded as 4/2=2 in 8-bit field) - // se_b form bits 0xE800, mask 0xFF00, B8 at bits 0..7, signed << 1 - // Target = pc + 4 = 4 bytes ahead, so B8 value = 2 (= 4/2) - // bits: 0xE8 | 0x04 wait no. Looking at binutils BD8(58, 0, 0) = (58 << 10) = 0xE800 - // Actually se_b is BD8(58,0,0). Let me just verify encoder produces something reasonable. - { - label_defs := [?]isa.Label_Definition{isa.Label_Definition(2)} // points to inst 2 - instructions := [?]v.Instruction{ - v.inst_branch(.SE_B, 0), - v.inst_none(.SE_BLR), - v.inst_none(.SE_BLR), - } - // Just check encode succeeds and roundtrips - code := make([]u8, 16, context.temp_allocator) - relocs: [dynamic]v.Relocation - errors: [dynamic]v.Error - defer delete(relocs); defer delete(errors) - byte_count, success := v.encode(instructions[:], label_defs[:], code, &relocs, &errors) - if !success { - fmt.printf(" [FAIL] se_b+label: encode failed\n") - for e in errors { fmt.printf(" code=%v\n", e.code) } - fail_count += 1 - } else { - fmt.printf(" [ok] se_b+label: %d bytes, bytes=", byte_count) - for i in 0.. first inst: se_b with displacement 4 (encoded as 4/2=2 in 8-bit field) + // se_b form bits 0xE800, mask 0xFF00, B8 at bits 0..7, signed << 1 + // Target = pc + 4 = 4 bytes ahead, so B8 value = 2 (= 4/2) + // bits: 0xE8 | 0x04 wait no. Looking at binutils BD8(58, 0, 0) = (58 << 10) = 0xE800 + // Actually se_b is BD8(58,0,0). Let me just verify encoder produces something reasonable. + { + label_defs := [?]isa.Label_Definition{isa.Label_Definition(2)} // points to inst 2 + instructions := [?]v.Instruction{ + v.inst_branch(.SE_B, 0), + v.inst_none(.SE_BLR), + v.inst_none(.SE_BLR), + } + // Just check encode succeeds and roundtrips + code := make([]u8, 16, context.temp_allocator) + relocs: [dynamic]v.Relocation + errors: [dynamic]v.Error + defer delete(relocs); defer delete(errors) + byte_count, success := v.encode(instructions[:], label_defs[:], code, &relocs, &errors) + if !success { + fmt.printf(" [FAIL] se_b+label: encode failed\n") + for e in errors { fmt.printf(" code=%v\n", e.code) } + fail_count += 1 + } else { + fmt.printf(" [ok] se_b+label: %d bytes, bytes=", byte_count) + for i in 0.. branch_test: %d passed, %d failed\n", ok_count, fail_count) - if fail_count > 0 { os.exit(1) } + fmt.printf("\n==> branch_test: %d passed, %d failed\n", ok_count, fail_count) + if fail_count > 0 { os.exit(1) } } diff --git a/core/rexcode/ppc_vle/tests/full_sweep.odin b/core/rexcode/ppc_vle/tests/full_sweep.odin index 1d31a1778..3eb289b7e 100644 --- a/core/rexcode/ppc_vle/tests/full_sweep.odin +++ b/core/rexcode/ppc_vle/tests/full_sweep.odin @@ -10,85 +10,85 @@ import "../../isa" stats: struct { ok, mn_alias, byte_mismatch, encode_fail, decode_fail: int } run_full_sweep :: proc() { - fmt.println("==== ppc_vle full sweep ====") + fmt.println("==== ppc_vle full sweep ====") - for mn in v.Mnemonic { - _run := v.ENCODE_RUNS[u16(mn)] - forms := v.ENCODE_FORMS[_run.start:][:_run.count] - for &f, fi in forms { - test_one(mn, fi, &f) - } - } + for mn in v.Mnemonic { + _run := v.ENCODE_RUNS[u16(mn)] + forms := v.ENCODE_FORMS[_run.start:][:_run.count] + for &f, fi in forms { + test_one(mn, fi, &f) + } + } - total := stats.ok + stats.mn_alias + stats.byte_mismatch + stats.encode_fail + stats.decode_fail - fmt.printf("\n[TOTAL] %d entries\n", total) - fmt.printf(" OK: %d (%.1f%%)\n", stats.ok, 100.0 * f32(stats.ok) / f32(total)) - fmt.printf(" MN_ALIAS: %d (%.1f%%)\n", stats.mn_alias, 100.0 * f32(stats.mn_alias) / f32(total)) - fmt.printf(" BYTE_MISMATCH: %d (%.1f%%)\n", stats.byte_mismatch, 100.0 * f32(stats.byte_mismatch) / f32(total)) - fmt.printf(" ENCODE_FAIL: %d (%.1f%%)\n", stats.encode_fail, 100.0 * f32(stats.encode_fail) / f32(total)) - fmt.printf(" DECODE_FAIL: %d (%.1f%%)\n", stats.decode_fail, 100.0 * f32(stats.decode_fail) / f32(total)) + total := stats.ok + stats.mn_alias + stats.byte_mismatch + stats.encode_fail + stats.decode_fail + fmt.printf("\n[TOTAL] %d entries\n", total) + fmt.printf(" OK: %d (%.1f%%)\n", stats.ok, 100.0 * f32(stats.ok) / f32(total)) + fmt.printf(" MN_ALIAS: %d (%.1f%%)\n", stats.mn_alias, 100.0 * f32(stats.mn_alias) / f32(total)) + fmt.printf(" BYTE_MISMATCH: %d (%.1f%%)\n", stats.byte_mismatch, 100.0 * f32(stats.byte_mismatch) / f32(total)) + fmt.printf(" ENCODE_FAIL: %d (%.1f%%)\n", stats.encode_fail, 100.0 * f32(stats.encode_fail) / f32(total)) + fmt.printf(" DECODE_FAIL: %d (%.1f%%)\n", stats.decode_fail, 100.0 * f32(stats.decode_fail) / f32(total)) } test_one :: proc(mn: v.Mnemonic, fi: int, f: ^v.Encoding) { - inst := v.Instruction{ - mnemonic = mn, - mode = .PPC32_VLE, - form_id = u16(fi + 1), - length = f.flags.short ? 2 : 4, - } - code := make([]u8, 8, context.temp_allocator) - label_defs: []isa.Label_Definition - relocs: [dynamic]v.Relocation - errors: [dynamic]v.Error - defer delete(relocs); defer delete(errors) + inst := v.Instruction{ + mnemonic = mn, + mode = .PPC32_VLE, + form_id = u16(fi + 1), + length = f.flags.short ? 2 : 4, + } + code := make([]u8, 8, context.temp_allocator) + label_defs: []isa.Label_Definition + relocs: [dynamic]v.Relocation + errors: [dynamic]v.Error + defer delete(relocs); defer delete(errors) - instructions := []v.Instruction{inst} - byte_count, success := v.encode(instructions, label_defs, code, &relocs, &errors) - if !success { - stats.encode_fail += 1 - return - } + instructions := []v.Instruction{inst} + byte_count, success := v.encode(instructions, label_defs, code, &relocs, &errors) + if !success { + stats.encode_fail += 1 + return + } - decoded: [dynamic]v.Instruction - info: [dynamic]v.Instruction_Info - dec_labels: [dynamic]v.Label_Definition - dec_errors: [dynamic]v.Error - defer delete(decoded); defer delete(info); defer delete(dec_labels); defer delete(dec_errors) + decoded: [dynamic]v.Instruction + info: [dynamic]v.Instruction_Info + dec_labels: [dynamic]v.Label_Definition + dec_errors: [dynamic]v.Error + defer delete(decoded); defer delete(info); defer delete(dec_labels); defer delete(dec_errors) - dbyte_count, dsuccess := v.decode(code[:byte_count], nil, &decoded, &info, &dec_labels, &dec_errors) - if !dsuccess || len(decoded) == 0 || decoded[0].mnemonic == .INVALID { - stats.decode_fail += 1 - return - } + dbyte_count, dsuccess := v.decode(code[:byte_count], nil, &decoded, &info, &dec_labels, &dec_errors) + if !dsuccess || len(decoded) == 0 || decoded[0].mnemonic == .INVALID { + stats.decode_fail += 1 + return + } - // Re-encode and check bytes - code2 := make([]u8, 8, context.temp_allocator) - re_relocs: [dynamic]v.Relocation - re_errors: [dynamic]v.Error - defer delete(re_relocs); defer delete(re_errors) + // Re-encode and check bytes + code2 := make([]u8, 8, context.temp_allocator) + re_relocs: [dynamic]v.Relocation + re_errors: [dynamic]v.Error + defer delete(re_relocs); defer delete(re_errors) - rrbyte_count, rrsuccess := v.encode(decoded[:], dec_labels[:], code2, &re_relocs, &re_errors) - if !rrsuccess || rrbyte_count != byte_count { - stats.byte_mismatch += 1 - return - } - for i in 0.. Date: Mon, 15 Jun 2026 21:58:46 +0100 Subject: [PATCH 11/27] Remove unused variable --- core/rexcode/x86/tests/test.odin | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/core/rexcode/x86/tests/test.odin b/core/rexcode/x86/tests/test.odin index 0879565c7..b82f0ade3 100644 --- a/core/rexcode/x86/tests/test.odin +++ b/core/rexcode/x86/tests/test.odin @@ -529,7 +529,7 @@ run_test :: proc(t: Test) -> bool { // ========================================================================= if len(code_to_decode) > 0 { - byte_count, ok := x86.decode( + _, ok := x86.decode( code_to_decode, nil, &decoded_insts, From 9fead11180acab2fb2c239fdc5d335d95aceb959 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 15 Jun 2026 22:25:32 +0100 Subject: [PATCH 12/27] x86: Precompute the `explicit_count` and `has_implicit` in the `Encoding_Flags` --- core/rexcode/x86/encoder.odin | 18 +- core/rexcode/x86/encoding_types.odin | 26 +- core/rexcode/x86/tablegen/gen.odin | 26 +- .../x86/tablegen/generated/encode_tables.odin | 4426 ++++++++--------- 4 files changed, 2261 insertions(+), 2235 deletions(-) diff --git a/core/rexcode/x86/encoder.odin b/core/rexcode/x86/encoder.odin index 95970d2ca..3164212af 100644 --- a/core/rexcode/x86/encoder.odin +++ b/core/rexcode/x86/encoder.odin @@ -706,16 +706,20 @@ encoding_matches_inline :: proc "contextless" (inst: ^Instruction, enc: ^Encodin // when not in Mode._32. if enc.flags.mode_32_only && mode != ._32 { return false } - // Count non-implicit encoding operands - encoding_operand_count: u8 = 0 - for op_type in enc.ops { - if op_type == .NONE { break } - if !is_implicit_op_inline(op_type) { encoding_operand_count += 1 } + explicit_count := enc.flags.explicit_count + + if !enc.flags.has_implicit { + if inst.operand_count != explicit_count { return false } + for i in 0 ..< explicit_count { + eff := mode_rewrite_op_type(enc.ops[i], mode, enc.flags.default_64) + operand_matches_inline(&inst.ops[i], eff) or_return + } + return true } // Special case: if user provides exactly one more operand than non-implicit count, // check if the extra operand matches an implicit operand (e.g., CL for shifts) - if inst.operand_count == encoding_operand_count + 1 { + if inst.operand_count == explicit_count + 1 { // Check if the last user operand matches an implicit operand in the encoding last_user_op := &inst.ops[inst.operand_count - 1] found_matching_implicit := false @@ -743,7 +747,7 @@ encoding_matches_inline :: proc "contextless" (inst: ^Instruction, enc: ^Encodin } // STandard case: operand count must match non-implicit count - if inst.operand_count != encoding_operand_count { return false } + if inst.operand_count != explicit_count { return false } // Match each user operand against non-implicit encoding operands user_idx: u8 = 0 diff --git a/core/rexcode/x86/encoding_types.odin b/core/rexcode/x86/encoding_types.odin index db75512df..01c70ec1b 100644 --- a/core/rexcode/x86/encoding_types.odin +++ b/core/rexcode/x86/encoding_types.odin @@ -246,18 +246,20 @@ VEX_L :: enum u8 { // ----------------------------------------------------------------------------- Encoding_Flags :: bit_field u32 { - esc: Escape | 2, // escape sequence - prefix: u8 | 2, // mandatory prefix: 0=none, 1=66, 2=F3, 3=F2 - vex_type: VEX_Type | 2, // VEX/EVEX/XOP - vex_w: VEX_W | 2, // VEX.W requirement - vex_l: VEX_L | 2, // VEX.L requirement - default_64: bool | 1, // default to 64-bit operand size (PUSH, POP, etc.) - force_rex_w: bool | 1, // always emit REX.W - no_rex: bool | 1, // REX prefix not allowed (high byte regs) - lock_ok: bool | 1, // LOCK prefix valid - rep_ok: bool | 1, // REP prefix valid - modrm_reg_ext: bool | 1, // ModR/M reg field is opcode extension (use ext field) - mode_32_only: bool | 1, // only valid in Mode._32 (e.g. short-form INC/DEC at 0x40-0x4F) + esc: Escape | 2, // escape sequence + prefix: u8 | 2, // mandatory prefix: 0=none, 1=66, 2=F3, 3=F2 + vex_type: VEX_Type | 2, // VEX/EVEX/XOP + vex_w: VEX_W | 2, // VEX.W requirement + vex_l: VEX_L | 2, // VEX.L requirement + default_64: bool | 1, // default to 64-bit operand size (PUSH, POP, etc.) + force_rex_w: bool | 1, // always emit REX.W + no_rex: bool | 1, // REX prefix not allowed (high byte regs) + lock_ok: bool | 1, // LOCK prefix valid + rep_ok: bool | 1, // REP prefix valid + modrm_reg_ext: bool | 1, // ModR/M reg field is opcode extension (use ext field) + mode_32_only: bool | 1, // only valid in Mode._32 (e.g. short-form INC/DEC at 0x40-0x4F) + explicit_count: u8 | 3, // 0..<4 non-implicit operands + has_implicit: bool | 1, // any implicit operand } // ----------------------------------------------------------------------------- diff --git a/core/rexcode/x86/tablegen/gen.odin b/core/rexcode/x86/tablegen/gen.odin index f7cd558e3..65bf106af 100644 --- a/core/rexcode/x86/tablegen/gen.odin +++ b/core/rexcode/x86/tablegen/gen.odin @@ -135,7 +135,7 @@ write_encoding :: proc(sb: ^strings.Builder, e: lib.Encoding, max_name: int) { for en, i in e.enc { print_enum_buffered(sb, en, 4, i+1 < len(e.enc)) } strings.write_string(sb, "}, ") fmt.sbprintf(sb, "0x%02X, %d, ", e.opcode, e.ext) - write_flags(sb, e.flags) + write_flags(sb, e, e.flags) strings.write_string(sb, "},\n") } @@ -228,7 +228,7 @@ gen_entries :: proc(sb: ^strings.Builder, name, typ: string, entries: []Collecte strings.write_string(sb, "}, {") for en, i in e.enc { print_enum_buffered(sb, en, 4, i+1 < len(e.enc)) } strings.write_string(sb, "}, ") - write_flags(sb, e.flags) + write_flags(sb, nil, e.flags) strings.write_string(sb, "},\n") } strings.write_string(sb, "}\n\n") @@ -366,7 +366,7 @@ print_enum_buffered :: proc(sb: ^strings.Builder, x: $T, max_name: int, comma: b // Complete Encoding_Flags emitter -- every field, so ENCODE_FORMS round-trips // the SoT exactly (mode_32_only is read by the encoder). -write_flags :: proc(sb: ^strings.Builder, flags: lib.Encoding_Flags) { +write_flags :: proc(sb: ^strings.Builder, enc: Maybe(Encoding), flags: lib.Encoding_Flags) { parts: [dynamic]string defer delete(parts) if flags.esc != .NONE { append(&parts, fmt.tprintf("esc=.%v", flags.esc)) } @@ -381,6 +381,26 @@ write_flags :: proc(sb: ^strings.Builder, flags: lib.Encoding_Flags) { if flags.rep_ok { append(&parts, "rep_ok=true") } if flags.modrm_reg_ext { append(&parts, "modrm_reg_ext=true") } if flags.mode_32_only { append(&parts, "mode_32_only=true") } + + if e, ok := enc.?; ok { + encoding_operand_count: u8 = 0 + has_implict := false + for op_type in e.ops { + if op_type == .NONE { break } + if lib.is_implicit_op_inline(op_type) { + has_implict = true + } else { + encoding_operand_count += 1 + } + } + if encoding_operand_count > 0 { + append(&parts, fmt.tprintf("explicit_count=%d", encoding_operand_count)) + } + if has_implict { + append(&parts, "has_implict=true") + } + } + strings.write_string(sb, "{") for part, i in parts { if i > 0 { strings.write_string(sb, ", ") } diff --git a/core/rexcode/x86/tablegen/generated/encode_tables.odin b/core/rexcode/x86/tablegen/generated/encode_tables.odin index 7bcea29d0..5acf93a23 100644 --- a/core/rexcode/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/x86/tablegen/generated/encode_tables.odin @@ -10,588 +10,588 @@ import lib "../.." @(rodata) ENCODE_FORMS := [2355]lib.Encoding{ // .MOV - {.MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x88, 0, {}}, - {.MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {}}, - {.MOV, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {}}, - {.MOV, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {force_rex_w=true}}, - {.MOV, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8A, 0, {}}, - {.MOV, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {}}, - {.MOV, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {}}, - {.MOV, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {force_rex_w=true}}, - {.MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, 0xB0, 0, {}}, - {.MOV, {.R16, .IMM16, .NONE, .NONE}, {.OP_R, .IW, .NONE, .NONE}, 0xB8, 0, {}}, - {.MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, 0xB8, 0, {}}, - {.MOV, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, 0xB8, 0, {force_rex_w=true}}, - {.MOV, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC6, 0, {modrm_reg_ext=true}}, - {.MOV, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true}}, - {.MOV, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true}}, - {.MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {force_rex_w=true, modrm_reg_ext=true}}, - {.MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {}}, - {.MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, - {.MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, - {.MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true}}, - {.MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {}}, - {.MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, - {.MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, - {.MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true}}, - {.MOV, {.RM16, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {}}, - {.MOV, {.RM64, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {force_rex_w=true}}, - {.MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {}}, - {.MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {force_rex_w=true}}, - {.MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F}}, - {.MOV, {.CR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F}}, - {.MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F}}, - {.MOV, {.DR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F}}, + {.MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x88, 0, {explicit_count=2}}, + {.MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {explicit_count=2}}, + {.MOV, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {explicit_count=2}}, + {.MOV, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {force_rex_w=true, explicit_count=2}}, + {.MOV, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8A, 0, {explicit_count=2}}, + {.MOV, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {explicit_count=2}}, + {.MOV, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {explicit_count=2}}, + {.MOV, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {force_rex_w=true, explicit_count=2}}, + {.MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, 0xB0, 0, {explicit_count=2}}, + {.MOV, {.R16, .IMM16, .NONE, .NONE}, {.OP_R, .IW, .NONE, .NONE}, 0xB8, 0, {explicit_count=2}}, + {.MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, 0xB8, 0, {explicit_count=2}}, + {.MOV, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, 0xB8, 0, {force_rex_w=true, explicit_count=2}}, + {.MOV, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC6, 0, {modrm_reg_ext=true, explicit_count=2}}, + {.MOV, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true, explicit_count=2}}, + {.MOV, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true, explicit_count=2}}, + {.MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, + {.MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {explicit_count=1, has_implict=true}}, + {.MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}}, + {.MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}}, + {.MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {explicit_count=1, has_implict=true}}, + {.MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}}, + {.MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}}, + {.MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.MOV, {.RM16, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {explicit_count=2}}, + {.MOV, {.RM64, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {force_rex_w=true, explicit_count=2}}, + {.MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {explicit_count=2}}, + {.MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {force_rex_w=true, explicit_count=2}}, + {.MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F, explicit_count=2}}, + {.MOV, {.CR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F, explicit_count=2}}, + {.MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F, explicit_count=2}}, + {.MOV, {.DR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F, explicit_count=2}}, // .MOVABS - {.MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, 0xB8, 0, {force_rex_w=true}}, - {.MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {}}, - {.MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, - {.MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, - {.MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true}}, - {.MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {}}, - {.MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, - {.MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, - {.MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true}}, + {.MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, 0xB8, 0, {force_rex_w=true, explicit_count=2}}, + {.MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {explicit_count=1, has_implict=true}}, + {.MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}}, + {.MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}}, + {.MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {explicit_count=1, has_implict=true}}, + {.MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}}, + {.MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}}, + {.MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, // .MOVZX - {.MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F}}, - {.MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F}}, - {.MOVZX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F, force_rex_w=true}}, - {.MOVZX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB7, 0, {esc=._0F}}, - {.MOVZX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB7, 0, {esc=._0F, force_rex_w=true}}, + {.MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F, explicit_count=2}}, + {.MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F, explicit_count=2}}, + {.MOVZX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, + {.MOVZX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB7, 0, {esc=._0F, explicit_count=2}}, + {.MOVZX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB7, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .MOVSX - {.MOVSX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F}}, - {.MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F}}, - {.MOVSX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F, force_rex_w=true}}, - {.MOVSX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBF, 0, {esc=._0F}}, - {.MOVSX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBF, 0, {esc=._0F, force_rex_w=true}}, + {.MOVSX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F, explicit_count=2}}, + {.MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F, explicit_count=2}}, + {.MOVSX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, + {.MOVSX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBF, 0, {esc=._0F, explicit_count=2}}, + {.MOVSX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBF, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .MOVSXD - {.MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x63, 0, {force_rex_w=true}}, + {.MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x63, 0, {force_rex_w=true, explicit_count=2}}, // .XCHG - {.XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {}}, - {.XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {}}, - {.XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {force_rex_w=true}}, - {.XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x86, 0, {lock_ok=true}}, - {.XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true}}, - {.XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true}}, - {.XCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {force_rex_w=true, lock_ok=true}}, + {.XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {explicit_count=1, has_implict=true}}, + {.XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {explicit_count=1, has_implict=true}}, + {.XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x86, 0, {lock_ok=true, explicit_count=2}}, + {.XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true, explicit_count=2}}, + {.XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true, explicit_count=2}}, + {.XCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {force_rex_w=true, lock_ok=true, explicit_count=2}}, // .PUSH - {.PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x50, 0, {}}, - {.PUSH, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x50, 0, {default_64=true}}, - {.PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 6, {modrm_reg_ext=true}}, - {.PUSH, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 6, {default_64=true, modrm_reg_ext=true}}, - {.PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x6A, 0, {}}, - {.PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, 0x68, 0, {}}, - {.PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x68, 0, {}}, - {.PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA0, 0, {esc=._0F}}, - {.PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA8, 0, {esc=._0F}}, + {.PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x50, 0, {explicit_count=1}}, + {.PUSH, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x50, 0, {default_64=true, explicit_count=1}}, + {.PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 6, {modrm_reg_ext=true, explicit_count=1}}, + {.PUSH, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 6, {default_64=true, modrm_reg_ext=true, explicit_count=1}}, + {.PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x6A, 0, {explicit_count=1}}, + {.PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, 0x68, 0, {explicit_count=1}}, + {.PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x68, 0, {explicit_count=1}}, + {.PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA0, 0, {esc=._0F, explicit_count=1}}, + {.PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA8, 0, {esc=._0F, explicit_count=1}}, // .POP - {.POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x58, 0, {}}, - {.POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x58, 0, {default_64=true}}, - {.POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x8F, 0, {modrm_reg_ext=true}}, - {.POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x8F, 0, {default_64=true, modrm_reg_ext=true}}, - {.POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA1, 0, {esc=._0F}}, - {.POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA9, 0, {esc=._0F}}, + {.POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x58, 0, {explicit_count=1}}, + {.POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x58, 0, {default_64=true, explicit_count=1}}, + {.POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x8F, 0, {modrm_reg_ext=true, explicit_count=1}}, + {.POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x8F, 0, {default_64=true, modrm_reg_ext=true, explicit_count=1}}, + {.POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA1, 0, {esc=._0F, explicit_count=1}}, + {.POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA9, 0, {esc=._0F, explicit_count=1}}, // .LEA - {.LEA, {.R16, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {}}, - {.LEA, {.R32, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {}}, - {.LEA, {.R64, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {force_rex_w=true}}, + {.LEA, {.R16, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {explicit_count=2}}, + {.LEA, {.R32, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {explicit_count=2}}, + {.LEA, {.R64, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {force_rex_w=true, explicit_count=2}}, // .ADD - {.ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x00, 0, {lock_ok=true}}, - {.ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {lock_ok=true}}, - {.ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {lock_ok=true}}, - {.ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {force_rex_w=true, lock_ok=true}}, - {.ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {}}, - {.ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {}}, - {.ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {}}, - {.ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {force_rex_w=true}}, - {.ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x04, 0, {}}, - {.ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x05, 0, {}}, - {.ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {}}, - {.ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {force_rex_w=true}}, - {.ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 0, {lock_ok=true, modrm_reg_ext=true}}, - {.ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 0, {lock_ok=true, modrm_reg_ext=true}}, - {.ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 0, {lock_ok=true, modrm_reg_ext=true}}, - {.ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 0, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {lock_ok=true, modrm_reg_ext=true}}, - {.ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {lock_ok=true, modrm_reg_ext=true}}, - {.ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x00, 0, {lock_ok=true, explicit_count=2}}, + {.ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {lock_ok=true, explicit_count=2}}, + {.ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {lock_ok=true, explicit_count=2}}, + {.ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {force_rex_w=true, lock_ok=true, explicit_count=2}}, + {.ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {explicit_count=2}}, + {.ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {explicit_count=2}}, + {.ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {explicit_count=2}}, + {.ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {force_rex_w=true, explicit_count=2}}, + {.ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x04, 0, {explicit_count=1, has_implict=true}}, + {.ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x05, 0, {explicit_count=1, has_implict=true}}, + {.ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {explicit_count=1, has_implict=true}}, + {.ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 0, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, // .ADC - {.ADC, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {lock_ok=true}}, - {.ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {lock_ok=true}}, - {.ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {lock_ok=true}}, - {.ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {force_rex_w=true, lock_ok=true}}, - {.ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {}}, - {.ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {}}, - {.ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {}}, - {.ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {force_rex_w=true}}, - {.ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x14, 0, {}}, - {.ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x15, 0, {}}, - {.ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {}}, - {.ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {force_rex_w=true}}, - {.ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 2, {lock_ok=true, modrm_reg_ext=true}}, - {.ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 2, {lock_ok=true, modrm_reg_ext=true}}, - {.ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 2, {lock_ok=true, modrm_reg_ext=true}}, - {.ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 2, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {lock_ok=true, modrm_reg_ext=true}}, - {.ADC, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {lock_ok=true, modrm_reg_ext=true}}, - {.ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.ADC, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {lock_ok=true, explicit_count=2}}, + {.ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {lock_ok=true, explicit_count=2}}, + {.ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {lock_ok=true, explicit_count=2}}, + {.ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {force_rex_w=true, lock_ok=true, explicit_count=2}}, + {.ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {explicit_count=2}}, + {.ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {explicit_count=2}}, + {.ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {explicit_count=2}}, + {.ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {force_rex_w=true, explicit_count=2}}, + {.ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x14, 0, {explicit_count=1, has_implict=true}}, + {.ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x15, 0, {explicit_count=1, has_implict=true}}, + {.ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {explicit_count=1, has_implict=true}}, + {.ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 2, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADC, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, // .SUB - {.SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x28, 0, {lock_ok=true}}, - {.SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {lock_ok=true}}, - {.SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {lock_ok=true}}, - {.SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {force_rex_w=true, lock_ok=true}}, - {.SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {}}, - {.SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {}}, - {.SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {}}, - {.SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {force_rex_w=true}}, - {.SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x2C, 0, {}}, - {.SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x2D, 0, {}}, - {.SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {}}, - {.SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {force_rex_w=true}}, - {.SUB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 5, {lock_ok=true, modrm_reg_ext=true}}, - {.SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 5, {lock_ok=true, modrm_reg_ext=true}}, - {.SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 5, {lock_ok=true, modrm_reg_ext=true}}, - {.SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 5, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {lock_ok=true, modrm_reg_ext=true}}, - {.SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {lock_ok=true, modrm_reg_ext=true}}, - {.SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x28, 0, {lock_ok=true, explicit_count=2}}, + {.SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {lock_ok=true, explicit_count=2}}, + {.SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {lock_ok=true, explicit_count=2}}, + {.SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {force_rex_w=true, lock_ok=true, explicit_count=2}}, + {.SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {explicit_count=2}}, + {.SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {explicit_count=2}}, + {.SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {explicit_count=2}}, + {.SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {force_rex_w=true, explicit_count=2}}, + {.SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x2C, 0, {explicit_count=1, has_implict=true}}, + {.SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x2D, 0, {explicit_count=1, has_implict=true}}, + {.SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {explicit_count=1, has_implict=true}}, + {.SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.SUB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 5, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 5, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 5, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 5, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, // .SBB - {.SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x18, 0, {lock_ok=true}}, - {.SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {lock_ok=true}}, - {.SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {lock_ok=true}}, - {.SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {force_rex_w=true, lock_ok=true}}, - {.SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1A, 0, {}}, - {.SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {}}, - {.SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {}}, - {.SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {force_rex_w=true}}, - {.SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x1C, 0, {}}, - {.SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x1D, 0, {}}, - {.SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {}}, - {.SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {force_rex_w=true}}, - {.SBB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 3, {lock_ok=true, modrm_reg_ext=true}}, - {.SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 3, {lock_ok=true, modrm_reg_ext=true}}, - {.SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 3, {lock_ok=true, modrm_reg_ext=true}}, - {.SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 3, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {lock_ok=true, modrm_reg_ext=true}}, - {.SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {lock_ok=true, modrm_reg_ext=true}}, - {.SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x18, 0, {lock_ok=true, explicit_count=2}}, + {.SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {lock_ok=true, explicit_count=2}}, + {.SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {lock_ok=true, explicit_count=2}}, + {.SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {force_rex_w=true, lock_ok=true, explicit_count=2}}, + {.SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1A, 0, {explicit_count=2}}, + {.SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {explicit_count=2}}, + {.SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {explicit_count=2}}, + {.SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {force_rex_w=true, explicit_count=2}}, + {.SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x1C, 0, {explicit_count=1, has_implict=true}}, + {.SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x1D, 0, {explicit_count=1, has_implict=true}}, + {.SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {explicit_count=1, has_implict=true}}, + {.SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.SBB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 3, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, // .MUL - {.MUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 4, {modrm_reg_ext=true}}, - {.MUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {modrm_reg_ext=true}}, - {.MUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {modrm_reg_ext=true}}, - {.MUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {force_rex_w=true, modrm_reg_ext=true}}, + {.MUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 4, {modrm_reg_ext=true, explicit_count=1}}, + {.MUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {modrm_reg_ext=true, explicit_count=1}}, + {.MUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {modrm_reg_ext=true, explicit_count=1}}, + {.MUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .IMUL - {.IMUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 5, {modrm_reg_ext=true}}, - {.IMUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {modrm_reg_ext=true}}, - {.IMUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {modrm_reg_ext=true}}, - {.IMUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {force_rex_w=true, modrm_reg_ext=true}}, - {.IMUL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F}}, - {.IMUL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F}}, - {.IMUL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F, force_rex_w=true}}, - {.IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {}}, - {.IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {}}, - {.IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {force_rex_w=true}}, - {.IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, 0x69, 0, {}}, - {.IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, 0x69, 0, {}}, - {.IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, 0x69, 0, {force_rex_w=true}}, + {.IMUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 5, {modrm_reg_ext=true, explicit_count=1}}, + {.IMUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {modrm_reg_ext=true, explicit_count=1}}, + {.IMUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {modrm_reg_ext=true, explicit_count=1}}, + {.IMUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, + {.IMUL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F, explicit_count=2}}, + {.IMUL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F, explicit_count=2}}, + {.IMUL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, + {.IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {explicit_count=3}}, + {.IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {explicit_count=3}}, + {.IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {force_rex_w=true, explicit_count=3}}, + {.IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, 0x69, 0, {explicit_count=3}}, + {.IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, 0x69, 0, {explicit_count=3}}, + {.IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, 0x69, 0, {force_rex_w=true, explicit_count=3}}, // .DIV - {.DIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 6, {modrm_reg_ext=true}}, - {.DIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {modrm_reg_ext=true}}, - {.DIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {modrm_reg_ext=true}}, - {.DIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {force_rex_w=true, modrm_reg_ext=true}}, + {.DIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 6, {modrm_reg_ext=true, explicit_count=1}}, + {.DIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {modrm_reg_ext=true, explicit_count=1}}, + {.DIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {modrm_reg_ext=true, explicit_count=1}}, + {.DIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .IDIV - {.IDIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 7, {modrm_reg_ext=true}}, - {.IDIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {modrm_reg_ext=true}}, - {.IDIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {modrm_reg_ext=true}}, - {.IDIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {force_rex_w=true, modrm_reg_ext=true}}, + {.IDIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 7, {modrm_reg_ext=true, explicit_count=1}}, + {.IDIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {modrm_reg_ext=true, explicit_count=1}}, + {.IDIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {modrm_reg_ext=true, explicit_count=1}}, + {.IDIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .INC - {.INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x40, 0, {mode_32_only=true}}, - {.INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x40, 0, {mode_32_only=true}}, - {.INC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFE, 0, {lock_ok=true, modrm_reg_ext=true}}, - {.INC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {lock_ok=true, modrm_reg_ext=true}}, - {.INC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {lock_ok=true, modrm_reg_ext=true}}, - {.INC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x40, 0, {mode_32_only=true, explicit_count=1}}, + {.INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x40, 0, {mode_32_only=true, explicit_count=1}}, + {.INC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFE, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.INC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.INC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.INC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, // .DEC - {.DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x48, 0, {mode_32_only=true}}, - {.DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x48, 0, {mode_32_only=true}}, - {.DEC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFE, 1, {lock_ok=true, modrm_reg_ext=true}}, - {.DEC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {lock_ok=true, modrm_reg_ext=true}}, - {.DEC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {lock_ok=true, modrm_reg_ext=true}}, - {.DEC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x48, 0, {mode_32_only=true, explicit_count=1}}, + {.DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x48, 0, {mode_32_only=true, explicit_count=1}}, + {.DEC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFE, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.DEC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.DEC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.DEC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, // .NEG - {.NEG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 3, {lock_ok=true, modrm_reg_ext=true}}, - {.NEG, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {lock_ok=true, modrm_reg_ext=true}}, - {.NEG, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {lock_ok=true, modrm_reg_ext=true}}, - {.NEG, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.NEG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.NEG, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.NEG, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.NEG, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, // .CMP - {.CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x38, 0, {}}, - {.CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {}}, - {.CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {}}, - {.CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {force_rex_w=true}}, - {.CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3A, 0, {}}, - {.CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {}}, - {.CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {}}, - {.CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {force_rex_w=true}}, - {.CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x3C, 0, {}}, - {.CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x3D, 0, {}}, - {.CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {}}, - {.CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {force_rex_w=true}}, - {.CMP, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 7, {modrm_reg_ext=true}}, - {.CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true}}, - {.CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true}}, - {.CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 7, {force_rex_w=true, modrm_reg_ext=true}}, - {.CMP, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {modrm_reg_ext=true}}, - {.CMP, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {modrm_reg_ext=true}}, - {.CMP, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {force_rex_w=true, modrm_reg_ext=true}}, + {.CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x38, 0, {explicit_count=2}}, + {.CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {explicit_count=2}}, + {.CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {explicit_count=2}}, + {.CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {force_rex_w=true, explicit_count=2}}, + {.CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3A, 0, {explicit_count=2}}, + {.CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {explicit_count=2}}, + {.CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {explicit_count=2}}, + {.CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {force_rex_w=true, explicit_count=2}}, + {.CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x3C, 0, {explicit_count=1, has_implict=true}}, + {.CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x3D, 0, {explicit_count=1, has_implict=true}}, + {.CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {explicit_count=1, has_implict=true}}, + {.CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.CMP, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 7, {modrm_reg_ext=true, explicit_count=2}}, + {.CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true, explicit_count=2}}, + {.CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true, explicit_count=2}}, + {.CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, + {.CMP, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {modrm_reg_ext=true, explicit_count=2}}, + {.CMP, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {modrm_reg_ext=true, explicit_count=2}}, + {.CMP, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .AND - {.AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {lock_ok=true}}, - {.AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {lock_ok=true}}, - {.AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {lock_ok=true}}, - {.AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {force_rex_w=true, lock_ok=true}}, - {.AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {}}, - {.AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {}}, - {.AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {}}, - {.AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {force_rex_w=true}}, - {.AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x24, 0, {}}, - {.AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x25, 0, {}}, - {.AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {}}, - {.AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {force_rex_w=true}}, - {.AND, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 4, {lock_ok=true, modrm_reg_ext=true}}, - {.AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 4, {lock_ok=true, modrm_reg_ext=true}}, - {.AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 4, {lock_ok=true, modrm_reg_ext=true}}, - {.AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 4, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {lock_ok=true, modrm_reg_ext=true}}, - {.AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {lock_ok=true, modrm_reg_ext=true}}, - {.AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {lock_ok=true, explicit_count=2}}, + {.AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {lock_ok=true, explicit_count=2}}, + {.AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {lock_ok=true, explicit_count=2}}, + {.AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {force_rex_w=true, lock_ok=true, explicit_count=2}}, + {.AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {explicit_count=2}}, + {.AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {explicit_count=2}}, + {.AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {explicit_count=2}}, + {.AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {force_rex_w=true, explicit_count=2}}, + {.AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x24, 0, {explicit_count=1, has_implict=true}}, + {.AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x25, 0, {explicit_count=1, has_implict=true}}, + {.AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {explicit_count=1, has_implict=true}}, + {.AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.AND, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 4, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 4, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 4, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 4, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, // .OR - {.OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x08, 0, {lock_ok=true}}, - {.OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {lock_ok=true}}, - {.OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {lock_ok=true}}, - {.OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {force_rex_w=true, lock_ok=true}}, - {.OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0A, 0, {}}, - {.OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {}}, - {.OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {}}, - {.OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {force_rex_w=true}}, - {.OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x0C, 0, {}}, - {.OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x0D, 0, {}}, - {.OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {}}, - {.OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {force_rex_w=true}}, - {.OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 1, {lock_ok=true, modrm_reg_ext=true}}, - {.OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 1, {lock_ok=true, modrm_reg_ext=true}}, - {.OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 1, {lock_ok=true, modrm_reg_ext=true}}, - {.OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 1, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {lock_ok=true, modrm_reg_ext=true}}, - {.OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {lock_ok=true, modrm_reg_ext=true}}, - {.OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x08, 0, {lock_ok=true, explicit_count=2}}, + {.OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {lock_ok=true, explicit_count=2}}, + {.OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {lock_ok=true, explicit_count=2}}, + {.OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {force_rex_w=true, lock_ok=true, explicit_count=2}}, + {.OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0A, 0, {explicit_count=2}}, + {.OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {explicit_count=2}}, + {.OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {explicit_count=2}}, + {.OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {force_rex_w=true, explicit_count=2}}, + {.OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x0C, 0, {explicit_count=1, has_implict=true}}, + {.OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x0D, 0, {explicit_count=1, has_implict=true}}, + {.OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {explicit_count=1, has_implict=true}}, + {.OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 1, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, // .XOR - {.XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {lock_ok=true}}, - {.XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {lock_ok=true}}, - {.XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {lock_ok=true}}, - {.XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {force_rex_w=true, lock_ok=true}}, - {.XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {}}, - {.XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {}}, - {.XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {}}, - {.XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {force_rex_w=true}}, - {.XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x34, 0, {}}, - {.XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x35, 0, {}}, - {.XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {}}, - {.XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {force_rex_w=true}}, - {.XOR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 6, {lock_ok=true, modrm_reg_ext=true}}, - {.XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 6, {lock_ok=true, modrm_reg_ext=true}}, - {.XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 6, {lock_ok=true, modrm_reg_ext=true}}, - {.XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 6, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {lock_ok=true, modrm_reg_ext=true}}, - {.XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {lock_ok=true, modrm_reg_ext=true}}, - {.XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {lock_ok=true, explicit_count=2}}, + {.XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {lock_ok=true, explicit_count=2}}, + {.XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {lock_ok=true, explicit_count=2}}, + {.XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {force_rex_w=true, lock_ok=true, explicit_count=2}}, + {.XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {explicit_count=2}}, + {.XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {explicit_count=2}}, + {.XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {explicit_count=2}}, + {.XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {force_rex_w=true, explicit_count=2}}, + {.XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x34, 0, {explicit_count=1, has_implict=true}}, + {.XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x35, 0, {explicit_count=1, has_implict=true}}, + {.XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {explicit_count=1, has_implict=true}}, + {.XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.XOR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 6, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 6, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 6, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 6, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, // .NOT - {.NOT, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 2, {lock_ok=true, modrm_reg_ext=true}}, - {.NOT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {lock_ok=true, modrm_reg_ext=true}}, - {.NOT, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {lock_ok=true, modrm_reg_ext=true}}, - {.NOT, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.NOT, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.NOT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.NOT, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, + {.NOT, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, // .TEST - {.TEST, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x84, 0, {}}, - {.TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {}}, - {.TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {}}, - {.TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {force_rex_w=true}}, - {.TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0xA8, 0, {}}, - {.TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0xA9, 0, {}}, - {.TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {}}, - {.TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {force_rex_w=true}}, - {.TEST, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xF6, 0, {modrm_reg_ext=true}}, - {.TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true}}, - {.TEST, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true}}, - {.TEST, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {force_rex_w=true, modrm_reg_ext=true}}, + {.TEST, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x84, 0, {explicit_count=2}}, + {.TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {explicit_count=2}}, + {.TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {explicit_count=2}}, + {.TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {force_rex_w=true, explicit_count=2}}, + {.TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0xA8, 0, {explicit_count=1, has_implict=true}}, + {.TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0xA9, 0, {explicit_count=1, has_implict=true}}, + {.TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {explicit_count=1, has_implict=true}}, + {.TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.TEST, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xF6, 0, {modrm_reg_ext=true, explicit_count=2}}, + {.TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true, explicit_count=2}}, + {.TEST, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true, explicit_count=2}}, + {.TEST, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .SHL - {.SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {force_rex_w=true, modrm_reg_ext=true}}, - {.SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {force_rex_w=true, modrm_reg_ext=true}}, - {.SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {force_rex_w=true, modrm_reg_ext=true}}, + {.SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 4, {modrm_reg_ext=true, explicit_count=2}}, + {.SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true, explicit_count=2}}, + {.SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true, explicit_count=2}}, + {.SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .SHR - {.SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {force_rex_w=true, modrm_reg_ext=true}}, - {.SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {force_rex_w=true, modrm_reg_ext=true}}, - {.SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {force_rex_w=true, modrm_reg_ext=true}}, + {.SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 5, {modrm_reg_ext=true, explicit_count=2}}, + {.SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true, explicit_count=2}}, + {.SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true, explicit_count=2}}, + {.SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .SAR - {.SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {force_rex_w=true, modrm_reg_ext=true}}, - {.SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {force_rex_w=true, modrm_reg_ext=true}}, - {.SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {force_rex_w=true, modrm_reg_ext=true}}, + {.SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 7, {modrm_reg_ext=true, explicit_count=2}}, + {.SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true, explicit_count=2}}, + {.SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true, explicit_count=2}}, + {.SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .ROL - {.ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {force_rex_w=true, modrm_reg_ext=true}}, - {.ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {force_rex_w=true, modrm_reg_ext=true}}, - {.ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {force_rex_w=true, modrm_reg_ext=true}}, + {.ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 0, {modrm_reg_ext=true, explicit_count=2}}, + {.ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true, explicit_count=2}}, + {.ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true, explicit_count=2}}, + {.ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .ROR - {.ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {force_rex_w=true, modrm_reg_ext=true}}, - {.ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {force_rex_w=true, modrm_reg_ext=true}}, - {.ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {force_rex_w=true, modrm_reg_ext=true}}, + {.ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 1, {modrm_reg_ext=true, explicit_count=2}}, + {.ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true, explicit_count=2}}, + {.ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true, explicit_count=2}}, + {.ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .RCL - {.RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {force_rex_w=true, modrm_reg_ext=true}}, - {.RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {force_rex_w=true, modrm_reg_ext=true}}, - {.RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {force_rex_w=true, modrm_reg_ext=true}}, + {.RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 2, {modrm_reg_ext=true, explicit_count=2}}, + {.RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true, explicit_count=2}}, + {.RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true, explicit_count=2}}, + {.RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .RCR - {.RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {force_rex_w=true, modrm_reg_ext=true}}, - {.RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {force_rex_w=true, modrm_reg_ext=true}}, - {.RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {force_rex_w=true, modrm_reg_ext=true}}, + {.RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 3, {modrm_reg_ext=true, explicit_count=2}}, + {.RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true, explicit_count=2}}, + {.RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true, explicit_count=2}}, + {.RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .SHLD - {.SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F}}, - {.SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F}}, - {.SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, force_rex_w=true}}, - {.SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F}}, - {.SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F}}, - {.SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, force_rex_w=true}}, + {.SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, explicit_count=3}}, + {.SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, explicit_count=3}}, + {.SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, force_rex_w=true, explicit_count=3}}, + {.SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, explicit_count=2, has_implict=true}}, + {.SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, explicit_count=2, has_implict=true}}, + {.SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, force_rex_w=true, explicit_count=2, has_implict=true}}, // .SHRD - {.SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F}}, - {.SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F}}, - {.SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, force_rex_w=true}}, - {.SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F}}, - {.SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F}}, - {.SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, force_rex_w=true}}, + {.SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, explicit_count=3}}, + {.SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, explicit_count=3}}, + {.SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, force_rex_w=true, explicit_count=3}}, + {.SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, explicit_count=2, has_implict=true}}, + {.SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, explicit_count=2, has_implict=true}}, + {.SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, force_rex_w=true, explicit_count=2, has_implict=true}}, // .BT - {.BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F}}, - {.BT, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F}}, - {.BT, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F, force_rex_w=true}}, - {.BT, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, modrm_reg_ext=true}}, - {.BT, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, modrm_reg_ext=true}}, - {.BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F, explicit_count=2}}, + {.BT, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F, explicit_count=2}}, + {.BT, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, + {.BT, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, modrm_reg_ext=true, explicit_count=2}}, + {.BT, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, modrm_reg_ext=true, explicit_count=2}}, + {.BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .BTS - {.BTS, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, lock_ok=true}}, - {.BTS, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, lock_ok=true}}, - {.BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, force_rex_w=true, lock_ok=true}}, - {.BTS, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {.BTS, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {.BTS, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.BTS, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.BTS, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, force_rex_w=true, lock_ok=true, explicit_count=2}}, + {.BTS, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.BTS, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.BTS, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, // .BTR - {.BTR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, lock_ok=true}}, - {.BTR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, lock_ok=true}}, - {.BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, force_rex_w=true, lock_ok=true}}, - {.BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {.BTR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {.BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.BTR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.BTR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, force_rex_w=true, lock_ok=true, explicit_count=2}}, + {.BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.BTR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, // .BTC - {.BTC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, lock_ok=true}}, - {.BTC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, lock_ok=true}}, - {.BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, force_rex_w=true, lock_ok=true}}, - {.BTC, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {.BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {.BTC, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.BTC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.BTC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, force_rex_w=true, lock_ok=true, explicit_count=2}}, + {.BTC, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, + {.BTC, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, // .BSF - {.BSF, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F}}, - {.BSF, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F}}, - {.BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, force_rex_w=true}}, + {.BSF, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, explicit_count=2}}, + {.BSF, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, explicit_count=2}}, + {.BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .BSR - {.BSR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F}}, - {.BSR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F}}, - {.BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, force_rex_w=true}}, + {.BSR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, explicit_count=2}}, + {.BSR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, explicit_count=2}}, + {.BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .POPCNT - {.POPCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=2}}, - {.POPCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=2}}, - {.POPCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=2, force_rex_w=true}}, + {.POPCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.POPCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.POPCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=2, force_rex_w=true, explicit_count=2}}, // .LZCNT - {.LZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=2}}, - {.LZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=2}}, - {.LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=2, force_rex_w=true}}, + {.LZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.LZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=2, force_rex_w=true, explicit_count=2}}, // .TZCNT - {.TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=2}}, - {.TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=2}}, - {.TZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=2, force_rex_w=true}}, + {.TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.TZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=2, force_rex_w=true, explicit_count=2}}, // .JMP - {.JMP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xEB, 0, {}}, - {.JMP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0xE9, 0, {}}, - {.JMP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 4, {default_64=true, modrm_reg_ext=true}}, - {.JMP, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {modrm_reg_ext=true}}, - {.JMP, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {modrm_reg_ext=true}}, - {.JMP, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {force_rex_w=true, modrm_reg_ext=true}}, + {.JMP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xEB, 0, {explicit_count=1}}, + {.JMP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0xE9, 0, {explicit_count=1}}, + {.JMP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 4, {default_64=true, modrm_reg_ext=true, explicit_count=1}}, + {.JMP, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {modrm_reg_ext=true, explicit_count=1}}, + {.JMP, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {modrm_reg_ext=true, explicit_count=1}}, + {.JMP, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .JA - {.JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x77, 0, {}}, - {.JA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x87, 0, {esc=._0F}}, + {.JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x77, 0, {explicit_count=1}}, + {.JA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x87, 0, {esc=._0F, explicit_count=1}}, // .JAE - {.JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {}}, - {.JAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F}}, + {.JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {explicit_count=1}}, + {.JAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F, explicit_count=1}}, // .JB - {.JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {}}, - {.JB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F}}, + {.JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {explicit_count=1}}, + {.JB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F, explicit_count=1}}, // .JBE - {.JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x76, 0, {}}, - {.JBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x86, 0, {esc=._0F}}, + {.JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x76, 0, {explicit_count=1}}, + {.JBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x86, 0, {esc=._0F, explicit_count=1}}, // .JC - {.JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {}}, - {.JC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F}}, + {.JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {explicit_count=1}}, + {.JC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F, explicit_count=1}}, // .JE - {.JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x74, 0, {}}, - {.JE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x84, 0, {esc=._0F}}, + {.JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x74, 0, {explicit_count=1}}, + {.JE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x84, 0, {esc=._0F, explicit_count=1}}, // .JZ - {.JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x74, 0, {}}, - {.JZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x84, 0, {esc=._0F}}, + {.JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x74, 0, {explicit_count=1}}, + {.JZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x84, 0, {esc=._0F, explicit_count=1}}, // .JG - {.JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7F, 0, {}}, - {.JG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8F, 0, {esc=._0F}}, + {.JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7F, 0, {explicit_count=1}}, + {.JG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8F, 0, {esc=._0F, explicit_count=1}}, // .JGE - {.JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7D, 0, {}}, - {.JGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8D, 0, {esc=._0F}}, + {.JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7D, 0, {explicit_count=1}}, + {.JGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8D, 0, {esc=._0F, explicit_count=1}}, // .JL - {.JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7C, 0, {}}, - {.JL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8C, 0, {esc=._0F}}, + {.JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7C, 0, {explicit_count=1}}, + {.JL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8C, 0, {esc=._0F, explicit_count=1}}, // .JLE - {.JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7E, 0, {}}, - {.JLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8E, 0, {esc=._0F}}, + {.JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7E, 0, {explicit_count=1}}, + {.JLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8E, 0, {esc=._0F, explicit_count=1}}, // .JNA - {.JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x76, 0, {}}, - {.JNA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x86, 0, {esc=._0F}}, + {.JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x76, 0, {explicit_count=1}}, + {.JNA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x86, 0, {esc=._0F, explicit_count=1}}, // .JNAE - {.JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {}}, - {.JNAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F}}, + {.JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {explicit_count=1}}, + {.JNAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F, explicit_count=1}}, // .JNB - {.JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {}}, - {.JNB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F}}, + {.JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {explicit_count=1}}, + {.JNB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F, explicit_count=1}}, // .JNBE - {.JNBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x77, 0, {}}, - {.JNBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x87, 0, {esc=._0F}}, + {.JNBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x77, 0, {explicit_count=1}}, + {.JNBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x87, 0, {esc=._0F, explicit_count=1}}, // .JNC - {.JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {}}, - {.JNC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F}}, + {.JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {explicit_count=1}}, + {.JNC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F, explicit_count=1}}, // .JNE - {.JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x75, 0, {}}, - {.JNE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x85, 0, {esc=._0F}}, + {.JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x75, 0, {explicit_count=1}}, + {.JNE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x85, 0, {esc=._0F, explicit_count=1}}, // .JNZ - {.JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x75, 0, {}}, - {.JNZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x85, 0, {esc=._0F}}, + {.JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x75, 0, {explicit_count=1}}, + {.JNZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x85, 0, {esc=._0F, explicit_count=1}}, // .JNG - {.JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7E, 0, {}}, - {.JNG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8E, 0, {esc=._0F}}, + {.JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7E, 0, {explicit_count=1}}, + {.JNG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8E, 0, {esc=._0F, explicit_count=1}}, // .JNGE - {.JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7C, 0, {}}, - {.JNGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8C, 0, {esc=._0F}}, + {.JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7C, 0, {explicit_count=1}}, + {.JNGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8C, 0, {esc=._0F, explicit_count=1}}, // .JNL - {.JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7D, 0, {}}, - {.JNL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8D, 0, {esc=._0F}}, + {.JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7D, 0, {explicit_count=1}}, + {.JNL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8D, 0, {esc=._0F, explicit_count=1}}, // .JNLE - {.JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7F, 0, {}}, - {.JNLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8F, 0, {esc=._0F}}, + {.JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7F, 0, {explicit_count=1}}, + {.JNLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8F, 0, {esc=._0F, explicit_count=1}}, // .JNO - {.JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x71, 0, {}}, - {.JNO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x81, 0, {esc=._0F}}, + {.JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x71, 0, {explicit_count=1}}, + {.JNO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x81, 0, {esc=._0F, explicit_count=1}}, // .JNP - {.JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7B, 0, {}}, - {.JNP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8B, 0, {esc=._0F}}, + {.JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7B, 0, {explicit_count=1}}, + {.JNP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8B, 0, {esc=._0F, explicit_count=1}}, // .JNS - {.JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x79, 0, {}}, - {.JNS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x89, 0, {esc=._0F}}, + {.JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x79, 0, {explicit_count=1}}, + {.JNS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x89, 0, {esc=._0F, explicit_count=1}}, // .JO - {.JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x70, 0, {}}, - {.JO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x80, 0, {esc=._0F}}, + {.JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x70, 0, {explicit_count=1}}, + {.JO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x80, 0, {esc=._0F, explicit_count=1}}, // .JP - {.JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7A, 0, {}}, - {.JP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8A, 0, {esc=._0F}}, + {.JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7A, 0, {explicit_count=1}}, + {.JP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8A, 0, {esc=._0F, explicit_count=1}}, // .JPE - {.JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7A, 0, {}}, - {.JPE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8A, 0, {esc=._0F}}, + {.JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7A, 0, {explicit_count=1}}, + {.JPE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8A, 0, {esc=._0F, explicit_count=1}}, // .JPO - {.JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7B, 0, {}}, - {.JPO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8B, 0, {esc=._0F}}, + {.JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7B, 0, {explicit_count=1}}, + {.JPO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8B, 0, {esc=._0F, explicit_count=1}}, // .JS - {.JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x78, 0, {}}, - {.JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x88, 0, {esc=._0F}}, + {.JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x78, 0, {explicit_count=1}}, + {.JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x88, 0, {esc=._0F, explicit_count=1}}, // .JCXZ - {.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {}}, + {.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {explicit_count=1}}, // .JECXZ - {.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {}}, + {.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {explicit_count=1}}, // .JRCXZ - {.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {force_rex_w=true}}, + {.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {force_rex_w=true, explicit_count=1}}, // .LOOP - {.LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE2, 0, {}}, + {.LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE2, 0, {explicit_count=1}}, // .LOOPE - {.LOOPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE1, 0, {}}, + {.LOOPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE1, 0, {explicit_count=1}}, // .LOOPNE - {.LOOPNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE0, 0, {}}, + {.LOOPNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE0, 0, {explicit_count=1}}, // .CALL - {.CALL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0xE8, 0, {}}, - {.CALL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 2, {default_64=true, modrm_reg_ext=true}}, - {.CALL, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {modrm_reg_ext=true}}, - {.CALL, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {modrm_reg_ext=true}}, - {.CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {force_rex_w=true, modrm_reg_ext=true}}, + {.CALL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0xE8, 0, {explicit_count=1}}, + {.CALL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 2, {default_64=true, modrm_reg_ext=true, explicit_count=1}}, + {.CALL, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {modrm_reg_ext=true, explicit_count=1}}, + {.CALL, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {modrm_reg_ext=true, explicit_count=1}}, + {.CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .RET {.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xC3, 0, {}}, - {.RET, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, 0xC2, 0, {}}, + {.RET, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, 0xC2, 0, {explicit_count=1}}, // .IRET {.IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCF, 0, {}}, // .IRETD @@ -599,7 +599,7 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .IRETQ {.IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCF, 0, {force_rex_w=true}}, // .INT - {.INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xCD, 0, {}}, + {.INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xCD, 0, {explicit_count=1}}, // .INT3 {.INT3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCC, 0, {}}, // .INTO @@ -613,185 +613,185 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .SYSEXIT {.SYSEXIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x35, 0, {esc=._0F}}, // .SETA - {.SETA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x97, 0, {esc=._0F}}, + {.SETA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x97, 0, {esc=._0F, explicit_count=1}}, // .SETAE - {.SETAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F}}, + {.SETAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F, explicit_count=1}}, // .SETB - {.SETB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F}}, + {.SETB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F, explicit_count=1}}, // .SETBE - {.SETBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x96, 0, {esc=._0F}}, + {.SETBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x96, 0, {esc=._0F, explicit_count=1}}, // .SETC - {.SETC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F}}, + {.SETC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F, explicit_count=1}}, // .SETE - {.SETE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x94, 0, {esc=._0F}}, + {.SETE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x94, 0, {esc=._0F, explicit_count=1}}, // .SETG - {.SETG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9F, 0, {esc=._0F}}, + {.SETG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9F, 0, {esc=._0F, explicit_count=1}}, // .SETGE - {.SETGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9D, 0, {esc=._0F}}, + {.SETGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9D, 0, {esc=._0F, explicit_count=1}}, // .SETL - {.SETL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9C, 0, {esc=._0F}}, + {.SETL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9C, 0, {esc=._0F, explicit_count=1}}, // .SETLE - {.SETLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9E, 0, {esc=._0F}}, + {.SETLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9E, 0, {esc=._0F, explicit_count=1}}, // .SETNA - {.SETNA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x96, 0, {esc=._0F}}, + {.SETNA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x96, 0, {esc=._0F, explicit_count=1}}, // .SETNAE - {.SETNAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F}}, + {.SETNAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F, explicit_count=1}}, // .SETNB - {.SETNB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F}}, + {.SETNB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F, explicit_count=1}}, // .SETNBE - {.SETNBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x97, 0, {esc=._0F}}, + {.SETNBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x97, 0, {esc=._0F, explicit_count=1}}, // .SETNC - {.SETNC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F}}, + {.SETNC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F, explicit_count=1}}, // .SETNE - {.SETNE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x95, 0, {esc=._0F}}, + {.SETNE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x95, 0, {esc=._0F, explicit_count=1}}, // .SETNG - {.SETNG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9E, 0, {esc=._0F}}, + {.SETNG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9E, 0, {esc=._0F, explicit_count=1}}, // .SETNGE - {.SETNGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9C, 0, {esc=._0F}}, + {.SETNGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9C, 0, {esc=._0F, explicit_count=1}}, // .SETNL - {.SETNL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9D, 0, {esc=._0F}}, + {.SETNL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9D, 0, {esc=._0F, explicit_count=1}}, // .SETNLE - {.SETNLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9F, 0, {esc=._0F}}, + {.SETNLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9F, 0, {esc=._0F, explicit_count=1}}, // .SETNO - {.SETNO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x91, 0, {esc=._0F}}, + {.SETNO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x91, 0, {esc=._0F, explicit_count=1}}, // .SETNP - {.SETNP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9B, 0, {esc=._0F}}, + {.SETNP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9B, 0, {esc=._0F, explicit_count=1}}, // .SETNS - {.SETNS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x99, 0, {esc=._0F}}, + {.SETNS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x99, 0, {esc=._0F, explicit_count=1}}, // .SETNZ - {.SETNZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x95, 0, {esc=._0F}}, + {.SETNZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x95, 0, {esc=._0F, explicit_count=1}}, // .SETO - {.SETO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x90, 0, {esc=._0F}}, + {.SETO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x90, 0, {esc=._0F, explicit_count=1}}, // .SETP - {.SETP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9A, 0, {esc=._0F}}, + {.SETP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9A, 0, {esc=._0F, explicit_count=1}}, // .SETPE - {.SETPE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9A, 0, {esc=._0F}}, + {.SETPE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9A, 0, {esc=._0F, explicit_count=1}}, // .SETPO - {.SETPO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9B, 0, {esc=._0F}}, + {.SETPO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9B, 0, {esc=._0F, explicit_count=1}}, // .SETS - {.SETS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x98, 0, {esc=._0F}}, + {.SETS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x98, 0, {esc=._0F, explicit_count=1}}, // .SETZ - {.SETZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x94, 0, {esc=._0F}}, + {.SETZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x94, 0, {esc=._0F, explicit_count=1}}, // .CMOVA - {.CMOVA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, - {.CMOVA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, - {.CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, explicit_count=2}}, + {.CMOVA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, explicit_count=2}}, + {.CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVAE - {.CMOVAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, explicit_count=2}}, + {.CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, explicit_count=2}}, + {.CMOVAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVB - {.CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, explicit_count=2}}, + {.CMOVB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, explicit_count=2}}, + {.CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVBE - {.CMOVBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, - {.CMOVBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, - {.CMOVBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, explicit_count=2}}, + {.CMOVBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, explicit_count=2}}, + {.CMOVBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVC - {.CMOVC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, explicit_count=2}}, + {.CMOVC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, explicit_count=2}}, + {.CMOVC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVE - {.CMOVE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, - {.CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, - {.CMOVE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, explicit_count=2}}, + {.CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, explicit_count=2}}, + {.CMOVE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVG - {.CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, - {.CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, - {.CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, explicit_count=2}}, + {.CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, explicit_count=2}}, + {.CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVGE - {.CMOVGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, - {.CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, - {.CMOVGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, explicit_count=2}}, + {.CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, explicit_count=2}}, + {.CMOVGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVL - {.CMOVL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, - {.CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, - {.CMOVL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, explicit_count=2}}, + {.CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, explicit_count=2}}, + {.CMOVL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVLE - {.CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, - {.CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, - {.CMOVLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, explicit_count=2}}, + {.CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, explicit_count=2}}, + {.CMOVLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNA - {.CMOVNA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, - {.CMOVNA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, - {.CMOVNA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNAE - {.CMOVNAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVNAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVNAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNB - {.CMOVNB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVNB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVNB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNBE - {.CMOVNBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, - {.CMOVNBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, - {.CMOVNBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNC - {.CMOVNC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVNC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVNC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNE - {.CMOVNE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, - {.CMOVNE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, - {.CMOVNE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNG - {.CMOVNG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, - {.CMOVNG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, - {.CMOVNG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNGE - {.CMOVNGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, - {.CMOVNGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, - {.CMOVNGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNL - {.CMOVNL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, - {.CMOVNL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, - {.CMOVNL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNLE - {.CMOVNLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, - {.CMOVNLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, - {.CMOVNLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNO - {.CMOVNO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F}}, - {.CMOVNO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F}}, - {.CMOVNO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNP - {.CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, - {.CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, - {.CMOVNP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNS - {.CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F}}, - {.CMOVNS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F}}, - {.CMOVNS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVNZ - {.CMOVNZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, - {.CMOVNZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, - {.CMOVNZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVNZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, explicit_count=2}}, + {.CMOVNZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVO - {.CMOVO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F}}, - {.CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F}}, - {.CMOVO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F, explicit_count=2}}, + {.CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F, explicit_count=2}}, + {.CMOVO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVP - {.CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, - {.CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, - {.CMOVP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, explicit_count=2}}, + {.CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, explicit_count=2}}, + {.CMOVP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVPE - {.CMOVPE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, - {.CMOVPE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, - {.CMOVPE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVPE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, explicit_count=2}}, + {.CMOVPE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, explicit_count=2}}, + {.CMOVPE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVPO - {.CMOVPO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, - {.CMOVPO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, - {.CMOVPO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVPO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, explicit_count=2}}, + {.CMOVPO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, explicit_count=2}}, + {.CMOVPO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVS - {.CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F}}, - {.CMOVS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F}}, - {.CMOVS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F, explicit_count=2}}, + {.CMOVS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F, explicit_count=2}}, + {.CMOVS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .CMOVZ - {.CMOVZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, - {.CMOVZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, - {.CMOVZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, force_rex_w=true}}, + {.CMOVZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, explicit_count=2}}, + {.CMOVZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, explicit_count=2}}, + {.CMOVZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .MOVS {.MOVS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA4, 0, {rep_ok=true}}, // .MOVSB @@ -874,9 +874,9 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.POPFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9D, 0, {}}, // .NOP {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x90, 0, {}}, - {.NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, modrm_reg_ext=true}}, - {.NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, modrm_reg_ext=true}}, - {.NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .HLT {.HLT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF4, 0, {}}, // .WAIT @@ -884,9 +884,9 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .LOCK {.LOCK, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0, 0, {}}, // .UD0 - {.UD0, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFF, 0, {esc=._0F}}, + {.UD0, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFF, 0, {esc=._0F, explicit_count=2}}, // .UD1 - {.UD1, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB9, 0, {esc=._0F}}, + {.UD1, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB9, 0, {esc=._0F, explicit_count=2}}, // .UD2 {.UD2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0B, 0, {esc=._0F}}, // .CPUID @@ -914,403 +914,403 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .CQO {.CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x99, 0, {force_rex_w=true}}, // .ANDN - {.ANDN, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF2, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.ANDN, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF2, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.ANDN, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF2, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.ANDN, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF2, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .BEXTR - {.BEXTR, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.BEXTR, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.BEXTR, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.BEXTR, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .BLSI - {.BLSI, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 3, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, - {.BLSI, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 3, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, + {.BLSI, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 3, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, explicit_count=2}}, + {.BLSI, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 3, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, explicit_count=2}}, // .BLSMSK - {.BLSMSK, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 2, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, - {.BLSMSK, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 2, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, + {.BLSMSK, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 2, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, explicit_count=2}}, + {.BLSMSK, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 2, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, explicit_count=2}}, // .BLSR - {.BLSR, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 1, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, - {.BLSR, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 1, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, + {.BLSR, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 1, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, explicit_count=2}}, + {.BLSR, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 1, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, explicit_count=2}}, // .BZHI - {.BZHI, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF5, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.BZHI, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF5, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.BZHI, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF5, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.BZHI, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF5, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .PDEP - {.PDEP, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.PDEP, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.PDEP, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.PDEP, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .PEXT - {.PEXT, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.PEXT, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.PEXT, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.PEXT, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .RORX - {.RORX, {.R32, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xF0, 0, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.RORX, {.R64, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xF0, 0, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.RORX, {.R32, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xF0, 0, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.RORX, {.R64, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xF0, 0, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .SARX - {.SARX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.SARX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.SARX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.SARX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .SHLX - {.SHLX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.SHLX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.SHLX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.SHLX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .SHRX - {.SHRX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.SHRX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.SHRX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.SHRX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .MULX - {.MULX, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF6, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.MULX, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF6, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.MULX, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF6, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.MULX, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF6, 0, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .ADCX - {.ADCX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=1}}, - {.ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=1, force_rex_w=true}}, + {.ADCX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=1, explicit_count=2}}, + {.ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=1, force_rex_w=true, explicit_count=2}}, // .ADOX - {.ADOX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=2}}, - {.ADOX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=2, force_rex_w=true}}, + {.ADOX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=2, explicit_count=2}}, + {.ADOX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=2, force_rex_w=true, explicit_count=2}}, // .MOVAPS - {.MOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F}}, - {.MOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F}}, + {.MOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, explicit_count=2}}, + {.MOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, explicit_count=2}}, // .MOVUPS - {.MOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F}}, - {.MOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F}}, + {.MOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, explicit_count=2}}, + {.MOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, explicit_count=2}}, // .MOVAPD - {.MOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=1}}, - {.MOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=1}}, + {.MOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.MOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MOVUPD - {.MOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=1}}, - {.MOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=1}}, + {.MOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.MOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MOVSS - {.MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=2}}, - {.MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=2}}, + {.MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .MOVSD_SSE - {.MOVSD_SSE, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=3}}, - {.MOVSD_SSE, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=3}}, + {.MOVSD_SSE, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=3, explicit_count=2}}, + {.MOVSD_SSE, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .MOVDQA - {.MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1}}, - {.MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1}}, + {.MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MOVDQU - {.MOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2}}, - {.MOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2}}, + {.MOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.MOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .MOVQ - {.MOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=2}}, - {.MOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xD6, 0, {esc=._0F, prefix=1}}, - {.MOVQ, {.MM, .MM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F}}, - {.MOVQ, {.MM_M64, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F}}, - {.MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=1, force_rex_w=true}}, - {.MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=1, force_rex_w=true}}, + {.MOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.MOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xD6, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.MOVQ, {.MM, .MM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, explicit_count=2}}, + {.MOVQ, {.MM_M64, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, explicit_count=2}}, + {.MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=1, force_rex_w=true, explicit_count=2}}, + {.MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=1, force_rex_w=true, explicit_count=2}}, // .MOVD - {.MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=1}}, - {.MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=1}}, - {.MOVD, {.MM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F}}, - {.MOVD, {.RM32, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F}}, + {.MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.MOVD, {.MM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, explicit_count=2}}, + {.MOVD, {.RM32, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, explicit_count=2}}, // .MOVLPS - {.MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F}}, - {.MOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F}}, + {.MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, explicit_count=2}}, + {.MOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, explicit_count=2}}, // .MOVHPS - {.MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F}}, - {.MOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F}}, + {.MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, explicit_count=2}}, + {.MOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, explicit_count=2}}, // .MOVLPD - {.MOVLPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=1}}, - {.MOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, prefix=1}}, + {.MOVLPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.MOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MOVHPD - {.MOVHPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=1}}, - {.MOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, prefix=1}}, + {.MOVHPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.MOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MOVLHPS - {.MOVLHPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F}}, + {.MOVLHPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, explicit_count=2}}, // .MOVHLPS - {.MOVHLPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F}}, + {.MOVHLPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, explicit_count=2}}, // .MOVMSKPS - {.MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F}}, - {.MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, force_rex_w=true}}, + {.MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, explicit_count=2}}, + {.MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .MOVMSKPD - {.MOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=1}}, - {.MOVMSKPD, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=1, force_rex_w=true}}, + {.MOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.MOVMSKPD, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=1, force_rex_w=true, explicit_count=2}}, // .MOVNTPS - {.MOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F}}, + {.MOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, explicit_count=2}}, // .MOVNTPD - {.MOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=1}}, + {.MOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MOVNTDQ - {.MOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=1}}, + {.MOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MOVNTDQA - {.MOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=1}}, + {.MOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .ADDPS - {.ADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F}}, + {.ADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, explicit_count=2}}, // .ADDPD - {.ADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=1}}, + {.ADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .ADDSS - {.ADDSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=2}}, + {.ADDSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .ADDSD - {.ADDSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=3}}, + {.ADDSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .SUBPS - {.SUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F}}, + {.SUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, explicit_count=2}}, // .SUBPD - {.SUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=1}}, + {.SUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .SUBSS - {.SUBSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=2}}, + {.SUBSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .SUBSD - {.SUBSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=3}}, + {.SUBSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .MULPS - {.MULPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F}}, + {.MULPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, explicit_count=2}}, // .MULPD - {.MULPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=1}}, + {.MULPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MULSS - {.MULSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=2}}, + {.MULSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .MULSD - {.MULSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=3}}, + {.MULSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .DIVPS - {.DIVPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F}}, + {.DIVPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, explicit_count=2}}, // .DIVPD - {.DIVPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=1}}, + {.DIVPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .DIVSS - {.DIVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=2}}, + {.DIVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .DIVSD - {.DIVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=3}}, + {.DIVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .SQRTPS - {.SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F}}, + {.SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, explicit_count=2}}, // .SQRTPD - {.SQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=1}}, + {.SQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .SQRTSS - {.SQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=2}}, + {.SQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .SQRTSD - {.SQRTSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=3}}, + {.SQRTSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .RCPPS - {.RCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F}}, + {.RCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, explicit_count=2}}, // .RCPSS - {.RCPSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, prefix=2}}, + {.RCPSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .RSQRTPS - {.RSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F}}, + {.RSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, explicit_count=2}}, // .RSQRTSS - {.RSQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, prefix=2}}, + {.RSQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .MAXPS - {.MAXPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F}}, + {.MAXPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, explicit_count=2}}, // .MAXPD - {.MAXPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=1}}, + {.MAXPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MAXSS - {.MAXSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=2}}, + {.MAXSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .MAXSD - {.MAXSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=3}}, + {.MAXSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .MINPS - {.MINPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F}}, + {.MINPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, explicit_count=2}}, // .MINPD - {.MINPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=1}}, + {.MINPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MINSS - {.MINSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=2}}, + {.MINSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .MINSD - {.MINSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=3}}, + {.MINSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .ANDPS - {.ANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x54, 0, {esc=._0F}}, + {.ANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x54, 0, {esc=._0F, explicit_count=2}}, // .ANDPD - {.ANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x54, 0, {esc=._0F, prefix=1}}, + {.ANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x54, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .ANDNPS - {.ANDNPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x55, 0, {esc=._0F}}, + {.ANDNPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x55, 0, {esc=._0F, explicit_count=2}}, // .ANDNPD - {.ANDNPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x55, 0, {esc=._0F, prefix=1}}, + {.ANDNPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x55, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .ORPS - {.ORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x56, 0, {esc=._0F}}, + {.ORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x56, 0, {esc=._0F, explicit_count=2}}, // .ORPD - {.ORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x56, 0, {esc=._0F, prefix=1}}, + {.ORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x56, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .XORPS - {.XORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x57, 0, {esc=._0F}}, + {.XORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x57, 0, {esc=._0F, explicit_count=2}}, // .XORPD - {.XORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x57, 0, {esc=._0F, prefix=1}}, + {.XORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x57, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .CMPPS - {.CMPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F}}, + {.CMPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, explicit_count=3}}, // .CMPPD - {.CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=1}}, + {.CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=1, explicit_count=3}}, // .CMPSS - {.CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=2}}, + {.CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=2, explicit_count=3}}, // .CMPSD_SSE - {.CMPSD_SSE, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=3}}, + {.CMPSD_SSE, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=3, explicit_count=3}}, // .COMISS - {.COMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F}}, + {.COMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, explicit_count=2}}, // .COMISD - {.COMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, prefix=1}}, + {.COMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .UCOMISS - {.UCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F}}, + {.UCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, explicit_count=2}}, // .UCOMISD - {.UCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, prefix=1}}, + {.UCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .SHUFPS - {.SHUFPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC6, 0, {esc=._0F}}, + {.SHUFPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC6, 0, {esc=._0F, explicit_count=3}}, // .SHUFPD - {.SHUFPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC6, 0, {esc=._0F, prefix=1}}, + {.SHUFPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC6, 0, {esc=._0F, prefix=1, explicit_count=3}}, // .UNPCKLPS - {.UNPCKLPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x14, 0, {esc=._0F}}, + {.UNPCKLPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x14, 0, {esc=._0F, explicit_count=2}}, // .UNPCKHPS - {.UNPCKHPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x15, 0, {esc=._0F}}, + {.UNPCKHPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x15, 0, {esc=._0F, explicit_count=2}}, // .UNPCKLPD - {.UNPCKLPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x14, 0, {esc=._0F, prefix=1}}, + {.UNPCKLPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x14, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .UNPCKHPD - {.UNPCKHPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x15, 0, {esc=._0F, prefix=1}}, + {.UNPCKHPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x15, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .CVTPS2PD - {.CVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F}}, + {.CVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, explicit_count=2}}, // .CVTPD2PS - {.CVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=1}}, + {.CVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .CVTSS2SD - {.CVTSS2SD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=2}}, + {.CVTSS2SD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .CVTSD2SS - {.CVTSD2SS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=3}}, + {.CVTSD2SS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .CVTPS2DQ - {.CVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=1}}, + {.CVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .CVTPD2DQ - {.CVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=3}}, + {.CVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .CVTDQ2PS - {.CVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F}}, + {.CVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, explicit_count=2}}, // .CVTDQ2PD - {.CVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=2}}, + {.CVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .CVTSS2SI - {.CVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=2}}, - {.CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=2, force_rex_w=true}}, + {.CVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=2, force_rex_w=true, explicit_count=2}}, // .CVTSD2SI - {.CVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=3}}, - {.CVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=3, force_rex_w=true}}, + {.CVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=3, explicit_count=2}}, + {.CVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=3, force_rex_w=true, explicit_count=2}}, // .CVTSI2SS - {.CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=2}}, - {.CVTSI2SS, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=2, force_rex_w=true}}, + {.CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.CVTSI2SS, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=2, force_rex_w=true, explicit_count=2}}, // .CVTSI2SD - {.CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=3}}, - {.CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=3, force_rex_w=true}}, + {.CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=3, explicit_count=2}}, + {.CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=3, force_rex_w=true, explicit_count=2}}, // .CVTTPS2DQ - {.CVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=2}}, + {.CVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .CVTTPD2DQ - {.CVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=1}}, + {.CVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .CVTTSS2SI - {.CVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=2}}, - {.CVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=2, force_rex_w=true}}, + {.CVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=2, explicit_count=2}}, + {.CVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=2, force_rex_w=true, explicit_count=2}}, // .CVTTSD2SI - {.CVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=3}}, - {.CVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=3, force_rex_w=true}}, + {.CVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=3, explicit_count=2}}, + {.CVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=3, force_rex_w=true, explicit_count=2}}, // .PADDB - {.PADDB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFC, 0, {esc=._0F, prefix=1}}, + {.PADDB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFC, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PADDW - {.PADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFD, 0, {esc=._0F, prefix=1}}, + {.PADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFD, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PADDD - {.PADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFE, 0, {esc=._0F, prefix=1}}, + {.PADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFE, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PADDQ - {.PADDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD4, 0, {esc=._0F, prefix=1}}, + {.PADDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD4, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PSUBB - {.PSUBB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F, prefix=1}}, + {.PSUBB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PSUBW - {.PSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF9, 0, {esc=._0F, prefix=1}}, + {.PSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF9, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PSUBD - {.PSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFA, 0, {esc=._0F, prefix=1}}, + {.PSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFA, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PSUBQ - {.PSUBQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFB, 0, {esc=._0F, prefix=1}}, + {.PSUBQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFB, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PADDSB - {.PADDSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEC, 0, {esc=._0F, prefix=1}}, + {.PADDSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEC, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PADDSW - {.PADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xED, 0, {esc=._0F, prefix=1}}, + {.PADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xED, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PADDUSB - {.PADDUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDC, 0, {esc=._0F, prefix=1}}, + {.PADDUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDC, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PADDUSW - {.PADDUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDD, 0, {esc=._0F, prefix=1}}, + {.PADDUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDD, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PSUBSB - {.PSUBSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE8, 0, {esc=._0F, prefix=1}}, + {.PSUBSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE8, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PSUBSW - {.PSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE9, 0, {esc=._0F, prefix=1}}, + {.PSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE9, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PSUBUSB - {.PSUBUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD8, 0, {esc=._0F, prefix=1}}, + {.PSUBUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD8, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PSUBUSW - {.PSUBUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD9, 0, {esc=._0F, prefix=1}}, + {.PSUBUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD9, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PMULLW - {.PMULLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD5, 0, {esc=._0F, prefix=1}}, + {.PMULLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD5, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PMULHW - {.PMULHW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE5, 0, {esc=._0F, prefix=1}}, + {.PMULHW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE5, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PMULHUW - {.PMULHUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE4, 0, {esc=._0F, prefix=1}}, + {.PMULHUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE4, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PMULUDQ - {.PMULUDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF4, 0, {esc=._0F, prefix=1}}, + {.PMULUDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF4, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PMADDWD - {.PMADDWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF5, 0, {esc=._0F, prefix=1}}, + {.PMADDWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF5, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PAND - {.PAND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F, prefix=1}}, + {.PAND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PANDN - {.PANDN, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDF, 0, {esc=._0F, prefix=1}}, + {.PANDN, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDF, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .POR - {.POR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEB, 0, {esc=._0F, prefix=1}}, + {.POR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEB, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PXOR - {.PXOR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEF, 0, {esc=._0F, prefix=1}}, + {.PXOR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEF, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PSLLW - {.PSLLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F, prefix=1}}, - {.PSLLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 6, {esc=._0F, prefix=1, modrm_reg_ext=true}}, + {.PSLLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.PSLLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 6, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=2}}, // .PSLLD - {.PSLLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF2, 0, {esc=._0F, prefix=1}}, - {.PSLLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 6, {esc=._0F, prefix=1, modrm_reg_ext=true}}, + {.PSLLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF2, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.PSLLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 6, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=2}}, // .PSLLQ - {.PSLLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF3, 0, {esc=._0F, prefix=1}}, - {.PSLLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x73, 6, {esc=._0F, prefix=1, modrm_reg_ext=true}}, + {.PSLLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF3, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.PSLLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x73, 6, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=2}}, // .PSRLW - {.PSRLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD1, 0, {esc=._0F, prefix=1}}, - {.PSRLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 2, {esc=._0F, prefix=1, modrm_reg_ext=true}}, + {.PSRLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD1, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.PSRLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 2, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=2}}, // .PSRLD - {.PSRLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD2, 0, {esc=._0F, prefix=1}}, - {.PSRLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 2, {esc=._0F, prefix=1, modrm_reg_ext=true}}, + {.PSRLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD2, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.PSRLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 2, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=2}}, // .PSRLQ - {.PSRLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD3, 0, {esc=._0F, prefix=1}}, - {.PSRLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x73, 2, {esc=._0F, prefix=1, modrm_reg_ext=true}}, + {.PSRLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD3, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.PSRLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x73, 2, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=2}}, // .PSRAW - {.PSRAW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE1, 0, {esc=._0F, prefix=1}}, - {.PSRAW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 4, {esc=._0F, prefix=1, modrm_reg_ext=true}}, + {.PSRAW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE1, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.PSRAW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 4, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=2}}, // .PSRAD - {.PSRAD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE2, 0, {esc=._0F, prefix=1}}, - {.PSRAD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 4, {esc=._0F, prefix=1, modrm_reg_ext=true}}, + {.PSRAD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE2, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.PSRAD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 4, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=2}}, // .PCMPEQB - {.PCMPEQB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x74, 0, {esc=._0F, prefix=1}}, + {.PCMPEQB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x74, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PCMPEQW - {.PCMPEQW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x75, 0, {esc=._0F, prefix=1}}, + {.PCMPEQW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x75, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PCMPEQD - {.PCMPEQD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x76, 0, {esc=._0F, prefix=1}}, + {.PCMPEQD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x76, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PCMPGTB - {.PCMPGTB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x64, 0, {esc=._0F, prefix=1}}, + {.PCMPGTB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x64, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PCMPGTW - {.PCMPGTW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x65, 0, {esc=._0F, prefix=1}}, + {.PCMPGTW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x65, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PCMPGTD - {.PCMPGTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x66, 0, {esc=._0F, prefix=1}}, + {.PCMPGTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x66, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PACKSSWB - {.PACKSSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x63, 0, {esc=._0F, prefix=1}}, + {.PACKSSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x63, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PACKSSDW - {.PACKSSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6B, 0, {esc=._0F, prefix=1}}, + {.PACKSSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6B, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PACKUSWB - {.PACKUSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x67, 0, {esc=._0F, prefix=1}}, + {.PACKUSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x67, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PUNPCKLBW - {.PUNPCKLBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x60, 0, {esc=._0F, prefix=1}}, + {.PUNPCKLBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x60, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PUNPCKLWD - {.PUNPCKLWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x61, 0, {esc=._0F, prefix=1}}, + {.PUNPCKLWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x61, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PUNPCKLDQ - {.PUNPCKLDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {esc=._0F, prefix=1}}, + {.PUNPCKLDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PUNPCKLQDQ - {.PUNPCKLQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6C, 0, {esc=._0F, prefix=1}}, + {.PUNPCKLQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6C, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PUNPCKHBW - {.PUNPCKHBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x68, 0, {esc=._0F, prefix=1}}, + {.PUNPCKHBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x68, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PUNPCKHWD - {.PUNPCKHWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x69, 0, {esc=._0F, prefix=1}}, + {.PUNPCKHWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x69, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PUNPCKHDQ - {.PUNPCKHDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6A, 0, {esc=._0F, prefix=1}}, + {.PUNPCKHDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6A, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PUNPCKHQDQ - {.PUNPCKHQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6D, 0, {esc=._0F, prefix=1}}, + {.PUNPCKHQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6D, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PSHUFD - {.PSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=1}}, + {.PSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=1, explicit_count=3}}, // .PSHUFHW - {.PSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=2}}, + {.PSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=2, explicit_count=3}}, // .PSHUFLW - {.PSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=3}}, + {.PSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=3, explicit_count=3}}, // .PSHUFW - {.PSHUFW, {.MM, .MM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F}}, + {.PSHUFW, {.MM, .MM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, explicit_count=3}}, // .PEXTRW - {.PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=1}}, - {.PEXTRW, {.R64, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=1, force_rex_w=true}}, + {.PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=1, explicit_count=3}}, + {.PEXTRW, {.R64, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=1, force_rex_w=true, explicit_count=3}}, // .PINSRW - {.PINSRW, {.XMM, .R32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC4, 0, {esc=._0F, prefix=1}}, - {.PINSRW, {.XMM, .M16, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC4, 0, {esc=._0F, prefix=1}}, + {.PINSRW, {.XMM, .R32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC4, 0, {esc=._0F, prefix=1, explicit_count=3}}, + {.PINSRW, {.XMM, .M16, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC4, 0, {esc=._0F, prefix=1, explicit_count=3}}, // .PMOVMSKB - {.PMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=1}}, - {.PMOVMSKB, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=1, force_rex_w=true}}, + {.PMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=1, explicit_count=2}}, + {.PMOVMSKB, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=1, force_rex_w=true, explicit_count=2}}, // .PAVGB - {.PAVGB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE0, 0, {esc=._0F, prefix=1}}, + {.PAVGB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE0, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PAVGW - {.PAVGW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE3, 0, {esc=._0F, prefix=1}}, + {.PAVGW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE3, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PMAXUB - {.PMAXUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDE, 0, {esc=._0F, prefix=1}}, + {.PMAXUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDE, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PMAXSW - {.PMAXSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEE, 0, {esc=._0F, prefix=1}}, + {.PMAXSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEE, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PMINUB - {.PMINUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDA, 0, {esc=._0F, prefix=1}}, + {.PMINUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDA, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PMINSW - {.PMINSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEA, 0, {esc=._0F, prefix=1}}, + {.PMINSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEA, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .PSADBW - {.PSADBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F, prefix=1}}, + {.PSADBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MASKMOVDQU - {.MASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF7, 0, {esc=._0F, prefix=1}}, + {.MASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF7, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .LFENCE {.LFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAE, 232, {esc=._0F}}, // .SFENCE @@ -1320,1829 +1320,1829 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .PAUSE {.PAUSE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x90, 0, {prefix=2}}, // .CLFLUSH - {.CLFLUSH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 7, {esc=._0F, modrm_reg_ext=true}}, + {.CLFLUSH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 7, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .ADDSUBPS - {.ADDSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD0, 0, {esc=._0F, prefix=3}}, + {.ADDSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD0, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .ADDSUBPD - {.ADDSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD0, 0, {esc=._0F, prefix=1}}, + {.ADDSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD0, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .HADDPS - {.HADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7C, 0, {esc=._0F, prefix=3}}, + {.HADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7C, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .HADDPD - {.HADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7C, 0, {esc=._0F, prefix=1}}, + {.HADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7C, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .HSUBPS - {.HSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7D, 0, {esc=._0F, prefix=3}}, + {.HSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7D, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .HSUBPD - {.HSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7D, 0, {esc=._0F, prefix=1}}, + {.HSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7D, 0, {esc=._0F, prefix=1, explicit_count=2}}, // .MOVDDUP - {.MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=3}}, + {.MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .MOVSLDUP - {.MOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=2}}, + {.MOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .MOVSHDUP - {.MOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=2}}, + {.MOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=2, explicit_count=2}}, // .LDDQU - {.LDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=3}}, + {.LDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=3, explicit_count=2}}, // .PSHUFB - {.PSHUFB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x00, 0, {esc=._0F38, prefix=1}}, + {.PSHUFB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x00, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PHADDW - {.PHADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x01, 0, {esc=._0F38, prefix=1}}, + {.PHADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x01, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PHADDD - {.PHADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F38, prefix=1}}, + {.PHADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PHADDSW - {.PHADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F38, prefix=1}}, + {.PHADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PHSUBW - {.PHSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x05, 0, {esc=._0F38, prefix=1}}, + {.PHSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x05, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PHSUBD - {.PHSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x06, 0, {esc=._0F38, prefix=1}}, + {.PHSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x06, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PHSUBSW - {.PHSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x07, 0, {esc=._0F38, prefix=1}}, + {.PHSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x07, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMADDUBSW - {.PMADDUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x04, 0, {esc=._0F38, prefix=1}}, + {.PMADDUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x04, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMULHRSW - {.PMULHRSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {esc=._0F38, prefix=1}}, + {.PMULHRSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PSIGNB - {.PSIGNB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x08, 0, {esc=._0F38, prefix=1}}, + {.PSIGNB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x08, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PSIGNW - {.PSIGNW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x09, 0, {esc=._0F38, prefix=1}}, + {.PSIGNW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x09, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PSIGND - {.PSIGND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0A, 0, {esc=._0F38, prefix=1}}, + {.PSIGND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0A, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PABSB - {.PABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=1}}, + {.PABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PABSW - {.PABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=1}}, + {.PABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PABSD - {.PABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=1}}, + {.PABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PALIGNR - {.PALIGNR, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0F, 0, {esc=._0F3A, prefix=1}}, + {.PALIGNR, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0F, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .BLENDPS - {.BLENDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0C, 0, {esc=._0F3A, prefix=1}}, + {.BLENDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0C, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .BLENDPD - {.BLENDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0D, 0, {esc=._0F3A, prefix=1}}, + {.BLENDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0D, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .BLENDVPS - {.BLENDVPS, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x14, 0, {esc=._0F38, prefix=1}}, + {.BLENDVPS, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implict=true}}, // .BLENDVPD - {.BLENDVPD, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x15, 0, {esc=._0F38, prefix=1}}, + {.BLENDVPD, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implict=true}}, // .PBLENDW - {.PBLENDW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0E, 0, {esc=._0F3A, prefix=1}}, + {.PBLENDW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0E, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PBLENDVB - {.PBLENDVB, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x10, 0, {esc=._0F38, prefix=1}}, + {.PBLENDVB, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x10, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implict=true}}, // .DPPS - {.DPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x40, 0, {esc=._0F3A, prefix=1}}, + {.DPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x40, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .DPPD - {.DPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x41, 0, {esc=._0F3A, prefix=1}}, + {.DPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x41, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .EXTRACTPS - {.EXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x17, 0, {esc=._0F3A, prefix=1}}, + {.EXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x17, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .INSERTPS - {.INSERTPS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x21, 0, {esc=._0F3A, prefix=1}}, + {.INSERTPS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x21, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .MPSADBW - {.MPSADBW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x42, 0, {esc=._0F3A, prefix=1}}, + {.MPSADBW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x42, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PACKUSDW - {.PACKUSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {esc=._0F38, prefix=1}}, + {.PACKUSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PEXTRB - {.PEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x14, 0, {esc=._0F3A, prefix=1}}, + {.PEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x14, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PEXTRD - {.PEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=1}}, + {.PEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PEXTRQ - {.PEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=1, force_rex_w=true}}, + {.PEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=1, force_rex_w=true, explicit_count=3}}, // .PHMINPOSUW - {.PHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F38, prefix=1}}, + {.PHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PINSRB - {.PINSRB, {.XMM, .RM8, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x20, 0, {esc=._0F3A, prefix=1}}, + {.PINSRB, {.XMM, .RM8, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x20, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PINSRD - {.PINSRD, {.XMM, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x22, 0, {esc=._0F3A, prefix=1}}, + {.PINSRD, {.XMM, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x22, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PINSRQ - {.PINSRQ, {.XMM, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x22, 0, {esc=._0F3A, prefix=1, force_rex_w=true}}, + {.PINSRQ, {.XMM, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x22, 0, {esc=._0F3A, prefix=1, force_rex_w=true, explicit_count=3}}, // .PMAXSB - {.PMAXSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3C, 0, {esc=._0F38, prefix=1}}, + {.PMAXSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3C, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMAXSD - {.PMAXSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3D, 0, {esc=._0F38, prefix=1}}, + {.PMAXSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3D, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMAXUW - {.PMAXUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3E, 0, {esc=._0F38, prefix=1}}, + {.PMAXUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3E, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMAXUD - {.PMAXUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3F, 0, {esc=._0F38, prefix=1}}, + {.PMAXUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3F, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMINSB - {.PMINSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=1}}, + {.PMINSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMINSD - {.PMINSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=1}}, + {.PMINSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMINUW - {.PMINUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3A, 0, {esc=._0F38, prefix=1}}, + {.PMINUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3A, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMINUD - {.PMINUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {esc=._0F38, prefix=1}}, + {.PMINUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVSXBW - {.PMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=1}}, + {.PMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVSXBD - {.PMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=1}}, + {.PMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVSXBQ - {.PMOVSXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=1}}, + {.PMOVSXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVSXWD - {.PMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=1}}, + {.PMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVSXWQ - {.PMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=1}}, + {.PMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVSXDQ - {.PMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=1}}, + {.PMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVZXBW - {.PMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=1}}, + {.PMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVZXBD - {.PMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=1}}, + {.PMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVZXBQ - {.PMOVZXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=1}}, + {.PMOVZXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVZXWD - {.PMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=1}}, + {.PMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVZXWQ - {.PMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=1}}, + {.PMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMOVZXDQ - {.PMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=1}}, + {.PMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMULDQ - {.PMULDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=1}}, + {.PMULDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PMULLD - {.PMULLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F38, prefix=1}}, + {.PMULLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PTEST - {.PTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=1}}, + {.PTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .ROUNDPS - {.ROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1}}, + {.ROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .ROUNDPD - {.ROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1}}, + {.ROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .ROUNDSS - {.ROUNDSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0A, 0, {esc=._0F3A, prefix=1}}, + {.ROUNDSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0A, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .ROUNDSD - {.ROUNDSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0B, 0, {esc=._0F3A, prefix=1}}, + {.ROUNDSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0B, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PCMPEQQ - {.PCMPEQQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=1}}, + {.PCMPEQQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .CRC32 - {.CRC32, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, prefix=3}}, - {.CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=3}}, - {.CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=3}}, - {.CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, prefix=3, force_rex_w=true}}, - {.CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=3, force_rex_w=true}}, + {.CRC32, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, prefix=3, explicit_count=2}}, + {.CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=3, explicit_count=2}}, + {.CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=3, explicit_count=2}}, + {.CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, prefix=3, force_rex_w=true, explicit_count=2}}, + {.CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=3, force_rex_w=true, explicit_count=2}}, // .PCMPESTRI - {.PCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x61, 0, {esc=._0F3A, prefix=1}}, + {.PCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x61, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PCMPESTRM - {.PCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x60, 0, {esc=._0F3A, prefix=1}}, + {.PCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x60, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PCMPISTRI - {.PCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x63, 0, {esc=._0F3A, prefix=1}}, + {.PCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x63, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PCMPISTRM - {.PCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x62, 0, {esc=._0F3A, prefix=1}}, + {.PCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x62, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PCMPGTQ - {.PCMPGTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x37, 0, {esc=._0F38, prefix=1}}, + {.PCMPGTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x37, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .PCLMULQDQ - {.PCLMULQDQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x44, 0, {esc=._0F3A, prefix=1}}, + {.PCLMULQDQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x44, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .AESDEC - {.AESDEC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDE, 0, {esc=._0F38, prefix=1}}, + {.AESDEC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDE, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .AESDECLAST - {.AESDECLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDF, 0, {esc=._0F38, prefix=1}}, + {.AESDECLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDF, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .AESENC - {.AESENC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDC, 0, {esc=._0F38, prefix=1}}, + {.AESENC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDC, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .AESENCLAST - {.AESENCLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDD, 0, {esc=._0F38, prefix=1}}, + {.AESENCLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDD, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .AESIMC - {.AESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F38, prefix=1}}, + {.AESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .AESKEYGENASSIST - {.AESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xDF, 0, {esc=._0F3A, prefix=1}}, + {.AESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xDF, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .SHA1MSG1 - {.SHA1MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC9, 0, {esc=._0F38}}, + {.SHA1MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC9, 0, {esc=._0F38, explicit_count=2}}, // .SHA1MSG2 - {.SHA1MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCA, 0, {esc=._0F38}}, + {.SHA1MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCA, 0, {esc=._0F38, explicit_count=2}}, // .SHA1NEXTE - {.SHA1NEXTE, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC8, 0, {esc=._0F38}}, + {.SHA1NEXTE, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC8, 0, {esc=._0F38, explicit_count=2}}, // .SHA1RNDS4 - {.SHA1RNDS4, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xCC, 0, {esc=._0F3A}}, + {.SHA1RNDS4, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xCC, 0, {esc=._0F3A, explicit_count=3}}, // .SHA256MSG1 - {.SHA256MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCC, 0, {esc=._0F38}}, + {.SHA256MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCC, 0, {esc=._0F38, explicit_count=2}}, // .SHA256MSG2 - {.SHA256MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCD, 0, {esc=._0F38}}, + {.SHA256MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCD, 0, {esc=._0F38, explicit_count=2}}, // .SHA256RNDS2 - {.SHA256RNDS2, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0xCB, 0, {esc=._0F38}}, + {.SHA256RNDS2, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0xCB, 0, {esc=._0F38, explicit_count=2, has_implict=true}}, // .VADDPS - {.VADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VADDPD - {.VADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VADDSS - {.VADDSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VADDSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, // .VADDSD - {.VADDSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, + {.VADDSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=3}}, // .VSUBPS - {.VSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VSUBPD - {.VSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VSUBSS - {.VSUBSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VSUBSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, // .VSUBSD - {.VSUBSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, + {.VSUBSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=3}}, // .VMULPS - {.VMULPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMULPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VMULPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMULPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VMULPD - {.VMULPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMULPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMULPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMULPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VMULSS - {.VMULSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VMULSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, // .VMULSD - {.VMULSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, + {.VMULSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=3}}, // .VDIVPS - {.VDIVPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VDIVPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VDIVPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VDIVPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VDIVPD - {.VDIVPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VDIVPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VDIVPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VDIVPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VDIVSS - {.VDIVSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VDIVSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, // .VDIVSD - {.VDIVSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, + {.VDIVSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=3}}, // .VSQRTPS - {.VSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VSQRTPD - {.VSQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VSQRTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VSQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VSQRTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VSQRTSS - {.VSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x51, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x51, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, // .VSQRTSD - {.VSQRTSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x51, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, + {.VSQRTSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x51, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=3}}, // .VRCPPS - {.VRCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VRCPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VRCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VRCPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VRCPSS - {.VRCPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x53, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VRCPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x53, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, // .VRSQRTPS - {.VRSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VRSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VRSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VRSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VRSQRTSS - {.VRSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x52, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VRSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x52, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, // .VMAXPS - {.VMAXPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMAXPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VMAXPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMAXPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VMAXPD - {.VMAXPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMAXPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMAXPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMAXPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VMAXSS - {.VMAXSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VMAXSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, // .VMAXSD - {.VMAXSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, + {.VMAXSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=3}}, // .VMINPS - {.VMINPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMINPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VMINPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMINPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VMINPD - {.VMINPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMINPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMINPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMINPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VMINSS - {.VMINSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VMINSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, // .VMINSD - {.VMINSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, + {.VMINSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=3}}, // .VANDPS - {.VANDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VANDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VANDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VANDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VANDPD - {.VANDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VANDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VANDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VANDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VANDNPS - {.VANDNPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VANDNPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VANDNPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VANDNPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VANDNPD - {.VANDNPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VANDNPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VANDNPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VANDNPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VORPS - {.VORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VORPD - {.VORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VXORPS - {.VXORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VXORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VXORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VXORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VXORPD - {.VXORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VXORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VXORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VXORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VCMPPS - {.VCMPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VCMPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VCMPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, + {.VCMPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VCMPPD - {.VCMPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VCMPPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VCMPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, + {.VCMPPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VCMPSS - {.VCMPSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VCMPSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=4}}, // .VCMPSD - {.VCMPSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, + {.VCMPSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=4}}, // .VCOMISS - {.VCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, vex_type=.VEX}}, + {.VCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, vex_type=.VEX, explicit_count=2}}, // .VCOMISD - {.VCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, prefix=1, vex_type=.VEX}}, + {.VCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, prefix=1, vex_type=.VEX, explicit_count=2}}, // .VUCOMISS - {.VUCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, vex_type=.VEX}}, + {.VUCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, vex_type=.VEX, explicit_count=2}}, // .VUCOMISD - {.VUCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, prefix=1, vex_type=.VEX}}, + {.VUCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, prefix=1, vex_type=.VEX, explicit_count=2}}, // .VSHUFPS - {.VSHUFPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VSHUFPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VSHUFPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, + {.VSHUFPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VSHUFPD - {.VSHUFPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VSHUFPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VSHUFPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, + {.VSHUFPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VUNPCKLPS - {.VUNPCKLPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VUNPCKLPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VUNPCKLPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VUNPCKLPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VUNPCKHPS - {.VUNPCKHPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VUNPCKHPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VUNPCKHPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VUNPCKHPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VUNPCKLPD - {.VUNPCKLPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VUNPCKLPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VUNPCKLPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VUNPCKLPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VUNPCKHPD - {.VUNPCKHPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VUNPCKHPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VUNPCKHPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VUNPCKHPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VBLENDPS - {.VBLENDPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0C, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VBLENDPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0C, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VBLENDPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0C, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, + {.VBLENDPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0C, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VBLENDPD - {.VBLENDPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0D, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VBLENDPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0D, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VBLENDPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0D, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, + {.VBLENDPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0D, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VBLENDVPS - {.VBLENDVPS, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4A, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VBLENDVPS, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4A, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VBLENDVPS, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4A, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VBLENDVPS, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4A, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, // .VBLENDVPD - {.VBLENDVPD, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4B, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VBLENDVPD, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4B, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VBLENDVPD, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4B, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VBLENDVPD, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4B, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, // .VDPPS - {.VDPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x40, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VDPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x40, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VDPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x40, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, + {.VDPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x40, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VDPPD - {.VDPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x41, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VDPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x41, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, // .VROUNDPS - {.VROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VROUNDPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VROUNDPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VROUNDPD - {.VROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VROUNDPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VROUNDPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VROUNDSS - {.VROUNDSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0A, 0, {esc=._0F3A, prefix=1, vex_type=.VEX}}, + {.VROUNDSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0A, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, explicit_count=4}}, // .VROUNDSD - {.VROUNDSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0B, 0, {esc=._0F3A, prefix=1, vex_type=.VEX}}, + {.VROUNDSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0B, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, explicit_count=4}}, // .VEXTRACTPS - {.VEXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x17, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VEXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x17, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, // .VINSERTPS - {.VINSERTPS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x21, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VINSERTPS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x21, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, // .VMOVAPS - {.VMOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVAPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {.VMOVAPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VMOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVAPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + {.VMOVAPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VMOVUPS - {.VMOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVUPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {.VMOVUPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VMOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVUPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + {.VMOVUPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VMOVAPD - {.VMOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVAPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VMOVAPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVAPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + {.VMOVAPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VMOVUPD - {.VMOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVUPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VMOVUPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVUPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + {.VMOVUPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VMOVSS - {.VMOVSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, - {.VMOVSS, {.M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, - {.VMOVSS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VMOVSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=2}}, + {.VMOVSS, {.M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=2}}, + {.VMOVSS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, // .VMOVSD - {.VMOVSD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, - {.VMOVSD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, - {.VMOVSD, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, + {.VMOVSD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=2}}, + {.VMOVSD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=2}}, + {.VMOVSD, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=3}}, // .VMOVDQA - {.VMOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVDQA, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VMOVDQA, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVDQA, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + {.VMOVDQA, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VMOVDQU - {.VMOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {.VMOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {.VMOVDQU, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}}, - {.VMOVDQU, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}}, + {.VMOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVDQU, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + {.VMOVDQU, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VMOVQ - {.VMOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {.VMOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xD6, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VMOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.VMOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xD6, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VMOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, // .VMOVD - {.VMOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VMOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, // .VMOVLPS - {.VMOVLPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, + {.VMOVLPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, // .VMOVHPS - {.VMOVHPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, + {.VMOVHPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, // .VMOVLPD - {.VMOVLPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VMOVLPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, // .VMOVHPD - {.VMOVHPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VMOVHPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, // .VMOVLHPS - {.VMOVLHPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, + {.VMOVLHPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, // .VMOVHLPS - {.VMOVHLPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, + {.VMOVHLPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, // .VMOVMSKPS - {.VMOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVMSKPS, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VMOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVMSKPS, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VMOVMSKPD - {.VMOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVMSKPD, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVMSKPD, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VMOVNTPS - {.VMOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVNTPS, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VMOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVNTPS, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VMOVNTPD - {.VMOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVNTPD, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVNTPD, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VMOVNTDQ - {.VMOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVNTDQ, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVNTDQ, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VMOVNTDQA - {.VMOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMOVNTDQA, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VMOVNTDQA, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VCVTPS2PD - {.VCVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPS2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VCVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VCVTPS2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VCVTPD2PS - {.VCVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPD2PS, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VCVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VCVTPD2PS, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VCVTSS2SD - {.VCVTSS2SD, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5A, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, + {.VCVTSS2SD, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5A, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, // .VCVTSD2SS - {.VCVTSD2SS, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5A, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, + {.VCVTSD2SS, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5A, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=3}}, // .VCVTPS2DQ - {.VCVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VCVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VCVTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VCVTPD2DQ - {.VCVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1}}, + {.VCVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VCVTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VCVTDQ2PS - {.VCVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VCVTDQ2PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {.VCVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VCVTDQ2PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VCVTDQ2PD - {.VCVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {.VCVTDQ2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}}, + {.VCVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VCVTDQ2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VCVTSS2SI - {.VCVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, - {.VCVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}}, + {.VCVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=2}}, + {.VCVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, explicit_count=2}}, // .VCVTSD2SI - {.VCVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, - {.VCVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}}, + {.VCVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=2}}, + {.VCVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, explicit_count=2}}, // .VCVTSI2SS - {.VCVTSI2SS, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, - {.VCVTSI2SS, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}}, + {.VCVTSI2SS, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=3}}, + {.VCVTSI2SS, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VCVTSI2SD - {.VCVTSI2SD, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, - {.VCVTSI2SD, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}}, + {.VCVTSI2SD, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=3}}, + {.VCVTSI2SD, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VCVTTPS2DQ - {.VCVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {.VCVTTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}}, + {.VCVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VCVTTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VCVTTPD2DQ - {.VCVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VCVTTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VCVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VCVTTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VCVTTSS2SI - {.VCVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=2, vex_type=.VEX}}, - {.VCVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}}, + {.VCVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=2, vex_type=.VEX, explicit_count=2}}, + {.VCVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, explicit_count=2}}, // .VCVTTSD2SI - {.VCVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=3, vex_type=.VEX}}, - {.VCVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}}, + {.VCVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=3, vex_type=.VEX, explicit_count=2}}, + {.VCVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, explicit_count=2}}, // .VPADDB - {.VPADDB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFC, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPADDB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFC, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPADDB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFC, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPADDB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFC, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPADDW - {.VPADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFD, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFD, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFD, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFD, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPADDD - {.VPADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFE, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFE, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFE, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFE, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPADDQ - {.VPADDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPADDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPADDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPADDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPSUBB - {.VPSUBB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF8, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSUBB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF8, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPSUBB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF8, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSUBB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF8, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPSUBW - {.VPSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF9, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF9, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF9, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF9, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPSUBD - {.VPSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFA, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFA, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFA, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFA, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPSUBQ - {.VPSUBQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSUBQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPSUBQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSUBQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMULLW - {.VPMULLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMULLW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMULLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMULLW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMULHW - {.VPMULHW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMULHW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMULHW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMULHW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMULHUW - {.VPMULHUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMULHUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMULHUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMULHUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMULUDQ - {.VPMULUDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMULUDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMULUDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMULUDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMADDWD - {.VPMADDWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMADDWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMADDWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMADDWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPAND - {.VPAND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPAND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPAND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPAND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPANDN - {.VPANDN, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPANDN, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPANDN, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPANDN, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPOR - {.VPOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEB, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPXOR - {.VPXOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEF, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPXOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEF, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPXOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEF, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPXOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEF, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPSLLW - {.VPSLLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSLLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {.VPSLLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VPSLLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, + {.VPSLLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSLLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, explicit_count=3}}, + {.VPSLLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + {.VPSLLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, explicit_count=3}}, // .VPSLLD - {.VPSLLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSLLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {.VPSLLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VPSLLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, + {.VPSLLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSLLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, explicit_count=3}}, + {.VPSLLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + {.VPSLLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, explicit_count=3}}, // .VPSLLQ - {.VPSLLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF3, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSLLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {.VPSLLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF3, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VPSLLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, + {.VPSLLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF3, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSLLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, explicit_count=3}}, + {.VPSLLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF3, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + {.VPSLLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 6, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, explicit_count=3}}, // .VPSRLW - {.VPSRLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSRLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {.VPSRLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VPSRLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, + {.VPSRLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSRLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, explicit_count=3}}, + {.VPSRLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + {.VPSRLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, explicit_count=3}}, // .VPSRLD - {.VPSRLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSRLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {.VPSRLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VPSRLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, + {.VPSRLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSRLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, explicit_count=3}}, + {.VPSRLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + {.VPSRLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, explicit_count=3}}, // .VPSRLQ - {.VPSRLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD3, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSRLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {.VPSRLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD3, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VPSRLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, + {.VPSRLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD3, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSRLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, explicit_count=3}}, + {.VPSRLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD3, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + {.VPSRLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 2, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, explicit_count=3}}, // .VPSRAW - {.VPSRAW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSRAW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 4, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {.VPSRAW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VPSRAW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 4, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, + {.VPSRAW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSRAW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 4, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, explicit_count=3}}, + {.VPSRAW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE1, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + {.VPSRAW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 4, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, explicit_count=3}}, // .VPSRAD - {.VPSRAD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSRAD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 4, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {.VPSRAD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VPSRAD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 4, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, + {.VPSRAD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSRAD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 4, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, explicit_count=3}}, + {.VPSRAD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE2, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + {.VPSRAD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 4, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, explicit_count=3}}, // .VPCMPEQB - {.VPCMPEQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x74, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPEQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x74, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPCMPEQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x74, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPCMPEQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x74, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPCMPEQW - {.VPCMPEQW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPEQW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPCMPEQW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPCMPEQW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPCMPEQD - {.VPCMPEQD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPEQD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPCMPEQD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPCMPEQD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPCMPEQQ - {.VPCMPEQQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x29, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPEQQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x29, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPCMPEQQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x29, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPCMPEQQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x29, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPCMPGTB - {.VPCMPGTB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPGTB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPCMPGTB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPCMPGTB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPCMPGTW - {.VPCMPGTW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPGTW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPCMPGTW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPCMPGTW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPCMPGTD - {.VPCMPGTD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPGTD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPCMPGTD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPCMPGTD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPCMPGTQ - {.VPCMPGTQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x37, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPGTQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x37, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPCMPGTQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x37, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPCMPGTQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x37, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPACKSSWB - {.VPACKSSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x63, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPACKSSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x63, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPACKSSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x63, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPACKSSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x63, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPACKSSDW - {.VPACKSSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPACKSSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPACKSSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPACKSSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPACKUSWB - {.VPACKUSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x67, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPACKUSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x67, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPACKUSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x67, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPACKUSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x67, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPACKUSDW - {.VPACKUSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPACKUSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPACKUSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPACKUSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPUNPCKLBW - {.VPUNPCKLBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x60, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKLBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x60, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPUNPCKLBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x60, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPUNPCKLBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x60, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPUNPCKLWD - {.VPUNPCKLWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x61, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKLWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x61, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPUNPCKLWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x61, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPUNPCKLWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x61, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPUNPCKLDQ - {.VPUNPCKLDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x62, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKLDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x62, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPUNPCKLDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x62, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPUNPCKLDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x62, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPUNPCKLQDQ - {.VPUNPCKLQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6C, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKLQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6C, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPUNPCKLQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6C, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPUNPCKLQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6C, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPUNPCKHBW - {.VPUNPCKHBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x68, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKHBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x68, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPUNPCKHBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x68, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPUNPCKHBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x68, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPUNPCKHWD - {.VPUNPCKHWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x69, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKHWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x69, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPUNPCKHWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x69, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPUNPCKHWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x69, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPUNPCKHDQ - {.VPUNPCKHDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKHDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPUNPCKHDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPUNPCKHDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPUNPCKHQDQ - {.VPUNPCKHQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6D, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKHQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6D, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPUNPCKHQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6D, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPUNPCKHQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6D, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPSHUFD - {.VPSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSHUFD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSHUFD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPSHUFHW - {.VPSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {.VPSHUFHW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}}, + {.VPSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSHUFHW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPSHUFLW - {.VPSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0}}, - {.VPSHUFLW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1}}, + {.VPSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSHUFLW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPEXTRB - {.VPEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x14, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VPEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x14, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, // .VPEXTRW - {.VPEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPEXTRW, {.RM16, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x15, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VPEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPEXTRW, {.RM16, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x15, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, // .VPEXTRD - {.VPEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VPEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, // .VPEXTRQ - {.VPEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.VPEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .VPINSRB - {.VPINSRB, {.XMM, .XMM, .RM8, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x20, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VPINSRB, {.XMM, .XMM, .RM8, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x20, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, // .VPINSRW - {.VPINSRW, {.XMM, .XMM, .RM16, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VPINSRW, {.XMM, .XMM, .RM16, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC4, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, // .VPINSRD - {.VPINSRD, {.XMM, .XMM, .RM32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x22, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VPINSRD, {.XMM, .XMM, .RM32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x22, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, // .VPINSRQ - {.VPINSRQ, {.XMM, .XMM, .RM64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x22, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.VPINSRQ, {.XMM, .XMM, .RM64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x22, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=4}}, // .VPMOVMSKB - {.VPMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVMSKB, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVMSKB, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPTEST - {.VPTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPTEST, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPTEST, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPSHUFB - {.VPSHUFB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x00, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSHUFB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x00, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPSHUFB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x00, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSHUFB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x00, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPHADDW - {.VPHADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x01, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPHADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x01, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPHADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x01, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPHADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x01, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPHADDD - {.VPHADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x02, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPHADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x02, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPHADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x02, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPHADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x02, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPHADDSW - {.VPHADDSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x03, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPHADDSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x03, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPHADDSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x03, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPHADDSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x03, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPHSUBW - {.VPHSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x05, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPHSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x05, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPHSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x05, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPHSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x05, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPHSUBD - {.VPHSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x06, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPHSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x06, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPHSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x06, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPHSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x06, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPHSUBSW - {.VPHSUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x07, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPHSUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x07, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPHSUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x07, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPHSUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x07, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMADDUBSW - {.VPMADDUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x04, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMADDUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x04, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMADDUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x04, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMADDUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x04, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMULHRSW - {.VPMULHRSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMULHRSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMULHRSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMULHRSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPSIGNB - {.VPSIGNB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x08, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSIGNB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x08, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPSIGNB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x08, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSIGNB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x08, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPSIGNW - {.VPSIGNW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x09, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSIGNW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x09, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPSIGNW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x09, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSIGNW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x09, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPSIGND - {.VPSIGND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPSIGND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPSIGND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPSIGND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPABSB - {.VPABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPABSB, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPABSB, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPABSW - {.VPABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPABSW, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPABSW, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPABSD - {.VPABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPABSD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPABSD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPALIGNR - {.VPALIGNR, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0F, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPALIGNR, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0F, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPALIGNR, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0F, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, + {.VPALIGNR, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0F, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VPBLENDW - {.VPBLENDW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0E, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPBLENDW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0E, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPBLENDW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0E, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, + {.VPBLENDW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0E, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VPBLENDVB - {.VPBLENDVB, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4C, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VPBLENDVB, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4C, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VPBLENDVB, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4C, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VPBLENDVB, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4C, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, // .VMPSADBW - {.VMPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, + {.VMPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VPHMINPOSUW - {.VPHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VPHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, // .VPMAXSB - {.VPMAXSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMAXSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMAXSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMAXSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMAXSD - {.VPMAXSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMAXSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMAXSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMAXSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMAXUW - {.VPMAXUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMAXUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMAXUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMAXUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMAXUD - {.VPMAXUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMAXUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMAXUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMAXUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMINSB - {.VPMINSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x38, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMINSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x38, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMINSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x38, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMINSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x38, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMINSD - {.VPMINSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x39, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMINSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x39, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMINSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x39, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMINSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x39, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMINUW - {.VPMINUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMINUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMINUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMINUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMINUD - {.VPMINUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMINUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMINUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMINUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMOVSXBW - {.VPMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVSXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMOVSXBD - {.VPMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVSXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMOVSXBQ - {.VPMOVSXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVSXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVSXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMOVSXWD - {.VPMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVSXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMOVSXWQ - {.VPMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVSXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMOVSXDQ - {.VPMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVSXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMOVZXBW - {.VPMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVZXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMOVZXBD - {.VPMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVZXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMOVZXBQ - {.VPMOVZXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVZXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVZXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMOVZXWD - {.VPMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVZXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMOVZXWQ - {.VPMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVZXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMOVZXDQ - {.VPMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VPMOVZXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VPMULDQ - {.VPMULDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x28, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMULDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x28, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMULDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x28, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMULDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x28, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VPMULLD - {.VPMULLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x40, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPMULLD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x40, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPMULLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x40, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VPMULLD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x40, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VMASKMOVDQU - {.VMASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF7, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VMASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF7, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, // .VPCLMULQDQ - {.VPCLMULQDQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x44, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VPCLMULQDQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x44, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPCLMULQDQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x44, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=4}}, + {.VPCLMULQDQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x44, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VAESDEC - {.VAESDEC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VAESDEC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, // .VAESDECLAST - {.VAESDECLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VAESDECLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, // .VAESENC - {.VAESENC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VAESENC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, // .VAESENCLAST - {.VAESENCLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDD, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VAESENCLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDD, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, // .VAESIMC - {.VAESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VAESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, // .VAESKEYGENASSIST - {.VAESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xDF, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, + {.VAESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xDF, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, // .VBROADCASTSS - {.VBROADCASTSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VBROADCASTSS, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VBROADCASTSS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VBROADCASTSS, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VBROADCASTSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VBROADCASTSS, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + {.VBROADCASTSS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VBROADCASTSS, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VBROADCASTSD - {.VBROADCASTSD, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x19, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VBROADCASTSD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x19, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VBROADCASTSD, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x19, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + {.VBROADCASTSD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x19, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VBROADCASTF128 - {.VBROADCASTF128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VBROADCASTF128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VEXTRACTF128 - {.VEXTRACTF128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x19, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VEXTRACTF128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x19, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VINSERTF128 - {.VINSERTF128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x18, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VINSERTF128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x18, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VPERM2F128 - {.VPERM2F128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x06, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPERM2F128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x06, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VMASKMOVPS - {.VMASKMOVPS, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMASKMOVPS, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VMASKMOVPS, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMASKMOVPS, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMASKMOVPS, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMASKMOVPS, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + {.VMASKMOVPS, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMASKMOVPS, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VMASKMOVPD - {.VMASKMOVPD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMASKMOVPD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VMASKMOVPD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VMASKMOVPD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VMASKMOVPD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMASKMOVPD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + {.VMASKMOVPD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VMASKMOVPD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VTESTPS - {.VTESTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VTESTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VTESTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VTESTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VTESTPD - {.VTESTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VTESTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VTESTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VTESTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VZEROALL {.VZEROALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x77, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, // .VZEROUPPER {.VZEROUPPER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x77, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, // .VBROADCASTI128 - {.VBROADCASTI128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VBROADCASTI128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, // .VEXTRACTI128 - {.VEXTRACTI128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x39, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VEXTRACTI128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x39, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, // .VINSERTI128 - {.VINSERTI128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x38, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VINSERTI128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x38, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VPERM2I128 - {.VPERM2I128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x46, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, + {.VPERM2I128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x46, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=4}}, // .VPERMD - {.VPERMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x36, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VPERMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x36, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VPERMPS - {.VPERMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VPERMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VPERMQ - {.VPERMQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x00, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VPERMQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x00, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VPERMPD - {.VPERMPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x01, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VPERMPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x01, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VPBLENDD - {.VPBLENDD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x02, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VPBLENDD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x02, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VPBLENDD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x02, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VPBLENDD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x02, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, // .VPSLLVD - {.VPSLLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VPSLLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VPSLLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPSLLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VPSLLVQ - {.VPSLLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VPSLLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VPSLLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPSLLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VPSRLVD - {.VPSRLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VPSRLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VPSRLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPSRLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VPSRLVQ - {.VPSRLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VPSRLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VPSRLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPSRLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VPSRAVD - {.VPSRAVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VPSRAVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VPSRAVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPSRAVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VPMASKMOVD - {.VPMASKMOVD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VPMASKMOVD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {.VPMASKMOVD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VPMASKMOVD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VPMASKMOVD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPMASKMOVD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPMASKMOVD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPMASKMOVD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VPMASKMOVQ - {.VPMASKMOVQ, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VPMASKMOVQ, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {.VPMASKMOVQ, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VPMASKMOVQ, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VPMASKMOVQ, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPMASKMOVQ, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPMASKMOVQ, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPMASKMOVQ, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VGATHERDPS - {.VGATHERDPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VGATHERDPS, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VGATHERDPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VGATHERDPS, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VGATHERDPD - {.VGATHERDPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VGATHERDPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VGATHERDPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VGATHERDPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VGATHERQPS - {.VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VGATHERQPD - {.VGATHERQPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VGATHERQPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VGATHERQPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VGATHERQPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VPGATHERDD - {.VPGATHERDD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VPGATHERDD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VPGATHERDD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPGATHERDD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VPGATHERDQ - {.VPGATHERDQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VPGATHERDQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VPGATHERDQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPGATHERDQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VPGATHERQD - {.VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VPGATHERQQ - {.VPGATHERQQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VPGATHERQQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VPGATHERQQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPGATHERQQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMADD132PS - {.VFMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMADD213PS - {.VFMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMADD231PS - {.VFMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMADD132PD - {.VFMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMADD213PD - {.VFMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMADD231PD - {.VFMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMADD132SS - {.VFMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x99, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x99, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFMADD213SS - {.VFMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA9, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA9, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFMADD231SS - {.VFMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB9, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB9, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFMADD132SD - {.VFMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x99, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x99, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFMADD213SD - {.VFMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA9, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA9, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFMADD231SD - {.VFMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB9, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB9, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFMSUB132PS - {.VFMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMSUB213PS - {.VFMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMSUB231PS - {.VFMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMSUB132PD - {.VFMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMSUB213PD - {.VFMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMSUB231PD - {.VFMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMSUB132SS - {.VFMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFMSUB213SS - {.VFMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAB, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAB, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFMSUB231SS - {.VFMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBB, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBB, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFMSUB132SD - {.VFMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9B, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFMSUB213SD - {.VFMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAB, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAB, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFMSUB231SD - {.VFMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBB, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBB, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFNMADD132PS - {.VFNMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFNMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFNMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFNMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFNMADD213PS - {.VFNMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFNMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFNMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFNMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFNMADD231PS - {.VFNMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFNMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFNMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFNMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFNMADD132PD - {.VFNMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFNMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFNMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFNMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFNMADD213PD - {.VFNMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFNMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFNMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFNMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFNMADD231PD - {.VFNMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFNMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFNMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFNMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFNMADD132SS - {.VFNMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFNMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFNMADD213SS - {.VFNMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAD, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFNMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAD, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFNMADD231SS - {.VFNMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBD, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFNMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBD, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFNMADD132SD - {.VFNMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFNMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9D, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFNMADD213SD - {.VFNMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAD, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFNMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAD, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFNMADD231SD - {.VFNMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBD, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFNMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBD, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFNMSUB132PS - {.VFNMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFNMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFNMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFNMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFNMSUB213PS - {.VFNMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFNMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFNMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFNMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFNMSUB231PS - {.VFNMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFNMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFNMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFNMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFNMSUB132PD - {.VFNMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFNMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFNMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFNMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFNMSUB213PD - {.VFNMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFNMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFNMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFNMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFNMSUB231PD - {.VFNMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFNMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFNMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFNMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFNMSUB132SS - {.VFNMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFNMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFNMSUB213SS - {.VFNMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAF, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFNMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAF, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFNMSUB231SS - {.VFNMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBF, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, + {.VFNMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBF, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, explicit_count=3}}, // .VFNMSUB132SD - {.VFNMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFNMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9F, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFNMSUB213SD - {.VFNMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAF, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFNMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAF, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFNMSUB231SD - {.VFNMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBF, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, + {.VFNMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBF, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, explicit_count=3}}, // .VFMADDSUB132PS - {.VFMADDSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMADDSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMADDSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMADDSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMADDSUB213PS - {.VFMADDSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMADDSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMADDSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMADDSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMADDSUB231PS - {.VFMADDSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMADDSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMADDSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMADDSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMADDSUB132PD - {.VFMADDSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMADDSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMADDSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMADDSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMADDSUB213PD - {.VFMADDSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMADDSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMADDSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMADDSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMADDSUB231PD - {.VFMADDSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMADDSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMADDSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMADDSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMSUBADD132PS - {.VFMSUBADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMSUBADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMSUBADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMSUBADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMSUBADD213PS - {.VFMSUBADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMSUBADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMSUBADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMSUBADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMSUBADD231PS - {.VFMSUBADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.VFMSUBADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.VFMSUBADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFMSUBADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .VFMSUBADD132PD - {.VFMSUBADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMSUBADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMSUBADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMSUBADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMSUBADD213PD - {.VFMSUBADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMSUBADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMSUBADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMSUBADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VFMSUBADD231PD - {.VFMSUBADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.VFMSUBADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.VFMSUBADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFMSUBADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .VCVTPH2PS - {.VCVTPH2PS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPH2PS, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VCVTPH2PS, {.ZMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_l=.L2}}, + {.VCVTPH2PS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=2}}, + {.VCVTPH2PS, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=2}}, + {.VCVTPH2PS, {.ZMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_l=.L2, explicit_count=2}}, // .VCVTPS2PH - {.VCVTPS2PH, {.XMM_M64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPS2PH, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {.VCVTPS2PH, {.YMM_M256, .ZMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_l=.L2}}, + {.VCVTPS2PH, {.XMM_M64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, + {.VCVTPS2PH, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, + {.VCVTPS2PH, {.YMM_M256, .ZMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_l=.L2, explicit_count=3}}, // .VMOVDQA32 - {.VMOVDQA32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VMOVDQA32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VMOVDQA32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VMOVDQA32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VMOVDQA32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {.VMOVDQA32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VMOVDQA32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VMOVDQA32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VMOVDQA32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VMOVDQA32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VMOVDQA32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, + {.VMOVDQA32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VMOVDQA64 - {.VMOVDQA64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VMOVDQA64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VMOVDQA64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VMOVDQA64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VMOVDQA64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {.VMOVDQA64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VMOVDQA64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VMOVDQA64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VMOVDQA64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VMOVDQA64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VMOVDQA64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, + {.VMOVDQA64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VMOVDQU8 - {.VMOVDQU8, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VMOVDQU8, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VMOVDQU8, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VMOVDQU8, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VMOVDQU8, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {.VMOVDQU8, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VMOVDQU8, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VMOVDQU8, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VMOVDQU8, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VMOVDQU8, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VMOVDQU8, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, + {.VMOVDQU8, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VMOVDQU16 - {.VMOVDQU16, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VMOVDQU16, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VMOVDQU16, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VMOVDQU16, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VMOVDQU16, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {.VMOVDQU16, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VMOVDQU16, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VMOVDQU16, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VMOVDQU16, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VMOVDQU16, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VMOVDQU16, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, + {.VMOVDQU16, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VMOVDQU32 - {.VMOVDQU32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VMOVDQU32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VMOVDQU32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VMOVDQU32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VMOVDQU32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {.VMOVDQU32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VMOVDQU32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VMOVDQU32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VMOVDQU32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VMOVDQU32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VMOVDQU32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, + {.VMOVDQU32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VMOVDQU64 - {.VMOVDQU64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VMOVDQU64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VMOVDQU64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VMOVDQU64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VMOVDQU64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {.VMOVDQU64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VMOVDQU64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VMOVDQU64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VMOVDQU64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VMOVDQU64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VMOVDQU64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, + {.VMOVDQU64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VPBLENDMB - {.VPBLENDMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPBLENDMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPBLENDMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPBLENDMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPBLENDMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPBLENDMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPBLENDMW - {.VPBLENDMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPBLENDMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPBLENDMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPBLENDMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPBLENDMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPBLENDMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPBLENDMD - {.VPBLENDMD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPBLENDMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPBLENDMD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPBLENDMD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPBLENDMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPBLENDMD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPBLENDMQ - {.VPBLENDMQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPBLENDMQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPBLENDMQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPBLENDMQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPBLENDMQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPBLENDMQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VBLENDMPS - {.VBLENDMPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VBLENDMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VBLENDMPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VBLENDMPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VBLENDMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VBLENDMPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VBLENDMPD - {.VBLENDMPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VBLENDMPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VBLENDMPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VBLENDMPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VBLENDMPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VBLENDMPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPCMPB - {.VPCMPB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPCMPB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPCMPB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPCMPB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VPCMPB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, + {.VPCMPB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=4}}, // .VPCMPUB - {.VPCMPUB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPCMPUB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPCMPUB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPCMPUB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VPCMPUB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, + {.VPCMPUB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=4}}, // .VPCMPW - {.VPCMPW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPCMPW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPCMPW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPCMPW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=4}}, + {.VPCMPW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=4}}, + {.VPCMPW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=4}}, // .VPCMPUW - {.VPCMPUW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPCMPUW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPCMPUW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPCMPUW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=4}}, + {.VPCMPUW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=4}}, + {.VPCMPUW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=4}}, // .VPCMPD - {.VPCMPD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPCMPD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPCMPD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPCMPD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VPCMPD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, + {.VPCMPD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=4}}, // .VPCMPUD - {.VPCMPUD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPCMPUD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPCMPUD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPCMPUD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VPCMPUD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, + {.VPCMPUD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=4}}, // .VPCMPQ - {.VPCMPQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPCMPQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPCMPQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPCMPQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=4}}, + {.VPCMPQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=4}}, + {.VPCMPQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=4}}, // .VPCMPUQ - {.VPCMPUQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPCMPUQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPCMPUQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPCMPUQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=4}}, + {.VPCMPUQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=4}}, + {.VPCMPUQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=4}}, // .VPTESTMB - {.VPTESTMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPTESTMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPTESTMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPTESTMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPTESTMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPTESTMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPTESTMW - {.VPTESTMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPTESTMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPTESTMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPTESTMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPTESTMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPTESTMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPTESTMD - {.VPTESTMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPTESTMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPTESTMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPTESTMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPTESTMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPTESTMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPTESTMQ - {.VPTESTMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPTESTMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPTESTMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPTESTMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPTESTMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPTESTMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPTESTNMB - {.VPTESTNMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPTESTNMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPTESTNMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPTESTNMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPTESTNMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPTESTNMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPTESTNMW - {.VPTESTNMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPTESTNMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPTESTNMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPTESTNMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPTESTNMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPTESTNMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPTESTNMD - {.VPTESTNMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPTESTNMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPTESTNMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPTESTNMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPTESTNMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPTESTNMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPTESTNMQ - {.VPTESTNMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPTESTNMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPTESTNMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPTESTNMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPTESTNMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPTESTNMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPCOMPRESSD - {.VPCOMPRESSD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPCOMPRESSD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPCOMPRESSD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPCOMPRESSD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPCOMPRESSD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPCOMPRESSD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPCOMPRESSQ - {.VPCOMPRESSQ, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPCOMPRESSQ, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPCOMPRESSQ, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPCOMPRESSQ, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VPCOMPRESSQ, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VPCOMPRESSQ, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VCOMPRESSPS - {.VCOMPRESSPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VCOMPRESSPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VCOMPRESSPS, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VCOMPRESSPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VCOMPRESSPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VCOMPRESSPS, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VCOMPRESSPD - {.VCOMPRESSPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VCOMPRESSPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VCOMPRESSPD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VCOMPRESSPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VCOMPRESSPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VCOMPRESSPD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VPEXPANDD - {.VPEXPANDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPEXPANDD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPEXPANDD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPEXPANDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPEXPANDD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPEXPANDD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPEXPANDQ - {.VPEXPANDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPEXPANDQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPEXPANDQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPEXPANDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VPEXPANDQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VPEXPANDQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VEXPANDPS - {.VEXPANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VEXPANDPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VEXPANDPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VEXPANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VEXPANDPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VEXPANDPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VEXPANDPD - {.VEXPANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VEXPANDPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VEXPANDPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VEXPANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VEXPANDPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VEXPANDPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VPCONFLICTD - {.VPCONFLICTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPCONFLICTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPCONFLICTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPCONFLICTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPCONFLICTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPCONFLICTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPCONFLICTQ - {.VPCONFLICTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPCONFLICTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPCONFLICTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPCONFLICTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VPCONFLICTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VPCONFLICTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VPLZCNTD - {.VPLZCNTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPLZCNTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPLZCNTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPLZCNTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPLZCNTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPLZCNTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPLZCNTQ - {.VPLZCNTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPLZCNTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPLZCNTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPLZCNTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VPLZCNTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VPLZCNTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VPERMI2B - {.VPERMI2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPERMI2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPERMI2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPERMI2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPERMI2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPERMI2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPERMI2W - {.VPERMI2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPERMI2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPERMI2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPERMI2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPERMI2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPERMI2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPERMI2D - {.VPERMI2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPERMI2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPERMI2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPERMI2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPERMI2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPERMI2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPERMI2Q - {.VPERMI2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPERMI2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPERMI2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPERMI2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPERMI2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPERMI2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPERMI2PS - {.VPERMI2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPERMI2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPERMI2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPERMI2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPERMI2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPERMI2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPERMI2PD - {.VPERMI2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPERMI2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPERMI2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPERMI2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPERMI2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPERMI2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPERMT2B - {.VPERMT2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPERMT2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPERMT2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPERMT2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPERMT2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPERMT2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPERMT2W - {.VPERMT2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPERMT2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPERMT2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPERMT2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPERMT2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPERMT2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPERMT2D - {.VPERMT2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPERMT2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPERMT2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPERMT2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPERMT2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPERMT2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPERMT2Q - {.VPERMT2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPERMT2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPERMT2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPERMT2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPERMT2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPERMT2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPERMT2PS - {.VPERMT2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPERMT2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPERMT2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPERMT2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPERMT2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPERMT2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPERMT2PD - {.VPERMT2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPERMT2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPERMT2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPERMT2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPERMT2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPERMT2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPERMB - {.VPERMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPERMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPERMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPERMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPERMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPERMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPERMW - {.VPERMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPERMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPERMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPERMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPERMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPERMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPMOVB2M - {.VPMOVB2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVB2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVB2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVB2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVB2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVB2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVW2M - {.VPMOVW2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPMOVW2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPMOVW2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPMOVW2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VPMOVW2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VPMOVW2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VPMOVD2M - {.VPMOVD2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVD2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVD2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVD2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVD2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVD2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVQ2M - {.VPMOVQ2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPMOVQ2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPMOVQ2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPMOVQ2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VPMOVQ2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VPMOVQ2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VPMOVM2B - {.VPMOVM2B, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVM2B, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVM2B, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVM2B, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVM2B, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVM2B, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVM2W - {.VPMOVM2W, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPMOVM2W, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPMOVM2W, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPMOVM2W, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VPMOVM2W, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VPMOVM2W, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VPMOVM2D - {.VPMOVM2D, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVM2D, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVM2D, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVM2D, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVM2D, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVM2D, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVM2Q - {.VPMOVM2Q, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPMOVM2Q, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPMOVM2Q, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPMOVM2Q, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VPMOVM2Q, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VPMOVM2Q, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VPMOVQB - {.VPMOVQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVSQB - {.VPMOVSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVUSQB - {.VPMOVUSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVUSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVUSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVUSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVUSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVUSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVQW - {.VPMOVQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVSQW - {.VPMOVSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVUSQW - {.VPMOVUSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVUSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVUSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVUSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVUSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVUSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVQD - {.VPMOVQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVSQD - {.VPMOVSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVUSQD - {.VPMOVUSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVUSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVUSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVUSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVUSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVUSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVDB - {.VPMOVDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVSDB - {.VPMOVSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVUSDB - {.VPMOVUSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVUSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVUSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVUSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVUSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVUSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVDW - {.VPMOVDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVSDW - {.VPMOVSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVUSDW - {.VPMOVUSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVUSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVUSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVUSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVUSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVUSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVWB - {.VPMOVWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVSWB - {.VPMOVSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPMOVUSWB - {.VPMOVUSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPMOVUSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPMOVUSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPMOVUSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPMOVUSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPMOVUSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPROLD - {.VPROLD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, - {.VPROLD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, modrm_reg_ext=true}}, - {.VPROLD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, modrm_reg_ext=true}}, + {.VPROLD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, explicit_count=3}}, + {.VPROLD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, modrm_reg_ext=true, explicit_count=3}}, + {.VPROLD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, modrm_reg_ext=true, explicit_count=3}}, // .VPROLQ - {.VPROLQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, - {.VPROLQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, modrm_reg_ext=true}}, - {.VPROLQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, modrm_reg_ext=true}}, + {.VPROLQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, explicit_count=3}}, + {.VPROLQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, modrm_reg_ext=true, explicit_count=3}}, + {.VPROLQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, modrm_reg_ext=true, explicit_count=3}}, // .VPROLVD - {.VPROLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPROLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPROLVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPROLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPROLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPROLVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPROLVQ - {.VPROLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPROLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPROLVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPROLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPROLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPROLVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPRORD - {.VPRORD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPRORD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPRORD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPRORD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPRORD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPRORD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPRORQ - {.VPRORQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPRORQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPRORQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPRORQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPRORQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPRORQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPRORVD - {.VPRORVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPRORVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPRORVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPRORVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VPRORVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VPRORVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VPRORVQ - {.VPRORVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPRORVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPRORVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPRORVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPRORVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPRORVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPSCATTERDD - {.VPSCATTERDD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPSCATTERDD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPSCATTERDD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPSCATTERDD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPSCATTERDD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPSCATTERDD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPSCATTERDQ - {.VPSCATTERDQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPSCATTERDQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPSCATTERDQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPSCATTERDQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VPSCATTERDQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VPSCATTERDQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VPSCATTERQD - {.VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPSCATTERQD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VPSCATTERQD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VPSCATTERQQ - {.VPSCATTERQQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPSCATTERQQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPSCATTERQQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPSCATTERQQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VPSCATTERQQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VPSCATTERQQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VSCATTERDPS - {.VSCATTERDPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VSCATTERDPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VSCATTERDPS, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VSCATTERDPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VSCATTERDPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VSCATTERDPS, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VSCATTERDPD - {.VSCATTERDPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VSCATTERDPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VSCATTERDPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VSCATTERDPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VSCATTERDPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VSCATTERDPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VSCATTERQPS - {.VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VSCATTERQPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VSCATTERQPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VSCATTERQPD - {.VSCATTERQPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VSCATTERQPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VSCATTERQPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VSCATTERQPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VSCATTERQPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VSCATTERQPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VPSRAVQ - {.VPSRAVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPSRAVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPSRAVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPSRAVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPSRAVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPSRAVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPSRAVW - {.VPSRAVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPSRAVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPSRAVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPSRAVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPSRAVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPSRAVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPSLLVW - {.VPSLLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPSLLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPSLLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPSLLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPSLLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPSLLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VPSRLVW - {.VPSRLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPSRLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPSRLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPSRLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPSRLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPSRLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VRANGEPS - {.VRANGEPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VRANGEPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VRANGEPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VRANGEPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VRANGEPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, + {.VRANGEPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=4}}, // .VRANGEPD - {.VRANGEPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VRANGEPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VRANGEPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VRANGEPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=4}}, + {.VRANGEPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=4}}, + {.VRANGEPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=4}}, // .VRANGESS - {.VRANGESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x51, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, + {.VRANGESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x51, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, explicit_count=4}}, // .VRANGESD - {.VRANGESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x51, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, + {.VRANGESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x51, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, explicit_count=4}}, // .VREDUCEPS - {.VREDUCEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VREDUCEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VREDUCEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VREDUCEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VREDUCEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VREDUCEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VREDUCEPD - {.VREDUCEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VREDUCEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VREDUCEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VREDUCEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VREDUCEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VREDUCEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VREDUCESS - {.VREDUCESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x57, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, + {.VREDUCESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x57, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, explicit_count=4}}, // .VREDUCESD - {.VREDUCESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x57, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, + {.VREDUCESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x57, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, explicit_count=4}}, // .VRNDSCALEPS - {.VRNDSCALEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VRNDSCALEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VRNDSCALEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VRNDSCALEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VRNDSCALEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VRNDSCALEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VRNDSCALEPD - {.VRNDSCALEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VRNDSCALEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VRNDSCALEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VRNDSCALEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VRNDSCALEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VRNDSCALEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VRNDSCALESS - {.VRNDSCALESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0A, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, + {.VRNDSCALESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0A, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, explicit_count=4}}, // .VRNDSCALESD - {.VRNDSCALESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0B, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, + {.VRNDSCALESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0B, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, explicit_count=4}}, // .VRSQRT14PS - {.VRSQRT14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VRSQRT14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VRSQRT14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VRSQRT14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VRSQRT14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VRSQRT14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VRSQRT14PD - {.VRSQRT14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VRSQRT14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VRSQRT14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VRSQRT14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VRSQRT14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VRSQRT14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VRSQRT14SS - {.VRSQRT14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}}, + {.VRSQRT14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, explicit_count=3}}, // .VRSQRT14SD - {.VRSQRT14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}}, + {.VRSQRT14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4F, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, explicit_count=3}}, // .VRCP14PS - {.VRCP14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VRCP14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VRCP14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VRCP14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VRCP14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VRCP14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VRCP14PD - {.VRCP14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VRCP14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VRCP14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VRCP14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VRCP14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VRCP14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VRCP14SS - {.VRCP14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}}, + {.VRCP14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, explicit_count=3}}, // .VRCP14SD - {.VRCP14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}}, + {.VRCP14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, explicit_count=3}}, // .VSCALEFPS - {.VSCALEFPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VSCALEFPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VSCALEFPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VSCALEFPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VSCALEFPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VSCALEFPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VSCALEFPD - {.VSCALEFPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VSCALEFPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VSCALEFPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VSCALEFPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VSCALEFPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VSCALEFPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VSCALEFSS - {.VSCALEFSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}}, + {.VSCALEFSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, explicit_count=3}}, // .VSCALEFSD - {.VSCALEFSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}}, + {.VSCALEFSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, explicit_count=3}}, // .VGETEXPPS - {.VGETEXPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VGETEXPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VGETEXPPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VGETEXPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.VGETEXPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=2}}, + {.VGETEXPPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=2}}, // .VGETEXPPD - {.VGETEXPPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VGETEXPPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VGETEXPPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VGETEXPPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.VGETEXPPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=2}}, + {.VGETEXPPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=2}}, // .VGETEXPSS - {.VGETEXPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x43, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}}, + {.VGETEXPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x43, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, explicit_count=3}}, // .VGETEXPSD - {.VGETEXPSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x43, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}}, + {.VGETEXPSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x43, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, explicit_count=3}}, // .VGETMANTPS - {.VGETMANTPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VGETMANTPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VGETMANTPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VGETMANTPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VGETMANTPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VGETMANTPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VGETMANTPD - {.VGETMANTPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VGETMANTPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VGETMANTPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VGETMANTPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VGETMANTPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VGETMANTPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VGETMANTSS - {.VGETMANTSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x27, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, + {.VGETMANTSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x27, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, explicit_count=4}}, // .VGETMANTSD - {.VGETMANTSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x27, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, + {.VGETMANTSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x27, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, explicit_count=4}}, // .VFIXUPIMMPS - {.VFIXUPIMMPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VFIXUPIMMPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VFIXUPIMMPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VFIXUPIMMPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VFIXUPIMMPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, + {.VFIXUPIMMPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=4}}, // .VFIXUPIMMPD - {.VFIXUPIMMPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VFIXUPIMMPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VFIXUPIMMPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VFIXUPIMMPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=4}}, + {.VFIXUPIMMPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=4}}, + {.VFIXUPIMMPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=4}}, // .VFIXUPIMMSS - {.VFIXUPIMMSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x55, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, + {.VFIXUPIMMSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x55, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, explicit_count=4}}, // .VFIXUPIMMSD - {.VFIXUPIMMSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x55, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, + {.VFIXUPIMMSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x55, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, explicit_count=4}}, // .VFPCLASSPS - {.VFPCLASSPS, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VFPCLASSPS, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VFPCLASSPS, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VFPCLASSPS, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, + {.VFPCLASSPS, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, + {.VFPCLASSPS, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=3}}, // .VFPCLASSPD - {.VFPCLASSPD, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VFPCLASSPD, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VFPCLASSPD, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VFPCLASSPD, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VFPCLASSPD, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VFPCLASSPD, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .VFPCLASSSS - {.VFPCLASSSS, {.K, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x67, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, + {.VFPCLASSSS, {.K, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x67, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, explicit_count=3}}, // .VFPCLASSSD - {.VFPCLASSSD, {.K, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x67, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, + {.VFPCLASSSD, {.K, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x67, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, explicit_count=3}}, // .VALIGNQ - {.VALIGNQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VALIGNQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VALIGNQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VALIGNQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=4}}, + {.VALIGNQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=4}}, + {.VALIGNQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=4}}, // .VALIGND - {.VALIGND, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VALIGND, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VALIGND, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VALIGND, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VALIGND, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, + {.VALIGND, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=4}}, // .VDBPSADBW - {.VDBPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VDBPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VDBPSADBW, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VDBPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VDBPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, + {.VDBPSADBW, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=4}}, // .VPTERNLOGD - {.VPTERNLOGD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {.VPTERNLOGD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {.VPTERNLOGD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, + {.VPTERNLOGD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, explicit_count=4}}, + {.VPTERNLOGD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, explicit_count=4}}, + {.VPTERNLOGD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, explicit_count=4}}, // .VPTERNLOGQ - {.VPTERNLOGQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPTERNLOGQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPTERNLOGQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPTERNLOGQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=4}}, + {.VPTERNLOGQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=4}}, + {.VPTERNLOGQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=4}}, // .VPMULTISHIFTQB - {.VPMULTISHIFTQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {.VPMULTISHIFTQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {.VPMULTISHIFTQB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, + {.VPMULTISHIFTQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, + {.VPMULTISHIFTQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, + {.VPMULTISHIFTQB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, explicit_count=3}}, // .KADDW - {.KADDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KADDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KADDB - {.KADDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KADDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KADDQ - {.KADDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KADDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KADDD - {.KADDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KADDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KANDW - {.KANDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KANDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KANDB - {.KANDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KANDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KANDQ - {.KANDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KANDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KANDD - {.KANDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KANDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KANDNW - {.KANDNW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KANDNW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KANDNB - {.KANDNB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KANDNB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KANDNQ - {.KANDNQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KANDNQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KANDND - {.KANDND, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KANDND, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KMOVW - {.KMOVW, {.K, .K_M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.KMOVW, {.M16, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.KMOVW, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.KMOVW, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KMOVW, {.K, .K_M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.KMOVW, {.M16, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.KMOVW, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.KMOVW, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, // .KMOVB - {.KMOVB, {.K, .K_M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.KMOVB, {.M8, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.KMOVB, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.KMOVB, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KMOVB, {.K, .K_M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.KMOVB, {.M8, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.KMOVB, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.KMOVB, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, // .KMOVQ - {.KMOVQ, {.K, .K_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.KMOVQ, {.M64, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.KMOVQ, {.K, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.KMOVQ, {.R64, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.KMOVQ, {.K, .K_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.KMOVQ, {.M64, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.KMOVQ, {.K, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.KMOVQ, {.R64, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, // .KMOVD - {.KMOVD, {.K, .K_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.KMOVD, {.M32, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {.KMOVD, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.KMOVD, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KMOVD, {.K, .K_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.KMOVD, {.M32, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, + {.KMOVD, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, + {.KMOVD, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, // .KNOTW - {.KNOTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KNOTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, // .KNOTB - {.KNOTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KNOTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, // .KNOTQ - {.KNOTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.KNOTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, // .KNOTD - {.KNOTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.KNOTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, // .KORW - {.KORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KORB - {.KORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KORQ - {.KORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KORD - {.KORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KORTESTW - {.KORTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KORTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, // .KORTESTB - {.KORTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KORTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, // .KORTESTQ - {.KORTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.KORTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, // .KORTESTD - {.KORTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.KORTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, // .KSHIFTLW - {.KSHIFTLW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x32, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.KSHIFTLW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x32, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .KSHIFTLB - {.KSHIFTLB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x32, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KSHIFTLB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x32, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, // .KSHIFTLQ - {.KSHIFTLQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x33, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.KSHIFTLQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x33, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .KSHIFTLD - {.KSHIFTLD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x33, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KSHIFTLD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x33, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, // .KSHIFTRW - {.KSHIFTRW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x30, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.KSHIFTRW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x30, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .KSHIFTRB - {.KSHIFTRB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x30, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KSHIFTRB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x30, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, // .KSHIFTRQ - {.KSHIFTRQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x31, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.KSHIFTRQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x31, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=3}}, // .KSHIFTRD - {.KSHIFTRD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x31, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KSHIFTRD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x31, 0, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=3}}, // .KTESTW - {.KTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, // .KTESTB - {.KTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, + {.KTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, explicit_count=2}}, // .KTESTQ - {.KTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.KTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, // .KTESTD - {.KTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {.KTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, explicit_count=2}}, // .KUNPCKBW - {.KUNPCKBW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KUNPCKBW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KUNPCKWD - {.KUNPCKWD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KUNPCKWD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KUNPCKDQ - {.KUNPCKDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KUNPCKDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KXNORW - {.KXNORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KXNORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KXNORB - {.KXNORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KXNORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KXNORQ - {.KXNORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KXNORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KXNORD - {.KXNORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KXNORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KXORW - {.KXORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KXORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KXORB - {.KXORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, + {.KXORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, explicit_count=3}}, // .KXORQ - {.KXORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KXORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .KXORD - {.KXORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, + {.KXORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, explicit_count=3}}, // .FADD - {.FADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 0, {}}, - {.FADD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 0, {}}, - {.FADD, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 192, {}}, - {.FADD, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 192, {}}, + {.FADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 0, {explicit_count=1}}, + {.FADD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 0, {explicit_count=1}}, + {.FADD, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 192, {explicit_count=1, has_implict=true}}, + {.FADD, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 192, {explicit_count=1, has_implict=true}}, // .FADDP - {.FADDP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 192, {}}, + {.FADDP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 192, {explicit_count=1, has_implict=true}}, {.FADDP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 193, {}}, // .FIADD - {.FIADD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 0, {}}, - {.FIADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 0, {}}, + {.FIADD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 0, {explicit_count=1}}, + {.FIADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 0, {explicit_count=1}}, // .FSUB - {.FSUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 4, {modrm_reg_ext=true}}, - {.FSUB, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 4, {modrm_reg_ext=true}}, - {.FSUB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 224, {}}, - {.FSUB, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 232, {}}, + {.FSUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 4, {modrm_reg_ext=true, explicit_count=1}}, + {.FSUB, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 4, {modrm_reg_ext=true, explicit_count=1}}, + {.FSUB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 224, {explicit_count=1, has_implict=true}}, + {.FSUB, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 232, {explicit_count=1, has_implict=true}}, // .FSUBP - {.FSUBP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 232, {}}, + {.FSUBP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 232, {explicit_count=1, has_implict=true}}, {.FSUBP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 233, {}}, // .FISUB - {.FISUB, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 4, {modrm_reg_ext=true}}, - {.FISUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 4, {modrm_reg_ext=true}}, + {.FISUB, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 4, {modrm_reg_ext=true, explicit_count=1}}, + {.FISUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 4, {modrm_reg_ext=true, explicit_count=1}}, // .FSUBR - {.FSUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 5, {modrm_reg_ext=true}}, - {.FSUBR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 5, {modrm_reg_ext=true}}, - {.FSUBR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 232, {}}, - {.FSUBR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 224, {}}, + {.FSUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 5, {modrm_reg_ext=true, explicit_count=1}}, + {.FSUBR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 5, {modrm_reg_ext=true, explicit_count=1}}, + {.FSUBR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 232, {explicit_count=1, has_implict=true}}, + {.FSUBR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 224, {explicit_count=1, has_implict=true}}, // .FSUBRP - {.FSUBRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 224, {}}, + {.FSUBRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 224, {explicit_count=1, has_implict=true}}, {.FSUBRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 225, {}}, // .FISUBR - {.FISUBR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 5, {modrm_reg_ext=true}}, - {.FISUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 5, {modrm_reg_ext=true}}, + {.FISUBR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 5, {modrm_reg_ext=true, explicit_count=1}}, + {.FISUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 5, {modrm_reg_ext=true, explicit_count=1}}, // .FMUL - {.FMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 1, {modrm_reg_ext=true}}, - {.FMUL, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 1, {modrm_reg_ext=true}}, - {.FMUL, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 200, {}}, - {.FMUL, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 200, {}}, + {.FMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 1, {modrm_reg_ext=true, explicit_count=1}}, + {.FMUL, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 1, {modrm_reg_ext=true, explicit_count=1}}, + {.FMUL, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 200, {explicit_count=1, has_implict=true}}, + {.FMUL, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 200, {explicit_count=1, has_implict=true}}, // .FMULP - {.FMULP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 200, {}}, + {.FMULP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 200, {explicit_count=1, has_implict=true}}, {.FMULP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 201, {}}, // .FIMUL - {.FIMUL, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 1, {modrm_reg_ext=true}}, - {.FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 1, {modrm_reg_ext=true}}, + {.FIMUL, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 1, {modrm_reg_ext=true, explicit_count=1}}, + {.FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 1, {modrm_reg_ext=true, explicit_count=1}}, // .FDIV - {.FDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 6, {modrm_reg_ext=true}}, - {.FDIV, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 6, {modrm_reg_ext=true}}, - {.FDIV, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 240, {}}, - {.FDIV, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 248, {}}, + {.FDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 6, {modrm_reg_ext=true, explicit_count=1}}, + {.FDIV, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 6, {modrm_reg_ext=true, explicit_count=1}}, + {.FDIV, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 240, {explicit_count=1, has_implict=true}}, + {.FDIV, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 248, {explicit_count=1, has_implict=true}}, // .FDIVP - {.FDIVP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 248, {}}, + {.FDIVP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 248, {explicit_count=1, has_implict=true}}, {.FDIVP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 249, {}}, // .FIDIV - {.FIDIV, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 6, {modrm_reg_ext=true}}, - {.FIDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 6, {modrm_reg_ext=true}}, + {.FIDIV, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 6, {modrm_reg_ext=true, explicit_count=1}}, + {.FIDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 6, {modrm_reg_ext=true, explicit_count=1}}, // .FDIVR - {.FDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 7, {modrm_reg_ext=true}}, - {.FDIVR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 7, {modrm_reg_ext=true}}, - {.FDIVR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 248, {}}, - {.FDIVR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 240, {}}, + {.FDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 7, {modrm_reg_ext=true, explicit_count=1}}, + {.FDIVR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 7, {modrm_reg_ext=true, explicit_count=1}}, + {.FDIVR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 248, {explicit_count=1, has_implict=true}}, + {.FDIVR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 240, {explicit_count=1, has_implict=true}}, // .FDIVRP - {.FDIVRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 240, {}}, + {.FDIVRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 240, {explicit_count=1, has_implict=true}}, {.FDIVRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 241, {}}, // .FIDIVR - {.FIDIVR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 7, {modrm_reg_ext=true}}, - {.FIDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 7, {modrm_reg_ext=true}}, + {.FIDIVR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 7, {modrm_reg_ext=true, explicit_count=1}}, + {.FIDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 7, {modrm_reg_ext=true, explicit_count=1}}, // .FSQRT {.FSQRT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 250, {}}, // .FABS @@ -3162,88 +3162,88 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .FXAM {.FXAM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 229, {}}, // .FLD - {.FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 0, {}}, - {.FLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 0, {}}, - {.FLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 5, {modrm_reg_ext=true}}, - {.FLD, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD9, 192, {}}, + {.FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 0, {explicit_count=1}}, + {.FLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 0, {explicit_count=1}}, + {.FLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 5, {modrm_reg_ext=true, explicit_count=1}}, + {.FLD, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD9, 192, {explicit_count=1}}, // .FILD - {.FILD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 0, {}}, - {.FILD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 0, {}}, - {.FILD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 5, {modrm_reg_ext=true}}, + {.FILD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 0, {explicit_count=1}}, + {.FILD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 0, {explicit_count=1}}, + {.FILD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 5, {modrm_reg_ext=true, explicit_count=1}}, // .FBLD - {.FBLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 4, {modrm_reg_ext=true}}, + {.FBLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 4, {modrm_reg_ext=true, explicit_count=1}}, // .FST - {.FST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 2, {modrm_reg_ext=true}}, - {.FST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 2, {modrm_reg_ext=true}}, - {.FST, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 208, {}}, + {.FST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 2, {modrm_reg_ext=true, explicit_count=1}}, + {.FST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 2, {modrm_reg_ext=true, explicit_count=1}}, + {.FST, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 208, {explicit_count=1}}, // .FSTP - {.FSTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 3, {modrm_reg_ext=true}}, - {.FSTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 3, {modrm_reg_ext=true}}, - {.FSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 7, {modrm_reg_ext=true}}, - {.FSTP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 216, {}}, + {.FSTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 3, {modrm_reg_ext=true, explicit_count=1}}, + {.FSTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 3, {modrm_reg_ext=true, explicit_count=1}}, + {.FSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 7, {modrm_reg_ext=true, explicit_count=1}}, + {.FSTP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 216, {explicit_count=1}}, // .FIST - {.FIST, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 2, {modrm_reg_ext=true}}, - {.FIST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 2, {modrm_reg_ext=true}}, + {.FIST, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 2, {modrm_reg_ext=true, explicit_count=1}}, + {.FIST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 2, {modrm_reg_ext=true, explicit_count=1}}, // .FISTP - {.FISTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 3, {modrm_reg_ext=true}}, - {.FISTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 3, {modrm_reg_ext=true}}, - {.FISTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 7, {modrm_reg_ext=true}}, + {.FISTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 3, {modrm_reg_ext=true, explicit_count=1}}, + {.FISTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 3, {modrm_reg_ext=true, explicit_count=1}}, + {.FISTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 7, {modrm_reg_ext=true, explicit_count=1}}, // .FISTTP - {.FISTTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 1, {modrm_reg_ext=true}}, - {.FISTTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 1, {modrm_reg_ext=true}}, - {.FISTTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 1, {modrm_reg_ext=true}}, + {.FISTTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 1, {modrm_reg_ext=true, explicit_count=1}}, + {.FISTTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 1, {modrm_reg_ext=true, explicit_count=1}}, + {.FISTTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 1, {modrm_reg_ext=true, explicit_count=1}}, // .FBSTP - {.FBSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 6, {modrm_reg_ext=true}}, + {.FBSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 6, {modrm_reg_ext=true, explicit_count=1}}, // .FXCH - {.FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD9, 200, {}}, + {.FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD9, 200, {explicit_count=1}}, {.FXCH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 201, {}}, // .FCMOVB - {.FCMOVB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 192, {}}, + {.FCMOVB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 192, {explicit_count=1, has_implict=true}}, // .FCMOVE - {.FCMOVE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 200, {}}, + {.FCMOVE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 200, {explicit_count=1, has_implict=true}}, // .FCMOVBE - {.FCMOVBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 208, {}}, + {.FCMOVBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 208, {explicit_count=1, has_implict=true}}, // .FCMOVU - {.FCMOVU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 216, {}}, + {.FCMOVU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 216, {explicit_count=1, has_implict=true}}, // .FCMOVNB - {.FCMOVNB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 192, {}}, + {.FCMOVNB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 192, {explicit_count=1, has_implict=true}}, // .FCMOVNE - {.FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 200, {}}, + {.FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 200, {explicit_count=1, has_implict=true}}, // .FCMOVNBE - {.FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 208, {}}, + {.FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 208, {explicit_count=1, has_implict=true}}, // .FCMOVNU - {.FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 216, {}}, + {.FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 216, {explicit_count=1, has_implict=true}}, // .FCOM - {.FCOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 2, {modrm_reg_ext=true}}, - {.FCOM, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 2, {modrm_reg_ext=true}}, - {.FCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD8, 208, {}}, + {.FCOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 2, {modrm_reg_ext=true, explicit_count=1}}, + {.FCOM, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 2, {modrm_reg_ext=true, explicit_count=1}}, + {.FCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD8, 208, {explicit_count=1}}, {.FCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD8, 209, {}}, // .FCOMP - {.FCOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 3, {modrm_reg_ext=true}}, - {.FCOMP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 3, {modrm_reg_ext=true}}, - {.FCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD8, 216, {}}, + {.FCOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 3, {modrm_reg_ext=true, explicit_count=1}}, + {.FCOMP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 3, {modrm_reg_ext=true, explicit_count=1}}, + {.FCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD8, 216, {explicit_count=1}}, {.FCOMP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD8, 217, {}}, // .FCOMPP {.FCOMPP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 217, {}}, // .FICOM - {.FICOM, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 2, {modrm_reg_ext=true}}, - {.FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 2, {modrm_reg_ext=true}}, + {.FICOM, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 2, {modrm_reg_ext=true, explicit_count=1}}, + {.FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 2, {modrm_reg_ext=true, explicit_count=1}}, // .FICOMP - {.FICOMP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 3, {modrm_reg_ext=true}}, - {.FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 3, {modrm_reg_ext=true}}, + {.FICOMP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 3, {modrm_reg_ext=true, explicit_count=1}}, + {.FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 3, {modrm_reg_ext=true, explicit_count=1}}, // .FCOMI - {.FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 240, {}}, + {.FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 240, {explicit_count=1, has_implict=true}}, // .FCOMIP - {.FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 240, {}}, + {.FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 240, {explicit_count=1, has_implict=true}}, // .FUCOMI - {.FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 232, {}}, + {.FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 232, {explicit_count=1, has_implict=true}}, // .FUCOMIP - {.FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 232, {}}, + {.FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 232, {explicit_count=1, has_implict=true}}, // .FUCOM - {.FUCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 224, {}}, + {.FUCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 224, {explicit_count=1}}, {.FUCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDD, 225, {}}, // .FUCOMP - {.FUCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 232, {}}, + {.FUCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 232, {explicit_count=1}}, {.FUCOMP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDD, 233, {}}, // .FUCOMPP {.FUCOMPP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDA, 233, {}}, @@ -3288,9 +3288,9 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .FDECSTP {.FDECSTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 246, {}}, // .FFREE - {.FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 192, {}}, + {.FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 192, {explicit_count=1}}, // .FFREEP - {.FFREEP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDF, 192, {}}, + {.FFREEP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDF, 192, {explicit_count=1}}, // .FNOP {.FNOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 208, {}}, // .FWAIT @@ -3300,92 +3300,92 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .FNCLEX {.FNCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDB, 226, {}}, // .FSTCW - {.FSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 7, {modrm_reg_ext=true}}, + {.FSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 7, {modrm_reg_ext=true, explicit_count=1}}, // .FNSTCW - {.FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 7, {modrm_reg_ext=true}}, + {.FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 7, {modrm_reg_ext=true, explicit_count=1}}, // .FLDCW - {.FLDCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 5, {modrm_reg_ext=true}}, + {.FLDCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 5, {modrm_reg_ext=true, explicit_count=1}}, // .FSTENV - {.FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 6, {modrm_reg_ext=true}}, + {.FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 6, {modrm_reg_ext=true, explicit_count=1}}, // .FNSTENV - {.FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 6, {modrm_reg_ext=true}}, + {.FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 6, {modrm_reg_ext=true, explicit_count=1}}, // .FLDENV - {.FLDENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 4, {modrm_reg_ext=true}}, + {.FLDENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 4, {modrm_reg_ext=true, explicit_count=1}}, // .FSAVE - {.FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 6, {modrm_reg_ext=true}}, + {.FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 6, {modrm_reg_ext=true, explicit_count=1}}, // .FNSAVE - {.FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 6, {modrm_reg_ext=true}}, + {.FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 6, {modrm_reg_ext=true, explicit_count=1}}, // .FRSTOR - {.FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 4, {modrm_reg_ext=true}}, + {.FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 4, {modrm_reg_ext=true, explicit_count=1}}, // .FSTSW - {.FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7, {modrm_reg_ext=true}}, - {.FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {}}, + {.FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7, {modrm_reg_ext=true, explicit_count=1}}, + {.FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {has_implict=true}}, // .FNSTSW - {.FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7, {modrm_reg_ext=true}}, - {.FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {}}, + {.FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7, {modrm_reg_ext=true, explicit_count=1}}, + {.FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {has_implict=true}}, // .FXSAVE - {.FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true}}, + {.FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .FXSAVE64 - {.FXSAVE64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.FXSAVE64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .FXRSTOR - {.FXRSTOR, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, modrm_reg_ext=true}}, + {.FXRSTOR, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .FXRSTOR64 - {.FXRSTOR64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.FXRSTOR64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .LGDT - {.LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 2, {esc=._0F, modrm_reg_ext=true}}, - {.LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 2, {esc=._0F, modrm_reg_ext=true}}, + {.LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 2, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 2, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .SGDT - {.SGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 0, {esc=._0F, modrm_reg_ext=true}}, - {.SGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 0, {esc=._0F, modrm_reg_ext=true}}, + {.SGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.SGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .LIDT - {.LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 3, {esc=._0F, modrm_reg_ext=true}}, - {.LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 3, {esc=._0F, modrm_reg_ext=true}}, + {.LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 3, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 3, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .SIDT - {.SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 1, {esc=._0F, modrm_reg_ext=true}}, - {.SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 1, {esc=._0F, modrm_reg_ext=true}}, + {.SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 1, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 1, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .LLDT - {.LLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 2, {esc=._0F, modrm_reg_ext=true}}, + {.LLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 2, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .SLDT - {.SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, modrm_reg_ext=true}}, - {.SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, modrm_reg_ext=true}}, - {.SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .LTR - {.LTR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 3, {esc=._0F, modrm_reg_ext=true}}, + {.LTR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 3, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .STR - {.STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, modrm_reg_ext=true}}, - {.STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, modrm_reg_ext=true}}, - {.STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .LMSW - {.LMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 6, {esc=._0F, modrm_reg_ext=true}}, + {.LMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 6, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .SMSW - {.SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, modrm_reg_ext=true}}, - {.SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, modrm_reg_ext=true}}, - {.SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .CLTS {.CLTS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x06, 0, {esc=._0F}}, // .ARPL - {.ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x63, 0, {}}, + {.ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x63, 0, {explicit_count=2}}, // .LAR - {.LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F}}, - {.LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F}}, - {.LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F, force_rex_w=true}}, + {.LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F, explicit_count=2}}, + {.LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F, explicit_count=2}}, + {.LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .LSL - {.LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F}}, - {.LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F}}, - {.LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F, force_rex_w=true}}, + {.LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F, explicit_count=2}}, + {.LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F, explicit_count=2}}, + {.LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F, force_rex_w=true, explicit_count=2}}, // .VERR - {.VERR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 4, {esc=._0F, modrm_reg_ext=true}}, + {.VERR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 4, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .VERW - {.VERW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 5, {esc=._0F, modrm_reg_ext=true}}, + {.VERW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 5, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .INVD {.INVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x08, 0, {esc=._0F}}, // .WBINVD {.WBINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x09, 0, {esc=._0F}}, // .INVLPG - {.INVLPG, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 7, {esc=._0F, modrm_reg_ext=true}}, + {.INVLPG, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 7, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .INVPCID - {.INVPCID, {.R32, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x82, 0, {esc=._0F38, prefix=1}}, - {.INVPCID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x82, 0, {esc=._0F38, prefix=1}}, + {.INVPCID, {.R32, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x82, 0, {esc=._0F38, prefix=1, explicit_count=2}}, + {.INVPCID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x82, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .RSM {.RSM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAA, 0, {esc=._0F}}, // .RDMSR @@ -3401,23 +3401,23 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .VMXOFF {.VMXOFF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 196, {esc=._0F}}, // .VMXON - {.VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, prefix=2, modrm_reg_ext=true}}, + {.VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, // .VMCLEAR - {.VMCLEAR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, prefix=1, modrm_reg_ext=true}}, + {.VMCLEAR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=1}}, // .VMPTRLD - {.VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, + {.VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .VMPTRST - {.VMPTRST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, + {.VMPTRST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .VMREAD - {.VMREAD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x78, 0, {esc=._0F}}, + {.VMREAD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x78, 0, {esc=._0F, explicit_count=2}}, // .VMWRITE - {.VMWRITE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F}}, + {.VMWRITE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F, explicit_count=2}}, // .VMFUNC {.VMFUNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 212, {esc=._0F}}, // .INVEPT - {.INVEPT, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x80, 0, {esc=._0F38, prefix=1}}, + {.INVEPT, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x80, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .INVVPID - {.INVVPID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x81, 0, {esc=._0F38, prefix=1}}, + {.INVVPID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x81, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .ENCLS {.ENCLS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 207, {esc=._0F}}, // .ENCLU @@ -3429,95 +3429,95 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .WRPKRU {.WRPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 239, {esc=._0F}}, // .INCSSPD - {.INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, prefix=2, modrm_reg_ext=true}}, + {.INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, // .INCSSPQ - {.INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true}}, + {.INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .RDSSPD - {.RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1E, 1, {esc=._0F, prefix=2, modrm_reg_ext=true}}, + {.RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1E, 1, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, // .RDSSPQ - {.RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1E, 1, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true}}, + {.RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1E, 1, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .SAVEPREVSSP {.SAVEPREVSSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 234, {esc=._0F, prefix=2}}, // .RSTORSSP - {.RSTORSSP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 5, {esc=._0F, prefix=2, modrm_reg_ext=true}}, + {.RSTORSSP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 5, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, // .WRSSD - {.WRSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF6, 0, {esc=._0F38}}, + {.WRSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, explicit_count=2}}, // .WRSSQ - {.WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, force_rex_w=true}}, + {.WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, force_rex_w=true, explicit_count=2}}, // .WRUSSD - {.WRUSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF5, 0, {esc=._0F38, prefix=1}}, + {.WRUSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF5, 0, {esc=._0F38, prefix=1, explicit_count=2}}, // .WRUSSQ - {.WRUSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF5, 0, {esc=._0F38, prefix=1, force_rex_w=true}}, + {.WRUSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF5, 0, {esc=._0F38, prefix=1, force_rex_w=true, explicit_count=2}}, // .SETSSBSY {.SETSSBSY, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 232, {esc=._0F, prefix=2}}, // .CLRSSBSY - {.CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=2, modrm_reg_ext=true}}, + {.CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=2, modrm_reg_ext=true, explicit_count=1}}, // .ENDBR64 {.ENDBR64, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1E, 250, {esc=._0F, prefix=2}}, // .ENDBR32 {.ENDBR32, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1E, 251, {esc=._0F, prefix=2}}, // .XSAVE - {.XSAVE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, modrm_reg_ext=true}}, + {.XSAVE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .XSAVE64 - {.XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .XRSTOR - {.XRSTOR, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, modrm_reg_ext=true}}, + {.XRSTOR, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .XRSTOR64 - {.XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .XSAVEOPT - {.XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true}}, + {.XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .XSAVEOPT64 - {.XSAVEOPT64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.XSAVEOPT64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .XSAVEC - {.XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 4, {esc=._0F, modrm_reg_ext=true}}, + {.XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 4, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .XSAVEC64 - {.XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .XSAVES - {.XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 5, {esc=._0F, modrm_reg_ext=true}}, + {.XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 5, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .XSAVES64 - {.XSAVES64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 5, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.XSAVES64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 5, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .XRSTORS - {.XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 3, {esc=._0F, modrm_reg_ext=true}}, + {.XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 3, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .XRSTORS64 - {.XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 3, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 3, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .PREFETCHT0 - {.PREFETCHT0, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 1, {esc=._0F, modrm_reg_ext=true}}, + {.PREFETCHT0, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 1, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .PREFETCHT1 - {.PREFETCHT1, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 2, {esc=._0F, modrm_reg_ext=true}}, + {.PREFETCHT1, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 2, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .PREFETCHT2 - {.PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 3, {esc=._0F, modrm_reg_ext=true}}, + {.PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 3, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .PREFETCHNTA - {.PREFETCHNTA, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 0, {esc=._0F, modrm_reg_ext=true}}, + {.PREFETCHNTA, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .PREFETCHW - {.PREFETCHW, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x0D, 1, {esc=._0F, modrm_reg_ext=true}}, + {.PREFETCHW, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x0D, 1, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .CLFLUSHOPT - {.CLFLUSHOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 7, {esc=._0F, prefix=1, modrm_reg_ext=true}}, + {.CLFLUSHOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 7, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=1}}, // .CLWB - {.CLWB, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=1, modrm_reg_ext=true}}, + {.CLWB, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=1, modrm_reg_ext=true, explicit_count=1}}, // .CLDEMOTE - {.CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1C, 0, {esc=._0F, modrm_reg_ext=true}}, + {.CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1C, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .BSWAP - {.BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xC8, 0, {esc=._0F}}, - {.BSWAP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xC8, 0, {esc=._0F, force_rex_w=true}}, + {.BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xC8, 0, {esc=._0F, explicit_count=1}}, + {.BSWAP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xC8, 0, {esc=._0F, force_rex_w=true, explicit_count=1}}, // .CMPXCHG - {.CMPXCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB0, 0, {esc=._0F, lock_ok=true}}, - {.CMPXCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, lock_ok=true}}, - {.CMPXCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, lock_ok=true}}, - {.CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, force_rex_w=true, lock_ok=true}}, + {.CMPXCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB0, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.CMPXCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.CMPXCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, force_rex_w=true, lock_ok=true, explicit_count=2}}, // .CMPXCHG8B - {.CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 1, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, + {.CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 1, {esc=._0F, lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, // .CMPXCHG16B - {.CMPXCHG16B, {.M128, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 1, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, + {.CMPXCHG16B, {.M128, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 1, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, explicit_count=1}}, // .XADD - {.XADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC0, 0, {esc=._0F, lock_ok=true}}, - {.XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, lock_ok=true}}, - {.XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, lock_ok=true}}, - {.XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, force_rex_w=true, lock_ok=true}}, + {.XADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC0, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, lock_ok=true, explicit_count=2}}, + {.XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, force_rex_w=true, lock_ok=true, explicit_count=2}}, // .BOUND - {.BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {}}, - {.BOUND, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {}}, + {.BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {explicit_count=2}}, + {.BOUND, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {explicit_count=2}}, // .ENTER - {.ENTER, {.IMM16, .IMM8, .NONE, .NONE}, {.IW, .IB, .NONE, .NONE}, 0xC8, 0, {}}, + {.ENTER, {.IMM16, .IMM8, .NONE, .NONE}, {.IW, .IB, .NONE, .NONE}, 0xC8, 0, {explicit_count=2}}, // .LEAVE {.LEAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xC9, 0, {}}, // .XLAT @@ -3525,20 +3525,20 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .XLATB {.XLATB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD7, 0, {}}, // .MOVBE - {.MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38}}, - {.MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38}}, - {.MOVBE, {.R64, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, force_rex_w=true}}, - {.MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38}}, - {.MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38}}, - {.MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, force_rex_w=true}}, + {.MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, explicit_count=2}}, + {.MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, explicit_count=2}}, + {.MOVBE, {.R64, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, force_rex_w=true, explicit_count=2}}, + {.MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, explicit_count=2}}, + {.MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, explicit_count=2}}, + {.MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, force_rex_w=true, explicit_count=2}}, // .RDRAND - {.RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, - {.RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, - {.RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, // .RDSEED - {.RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, - {.RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, - {.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, + {.RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, + {.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, explicit_count=1}}, } @(rodata) From 29594d1ed444ead3ddd4b45408cbff292795cdcb Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 15 Jun 2026 22:58:06 +0100 Subject: [PATCH 13/27] Add to the Encoding_Flags `op_count` and `needs_modrm` --- core/rexcode/x86/decoder.odin | 21 +- core/rexcode/x86/encoding_types.odin | 6 +- core/rexcode/x86/tablegen/gen.odin | 25 +- .../x86/tablegen/generated/decode_tables.odin | 4426 ++++++++--------- 4 files changed, 2246 insertions(+), 2232 deletions(-) diff --git a/core/rexcode/x86/decoder.odin b/core/rexcode/x86/decoder.odin index da8ce469e..d66ef36d4 100644 --- a/core/rexcode/x86/decoder.odin +++ b/core/rexcode/x86/decoder.odin @@ -573,21 +573,14 @@ decode_opcode_vex :: #force_inline proc(state: ^Decoder_State) -> (entry: ^Decod decode_operands :: proc(state: ^Decoder_State, entry: ^Decode_Entry) -> (inst: Instruction, err: Error_Code) { inst.mnemonic = entry.mnemonic - // Check if we need ModR/M - needs_modrm := false - for enc in entry.enc { - if enc == .MR || enc == .REG || enc == .VVVV { - needs_modrm = true - break - } - } - modrm: u8 = 0 modrm_info: ModRM_Info sib: u8 = 0 sib_info: SIB_Info has_sib := false + needs_modrm := entry.flags.needs_modrm + if needs_modrm { if state.position >= len(state.data) { return {}, .BUFFER_TOO_SHORT @@ -616,18 +609,16 @@ decode_operands :: proc(state: ^Decoder_State, entry: ^Decode_Entry) -> (inst: I } // Decode each operand - for op_type, i in entry.ops { - if op_type == .NONE { - break - } + op_count := entry.flags.op_count + for i in 0.. 0 { + append(&parts, fmt.tprintf("op_count=%d", op_count)) + } + if needs_modrm { + append(&parts, "needs_modrm=true") + } } strings.write_string(sb, "{") diff --git a/core/rexcode/x86/tablegen/generated/decode_tables.odin b/core/rexcode/x86/tablegen/generated/decode_tables.odin index f805b5a7d..4288ed522 100644 --- a/core/rexcode/x86/tablegen/generated/decode_tables.odin +++ b/core/rexcode/x86/tablegen/generated/decode_tables.odin @@ -145,237 +145,237 @@ SIB_TABLE := [256]lib.SIB_Info{ @(rodata) LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ - {.NONE, 0, 0x00, 0xFF, .ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x01, 0xFF, .ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x01, 0xFF, .ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x01, 0xFF, .ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}}, - {.NONE, 0, 0x02, 0xFF, .ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x03, 0xFF, .ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x03, 0xFF, .ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x03, 0xFF, .ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x04, 0xFF, .ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}}, - {.NONE, 0, 0x05, 0xFF, .ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x05, 0xFF, .ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}}, - {.NONE, 0, 0x05, 0xFF, .ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}}, - {.NONE, 0, 0x08, 0xFF, .OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x0A, 0xFF, .OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x0B, 0xFF, .OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x0B, 0xFF, .OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x0C, 0xFF, .OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}}, - {.NONE, 0, 0x0D, 0xFF, .OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x0D, 0xFF, .OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}}, - {.NONE, 0, 0x0D, 0xFF, .OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}}, - {.NONE, 0, 0x10, 0xFF, .ADC, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x11, 0xFF, .ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}}, - {.NONE, 0, 0x11, 0xFF, .ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x11, 0xFF, .ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x12, 0xFF, .ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x13, 0xFF, .ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x13, 0xFF, .ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x13, 0xFF, .ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x14, 0xFF, .ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}}, - {.NONE, 0, 0x15, 0xFF, .ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}}, - {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x15, 0xFF, .ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}}, - {.NONE, 0, 0x18, 0xFF, .SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x19, 0xFF, .SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x19, 0xFF, .SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}}, - {.NONE, 0, 0x1A, 0xFF, .SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x1B, 0xFF, .SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x1B, 0xFF, .SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x1B, 0xFF, .SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x1C, 0xFF, .SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}}, - {.NONE, 0, 0x1D, 0xFF, .SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x1D, 0xFF, .SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}}, - {.NONE, 0, 0x1D, 0xFF, .SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}}, - {.NONE, 0, 0x20, 0xFF, .AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x21, 0xFF, .AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x21, 0xFF, .AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}}, - {.NONE, 0, 0x21, 0xFF, .AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x22, 0xFF, .AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x23, 0xFF, .AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x23, 0xFF, .AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x23, 0xFF, .AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x24, 0xFF, .AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}}, - {.NONE, 0, 0x25, 0xFF, .AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}}, - {.NONE, 0, 0x25, 0xFF, .AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}}, - {.NONE, 0, 0x25, 0xFF, .AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x28, 0xFF, .SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x29, 0xFF, .SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}}, - {.NONE, 0, 0x29, 0xFF, .SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x29, 0xFF, .SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x2A, 0xFF, .SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x2B, 0xFF, .SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x2B, 0xFF, .SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x2C, 0xFF, .SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}}, - {.NONE, 0, 0x2D, 0xFF, .SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}}, - {.NONE, 0, 0x2D, 0xFF, .SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x2D, 0xFF, .SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}}, - {.NONE, 0, 0x30, 0xFF, .XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}}, - {.NONE, 0, 0x31, 0xFF, .XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x32, 0xFF, .XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x33, 0xFF, .XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x33, 0xFF, .XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x33, 0xFF, .XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x34, 0xFF, .XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}}, - {.NONE, 0, 0x35, 0xFF, .XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}}, - {.NONE, 0, 0x35, 0xFF, .XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x35, 0xFF, .XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}}, - {.NONE, 0, 0x38, 0xFF, .CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}}, - {.NONE, 0, 0x39, 0xFF, .CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x39, 0xFF, .CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}}, - {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}}, - {.NONE, 0, 0x3A, 0xFF, .CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x3B, 0xFF, .CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x3C, 0xFF, .CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}}, - {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}}, - {.NONE, 0, 0x3D, 0xFF, .CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x3D, 0xFF, .CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}}, - {.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true}}, - {.NONE, 0, 0x40, 0xFF, .INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true}}, - {.NONE, 0, 0x48, 0xFF, .DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true}}, - {.NONE, 0, 0x48, 0xFF, .DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true}}, - {.NONE, 0, 0x50, 0xFF, .PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x50, 0xFF, .PUSH, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true}}, - {.NONE, 0, 0x58, 0xFF, .POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true}}, - {.NONE, 0, 0x58, 0xFF, .POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x62, 0xFF, .BOUND, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x62, 0xFF, .BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x63, 0xFF, .MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x63, 0xFF, .ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}}, - {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x69, 0xFF, .IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, {}}, - {.NONE, 0, 0x69, 0xFF, .IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x69, 0xFF, .IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {}}, - {.NONE, 0, 0x6A, 0xFF, .PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {}}, - {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {}}, - {.NONE, 0, 0x70, 0xFF, .JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x71, 0xFF, .JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x72, 0xFF, .JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x72, 0xFF, .JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x72, 0xFF, .JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x73, 0xFF, .JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x73, 0xFF, .JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x74, 0xFF, .JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x74, 0xFF, .JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x75, 0xFF, .JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x75, 0xFF, .JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x76, 0xFF, .JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x76, 0xFF, .JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x77, 0xFF, .JNBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x77, 0xFF, .JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x78, 0xFF, .JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x79, 0xFF, .JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7A, 0xFF, .JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7A, 0xFF, .JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7B, 0xFF, .JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7B, 0xFF, .JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7C, 0xFF, .JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7C, 0xFF, .JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7D, 0xFF, .JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7D, 0xFF, .JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7E, 0xFF, .JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7E, 0xFF, .JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7F, 0xFF, .JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x80, 0x00, .ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x80, 0x01, .OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x80, 0x02, .ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x80, 0x03, .SBB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x80, 0x04, .AND, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x80, 0x05, .SUB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x80, 0x06, .XOR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x80, 0x07, .CMP, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x00, .ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x00, .ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x00, .ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x02, .ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x02, .ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x02, .ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x03, .SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x03, .SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x03, .SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x04, .AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x04, .AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x04, .AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x05, .SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x05, .SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x05, .SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x06, .XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x06, .XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x06, .XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x07, .CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x07, .CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x81, 0x07, .CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x00, .ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x00, .ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x00, .ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x01, .OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x01, .OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x01, .OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x02, .ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x02, .ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x02, .ADC, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x03, .SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x03, .SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x03, .SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x04, .AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x04, .AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x04, .AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x05, .SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x05, .SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x05, .SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x06, .XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x06, .XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x06, .XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x07, .CMP, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x07, .CMP, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x83, 0x07, .CMP, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0x84, 0xFF, .TEST, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}}, - {.NONE, 0, 0x85, 0xFF, .TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x85, 0xFF, .TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}}, - {.NONE, 0, 0x85, 0xFF, .TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}}, - {.NONE, 0, 0x86, 0xFF, .XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true}}, - {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true}}, - {.NONE, 0, 0x88, 0xFF, .MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}}, - {.NONE, 0, 0x89, 0xFF, .MOV, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x89, 0xFF, .MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}}, - {.NONE, 0, 0x89, 0xFF, .MOV, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}}, - {.NONE, 0, 0x8A, 0xFF, .MOV, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x8B, 0xFF, .MOV, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x8B, 0xFF, .MOV, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x8B, 0xFF, .MOV, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x8C, 0xFF, .MOV, {.RM64, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x8C, 0xFF, .MOV, {.RM16, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {}}, - {.NONE, 0, 0x8D, 0xFF, .LEA, {.R64, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x8D, 0xFF, .LEA, {.R16, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x8D, 0xFF, .LEA, {.R32, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {}}, - {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0x8F, 0x00, .POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0x8F, 0x00, .POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}}, - {.NONE, 0, 0x90, 0xFF, .XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0x90, 0xFF, .XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0x90, 0xFF, .XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {force_rex_w=true}}, + {.NONE, 0, 0x00, 0xFF, .ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x01, 0xFF, .ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x01, 0xFF, .ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x01, 0xFF, .ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x02, 0xFF, .ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x03, 0xFF, .ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x03, 0xFF, .ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x03, 0xFF, .ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x04, 0xFF, .ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x05, 0xFF, .ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x05, 0xFF, .ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x05, 0xFF, .ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x08, 0xFF, .OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x0A, 0xFF, .OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x0B, 0xFF, .OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x0B, 0xFF, .OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x0C, 0xFF, .OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x0D, 0xFF, .OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x0D, 0xFF, .OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x0D, 0xFF, .OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x10, 0xFF, .ADC, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x11, 0xFF, .ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x11, 0xFF, .ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x11, 0xFF, .ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x12, 0xFF, .ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x13, 0xFF, .ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x13, 0xFF, .ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x13, 0xFF, .ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x14, 0xFF, .ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x15, 0xFF, .ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x15, 0xFF, .ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x18, 0xFF, .SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x19, 0xFF, .SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x19, 0xFF, .SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x1A, 0xFF, .SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x1B, 0xFF, .SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x1B, 0xFF, .SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x1B, 0xFF, .SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x1C, 0xFF, .SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x1D, 0xFF, .SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x1D, 0xFF, .SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x1D, 0xFF, .SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x20, 0xFF, .AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x21, 0xFF, .AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x21, 0xFF, .AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x21, 0xFF, .AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x22, 0xFF, .AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x23, 0xFF, .AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x23, 0xFF, .AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x23, 0xFF, .AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x24, 0xFF, .AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x25, 0xFF, .AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x25, 0xFF, .AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x25, 0xFF, .AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x28, 0xFF, .SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x29, 0xFF, .SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x29, 0xFF, .SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x29, 0xFF, .SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2A, 0xFF, .SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2B, 0xFF, .SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2B, 0xFF, .SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2C, 0xFF, .SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x2D, 0xFF, .SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x2D, 0xFF, .SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x2D, 0xFF, .SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x30, 0xFF, .XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x31, 0xFF, .XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x32, 0xFF, .XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x33, 0xFF, .XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x33, 0xFF, .XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x33, 0xFF, .XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x34, 0xFF, .XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x35, 0xFF, .XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x35, 0xFF, .XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x35, 0xFF, .XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x38, 0xFF, .CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x39, 0xFF, .CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x39, 0xFF, .CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x3A, 0xFF, .CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x3B, 0xFF, .CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x3C, 0xFF, .CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x3D, 0xFF, .CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x3D, 0xFF, .CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, + {.NONE, 0, 0x40, 0xFF, .INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, + {.NONE, 0, 0x48, 0xFF, .DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, + {.NONE, 0, 0x48, 0xFF, .DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, + {.NONE, 0, 0x50, 0xFF, .PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x50, 0xFF, .PUSH, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, + {.NONE, 0, 0x58, 0xFF, .POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, + {.NONE, 0, 0x58, 0xFF, .POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x62, 0xFF, .BOUND, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x62, 0xFF, .BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x63, 0xFF, .MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x63, 0xFF, .ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x69, 0xFF, .IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, {op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x69, 0xFF, .IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x69, 0xFF, .IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x6A, 0xFF, .PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, + {.NONE, 0, 0x70, 0xFF, .JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x71, 0xFF, .JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x72, 0xFF, .JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x72, 0xFF, .JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x72, 0xFF, .JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x73, 0xFF, .JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x73, 0xFF, .JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x74, 0xFF, .JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x74, 0xFF, .JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x75, 0xFF, .JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x75, 0xFF, .JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x76, 0xFF, .JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x76, 0xFF, .JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x77, 0xFF, .JNBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x77, 0xFF, .JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x78, 0xFF, .JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x79, 0xFF, .JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7A, 0xFF, .JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7A, 0xFF, .JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7B, 0xFF, .JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7B, 0xFF, .JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7C, 0xFF, .JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7C, 0xFF, .JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7D, 0xFF, .JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7D, 0xFF, .JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7E, 0xFF, .JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7E, 0xFF, .JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7F, 0xFF, .JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x80, 0x00, .ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x80, 0x01, .OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x80, 0x02, .ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x80, 0x03, .SBB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x80, 0x04, .AND, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x80, 0x05, .SUB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x80, 0x06, .XOR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x80, 0x07, .CMP, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x00, .ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x00, .ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x00, .ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x02, .ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x02, .ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x02, .ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x03, .SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x03, .SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x03, .SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x04, .AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x04, .AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x04, .AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x05, .SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x05, .SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x05, .SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x06, .XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x06, .XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x06, .XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x07, .CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x07, .CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x07, .CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x00, .ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x00, .ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x00, .ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x01, .OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x01, .OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x01, .OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x02, .ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x02, .ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x02, .ADC, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x03, .SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x03, .SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x03, .SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x04, .AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x04, .AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x04, .AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x05, .SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x05, .SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x05, .SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x06, .XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x06, .XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x06, .XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x07, .CMP, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x07, .CMP, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x07, .CMP, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x84, 0xFF, .TEST, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x85, 0xFF, .TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x85, 0xFF, .TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x85, 0xFF, .TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x86, 0xFF, .XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x88, 0xFF, .MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x89, 0xFF, .MOV, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x89, 0xFF, .MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x89, 0xFF, .MOV, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8A, 0xFF, .MOV, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8B, 0xFF, .MOV, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8B, 0xFF, .MOV, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8B, 0xFF, .MOV, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8C, 0xFF, .MOV, {.RM64, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8C, 0xFF, .MOV, {.RM16, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8D, 0xFF, .LEA, {.R64, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8D, 0xFF, .LEA, {.R16, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8D, 0xFF, .LEA, {.R32, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x8F, 0x00, .POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0x8F, 0x00, .POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0x90, 0xFF, .XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x90, 0xFF, .XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x90, 0xFF, .XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x90, 0xFF, .NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x98, 0xFF, .CDQE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0x98, 0xFF, .CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, @@ -393,22 +393,22 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0x9D, 0xFF, .POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9E, 0xFF, .SAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9F, 0xFF, .LAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA0, 0xFF, .MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA0, 0xFF, .MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0xA1, 0xFF, .MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA1, 0xFF, .MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA1, 0xFF, .MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0xA2, 0xFF, .MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA2, 0xFF, .MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true}}, + {.NONE, 0, 0xA0, 0xFF, .MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA0, 0xFF, .MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0xA1, 0xFF, .MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA1, 0xFF, .MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA1, 0xFF, .MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0xA2, 0xFF, .MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA2, 0xFF, .MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xA4, 0xFF, .MOVS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA4, 0xFF, .MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, @@ -419,10 +419,10 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xA7, 0xFF, .CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xA8, 0xFF, .TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA9, 0xFF, .TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {}}, - {.NONE, 0, 0xA9, 0xFF, .TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true}}, + {.NONE, 0, 0xA8, 0xFF, .TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA9, 0xFF, .TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xA9, 0xFF, .TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xAA, 0xFF, .STOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAA, 0xFF, .STOSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, @@ -438,137 +438,137 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xAF, 0xFF, .SCASQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xB0, 0xFF, .MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, {}}, - {.NONE, 0, 0xB8, 0xFF, .MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0xB8, 0xFF, .MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, {}}, - {.NONE, 0, 0xB8, 0xFF, .MOV, {.R16, .IMM16, .NONE, .NONE}, {.OP_R, .IW, .NONE, .NONE}, {}}, - {.NONE, 0, 0xB8, 0xFF, .MOV, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0xC0, 0x00, .ROL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC0, 0x01, .ROR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC0, 0x02, .RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC0, 0x03, .RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC0, 0x04, .SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC0, 0x05, .SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC0, 0x07, .SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x00, .ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x00, .ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x01, .ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x01, .ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x02, .RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x02, .RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x02, .RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x03, .RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x03, .RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x03, .RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x04, .SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x04, .SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x04, .SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x05, .SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x05, .SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x05, .SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x07, .SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x07, .SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC1, 0x07, .SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xC2, 0xFF, .RET, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xB0, 0xFF, .MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xB8, 0xFF, .MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0xB8, 0xFF, .MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xB8, 0xFF, .MOV, {.R16, .IMM16, .NONE, .NONE}, {.OP_R, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xB8, 0xFF, .MOV, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0xC0, 0x00, .ROL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC0, 0x01, .ROR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC0, 0x02, .RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC0, 0x03, .RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC0, 0x04, .SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC0, 0x05, .SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC0, 0x07, .SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x00, .ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x00, .ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x01, .ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x01, .ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x02, .RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x02, .RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x02, .RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x03, .RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x03, .RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x03, .RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x04, .SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x04, .SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x04, .SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x05, .SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x05, .SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x05, .SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x07, .SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x07, .SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x07, .SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC2, 0xFF, .RET, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xC3, 0xFF, .RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xC6, 0x00, .MOV, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC7, 0x00, .MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xC7, 0x00, .MOV, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC7, 0x00, .MOV, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xC8, 0xFF, .ENTER, {.IMM16, .IMM8, .NONE, .NONE}, {.IW, .IB, .NONE, .NONE}, {}}, + {.NONE, 0, 0xC6, 0x00, .MOV, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC7, 0x00, .MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC7, 0x00, .MOV, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC7, 0x00, .MOV, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC8, 0xFF, .ENTER, {.IMM16, .IMM8, .NONE, .NONE}, {.IW, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xC9, 0xFF, .LEAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCC, 0xFF, .INT3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xCD, 0xFF, .INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xCD, 0xFF, .INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xCE, 0xFF, .INTO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCF, 0xFF, .IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0xCF, 0xFF, .IRETD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCF, 0xFF, .IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD0, 0x00, .ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD0, 0x01, .ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD0, 0x02, .RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD0, 0x03, .RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD0, 0x04, .SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD0, 0x05, .SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD0, 0x07, .SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x00, .ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x00, .ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x00, .ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x01, .ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x01, .ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x01, .ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x02, .RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x02, .RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x02, .RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x03, .RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x03, .RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x03, .RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x04, .SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x04, .SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x04, .SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x05, .SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x05, .SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x05, .SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x07, .SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x07, .SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD1, 0x07, .SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD2, 0x00, .ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD2, 0x01, .ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD2, 0x02, .RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD2, 0x03, .RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD2, 0x04, .SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD2, 0x05, .SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD2, 0x07, .SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x00, .ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x00, .ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x00, .ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x01, .ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x01, .ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x01, .ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x02, .RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x02, .RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x02, .RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x03, .RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x03, .RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x03, .RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x04, .SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x04, .SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x04, .SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x05, .SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x05, .SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x05, .SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x07, .SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x07, .SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD3, 0x07, .SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, + {.NONE, 0, 0xD0, 0x00, .ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD0, 0x01, .ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD0, 0x02, .RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD0, 0x03, .RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD0, 0x04, .SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD0, 0x05, .SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD0, 0x07, .SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x00, .ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x00, .ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x00, .ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x01, .ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x01, .ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x01, .ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x02, .RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x02, .RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x02, .RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x03, .RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x03, .RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x03, .RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x04, .SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x04, .SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x04, .SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x05, .SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x05, .SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x05, .SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x07, .SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x07, .SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x07, .SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD2, 0x00, .ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD2, 0x01, .ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD2, 0x02, .RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD2, 0x03, .RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD2, 0x04, .SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD2, 0x05, .SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD2, 0x07, .SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x00, .ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x00, .ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x00, .ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x01, .ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x01, .ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x01, .ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x02, .RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x02, .RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x02, .RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x03, .RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x03, .RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x03, .RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x04, .SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x04, .SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x04, .SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x05, .SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x05, .SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x05, .SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x07, .SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x07, .SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x07, .SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD7, 0xFF, .XLATB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD7, 0xFF, .XLAT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD8, 0x01, .FMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD8, 0x02, .FCOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD8, 0x03, .FCOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD8, 0x04, .FSUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD8, 0x05, .FSUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD8, 0x06, .FDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD8, 0x07, .FDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD8, 0xFF, .FSUB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, + {.NONE, 0, 0xD8, 0x01, .FMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD8, 0x02, .FCOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD8, 0x03, .FCOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD8, 0x04, .FSUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD8, 0x05, .FSUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD8, 0x06, .FDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD8, 0x07, .FDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD8, 0xFF, .FSUB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xD8, 0xFF, .FCOMP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD8, 0xFF, .FCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD8, 0xFF, .FDIVR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD8, 0xFF, .FDIV, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD8, 0xFF, .FMUL, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD8, 0xFF, .FCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD8, 0xFF, .FSUBR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD8, 0xFF, .FADD, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, + {.NONE, 0, 0xD8, 0xFF, .FCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xD8, 0xFF, .FDIVR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xD8, 0xFF, .FDIV, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xD8, 0xFF, .FMUL, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xD8, 0xFF, .FCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xD8, 0xFF, .FSUBR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xD8, 0xFF, .FADD, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xD8, 0xFF, .FCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD8, 0xFF, .FADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD9, 0x02, .FST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD9, 0x03, .FSTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD9, 0x04, .FLDENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD9, 0x05, .FLDCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD9, 0x06, .FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD9, 0x06, .FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD9, 0x07, .FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xD9, 0x07, .FSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, + {.NONE, 0, 0xD8, 0xFF, .FADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0x02, .FST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0x03, .FSTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0x04, .FLDENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0x05, .FLDCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0x06, .FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0x06, .FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0x07, .FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xD9, 0x07, .FSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0xFF, .FYL2X, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FLDL2E, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FYL2XP1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, @@ -576,7 +576,7 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0xFF, .FXTRACT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FLD1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD9, 0xFF, .FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xD9, 0xFF, .FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0xFF, .FINCSTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FNOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FSINCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, @@ -586,7 +586,7 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0xFF, .F2XM1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FCHS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FPREM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD9, 0xFF, .FLD, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xD9, 0xFF, .FLD, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xD9, 0xFF, .FSCALE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FABS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FSIN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, @@ -597,191 +597,191 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0xFF, .FPTAN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FSQRT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FLDL2T, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD9, 0xFF, .FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xD9, 0xFF, .FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xD9, 0xFF, .FRNDINT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FLDLG2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFF, .FDECSTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDA, 0x01, .FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDA, 0x02, .FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDA, 0x03, .FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDA, 0x04, .FISUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDA, 0x05, .FISUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDA, 0x06, .FIDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDA, 0x07, .FIDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDA, 0xFF, .FCMOVB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, + {.NONE, 0, 0xDA, 0x01, .FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDA, 0x02, .FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDA, 0x03, .FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDA, 0x04, .FISUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDA, 0x05, .FISUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDA, 0x06, .FIDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDA, 0x07, .FIDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDA, 0xFF, .FCMOVB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDA, 0xFF, .FUCOMPP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDA, 0xFF, .FIADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDA, 0xFF, .FCMOVBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDA, 0xFF, .FCMOVU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDA, 0xFF, .FCMOVE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDB, 0x01, .FISTTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDB, 0x02, .FIST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDB, 0x03, .FISTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDB, 0x05, .FLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDB, 0x07, .FSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDB, 0xFF, .FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDB, 0xFF, .FCMOVNB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, + {.NONE, 0, 0xDA, 0xFF, .FIADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDA, 0xFF, .FCMOVBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDA, 0xFF, .FCMOVU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDA, 0xFF, .FCMOVE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDB, 0x01, .FISTTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDB, 0x02, .FIST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDB, 0x03, .FISTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDB, 0x05, .FLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDB, 0x07, .FSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDB, 0xFF, .FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDB, 0xFF, .FCMOVNB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xFF, .FNCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xFF, .FNINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDB, 0xFF, .FILD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xDB, 0xFF, .FILD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDB, 0xFF, .FINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xFF, .FCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDB, 0xFF, .FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDB, 0xFF, .FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDB, 0xFF, .FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDB, 0xFF, .FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDC, 0x01, .FMUL, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDC, 0x02, .FCOM, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDC, 0x03, .FCOMP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDC, 0x04, .FSUB, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDC, 0x05, .FSUBR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDC, 0x06, .FDIV, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDC, 0x07, .FDIVR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDC, 0xFF, .FDIV, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDC, 0xFF, .FSUBR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDC, 0xFF, .FDIVR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDC, 0xFF, .FSUB, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDC, 0xFF, .FMUL, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDC, 0xFF, .FADD, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDC, 0xFF, .FADD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDD, 0x01, .FISTTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDD, 0x02, .FST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDD, 0x03, .FSTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDD, 0x04, .FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDD, 0x06, .FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDD, 0x06, .FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDD, 0x07, .FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDD, 0x07, .FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDD, 0xFF, .FST, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDD, 0xFF, .FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDD, 0xFF, .FSTP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDD, 0xFF, .FLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDD, 0xFF, .FUCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xDB, 0xFF, .FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDB, 0xFF, .FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDB, 0xFF, .FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDB, 0xFF, .FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDC, 0x01, .FMUL, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDC, 0x02, .FCOM, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDC, 0x03, .FCOMP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDC, 0x04, .FSUB, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDC, 0x05, .FSUBR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDC, 0x06, .FDIV, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDC, 0x07, .FDIVR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDC, 0xFF, .FDIV, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDC, 0xFF, .FSUBR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDC, 0xFF, .FDIVR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDC, 0xFF, .FSUB, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDC, 0xFF, .FMUL, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDC, 0xFF, .FADD, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDC, 0xFF, .FADD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0x01, .FISTTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0x02, .FST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0x03, .FSTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0x04, .FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0x06, .FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0x06, .FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0x07, .FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0x07, .FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0xFF, .FST, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xDD, 0xFF, .FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xDD, 0xFF, .FSTP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xDD, 0xFF, .FLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDD, 0xFF, .FUCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDD, 0xFF, .FUCOMP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDD, 0xFF, .FUCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xDD, 0xFF, .FUCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDD, 0xFF, .FUCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDE, 0x01, .FIMUL, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDE, 0x02, .FICOM, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDE, 0x03, .FICOMP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDE, 0x04, .FISUB, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDE, 0x05, .FISUBR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDE, 0x06, .FIDIV, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDE, 0x07, .FIDIVR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, + {.NONE, 0, 0xDE, 0x01, .FIMUL, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDE, 0x02, .FICOM, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDE, 0x03, .FICOMP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDE, 0x04, .FISUB, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDE, 0x05, .FISUBR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDE, 0x06, .FIDIV, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDE, 0x07, .FIDIVR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDE, 0xFF, .FSUBRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDE, 0xFF, .FSUBP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, + {.NONE, 0, 0xDE, 0xFF, .FSUBP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDE, 0xFF, .FADDP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDE, 0xFF, .FDIVRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDE, 0xFF, .FADDP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDE, 0xFF, .FIADD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xDE, 0xFF, .FADDP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDE, 0xFF, .FIADD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDE, 0xFF, .FCOMPP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDE, 0xFF, .FSUBRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDE, 0xFF, .FMULP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDE, 0xFF, .FDIVRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, + {.NONE, 0, 0xDE, 0xFF, .FSUBRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDE, 0xFF, .FMULP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDE, 0xFF, .FDIVRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDE, 0xFF, .FSUBP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDE, 0xFF, .FMULP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDE, 0xFF, .FDIVP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDE, 0xFF, .FDIVP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDF, 0x01, .FISTTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDF, 0x02, .FIST, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDF, 0x03, .FISTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDF, 0x04, .FBLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDF, 0x05, .FILD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDF, 0x06, .FBSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDF, 0x07, .FISTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xDF, 0xFF, .FFREEP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDF, 0xFF, .FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDF, 0xFF, .FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDF, 0xFF, .FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDF, 0xFF, .FILD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDF, 0xFF, .FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xE0, 0xFF, .LOOPNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xE1, 0xFF, .LOOPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xE2, 0xFF, .LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xE3, 0xFF, .JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xE3, 0xFF, .JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xE3, 0xFF, .JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {force_rex_w=true}}, - {.NONE, 0, 0xE8, 0xFF, .CALL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xE9, 0xFF, .JMP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xEB, 0xFF, .JMP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xDE, 0xFF, .FDIVP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDF, 0x01, .FISTTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDF, 0x02, .FIST, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDF, 0x03, .FISTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDF, 0x04, .FBLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDF, 0x05, .FILD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDF, 0x06, .FBSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDF, 0x07, .FISTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDF, 0xFF, .FFREEP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xDF, 0xFF, .FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDF, 0xFF, .FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xDF, 0xFF, .FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xDF, 0xFF, .FILD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xDF, 0xFF, .FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xE0, 0xFF, .LOOPNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xE1, 0xFF, .LOOPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xE2, 0xFF, .LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xE3, 0xFF, .JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xE3, 0xFF, .JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xE3, 0xFF, .JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {force_rex_w=true, op_count=1}}, + {.NONE, 0, 0xE8, 0xFF, .CALL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xE9, 0xFF, .JMP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xEB, 0xFF, .JMP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xF0, 0xFF, .LOCK, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xF4, 0xFF, .HLT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xF5, 0xFF, .CMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xF6, 0x00, .TEST, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF6, 0x02, .NOT, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF6, 0x03, .NEG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF6, 0x04, .MUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF6, 0x05, .IMUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF6, 0x06, .DIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF6, 0x07, .IDIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x00, .TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x00, .TEST, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x00, .TEST, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x02, .NOT, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x02, .NOT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x02, .NOT, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x03, .NEG, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x03, .NEG, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x03, .NEG, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x04, .MUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x04, .MUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x04, .MUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x06, .DIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x06, .DIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x06, .DIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x07, .IDIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x07, .IDIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xF7, 0x07, .IDIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, + {.NONE, 0, 0xF6, 0x00, .TEST, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xF6, 0x02, .NOT, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF6, 0x03, .NEG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF6, 0x04, .MUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF6, 0x05, .IMUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF6, 0x06, .DIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF6, 0x07, .IDIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x00, .TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x00, .TEST, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x00, .TEST, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x02, .NOT, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x02, .NOT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x02, .NOT, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x03, .NEG, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x03, .NEG, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x03, .NEG, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x04, .MUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x04, .MUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x04, .MUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x06, .DIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x06, .DIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x06, .DIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x07, .IDIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x07, .IDIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x07, .IDIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF8, 0xFF, .CLC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xF9, 0xFF, .STC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xFA, 0xFF, .CLI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xFB, 0xFF, .STI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xFC, 0xFF, .CLD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xFD, 0xFF, .STD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xFE, 0x00, .INC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFE, 0x01, .DEC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x00, .INC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x00, .INC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x00, .INC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x01, .DEC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x01, .DEC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x01, .DEC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x02, .CALL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x04, .JMP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x06, .PUSH, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true}}, - {.NONE, 0, 0xFF, 0x06, .PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true}}, + {.NONE, 0, 0xFE, 0x00, .INC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFE, 0x01, .DEC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x00, .INC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x00, .INC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x00, .INC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x01, .DEC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x01, .DEC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x01, .DEC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x02, .CALL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x04, .JMP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x06, .PUSH, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x06, .PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 2, 0x90, 0xFF, .PAUSE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {prefix=2}}, - {._0F, 0, 0x00, 0x00, .SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x00, 0x01, .STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x00, 0x01, .STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x00, 0x02, .LLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x00, 0x03, .LTR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x00, 0x04, .VERR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x00, 0x05, .VERW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x00, .SGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x00, .SGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x01, .SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x01, .SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x02, .LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x02, .LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x03, .LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x03, .LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x04, .SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x04, .SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x04, .SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x06, .LMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x01, 0x07, .INVLPG, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, + {._0F, 0, 0x00, 0x00, .SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x01, .STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x01, .STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x02, .LLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x03, .LTR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x04, .VERR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x05, .VERW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x00, .SGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x00, .SGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x01, .SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x01, .SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x02, .LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x02, .LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x03, .LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x03, .LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x04, .SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x04, .SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x04, .SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x06, .LMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x07, .INVLPG, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0xFF, .ENCLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xFF, .RDPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xFF, .VMFUNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, @@ -795,1719 +795,1719 @@ LEGACY_DECODE_ENTRIES := [1270]lib.Decode_Entry{ {._0F, 0, 0x01, 0xFF, .RDTSCP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xFF, .XGETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xFF, .XSETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x03, 0xFF, .LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x03, 0xFF, .LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x03, 0xFF, .LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x03, 0xFF, .LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x03, 0xFF, .LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x03, 0xFF, .LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x05, 0xFF, .SYSCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x06, 0xFF, .CLTS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x07, 0xFF, .SYSRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x08, 0xFF, .INVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x09, 0xFF, .WBINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x0B, 0xFF, .UD2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x0D, 0x01, .PREFETCHW, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x10, 0xFF, .MOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x11, 0xFF, .MOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x12, 0xFF, .MOVHLPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x12, 0xFF, .MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x13, 0xFF, .MOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x14, 0xFF, .UNPCKLPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x15, 0xFF, .UNPCKHPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x16, 0xFF, .MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x16, 0xFF, .MOVLHPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x17, 0xFF, .MOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x18, 0x00, .PREFETCHNTA, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x18, 0x01, .PREFETCHT0, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x18, 0x02, .PREFETCHT1, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x18, 0x03, .PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x1C, 0x00, .CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x1F, 0x00, .NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0x1F, 0x00, .NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0x20, 0xFF, .MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x21, 0xFF, .MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x22, 0xFF, .MOV, {.CR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x23, 0xFF, .MOV, {.DR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x28, 0xFF, .MOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x29, 0xFF, .MOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x2B, 0xFF, .MOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x2E, 0xFF, .UCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x2F, 0xFF, .COMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x0D, 0x01, .PREFETCHW, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x10, 0xFF, .MOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x11, 0xFF, .MOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x12, 0xFF, .MOVHLPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x12, 0xFF, .MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x13, 0xFF, .MOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x14, 0xFF, .UNPCKLPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x15, 0xFF, .UNPCKHPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x16, 0xFF, .MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x16, 0xFF, .MOVLHPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x17, 0xFF, .MOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x18, 0x00, .PREFETCHNTA, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x18, 0x01, .PREFETCHT0, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x18, 0x02, .PREFETCHT1, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x18, 0x03, .PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x1C, 0x00, .CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x1F, 0x00, .NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x1F, 0x00, .NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x20, 0xFF, .MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x21, 0xFF, .MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x22, 0xFF, .MOV, {.CR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x23, 0xFF, .MOV, {.DR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x28, 0xFF, .MOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x29, 0xFF, .MOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x2B, 0xFF, .MOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x2E, 0xFF, .UCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x2F, 0xFF, .COMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x30, 0xFF, .WRMSR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x31, 0xFF, .RDTSC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x32, 0xFF, .RDMSR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x33, 0xFF, .RDPMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x34, 0xFF, .SYSENTER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x35, 0xFF, .SYSEXIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x40, 0xFF, .CMOVO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x40, 0xFF, .CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x40, 0xFF, .CMOVO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x42, 0xFF, .CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x44, 0xFF, .CMOVE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x44, 0xFF, .CMOVE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x44, 0xFF, .CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x47, 0xFF, .CMOVA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x48, 0xFF, .CMOVS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x48, 0xFF, .CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x48, 0xFF, .CMOVS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0x51, 0xFF, .SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x52, 0xFF, .RSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x53, 0xFF, .RCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x54, 0xFF, .ANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x55, 0xFF, .ANDNPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x56, 0xFF, .ORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x57, 0xFF, .XORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x58, 0xFF, .ADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x59, 0xFF, .MULPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x5A, 0xFF, .CVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x5B, 0xFF, .CVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x5C, 0xFF, .SUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x5D, 0xFF, .MINPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x5E, 0xFF, .DIVPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x5F, 0xFF, .MAXPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x6E, 0xFF, .MOVD, {.MM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x6F, 0xFF, .MOVQ, {.MM, .MM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x70, 0xFF, .PSHUFW, {.MM, .MM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F}}, - {._0F, 0, 0x78, 0xFF, .VMREAD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x79, 0xFF, .VMWRITE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x7E, 0xFF, .MOVD, {.RM32, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x7F, 0xFF, .MOVQ, {.MM_M64, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x80, 0xFF, .JO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x81, 0xFF, .JNO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x82, 0xFF, .JNAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x82, 0xFF, .JB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x82, 0xFF, .JC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x83, 0xFF, .JNC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x83, 0xFF, .JNB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x83, 0xFF, .JAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x84, 0xFF, .JZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x84, 0xFF, .JE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x85, 0xFF, .JNE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x85, 0xFF, .JNZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x86, 0xFF, .JNA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x86, 0xFF, .JBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x87, 0xFF, .JNBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x87, 0xFF, .JA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x88, 0xFF, .JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x89, 0xFF, .JNS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8A, 0xFF, .JP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8A, 0xFF, .JPE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8B, 0xFF, .JPO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8B, 0xFF, .JNP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8C, 0xFF, .JNGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8C, 0xFF, .JL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8D, 0xFF, .JNL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8D, 0xFF, .JGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8E, 0xFF, .JLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8E, 0xFF, .JNG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8F, 0xFF, .JNLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x8F, 0xFF, .JG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x90, 0xFF, .SETO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x91, 0xFF, .SETNO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x92, 0xFF, .SETNAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x92, 0xFF, .SETB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x92, 0xFF, .SETC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x93, 0xFF, .SETNC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x93, 0xFF, .SETNB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x93, 0xFF, .SETAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x94, 0xFF, .SETZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x94, 0xFF, .SETE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x95, 0xFF, .SETNZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x95, 0xFF, .SETNE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x96, 0xFF, .SETNA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x96, 0xFF, .SETBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x97, 0xFF, .SETNBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x97, 0xFF, .SETA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x98, 0xFF, .SETS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x99, 0xFF, .SETNS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9A, 0xFF, .SETP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9A, 0xFF, .SETPE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9B, 0xFF, .SETPO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9B, 0xFF, .SETNP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9C, 0xFF, .SETNGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9C, 0xFF, .SETL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9D, 0xFF, .SETNL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9D, 0xFF, .SETGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9E, 0xFF, .SETNG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9E, 0xFF, .SETLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9F, 0xFF, .SETNLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x9F, 0xFF, .SETG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xA0, 0xFF, .PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xA1, 0xFF, .POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0x40, 0xFF, .CMOVO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x40, 0xFF, .CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x40, 0xFF, .CMOVO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x44, 0xFF, .CMOVE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x44, 0xFF, .CMOVE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x44, 0xFF, .CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .CMOVA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .CMOVA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x48, 0xFF, .CMOVS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x48, 0xFF, .CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x48, 0xFF, .CMOVS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x51, 0xFF, .SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x52, 0xFF, .RSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x53, 0xFF, .RCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x54, 0xFF, .ANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x55, 0xFF, .ANDNPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x56, 0xFF, .ORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x57, 0xFF, .XORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x58, 0xFF, .ADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x59, 0xFF, .MULPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x5A, 0xFF, .CVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x5B, 0xFF, .CVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x5C, 0xFF, .SUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x5D, 0xFF, .MINPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x5E, 0xFF, .DIVPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x5F, 0xFF, .MAXPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x6E, 0xFF, .MOVD, {.MM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x6F, 0xFF, .MOVQ, {.MM, .MM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x70, 0xFF, .PSHUFW, {.MM, .MM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x78, 0xFF, .VMREAD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x79, 0xFF, .VMWRITE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x7E, 0xFF, .MOVD, {.RM32, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x7F, 0xFF, .MOVQ, {.MM_M64, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x80, 0xFF, .JO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x81, 0xFF, .JNO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x82, 0xFF, .JNAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x82, 0xFF, .JB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x82, 0xFF, .JC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x83, 0xFF, .JNC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x83, 0xFF, .JNB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x83, 0xFF, .JAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x84, 0xFF, .JZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x84, 0xFF, .JE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x85, 0xFF, .JNE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x85, 0xFF, .JNZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x86, 0xFF, .JNA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x86, 0xFF, .JBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x87, 0xFF, .JNBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x87, 0xFF, .JA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x88, 0xFF, .JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x89, 0xFF, .JNS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8A, 0xFF, .JP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8A, 0xFF, .JPE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8B, 0xFF, .JPO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8B, 0xFF, .JNP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8C, 0xFF, .JNGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8C, 0xFF, .JL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8D, 0xFF, .JNL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8D, 0xFF, .JGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8E, 0xFF, .JLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8E, 0xFF, .JNG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8F, 0xFF, .JNLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x8F, 0xFF, .JG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0x90, 0xFF, .SETO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x91, 0xFF, .SETNO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x92, 0xFF, .SETNAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x92, 0xFF, .SETB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x92, 0xFF, .SETC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x93, 0xFF, .SETNC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x93, 0xFF, .SETNB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x93, 0xFF, .SETAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x94, 0xFF, .SETZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x94, 0xFF, .SETE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x95, 0xFF, .SETNZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x95, 0xFF, .SETNE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x96, 0xFF, .SETNA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x96, 0xFF, .SETBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x97, 0xFF, .SETNBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x97, 0xFF, .SETA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x98, 0xFF, .SETS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x99, 0xFF, .SETNS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9A, 0xFF, .SETP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9A, 0xFF, .SETPE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9B, 0xFF, .SETPO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9B, 0xFF, .SETNP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9C, 0xFF, .SETNGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9C, 0xFF, .SETL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9D, 0xFF, .SETNL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9D, 0xFF, .SETGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9E, 0xFF, .SETNG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9E, 0xFF, .SETLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9F, 0xFF, .SETNLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x9F, 0xFF, .SETG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xA0, 0xFF, .PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0xA1, 0xFF, .POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xA2, 0xFF, .CPUID, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xA3, 0xFF, .BT, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xA3, 0xFF, .BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xA3, 0xFF, .BT, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F}}, - {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F}}, - {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F}}, - {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F}}, - {._0F, 0, 0xA8, 0xFF, .PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xA9, 0xFF, .POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F}}, + {._0F, 0, 0xA3, 0xFF, .BT, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xA3, 0xFF, .BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xA3, 0xFF, .BT, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xA8, 0xFF, .PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0xA9, 0xFF, .POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xAA, 0xFF, .RSM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xAB, 0xFF, .BTS, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xAB, 0xFF, .BTS, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xAB, 0xFF, .BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}}, - {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F}}, - {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F}}, - {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F}}, - {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F}}, - {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xAE, 0x00, .FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xAE, 0x00, .FXSAVE64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0xAE, 0x01, .FXRSTOR64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0xAE, 0x01, .FXRSTOR, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xAE, 0x04, .XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0xAE, 0x04, .XSAVE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xAE, 0x05, .XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0xAE, 0x05, .XRSTOR, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xAE, 0x06, .XSAVEOPT64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0xAE, 0x06, .XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xAE, 0x07, .CLFLUSH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, + {._0F, 0, 0xAB, 0xFF, .BTS, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xAB, 0xFF, .BTS, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xAB, 0xFF, .BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x00, .FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x00, .FXSAVE64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x01, .FXRSTOR64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x01, .FXRSTOR, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x04, .XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x04, .XSAVE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x05, .XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x05, .XRSTOR, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x06, .XSAVEOPT64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x06, .XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x07, .CLFLUSH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0xFF, .MFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0xAE, 0xFF, .SFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0xAE, 0xFF, .LFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xAF, 0xFF, .IMUL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xAF, 0xFF, .IMUL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xAF, 0xFF, .IMUL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xB0, 0xFF, .CMPXCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}}, - {._0F, 0, 0xB3, 0xFF, .BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}}, - {._0F, 0, 0xB3, 0xFF, .BTR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xB3, 0xFF, .BTR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xB7, 0xFF, .MOVZX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xB7, 0xFF, .MOVZX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xB9, 0xFF, .UD1, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xBA, 0x04, .BT, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xBA, 0x04, .BT, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xBA, 0x04, .BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0xBA, 0x05, .BTS, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {._0F, 0, 0xBA, 0x05, .BTS, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {._0F, 0, 0xBA, 0x05, .BTS, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {._0F, 0, 0xBA, 0x06, .BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {._0F, 0, 0xBA, 0x06, .BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {._0F, 0, 0xBA, 0x06, .BTR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {._0F, 0, 0xBA, 0x07, .BTC, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {._0F, 0, 0xBA, 0x07, .BTC, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {._0F, 0, 0xBA, 0x07, .BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {._0F, 0, 0xBB, 0xFF, .BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}}, - {._0F, 0, 0xBB, 0xFF, .BTC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xBB, 0xFF, .BTC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xBC, 0xFF, .BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xBC, 0xFF, .BSF, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xBC, 0xFF, .BSF, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xBD, 0xFF, .BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xBD, 0xFF, .BSR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xBD, 0xFF, .BSR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xC0, 0xFF, .XADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xC1, 0xFF, .XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true}}, - {._0F, 0, 0xC1, 0xFF, .XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xC1, 0xFF, .XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true}}, - {._0F, 0, 0xC2, 0xFF, .CMPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F}}, - {._0F, 0, 0xC6, 0xFF, .SHUFPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F}}, - {._0F, 0, 0xC7, 0x01, .CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x01, .CMPXCHG16B, {.M128, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x03, .XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x03, .XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x04, .XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x04, .XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x05, .XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x05, .XSAVES64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x06, .RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x06, .VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x06, .RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x06, .RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x07, .RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x07, .VMPTRST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x07, .RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xC7, 0x07, .RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true}}, - {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true}}, - {._0F, 0, 0xFF, 0xFF, .UD0, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F}}, - {._0F, 1, 0x10, 0xFF, .MOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x11, 0xFF, .MOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x12, 0xFF, .MOVLPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x13, 0xFF, .MOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x14, 0xFF, .UNPCKLPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x15, 0xFF, .UNPCKHPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x16, 0xFF, .MOVHPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x17, 0xFF, .MOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x28, 0xFF, .MOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x29, 0xFF, .MOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x2B, 0xFF, .MOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x2E, 0xFF, .UCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x2F, 0xFF, .COMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}}, - {._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x51, 0xFF, .SQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x54, 0xFF, .ANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x55, 0xFF, .ANDNPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x56, 0xFF, .ORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x57, 0xFF, .XORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x58, 0xFF, .ADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x59, 0xFF, .MULPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x5A, 0xFF, .CVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x5B, 0xFF, .CVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x5C, 0xFF, .SUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x5D, 0xFF, .MINPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x5E, 0xFF, .DIVPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x5F, 0xFF, .MAXPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x60, 0xFF, .PUNPCKLBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x61, 0xFF, .PUNPCKLWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x62, 0xFF, .PUNPCKLDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x63, 0xFF, .PACKSSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x64, 0xFF, .PCMPGTB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x65, 0xFF, .PCMPGTW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x66, 0xFF, .PCMPGTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x67, 0xFF, .PACKUSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x68, 0xFF, .PUNPCKHBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x69, 0xFF, .PUNPCKHWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x6A, 0xFF, .PUNPCKHDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x6B, 0xFF, .PACKSSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x6C, 0xFF, .PUNPCKLQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x6D, 0xFF, .PUNPCKHQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x6E, 0xFF, .MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x6E, 0xFF, .MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}}, - {._0F, 1, 0x6F, 0xFF, .MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x70, 0xFF, .PSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x71, 0x02, .PSRLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}}, - {._0F, 1, 0x71, 0x04, .PSRAW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}}, - {._0F, 1, 0x71, 0x06, .PSLLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x02, .PSRLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x04, .PSRAD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x06, .PSLLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}}, - {._0F, 1, 0x73, 0x02, .PSRLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}}, - {._0F, 1, 0x73, 0x06, .PSLLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}}, - {._0F, 1, 0x74, 0xFF, .PCMPEQB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x75, 0xFF, .PCMPEQW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x76, 0xFF, .PCMPEQD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x7C, 0xFF, .HADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x7D, 0xFF, .HSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x7E, 0xFF, .MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0x7E, 0xFF, .MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}}, - {._0F, 1, 0x7F, 0xFF, .MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xAE, 0x06, .CLWB, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}}, - {._0F, 1, 0xAE, 0x07, .CLFLUSHOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}}, - {._0F, 1, 0xC2, 0xFF, .CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .R32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .M16, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R64, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}}, - {._0F, 1, 0xC6, 0xFF, .SHUFPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xC7, 0x06, .VMCLEAR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true}}, - {._0F, 1, 0xD0, 0xFF, .ADDSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xD1, 0xFF, .PSRLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xD2, 0xFF, .PSRLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xD3, 0xFF, .PSRLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xD4, 0xFF, .PADDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xD5, 0xFF, .PMULLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xD6, 0xFF, .MOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xD7, 0xFF, .PMOVMSKB, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true}}, - {._0F, 1, 0xD7, 0xFF, .PMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xD8, 0xFF, .PSUBUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xD9, 0xFF, .PSUBUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xDA, 0xFF, .PMINUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xDB, 0xFF, .PAND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xDC, 0xFF, .PADDUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xDD, 0xFF, .PADDUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xDE, 0xFF, .PMAXUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xDF, 0xFF, .PANDN, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xE0, 0xFF, .PAVGB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xE1, 0xFF, .PSRAW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xE2, 0xFF, .PSRAD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xE3, 0xFF, .PAVGW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xE4, 0xFF, .PMULHUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xE5, 0xFF, .PMULHW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xE6, 0xFF, .CVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xE7, 0xFF, .MOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xE8, 0xFF, .PSUBSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xE9, 0xFF, .PSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xEA, 0xFF, .PMINSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xEB, 0xFF, .POR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xEC, 0xFF, .PADDSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xED, 0xFF, .PADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xEE, 0xFF, .PMAXSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xEF, 0xFF, .PXOR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xF1, 0xFF, .PSLLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xF2, 0xFF, .PSLLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xF3, 0xFF, .PSLLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xF4, 0xFF, .PMULUDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xF5, 0xFF, .PMADDWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xF6, 0xFF, .PSADBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xF7, 0xFF, .MASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xF8, 0xFF, .PSUBB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xF9, 0xFF, .PSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xFA, 0xFF, .PSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xFB, 0xFF, .PSUBQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xFC, 0xFF, .PADDB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xFD, 0xFF, .PADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 1, 0xFE, 0xFF, .PADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1}}, - {._0F, 2, 0x01, 0x05, .RSTORSSP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}}, + {._0F, 0, 0xAF, 0xFF, .IMUL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xAF, 0xFF, .IMUL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xAF, 0xFF, .IMUL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB0, 0xFF, .CMPXCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB3, 0xFF, .BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB3, 0xFF, .BTR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB3, 0xFF, .BTR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB7, 0xFF, .MOVZX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB7, 0xFF, .MOVZX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB9, 0xFF, .UD1, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x04, .BT, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x04, .BT, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x04, .BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x05, .BTS, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x05, .BTS, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x05, .BTS, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x06, .BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x06, .BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x06, .BTR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x07, .BTC, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x07, .BTC, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x07, .BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBB, 0xFF, .BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBB, 0xFF, .BTC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBB, 0xFF, .BTC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBC, 0xFF, .BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBC, 0xFF, .BSF, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBC, 0xFF, .BSF, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBD, 0xFF, .BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBD, 0xFF, .BSR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBD, 0xFF, .BSR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xC0, 0xFF, .XADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xC1, 0xFF, .XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xC1, 0xFF, .XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xC1, 0xFF, .XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xC2, 0xFF, .CMPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xC6, 0xFF, .SHUFPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x01, .CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x01, .CMPXCHG16B, {.M128, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x03, .XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x03, .XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x04, .XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x04, .XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x05, .XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x05, .XSAVES64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x06, .RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x06, .VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x06, .RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x06, .RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x07, .RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x07, .VMPTRST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x07, .RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x07, .RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, + {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=1}}, + {._0F, 0, 0xFF, 0xFF, .UD0, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x10, 0xFF, .MOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x11, 0xFF, .MOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x12, 0xFF, .MOVLPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x13, 0xFF, .MOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x14, 0xFF, .UNPCKLPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x15, 0xFF, .UNPCKHPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x16, 0xFF, .MOVHPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x17, 0xFF, .MOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x28, 0xFF, .MOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x29, 0xFF, .MOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x2B, 0xFF, .MOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x2E, 0xFF, .UCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x2F, 0xFF, .COMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x50, 0xFF, .MOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x51, 0xFF, .SQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x54, 0xFF, .ANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x55, 0xFF, .ANDNPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x56, 0xFF, .ORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x57, 0xFF, .XORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x58, 0xFF, .ADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x59, 0xFF, .MULPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x5A, 0xFF, .CVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x5B, 0xFF, .CVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x5C, 0xFF, .SUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x5D, 0xFF, .MINPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x5E, 0xFF, .DIVPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x5F, 0xFF, .MAXPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x60, 0xFF, .PUNPCKLBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x61, 0xFF, .PUNPCKLWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x62, 0xFF, .PUNPCKLDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x63, 0xFF, .PACKSSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x64, 0xFF, .PCMPGTB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x65, 0xFF, .PCMPGTW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x66, 0xFF, .PCMPGTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x67, 0xFF, .PACKUSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x68, 0xFF, .PUNPCKHBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x69, 0xFF, .PUNPCKHWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6A, 0xFF, .PUNPCKHDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6B, 0xFF, .PACKSSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6C, 0xFF, .PUNPCKLQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6D, 0xFF, .PUNPCKHQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6E, 0xFF, .MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6E, 0xFF, .MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6F, 0xFF, .MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x70, 0xFF, .PSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x71, 0x02, .PSRLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x71, 0x04, .PSRAW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x71, 0x06, .PSLLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x72, 0x02, .PSRLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x72, 0x04, .PSRAD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x72, 0x06, .PSLLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x73, 0x02, .PSRLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x73, 0x06, .PSLLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x74, 0xFF, .PCMPEQB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x75, 0xFF, .PCMPEQW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x76, 0xFF, .PCMPEQD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7C, 0xFF, .HADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7D, 0xFF, .HSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7E, 0xFF, .MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7E, 0xFF, .MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7F, 0xFF, .MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xAE, 0x06, .CLWB, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 1, 0xAE, 0x07, .CLFLUSHOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 1, 0xC2, 0xFF, .CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .R32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .M16, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R64, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xC6, 0xFF, .SHUFPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xC7, 0x06, .VMCLEAR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 1, 0xD0, 0xFF, .ADDSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD1, 0xFF, .PSRLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD2, 0xFF, .PSRLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD3, 0xFF, .PSRLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD4, 0xFF, .PADDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD5, 0xFF, .PMULLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD6, 0xFF, .MOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD7, 0xFF, .PMOVMSKB, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD7, 0xFF, .PMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD8, 0xFF, .PSUBUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD9, 0xFF, .PSUBUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xDA, 0xFF, .PMINUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xDB, 0xFF, .PAND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xDC, 0xFF, .PADDUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xDD, 0xFF, .PADDUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xDE, 0xFF, .PMAXUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xDF, 0xFF, .PANDN, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE0, 0xFF, .PAVGB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE1, 0xFF, .PSRAW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE2, 0xFF, .PSRAD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE3, 0xFF, .PAVGW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE4, 0xFF, .PMULHUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE5, 0xFF, .PMULHW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE6, 0xFF, .CVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE7, 0xFF, .MOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE8, 0xFF, .PSUBSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE9, 0xFF, .PSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xEA, 0xFF, .PMINSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xEB, 0xFF, .POR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xEC, 0xFF, .PADDSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xED, 0xFF, .PADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xEE, 0xFF, .PMAXSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xEF, 0xFF, .PXOR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xF1, 0xFF, .PSLLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xF2, 0xFF, .PSLLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xF3, 0xFF, .PSLLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xF4, 0xFF, .PMULUDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xF5, 0xFF, .PMADDWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xF6, 0xFF, .PSADBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xF7, 0xFF, .MASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xF8, 0xFF, .PSUBB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xF9, 0xFF, .PSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xFA, 0xFF, .PSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xFB, 0xFF, .PSUBQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xFC, 0xFF, .PADDB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xFD, 0xFF, .PADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xFE, 0xFF, .PADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x01, 0x05, .RSTORSSP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0x01, 0xFF, .SETSSBSY, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, {._0F, 2, 0x01, 0xFF, .SAVEPREVSSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x10, 0xFF, .MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x11, 0xFF, .MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x12, 0xFF, .MOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x16, 0xFF, .MOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x1E, 0x01, .RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 2, 0x1E, 0x01, .RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}}, + {._0F, 2, 0x10, 0xFF, .MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x11, 0xFF, .MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x12, 0xFF, .MOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x16, 0xFF, .MOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x1E, 0x01, .RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0x1E, 0x01, .RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0x1E, 0xFF, .ENDBR64, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, {._0F, 2, 0x1E, 0xFF, .ENDBR32, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}}, - {._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}}, - {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}}, - {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x51, 0xFF, .SQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x52, 0xFF, .RSQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x53, 0xFF, .RCPSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x58, 0xFF, .ADDSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x59, 0xFF, .MULSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x5A, 0xFF, .CVTSS2SD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x5B, 0xFF, .CVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x5C, 0xFF, .SUBSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x5D, 0xFF, .MINSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x5E, 0xFF, .DIVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x5F, 0xFF, .MAXSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x6F, 0xFF, .MOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x70, 0xFF, .PSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x7E, 0xFF, .MOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x7F, 0xFF, .MOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0xAE, 0x05, .INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}}, - {._0F, 2, 0xAE, 0x05, .INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true}}, - {._0F, 2, 0xAE, 0x06, .CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}}, - {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}}, - {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}}, - {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true}}, - {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0xC2, 0xFF, .CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0xC7, 0x06, .VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true}}, - {._0F, 2, 0xE6, 0xFF, .CVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 3, 0x10, 0xFF, .MOVSD_SSE, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x11, 0xFF, .MOVSD_SSE, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x12, 0xFF, .MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true}}, - {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true}}, - {._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x2D, 0xFF, .CVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x2D, 0xFF, .CVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true}}, - {._0F, 3, 0x51, 0xFF, .SQRTSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x58, 0xFF, .ADDSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x59, 0xFF, .MULSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x5A, 0xFF, .CVTSD2SS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x5C, 0xFF, .SUBSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x5D, 0xFF, .MINSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x5E, 0xFF, .DIVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x5F, 0xFF, .MAXSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x70, 0xFF, .PSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x7C, 0xFF, .HADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0x7D, 0xFF, .HSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0xC2, 0xFF, .CMPSD_SSE, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0xD0, 0xFF, .ADDSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0xE6, 0xFF, .CVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F, 3, 0xF0, 0xFF, .LDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3}}, - {._0F38, 0, 0xC8, 0xFF, .SHA1NEXTE, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}}, - {._0F38, 0, 0xC9, 0xFF, .SHA1MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}}, - {._0F38, 0, 0xCA, 0xFF, .SHA1MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}}, - {._0F38, 0, 0xCB, 0xFF, .SHA256RNDS2, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38}}, - {._0F38, 0, 0xCC, 0xFF, .SHA256MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}}, - {._0F38, 0, 0xCD, 0xFF, .SHA256MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}}, - {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}}, - {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38}}, - {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R64, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, force_rex_w=true}}, - {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38}}, - {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38}}, - {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true}}, - {._0F38, 0, 0xF6, 0xFF, .WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true}}, - {._0F38, 0, 0xF6, 0xFF, .WRSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38}}, - {._0F38, 1, 0x00, 0xFF, .PSHUFB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x01, 0xFF, .PHADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x02, 0xFF, .PHADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x03, 0xFF, .PHADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x04, 0xFF, .PMADDUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x05, 0xFF, .PHSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x06, 0xFF, .PHSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x07, 0xFF, .PHSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x08, 0xFF, .PSIGNB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x09, 0xFF, .PSIGNW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x0A, 0xFF, .PSIGND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x0B, 0xFF, .PMULHRSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x10, 0xFF, .PBLENDVB, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x14, 0xFF, .BLENDVPS, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x15, 0xFF, .BLENDVPD, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x17, 0xFF, .PTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x1C, 0xFF, .PABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x1D, 0xFF, .PABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x1E, 0xFF, .PABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x20, 0xFF, .PMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x21, 0xFF, .PMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x22, 0xFF, .PMOVSXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x23, 0xFF, .PMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x24, 0xFF, .PMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x25, 0xFF, .PMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x28, 0xFF, .PMULDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x29, 0xFF, .PCMPEQQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x2A, 0xFF, .MOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x2B, 0xFF, .PACKUSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x30, 0xFF, .PMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x31, 0xFF, .PMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x32, 0xFF, .PMOVZXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x33, 0xFF, .PMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x34, 0xFF, .PMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x35, 0xFF, .PMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x37, 0xFF, .PCMPGTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x38, 0xFF, .PMINSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x39, 0xFF, .PMINSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x3A, 0xFF, .PMINUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x3B, 0xFF, .PMINUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x3C, 0xFF, .PMAXSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x3D, 0xFF, .PMAXSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x3E, 0xFF, .PMAXUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x3F, 0xFF, .PMAXUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x40, 0xFF, .PMULLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x41, 0xFF, .PHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x80, 0xFF, .INVEPT, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x81, 0xFF, .INVVPID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x82, 0xFF, .INVPCID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0x82, 0xFF, .INVPCID, {.R32, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0xDB, 0xFF, .AESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0xDC, 0xFF, .AESENC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0xDD, 0xFF, .AESENCLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0xDE, 0xFF, .AESDEC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0xDF, 0xFF, .AESDECLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0xF5, 0xFF, .WRUSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 1, 0xF5, 0xFF, .WRUSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true}}, - {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true}}, - {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1}}, - {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true}}, - {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2}}, - {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true}}, - {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3}}, - {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true}}, - {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3}}, - {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3}}, - {._0F3A, 0, 0xCC, 0xFF, .SHA1RNDS4, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A}}, - {._0F3A, 1, 0x08, 0xFF, .ROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x09, 0xFF, .ROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x0A, 0xFF, .ROUNDSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x0B, 0xFF, .ROUNDSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x0C, 0xFF, .BLENDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x0D, 0xFF, .BLENDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x0E, 0xFF, .PBLENDW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x0F, 0xFF, .PALIGNR, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x14, 0xFF, .PEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x16, 0xFF, .PEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x16, 0xFF, .PEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, force_rex_w=true}}, - {._0F3A, 1, 0x17, 0xFF, .EXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x20, 0xFF, .PINSRB, {.XMM, .RM8, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x21, 0xFF, .INSERTPS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x22, 0xFF, .PINSRD, {.XMM, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x22, 0xFF, .PINSRQ, {.XMM, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, force_rex_w=true}}, - {._0F3A, 1, 0x40, 0xFF, .DPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x41, 0xFF, .DPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x42, 0xFF, .MPSADBW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x44, 0xFF, .PCLMULQDQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x60, 0xFF, .PCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x61, 0xFF, .PCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x62, 0xFF, .PCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0x63, 0xFF, .PCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, - {._0F3A, 1, 0xDF, 0xFF, .AESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1}}, + {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x51, 0xFF, .SQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x52, 0xFF, .RSQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x53, 0xFF, .RCPSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x58, 0xFF, .ADDSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x59, 0xFF, .MULSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x5A, 0xFF, .CVTSS2SD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x5B, 0xFF, .CVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x5C, 0xFF, .SUBSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x5D, 0xFF, .MINSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x5E, 0xFF, .DIVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x5F, 0xFF, .MAXSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x6F, 0xFF, .MOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x70, 0xFF, .PSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x7E, 0xFF, .MOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x7F, 0xFF, .MOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x05, .INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x05, .INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x06, .CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xC2, 0xFF, .CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, op_count=3, needs_modrm=true}}, + {._0F, 2, 0xC7, 0x06, .VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xE6, 0xFF, .CVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x10, 0xFF, .MOVSD_SSE, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x11, 0xFF, .MOVSD_SSE, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x12, 0xFF, .MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2D, 0xFF, .CVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2D, 0xFF, .CVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x51, 0xFF, .SQRTSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x58, 0xFF, .ADDSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x59, 0xFF, .MULSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x5A, 0xFF, .CVTSD2SS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x5C, 0xFF, .SUBSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x5D, 0xFF, .MINSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x5E, 0xFF, .DIVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x5F, 0xFF, .MAXSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x70, 0xFF, .PSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x7C, 0xFF, .HADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x7D, 0xFF, .HSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0xC2, 0xFF, .CMPSD_SSE, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, op_count=3, needs_modrm=true}}, + {._0F, 3, 0xD0, 0xFF, .ADDSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0xE6, 0xFF, .CVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0xF0, 0xFF, .LDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xC8, 0xFF, .SHA1NEXTE, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xC9, 0xFF, .SHA1MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xCA, 0xFF, .SHA1MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xCB, 0xFF, .SHA256RNDS2, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38, op_count=3, needs_modrm=true}}, + {._0F38, 0, 0xCC, 0xFF, .SHA256MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xCD, 0xFF, .SHA256MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R64, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF6, 0xFF, .WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF6, 0xFF, .WRSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x00, 0xFF, .PSHUFB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x01, 0xFF, .PHADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x02, 0xFF, .PHADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x03, 0xFF, .PHADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x04, 0xFF, .PMADDUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x05, 0xFF, .PHSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x06, 0xFF, .PHSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x07, 0xFF, .PHSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x08, 0xFF, .PSIGNB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x09, 0xFF, .PSIGNW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x0A, 0xFF, .PSIGND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x0B, 0xFF, .PMULHRSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x10, 0xFF, .PBLENDVB, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38, prefix=1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x14, 0xFF, .BLENDVPS, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38, prefix=1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x15, 0xFF, .BLENDVPD, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, {esc=._0F38, prefix=1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x17, 0xFF, .PTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1C, 0xFF, .PABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1D, 0xFF, .PABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1E, 0xFF, .PABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x20, 0xFF, .PMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x21, 0xFF, .PMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x22, 0xFF, .PMOVSXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x23, 0xFF, .PMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x24, 0xFF, .PMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x25, 0xFF, .PMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x28, 0xFF, .PMULDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x29, 0xFF, .PCMPEQQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x2A, 0xFF, .MOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x2B, 0xFF, .PACKUSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x30, 0xFF, .PMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x31, 0xFF, .PMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x32, 0xFF, .PMOVZXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x33, 0xFF, .PMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x34, 0xFF, .PMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x35, 0xFF, .PMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x37, 0xFF, .PCMPGTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x38, 0xFF, .PMINSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x39, 0xFF, .PMINSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x3A, 0xFF, .PMINUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x3B, 0xFF, .PMINUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x3C, 0xFF, .PMAXSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x3D, 0xFF, .PMAXSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x3E, 0xFF, .PMAXUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x3F, 0xFF, .PMAXUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x40, 0xFF, .PMULLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x41, 0xFF, .PHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x80, 0xFF, .INVEPT, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x81, 0xFF, .INVVPID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x82, 0xFF, .INVPCID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x82, 0xFF, .INVPCID, {.R32, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xDB, 0xFF, .AESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xDC, 0xFF, .AESENC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xDD, 0xFF, .AESENCLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xDE, 0xFF, .AESDEC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xDF, 0xFF, .AESDECLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xF5, 0xFF, .WRUSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xF5, 0xFF, .WRUSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xF6, 0xFF, .ADCX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0xF6, 0xFF, .ADOX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F3A, 0, 0xCC, 0xFF, .SHA1RNDS4, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x08, 0xFF, .ROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x09, 0xFF, .ROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x0A, 0xFF, .ROUNDSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x0B, 0xFF, .ROUNDSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x0C, 0xFF, .BLENDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x0D, 0xFF, .BLENDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x0E, 0xFF, .PBLENDW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x0F, 0xFF, .PALIGNR, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x14, 0xFF, .PEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x16, 0xFF, .PEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x16, 0xFF, .PEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, force_rex_w=true, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x17, 0xFF, .EXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x20, 0xFF, .PINSRB, {.XMM, .RM8, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x21, 0xFF, .INSERTPS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x22, 0xFF, .PINSRD, {.XMM, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x22, 0xFF, .PINSRQ, {.XMM, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, force_rex_w=true, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x40, 0xFF, .DPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x41, 0xFF, .DPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x42, 0xFF, .MPSADBW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x44, 0xFF, .PCLMULQDQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x60, 0xFF, .PCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x61, 0xFF, .PCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x62, 0xFF, .PCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x63, 0xFF, .PCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0xDF, 0xFF, .AESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, op_count=3, needs_modrm=true}}, } @(rodata) VEX_DECODE_ENTRIES := [667]lib.VEX_Decode_Entry{ - {._0F, 0, 0x10, 0xFF, .WIG, .L1, .VMOVUPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x10, 0xFF, .WIG, .L0, .VMOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x11, 0xFF, .WIG, .L0, .VMOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x11, 0xFF, .WIG, .L1, .VMOVUPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x12, 0xFF, .WIG, .L0, .VMOVHLPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x12, 0xFF, .WIG, .L0, .VMOVLPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x13, 0xFF, .WIG, .L0, .VMOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x14, 0xFF, .WIG, .L0, .VUNPCKLPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x14, 0xFF, .WIG, .L1, .VUNPCKLPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x15, 0xFF, .WIG, .L1, .VUNPCKHPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x15, 0xFF, .WIG, .L0, .VUNPCKHPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x16, 0xFF, .WIG, .L0, .VMOVHPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x16, 0xFF, .WIG, .L0, .VMOVLHPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x17, 0xFF, .WIG, .L0, .VMOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x28, 0xFF, .WIG, .L0, .VMOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x28, 0xFF, .WIG, .L1, .VMOVAPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x29, 0xFF, .WIG, .L0, .VMOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x29, 0xFF, .WIG, .L1, .VMOVAPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x2B, 0xFF, .WIG, .L1, .VMOVNTPS, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x2B, 0xFF, .WIG, .L0, .VMOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x2E, 0xFF, .WIG, .LIG, .VUCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX}}, - {._0F, 0, 0x2F, 0xFF, .WIG, .LIG, .VCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX}}, - {._0F, 0, 0x41, 0xFF, .W0, .L1, .KANDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 0, 0x41, 0xFF, .W1, .L1, .KANDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 0, 0x42, 0xFF, .W1, .L1, .KANDNQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 0, 0x42, 0xFF, .W0, .L1, .KANDNW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 0, 0x44, 0xFF, .W1, .L0, .KNOTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 0, 0x44, 0xFF, .W0, .L0, .KNOTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 0, 0x45, 0xFF, .W0, .L1, .KORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 0, 0x45, 0xFF, .W1, .L1, .KORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 0, 0x46, 0xFF, .W1, .L1, .KXNORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 0, 0x46, 0xFF, .W0, .L1, .KXNORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 0, 0x47, 0xFF, .W1, .L1, .KXORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 0, 0x47, 0xFF, .W0, .L1, .KXORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 0, 0x4A, 0xFF, .W0, .L1, .KADDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 0, 0x4A, 0xFF, .W1, .L1, .KADDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 0, 0x4B, 0xFF, .W1, .L1, .KUNPCKDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 0, 0x4B, 0xFF, .W0, .L1, .KUNPCKWD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 0, 0x50, 0xFF, .WIG, .L1, .VMOVMSKPS, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x50, 0xFF, .WIG, .L0, .VMOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x51, 0xFF, .WIG, .L1, .VSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x51, 0xFF, .WIG, .L0, .VSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x52, 0xFF, .WIG, .L1, .VRSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x52, 0xFF, .WIG, .L0, .VRSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x53, 0xFF, .WIG, .L0, .VRCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x53, 0xFF, .WIG, .L1, .VRCPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x54, 0xFF, .WIG, .L0, .VANDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x54, 0xFF, .WIG, .L1, .VANDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x55, 0xFF, .WIG, .L0, .VANDNPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x55, 0xFF, .WIG, .L1, .VANDNPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x56, 0xFF, .WIG, .L0, .VORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x56, 0xFF, .WIG, .L1, .VORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x57, 0xFF, .WIG, .L0, .VXORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x57, 0xFF, .WIG, .L1, .VXORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x58, 0xFF, .WIG, .L0, .VADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x58, 0xFF, .WIG, .L1, .VADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x59, 0xFF, .WIG, .L0, .VMULPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x59, 0xFF, .WIG, .L1, .VMULPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x5A, 0xFF, .WIG, .L1, .VCVTPS2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x5A, 0xFF, .WIG, .L0, .VCVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x5B, 0xFF, .WIG, .L1, .VCVTDQ2PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x5B, 0xFF, .WIG, .L0, .VCVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x5C, 0xFF, .WIG, .L0, .VSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x5C, 0xFF, .WIG, .L1, .VSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x5D, 0xFF, .WIG, .L1, .VMINPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x5D, 0xFF, .WIG, .L0, .VMINPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x5E, 0xFF, .WIG, .L0, .VDIVPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x5E, 0xFF, .WIG, .L1, .VDIVPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0x5F, 0xFF, .WIG, .L0, .VMAXPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x5F, 0xFF, .WIG, .L1, .VMAXPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {._0F, 0, 0x10, 0xFF, .WIG, .L1, .VMOVUPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x10, 0xFF, .WIG, .L0, .VMOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x11, 0xFF, .WIG, .L0, .VMOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x11, 0xFF, .WIG, .L1, .VMOVUPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x12, 0xFF, .WIG, .L0, .VMOVHLPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x12, 0xFF, .WIG, .L0, .VMOVLPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x13, 0xFF, .WIG, .L0, .VMOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x14, 0xFF, .WIG, .L0, .VUNPCKLPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x14, 0xFF, .WIG, .L1, .VUNPCKLPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x15, 0xFF, .WIG, .L1, .VUNPCKHPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x15, 0xFF, .WIG, .L0, .VUNPCKHPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x16, 0xFF, .WIG, .L0, .VMOVHPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x16, 0xFF, .WIG, .L0, .VMOVLHPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x17, 0xFF, .WIG, .L0, .VMOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x28, 0xFF, .WIG, .L0, .VMOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x28, 0xFF, .WIG, .L1, .VMOVAPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x29, 0xFF, .WIG, .L0, .VMOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x29, 0xFF, .WIG, .L1, .VMOVAPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x2B, 0xFF, .WIG, .L1, .VMOVNTPS, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x2B, 0xFF, .WIG, .L0, .VMOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x2E, 0xFF, .WIG, .LIG, .VUCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x2F, 0xFF, .WIG, .LIG, .VCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x41, 0xFF, .W0, .L1, .KANDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x41, 0xFF, .W1, .L1, .KANDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .W1, .L1, .KANDNQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .W0, .L1, .KANDNW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x44, 0xFF, .W1, .L0, .KNOTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x44, 0xFF, .W0, .L0, .KNOTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x45, 0xFF, .W0, .L1, .KORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x45, 0xFF, .W1, .L1, .KORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .W1, .L1, .KXNORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x46, 0xFF, .W0, .L1, .KXNORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .W1, .L1, .KXORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .W0, .L1, .KXORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .W0, .L1, .KADDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .W1, .L1, .KADDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .W1, .L1, .KUNPCKDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .W0, .L1, .KUNPCKWD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x50, 0xFF, .WIG, .L1, .VMOVMSKPS, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x50, 0xFF, .WIG, .L0, .VMOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x51, 0xFF, .WIG, .L1, .VSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x51, 0xFF, .WIG, .L0, .VSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x52, 0xFF, .WIG, .L1, .VRSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x52, 0xFF, .WIG, .L0, .VRSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x53, 0xFF, .WIG, .L0, .VRCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x53, 0xFF, .WIG, .L1, .VRCPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x54, 0xFF, .WIG, .L0, .VANDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x54, 0xFF, .WIG, .L1, .VANDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x55, 0xFF, .WIG, .L0, .VANDNPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x55, 0xFF, .WIG, .L1, .VANDNPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x56, 0xFF, .WIG, .L0, .VORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x56, 0xFF, .WIG, .L1, .VORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x57, 0xFF, .WIG, .L0, .VXORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x57, 0xFF, .WIG, .L1, .VXORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x58, 0xFF, .WIG, .L0, .VADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x58, 0xFF, .WIG, .L1, .VADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x59, 0xFF, .WIG, .L0, .VMULPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x59, 0xFF, .WIG, .L1, .VMULPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x5A, 0xFF, .WIG, .L1, .VCVTPS2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x5A, 0xFF, .WIG, .L0, .VCVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x5B, 0xFF, .WIG, .L1, .VCVTDQ2PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x5B, 0xFF, .WIG, .L0, .VCVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x5C, 0xFF, .WIG, .L0, .VSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x5C, 0xFF, .WIG, .L1, .VSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x5D, 0xFF, .WIG, .L1, .VMINPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x5D, 0xFF, .WIG, .L0, .VMINPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x5E, 0xFF, .WIG, .L0, .VDIVPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x5E, 0xFF, .WIG, .L1, .VDIVPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x5F, 0xFF, .WIG, .L0, .VMAXPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 0, 0x5F, 0xFF, .WIG, .L1, .VMAXPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, {._0F, 0, 0x77, 0xFF, .WIG, .L1, .VZEROALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {._0F, 0, 0x77, 0xFF, .WIG, .L0, .VZEROUPPER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0x90, 0xFF, .W1, .L0, .KMOVQ, {.K, .K_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 0, 0x90, 0xFF, .W0, .L0, .KMOVW, {.K, .K_M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 0, 0x91, 0xFF, .W1, .L0, .KMOVQ, {.M64, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 0, 0x91, 0xFF, .W0, .L0, .KMOVW, {.M16, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 0, 0x92, 0xFF, .W0, .L0, .KMOVW, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 0, 0x93, 0xFF, .W0, .L0, .KMOVW, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 0, 0x98, 0xFF, .W0, .L0, .KORTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 0, 0x98, 0xFF, .W1, .L0, .KORTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 0, 0x99, 0xFF, .W1, .L0, .KTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 0, 0x99, 0xFF, .W0, .L0, .KTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 0, 0xC2, 0xFF, .WIG, .L0, .VCMPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 0, 0xC2, 0xFF, .WIG, .L1, .VCMPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0xC6, 0xFF, .WIG, .L1, .VSHUFPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {._0F, 0, 0xC6, 0xFF, .WIG, .L0, .VSHUFPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x10, 0xFF, .WIG, .L0, .VMOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x10, 0xFF, .WIG, .L1, .VMOVUPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x11, 0xFF, .WIG, .L1, .VMOVUPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x11, 0xFF, .WIG, .L0, .VMOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x12, 0xFF, .WIG, .L0, .VMOVLPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x13, 0xFF, .WIG, .L0, .VMOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x14, 0xFF, .WIG, .L0, .VUNPCKLPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x14, 0xFF, .WIG, .L1, .VUNPCKLPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x15, 0xFF, .WIG, .L1, .VUNPCKHPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x15, 0xFF, .WIG, .L0, .VUNPCKHPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x16, 0xFF, .WIG, .L0, .VMOVHPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x17, 0xFF, .WIG, .L0, .VMOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x28, 0xFF, .WIG, .L0, .VMOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x28, 0xFF, .WIG, .L1, .VMOVAPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x29, 0xFF, .WIG, .L1, .VMOVAPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x29, 0xFF, .WIG, .L0, .VMOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x2B, 0xFF, .WIG, .L0, .VMOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x2B, 0xFF, .WIG, .L1, .VMOVNTPD, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x2E, 0xFF, .WIG, .LIG, .VUCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX}}, - {._0F, 1, 0x2F, 0xFF, .WIG, .LIG, .VCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX}}, - {._0F, 1, 0x41, 0xFF, .W1, .L1, .KANDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 1, 0x41, 0xFF, .W0, .L1, .KANDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 1, 0x42, 0xFF, .W0, .L1, .KANDNB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 1, 0x42, 0xFF, .W1, .L1, .KANDND, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 1, 0x44, 0xFF, .W1, .L0, .KNOTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 1, 0x44, 0xFF, .W0, .L0, .KNOTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 1, 0x45, 0xFF, .W0, .L1, .KORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 1, 0x45, 0xFF, .W1, .L1, .KORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 1, 0x46, 0xFF, .W1, .L1, .KXNORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 1, 0x46, 0xFF, .W0, .L1, .KXNORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 1, 0x47, 0xFF, .W1, .L1, .KXORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 1, 0x47, 0xFF, .W0, .L1, .KXORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 1, 0x4A, 0xFF, .W0, .L1, .KADDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 1, 0x4A, 0xFF, .W1, .L1, .KADDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 1, 0x4B, 0xFF, .W0, .L1, .KUNPCKBW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 1, 0x50, 0xFF, .WIG, .L0, .VMOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x50, 0xFF, .WIG, .L1, .VMOVMSKPD, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x51, 0xFF, .WIG, .L1, .VSQRTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x51, 0xFF, .WIG, .L0, .VSQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x54, 0xFF, .WIG, .L1, .VANDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x54, 0xFF, .WIG, .L0, .VANDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x55, 0xFF, .WIG, .L0, .VANDNPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x55, 0xFF, .WIG, .L1, .VANDNPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x56, 0xFF, .WIG, .L1, .VORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x56, 0xFF, .WIG, .L0, .VORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x57, 0xFF, .WIG, .L0, .VXORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x57, 0xFF, .WIG, .L1, .VXORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x58, 0xFF, .WIG, .L0, .VADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x58, 0xFF, .WIG, .L1, .VADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x59, 0xFF, .WIG, .L1, .VMULPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x59, 0xFF, .WIG, .L0, .VMULPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x5A, 0xFF, .WIG, .L0, .VCVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x5A, 0xFF, .WIG, .L1, .VCVTPD2PS, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x5B, 0xFF, .WIG, .L0, .VCVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x5B, 0xFF, .WIG, .L1, .VCVTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x5C, 0xFF, .WIG, .L1, .VSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x5C, 0xFF, .WIG, .L0, .VSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x5D, 0xFF, .WIG, .L0, .VMINPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x5D, 0xFF, .WIG, .L1, .VMINPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x5E, 0xFF, .WIG, .L1, .VDIVPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x5E, 0xFF, .WIG, .L0, .VDIVPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x5F, 0xFF, .WIG, .L0, .VMAXPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x5F, 0xFF, .WIG, .L1, .VMAXPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x60, 0xFF, .WIG, .L1, .VPUNPCKLBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x60, 0xFF, .WIG, .L0, .VPUNPCKLBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x61, 0xFF, .WIG, .L0, .VPUNPCKLWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x61, 0xFF, .WIG, .L1, .VPUNPCKLWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x62, 0xFF, .WIG, .L1, .VPUNPCKLDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x62, 0xFF, .WIG, .L0, .VPUNPCKLDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x63, 0xFF, .WIG, .L0, .VPACKSSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x63, 0xFF, .WIG, .L1, .VPACKSSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x64, 0xFF, .WIG, .L1, .VPCMPGTB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x64, 0xFF, .WIG, .L0, .VPCMPGTB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x65, 0xFF, .WIG, .L1, .VPCMPGTW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x65, 0xFF, .WIG, .L0, .VPCMPGTW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x66, 0xFF, .WIG, .L1, .VPCMPGTD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x66, 0xFF, .WIG, .L0, .VPCMPGTD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x67, 0xFF, .WIG, .L0, .VPACKUSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x67, 0xFF, .WIG, .L1, .VPACKUSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x68, 0xFF, .WIG, .L1, .VPUNPCKHBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x68, 0xFF, .WIG, .L0, .VPUNPCKHBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x69, 0xFF, .WIG, .L1, .VPUNPCKHWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x69, 0xFF, .WIG, .L0, .VPUNPCKHWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x6A, 0xFF, .WIG, .L0, .VPUNPCKHDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x6A, 0xFF, .WIG, .L1, .VPUNPCKHDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x6B, 0xFF, .WIG, .L0, .VPACKSSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x6B, 0xFF, .WIG, .L1, .VPACKSSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x6C, 0xFF, .WIG, .L0, .VPUNPCKLQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x6C, 0xFF, .WIG, .L1, .VPUNPCKLQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x6D, 0xFF, .WIG, .L0, .VPUNPCKHQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x6D, 0xFF, .WIG, .L1, .VPUNPCKHQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x6E, 0xFF, .WIG, .L0, .VMOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x6E, 0xFF, .W1, .L0, .VMOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 1, 0x6F, 0xFF, .WIG, .L1, .VMOVDQA, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x6F, 0xFF, .WIG, .L0, .VMOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x70, 0xFF, .WIG, .L0, .VPSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x70, 0xFF, .WIG, .L1, .VPSHUFD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x71, 0x02, .WIG, .L1, .VPSRLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, - {._0F, 1, 0x71, 0x02, .WIG, .L0, .VPSRLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {._0F, 1, 0x71, 0x04, .WIG, .L1, .VPSRAW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, - {._0F, 1, 0x71, 0x04, .WIG, .L0, .VPSRAW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {._0F, 1, 0x71, 0x06, .WIG, .L1, .VPSLLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, - {._0F, 1, 0x71, 0x06, .WIG, .L0, .VPSLLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x02, .WIG, .L0, .VPSRLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x02, .WIG, .L1, .VPSRLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x04, .WIG, .L0, .VPSRAD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x04, .WIG, .L1, .VPSRAD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x06, .WIG, .L1, .VPSLLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x06, .WIG, .L0, .VPSLLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {._0F, 1, 0x73, 0x02, .WIG, .L0, .VPSRLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {._0F, 1, 0x73, 0x02, .WIG, .L1, .VPSRLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, - {._0F, 1, 0x73, 0x06, .WIG, .L1, .VPSLLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, - {._0F, 1, 0x73, 0x06, .WIG, .L0, .VPSLLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, - {._0F, 1, 0x74, 0xFF, .WIG, .L0, .VPCMPEQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x74, 0xFF, .WIG, .L1, .VPCMPEQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x75, 0xFF, .WIG, .L0, .VPCMPEQW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x75, 0xFF, .WIG, .L1, .VPCMPEQW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x76, 0xFF, .WIG, .L0, .VPCMPEQD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x76, 0xFF, .WIG, .L1, .VPCMPEQD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x7E, 0xFF, .WIG, .L0, .VMOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x7E, 0xFF, .W1, .L0, .VMOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 1, 0x7F, 0xFF, .WIG, .L1, .VMOVDQA, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0x7F, 0xFF, .WIG, .L0, .VMOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0x90, 0xFF, .W1, .L0, .KMOVD, {.K, .K_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 1, 0x90, 0xFF, .W0, .L0, .KMOVB, {.K, .K_M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 1, 0x91, 0xFF, .W0, .L0, .KMOVB, {.M8, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 1, 0x91, 0xFF, .W1, .L0, .KMOVD, {.M32, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 1, 0x92, 0xFF, .W0, .L0, .KMOVB, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 1, 0x93, 0xFF, .W0, .L0, .KMOVB, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 1, 0x98, 0xFF, .W0, .L0, .KORTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 1, 0x98, 0xFF, .W1, .L0, .KORTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 1, 0x99, 0xFF, .W1, .L0, .KTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 1, 0x99, 0xFF, .W0, .L0, .KTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 1, 0xC2, 0xFF, .WIG, .L1, .VCMPPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xC2, 0xFF, .WIG, .L0, .VCMPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xC4, 0xFF, .WIG, .L0, .VPINSRW, {.XMM, .XMM, .RM16, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xC5, 0xFF, .WIG, .L0, .VPEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xC6, 0xFF, .WIG, .L0, .VSHUFPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xC6, 0xFF, .WIG, .L1, .VSHUFPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xD1, 0xFF, .WIG, .L1, .VPSRLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xD1, 0xFF, .WIG, .L0, .VPSRLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xD2, 0xFF, .WIG, .L0, .VPSRLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xD2, 0xFF, .WIG, .L1, .VPSRLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xD3, 0xFF, .WIG, .L1, .VPSRLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xD3, 0xFF, .WIG, .L0, .VPSRLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xD4, 0xFF, .WIG, .L0, .VPADDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xD4, 0xFF, .WIG, .L1, .VPADDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xD5, 0xFF, .WIG, .L0, .VPMULLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xD5, 0xFF, .WIG, .L1, .VPMULLW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xD6, 0xFF, .WIG, .L0, .VMOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xD7, 0xFF, .WIG, .L0, .VPMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xD7, 0xFF, .WIG, .L1, .VPMOVMSKB, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xDB, 0xFF, .WIG, .L1, .VPAND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xDB, 0xFF, .WIG, .L0, .VPAND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xDF, 0xFF, .WIG, .L1, .VPANDN, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xDF, 0xFF, .WIG, .L0, .VPANDN, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xE1, 0xFF, .WIG, .L1, .VPSRAW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xE1, 0xFF, .WIG, .L0, .VPSRAW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xE2, 0xFF, .WIG, .L1, .VPSRAD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xE2, 0xFF, .WIG, .L0, .VPSRAD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xE4, 0xFF, .WIG, .L0, .VPMULHUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xE4, 0xFF, .WIG, .L1, .VPMULHUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xE5, 0xFF, .WIG, .L1, .VPMULHW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xE5, 0xFF, .WIG, .L0, .VPMULHW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xE6, 0xFF, .WIG, .L1, .VCVTTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xE6, 0xFF, .WIG, .L0, .VCVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xE7, 0xFF, .WIG, .L1, .VMOVNTDQ, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xE7, 0xFF, .WIG, .L0, .VMOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xEB, 0xFF, .WIG, .L1, .VPOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xEB, 0xFF, .WIG, .L0, .VPOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xEF, 0xFF, .WIG, .L0, .VPXOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xEF, 0xFF, .WIG, .L1, .VPXOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xF1, 0xFF, .WIG, .L0, .VPSLLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xF1, 0xFF, .WIG, .L1, .VPSLLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xF2, 0xFF, .WIG, .L0, .VPSLLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xF2, 0xFF, .WIG, .L1, .VPSLLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xF3, 0xFF, .WIG, .L1, .VPSLLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xF3, 0xFF, .WIG, .L0, .VPSLLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xF4, 0xFF, .WIG, .L0, .VPMULUDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xF4, 0xFF, .WIG, .L1, .VPMULUDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xF5, 0xFF, .WIG, .L1, .VPMADDWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xF5, 0xFF, .WIG, .L0, .VPMADDWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xF7, 0xFF, .WIG, .L0, .VMASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xF8, 0xFF, .WIG, .L1, .VPSUBB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xF8, 0xFF, .WIG, .L0, .VPSUBB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xF9, 0xFF, .WIG, .L1, .VPSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xF9, 0xFF, .WIG, .L0, .VPSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xFA, 0xFF, .WIG, .L0, .VPSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xFA, 0xFF, .WIG, .L1, .VPSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xFB, 0xFF, .WIG, .L1, .VPSUBQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xFB, 0xFF, .WIG, .L0, .VPSUBQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xFC, 0xFF, .WIG, .L0, .VPADDB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xFC, 0xFF, .WIG, .L1, .VPADDB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xFD, 0xFF, .WIG, .L0, .VPADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xFD, 0xFF, .WIG, .L1, .VPADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 1, 0xFE, 0xFF, .WIG, .L0, .VPADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F, 1, 0xFE, 0xFF, .WIG, .L1, .VPADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F, 2, 0x10, 0xFF, .WIG, .LIG, .VMOVSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x10, 0xFF, .WIG, .LIG, .VMOVSS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x11, 0xFF, .WIG, .LIG, .VMOVSS, {.M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x2A, 0xFF, .W1, .LIG, .VCVTSI2SS, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}}, - {._0F, 2, 0x2A, 0xFF, .WIG, .LIG, .VCVTSI2SS, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x2C, 0xFF, .WIG, .LIG, .VCVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x2C, 0xFF, .W1, .LIG, .VCVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}}, - {._0F, 2, 0x2D, 0xFF, .WIG, .LIG, .VCVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x2D, 0xFF, .W1, .LIG, .VCVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1}}, - {._0F, 2, 0x51, 0xFF, .WIG, .LIG, .VSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x52, 0xFF, .WIG, .LIG, .VRSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x53, 0xFF, .WIG, .LIG, .VRCPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x58, 0xFF, .WIG, .LIG, .VADDSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x59, 0xFF, .WIG, .LIG, .VMULSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x5A, 0xFF, .WIG, .LIG, .VCVTSS2SD, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x5B, 0xFF, .WIG, .L1, .VCVTTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}}, - {._0F, 2, 0x5B, 0xFF, .WIG, .L0, .VCVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {._0F, 2, 0x5C, 0xFF, .WIG, .LIG, .VSUBSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x5D, 0xFF, .WIG, .LIG, .VMINSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x5E, 0xFF, .WIG, .LIG, .VDIVSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x5F, 0xFF, .WIG, .LIG, .VMAXSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0x6F, 0xFF, .WIG, .L1, .VMOVDQU, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}}, - {._0F, 2, 0x6F, 0xFF, .WIG, .L0, .VMOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {._0F, 2, 0x70, 0xFF, .WIG, .L1, .VPSHUFHW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}}, - {._0F, 2, 0x70, 0xFF, .WIG, .L0, .VPSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {._0F, 2, 0x7E, 0xFF, .WIG, .L0, .VMOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {._0F, 2, 0x7F, 0xFF, .WIG, .L1, .VMOVDQU, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}}, - {._0F, 2, 0x7F, 0xFF, .WIG, .L0, .VMOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {._0F, 2, 0xC2, 0xFF, .WIG, .LIG, .VCMPSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=2, vex_type=.VEX}}, - {._0F, 2, 0xE6, 0xFF, .WIG, .L1, .VCVTDQ2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1}}, - {._0F, 2, 0xE6, 0xFF, .WIG, .L0, .VCVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0}}, - {._0F, 3, 0x10, 0xFF, .WIG, .LIG, .VMOVSD, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x10, 0xFF, .WIG, .LIG, .VMOVSD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x11, 0xFF, .WIG, .LIG, .VMOVSD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x2A, 0xFF, .WIG, .LIG, .VCVTSI2SD, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x2A, 0xFF, .W1, .LIG, .VCVTSI2SD, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}}, - {._0F, 3, 0x2C, 0xFF, .W1, .LIG, .VCVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}}, - {._0F, 3, 0x2C, 0xFF, .WIG, .LIG, .VCVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x2D, 0xFF, .WIG, .LIG, .VCVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x2D, 0xFF, .W1, .LIG, .VCVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1}}, - {._0F, 3, 0x51, 0xFF, .WIG, .LIG, .VSQRTSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x58, 0xFF, .WIG, .LIG, .VADDSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x59, 0xFF, .WIG, .LIG, .VMULSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x5A, 0xFF, .WIG, .LIG, .VCVTSD2SS, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x5C, 0xFF, .WIG, .LIG, .VSUBSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x5D, 0xFF, .WIG, .LIG, .VMINSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x5E, 0xFF, .WIG, .LIG, .VDIVSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x5F, 0xFF, .WIG, .LIG, .VMAXSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0x70, 0xFF, .WIG, .L1, .VPSHUFLW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1}}, - {._0F, 3, 0x70, 0xFF, .WIG, .L0, .VPSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0}}, - {._0F, 3, 0x92, 0xFF, .W1, .L0, .KMOVQ, {.K, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 3, 0x92, 0xFF, .W0, .L0, .KMOVD, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 3, 0x93, 0xFF, .W0, .L0, .KMOVD, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 3, 0x93, 0xFF, .W1, .L0, .KMOVQ, {.R64, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 3, 0xC2, 0xFF, .WIG, .LIG, .VCMPSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=3, vex_type=.VEX}}, - {._0F, 3, 0xE6, 0xFF, .WIG, .L1, .VCVTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1}}, - {._0F, 3, 0xE6, 0xFF, .WIG, .L0, .VCVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 0, 0xF2, 0xFF, .W1, .L0, .ANDN, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 0, 0xF2, 0xFF, .W0, .L0, .ANDN, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 0, 0xF3, 0x01, .W1, .L0, .BLSR, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, - {._0F38, 0, 0xF3, 0x01, .W0, .L0, .BLSR, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, - {._0F38, 0, 0xF3, 0x02, .W0, .L0, .BLSMSK, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, - {._0F38, 0, 0xF3, 0x02, .W1, .L0, .BLSMSK, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, - {._0F38, 0, 0xF3, 0x03, .W1, .L0, .BLSI, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, - {._0F38, 0, 0xF3, 0x03, .W0, .L0, .BLSI, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, - {._0F38, 0, 0xF5, 0xFF, .W0, .L0, .BZHI, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 0, 0xF5, 0xFF, .W1, .L0, .BZHI, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 0, 0xF7, 0xFF, .W1, .L0, .BEXTR, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 0, 0xF7, 0xFF, .W0, .L0, .BEXTR, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x00, 0xFF, .WIG, .L0, .VPSHUFB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x00, 0xFF, .WIG, .L1, .VPSHUFB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x01, 0xFF, .WIG, .L0, .VPHADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x01, 0xFF, .WIG, .L1, .VPHADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x02, 0xFF, .WIG, .L1, .VPHADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x02, 0xFF, .WIG, .L0, .VPHADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x03, 0xFF, .WIG, .L0, .VPHADDSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x03, 0xFF, .WIG, .L1, .VPHADDSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x04, 0xFF, .WIG, .L0, .VPMADDUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x04, 0xFF, .WIG, .L1, .VPMADDUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x05, 0xFF, .WIG, .L0, .VPHSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x05, 0xFF, .WIG, .L1, .VPHSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x06, 0xFF, .WIG, .L1, .VPHSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x06, 0xFF, .WIG, .L0, .VPHSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x07, 0xFF, .WIG, .L1, .VPHSUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x07, 0xFF, .WIG, .L0, .VPHSUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x08, 0xFF, .WIG, .L1, .VPSIGNB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x08, 0xFF, .WIG, .L0, .VPSIGNB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x09, 0xFF, .WIG, .L0, .VPSIGNW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x09, 0xFF, .WIG, .L1, .VPSIGNW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x0A, 0xFF, .WIG, .L0, .VPSIGND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x0A, 0xFF, .WIG, .L1, .VPSIGND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x0B, 0xFF, .WIG, .L1, .VPMULHRSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x0B, 0xFF, .WIG, .L0, .VPMULHRSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x0E, 0xFF, .WIG, .L1, .VTESTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x0E, 0xFF, .WIG, .L0, .VTESTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x0F, 0xFF, .WIG, .L0, .VTESTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x0F, 0xFF, .WIG, .L1, .VTESTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x13, 0xFF, .WIG, .L0, .VCVTPH2PS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x13, 0xFF, .WIG, .L1, .VCVTPH2PS, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x16, 0xFF, .W0, .L1, .VPERMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x17, 0xFF, .WIG, .L0, .VPTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x17, 0xFF, .WIG, .L1, .VPTEST, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x18, 0xFF, .WIG, .L1, .VBROADCASTSS, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x18, 0xFF, .WIG, .L0, .VBROADCASTSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x18, 0xFF, .WIG, .L1, .VBROADCASTSS, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x18, 0xFF, .WIG, .L0, .VBROADCASTSS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x19, 0xFF, .WIG, .L1, .VBROADCASTSD, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x19, 0xFF, .WIG, .L1, .VBROADCASTSD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x1A, 0xFF, .WIG, .L1, .VBROADCASTF128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x1C, 0xFF, .WIG, .L1, .VPABSB, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x1C, 0xFF, .WIG, .L0, .VPABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x1D, 0xFF, .WIG, .L0, .VPABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x1D, 0xFF, .WIG, .L1, .VPABSW, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x1E, 0xFF, .WIG, .L0, .VPABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x1E, 0xFF, .WIG, .L1, .VPABSD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x20, 0xFF, .WIG, .L1, .VPMOVSXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x20, 0xFF, .WIG, .L0, .VPMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x21, 0xFF, .WIG, .L0, .VPMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x21, 0xFF, .WIG, .L1, .VPMOVSXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x22, 0xFF, .WIG, .L1, .VPMOVSXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x22, 0xFF, .WIG, .L0, .VPMOVSXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x23, 0xFF, .WIG, .L0, .VPMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x23, 0xFF, .WIG, .L1, .VPMOVSXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x24, 0xFF, .WIG, .L0, .VPMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x24, 0xFF, .WIG, .L1, .VPMOVSXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x25, 0xFF, .WIG, .L1, .VPMOVSXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x25, 0xFF, .WIG, .L0, .VPMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x28, 0xFF, .WIG, .L1, .VPMULDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x28, 0xFF, .WIG, .L0, .VPMULDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x29, 0xFF, .WIG, .L1, .VPCMPEQQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x29, 0xFF, .WIG, .L0, .VPCMPEQQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x2A, 0xFF, .WIG, .L0, .VMOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x2A, 0xFF, .WIG, .L1, .VMOVNTDQA, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x2B, 0xFF, .WIG, .L1, .VPACKUSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x2B, 0xFF, .WIG, .L0, .VPACKUSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x2C, 0xFF, .WIG, .L0, .VMASKMOVPS, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x2C, 0xFF, .WIG, .L1, .VMASKMOVPS, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x2D, 0xFF, .WIG, .L1, .VMASKMOVPD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x2D, 0xFF, .WIG, .L0, .VMASKMOVPD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x2E, 0xFF, .WIG, .L0, .VMASKMOVPS, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x2E, 0xFF, .WIG, .L1, .VMASKMOVPS, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x2F, 0xFF, .WIG, .L1, .VMASKMOVPD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x2F, 0xFF, .WIG, .L0, .VMASKMOVPD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x30, 0xFF, .WIG, .L1, .VPMOVZXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x30, 0xFF, .WIG, .L0, .VPMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x31, 0xFF, .WIG, .L1, .VPMOVZXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x31, 0xFF, .WIG, .L0, .VPMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x32, 0xFF, .WIG, .L1, .VPMOVZXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x32, 0xFF, .WIG, .L0, .VPMOVZXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x33, 0xFF, .WIG, .L0, .VPMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x33, 0xFF, .WIG, .L1, .VPMOVZXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x34, 0xFF, .WIG, .L0, .VPMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x34, 0xFF, .WIG, .L1, .VPMOVZXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x35, 0xFF, .WIG, .L1, .VPMOVZXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x35, 0xFF, .WIG, .L0, .VPMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x36, 0xFF, .W0, .L1, .VPERMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x37, 0xFF, .WIG, .L0, .VPCMPGTQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x37, 0xFF, .WIG, .L1, .VPCMPGTQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x38, 0xFF, .WIG, .L0, .VPMINSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x38, 0xFF, .WIG, .L1, .VPMINSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x39, 0xFF, .WIG, .L0, .VPMINSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x39, 0xFF, .WIG, .L1, .VPMINSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x3A, 0xFF, .WIG, .L0, .VPMINUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x3A, 0xFF, .WIG, .L1, .VPMINUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x3B, 0xFF, .WIG, .L0, .VPMINUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x3B, 0xFF, .WIG, .L1, .VPMINUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x3C, 0xFF, .WIG, .L1, .VPMAXSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x3C, 0xFF, .WIG, .L0, .VPMAXSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x3D, 0xFF, .WIG, .L0, .VPMAXSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x3D, 0xFF, .WIG, .L1, .VPMAXSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x3E, 0xFF, .WIG, .L1, .VPMAXUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x3E, 0xFF, .WIG, .L0, .VPMAXUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x3F, 0xFF, .WIG, .L0, .VPMAXUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x3F, 0xFF, .WIG, .L1, .VPMAXUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x40, 0xFF, .WIG, .L1, .VPMULLD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x40, 0xFF, .WIG, .L0, .VPMULLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x41, 0xFF, .WIG, .L0, .VPHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0x45, 0xFF, .W1, .L0, .VPSRLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x45, 0xFF, .W0, .L1, .VPSRLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x45, 0xFF, .W1, .L1, .VPSRLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x45, 0xFF, .W0, .L0, .VPSRLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x46, 0xFF, .W0, .L0, .VPSRAVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x46, 0xFF, .W0, .L1, .VPSRAVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x47, 0xFF, .W1, .L1, .VPSLLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x47, 0xFF, .W1, .L0, .VPSLLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x47, 0xFF, .W0, .L0, .VPSLLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x47, 0xFF, .W0, .L1, .VPSLLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x5A, 0xFF, .WIG, .L1, .VBROADCASTI128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F38, 1, 0x8C, 0xFF, .W1, .L1, .VPMASKMOVQ, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x8C, 0xFF, .W0, .L0, .VPMASKMOVD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x8C, 0xFF, .W0, .L1, .VPMASKMOVD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x8C, 0xFF, .W1, .L0, .VPMASKMOVQ, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x8E, 0xFF, .W0, .L0, .VPMASKMOVD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x8E, 0xFF, .W1, .L1, .VPMASKMOVQ, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x8E, 0xFF, .W1, .L0, .VPMASKMOVQ, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x8E, 0xFF, .W0, .L1, .VPMASKMOVD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x90, 0xFF, .W0, .L1, .VPGATHERDD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x90, 0xFF, .W0, .L0, .VPGATHERDD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x90, 0xFF, .W1, .L1, .VPGATHERDQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x90, 0xFF, .W1, .L0, .VPGATHERDQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x91, 0xFF, .W1, .L1, .VPGATHERQQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x91, 0xFF, .W0, .L1, .VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x91, 0xFF, .W1, .L0, .VPGATHERQQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x91, 0xFF, .W0, .L0, .VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x92, 0xFF, .W1, .L0, .VGATHERDPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x92, 0xFF, .W0, .L0, .VGATHERDPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x92, 0xFF, .W0, .L1, .VGATHERDPS, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x92, 0xFF, .W1, .L1, .VGATHERDPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x93, 0xFF, .W1, .L0, .VGATHERQPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x93, 0xFF, .W0, .L0, .VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x93, 0xFF, .W1, .L1, .VGATHERQPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x93, 0xFF, .W0, .L1, .VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x96, 0xFF, .W1, .L0, .VFMADDSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x96, 0xFF, .W0, .L1, .VFMADDSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x96, 0xFF, .W1, .L1, .VFMADDSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x96, 0xFF, .W0, .L0, .VFMADDSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x97, 0xFF, .W1, .L0, .VFMSUBADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x97, 0xFF, .W1, .L1, .VFMSUBADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x97, 0xFF, .W0, .L1, .VFMSUBADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x97, 0xFF, .W0, .L0, .VFMSUBADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x98, 0xFF, .W1, .L0, .VFMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x98, 0xFF, .W1, .L1, .VFMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x98, 0xFF, .W0, .L0, .VFMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x98, 0xFF, .W0, .L1, .VFMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x99, 0xFF, .W1, .LIG, .VFMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0x99, 0xFF, .W0, .LIG, .VFMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0x9A, 0xFF, .W1, .L0, .VFMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x9A, 0xFF, .W0, .L1, .VFMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x9A, 0xFF, .W1, .L1, .VFMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x9A, 0xFF, .W0, .L0, .VFMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x9B, 0xFF, .W0, .LIG, .VFMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0x9B, 0xFF, .W1, .LIG, .VFMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0x9C, 0xFF, .W0, .L0, .VFNMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x9C, 0xFF, .W1, .L1, .VFNMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x9C, 0xFF, .W0, .L1, .VFNMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x9C, 0xFF, .W1, .L0, .VFNMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x9D, 0xFF, .W1, .LIG, .VFNMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0x9D, 0xFF, .W0, .LIG, .VFNMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0x9E, 0xFF, .W0, .L1, .VFNMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x9E, 0xFF, .W0, .L0, .VFNMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x9E, 0xFF, .W1, .L0, .VFNMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x9E, 0xFF, .W1, .L1, .VFNMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x9F, 0xFF, .W0, .LIG, .VFNMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0x9F, 0xFF, .W1, .LIG, .VFNMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0xA6, 0xFF, .W1, .L1, .VFMADDSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xA6, 0xFF, .W0, .L0, .VFMADDSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xA6, 0xFF, .W1, .L0, .VFMADDSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xA6, 0xFF, .W0, .L1, .VFMADDSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xA7, 0xFF, .W1, .L0, .VFMSUBADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xA7, 0xFF, .W1, .L1, .VFMSUBADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xA7, 0xFF, .W0, .L0, .VFMSUBADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xA7, 0xFF, .W0, .L1, .VFMSUBADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xA8, 0xFF, .W1, .L0, .VFMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xA8, 0xFF, .W1, .L1, .VFMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xA8, 0xFF, .W0, .L1, .VFMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xA8, 0xFF, .W0, .L0, .VFMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xA9, 0xFF, .W0, .LIG, .VFMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0xA9, 0xFF, .W1, .LIG, .VFMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0xAA, 0xFF, .W1, .L0, .VFMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xAA, 0xFF, .W0, .L0, .VFMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xAA, 0xFF, .W0, .L1, .VFMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xAA, 0xFF, .W1, .L1, .VFMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xAB, 0xFF, .W1, .LIG, .VFMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0xAB, 0xFF, .W0, .LIG, .VFMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0xAC, 0xFF, .W0, .L1, .VFNMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xAC, 0xFF, .W1, .L1, .VFNMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xAC, 0xFF, .W0, .L0, .VFNMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xAC, 0xFF, .W1, .L0, .VFNMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xAD, 0xFF, .W1, .LIG, .VFNMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0xAD, 0xFF, .W0, .LIG, .VFNMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0xAE, 0xFF, .W0, .L1, .VFNMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xAE, 0xFF, .W1, .L0, .VFNMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xAE, 0xFF, .W1, .L1, .VFNMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xAE, 0xFF, .W0, .L0, .VFNMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xAF, 0xFF, .W0, .LIG, .VFNMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0xAF, 0xFF, .W1, .LIG, .VFNMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0xB6, 0xFF, .W0, .L1, .VFMADDSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xB6, 0xFF, .W0, .L0, .VFMADDSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xB6, 0xFF, .W1, .L0, .VFMADDSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xB6, 0xFF, .W1, .L1, .VFMADDSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xB7, 0xFF, .W1, .L0, .VFMSUBADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xB7, 0xFF, .W0, .L1, .VFMSUBADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xB7, 0xFF, .W0, .L0, .VFMSUBADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xB7, 0xFF, .W1, .L1, .VFMSUBADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xB8, 0xFF, .W1, .L1, .VFMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xB8, 0xFF, .W0, .L1, .VFMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xB8, 0xFF, .W0, .L0, .VFMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xB8, 0xFF, .W1, .L0, .VFMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xB9, 0xFF, .W1, .LIG, .VFMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0xB9, 0xFF, .W0, .LIG, .VFMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0xBA, 0xFF, .W1, .L1, .VFMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xBA, 0xFF, .W1, .L0, .VFMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xBA, 0xFF, .W0, .L1, .VFMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xBA, 0xFF, .W0, .L0, .VFMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xBB, 0xFF, .W1, .LIG, .VFMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0xBB, 0xFF, .W0, .LIG, .VFMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0xBC, 0xFF, .W1, .L0, .VFNMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xBC, 0xFF, .W1, .L1, .VFNMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xBC, 0xFF, .W0, .L0, .VFNMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xBC, 0xFF, .W0, .L1, .VFNMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xBD, 0xFF, .W1, .LIG, .VFNMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0xBD, 0xFF, .W0, .LIG, .VFNMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0xBE, 0xFF, .W1, .L1, .VFNMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xBE, 0xFF, .W1, .L0, .VFNMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xBE, 0xFF, .W0, .L1, .VFNMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xBE, 0xFF, .W0, .L0, .VFNMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xBF, 0xFF, .W1, .LIG, .VFNMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1}}, - {._0F38, 1, 0xBF, 0xFF, .W0, .LIG, .VFNMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0}}, - {._0F38, 1, 0xDB, 0xFF, .WIG, .L0, .VAESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0xDC, 0xFF, .WIG, .L0, .VAESENC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0xDD, 0xFF, .WIG, .L0, .VAESENCLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0xDE, 0xFF, .WIG, .L0, .VAESDEC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0xDF, 0xFF, .WIG, .L0, .VAESDECLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F38, 1, 0xF7, 0xFF, .W1, .L0, .SHLX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xF7, 0xFF, .W0, .L0, .SHLX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0xF5, 0xFF, .W1, .L0, .PEXT, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 2, 0xF5, 0xFF, .W0, .L0, .PEXT, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0xF7, 0xFF, .W0, .L0, .SARX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0xF7, 0xFF, .W1, .L0, .SARX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 3, 0xF5, 0xFF, .W0, .L0, .PDEP, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 3, 0xF5, 0xFF, .W1, .L0, .PDEP, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 3, 0xF6, 0xFF, .W1, .L0, .MULX, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 3, 0xF6, 0xFF, .W0, .L0, .MULX, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 3, 0xF7, 0xFF, .W0, .L0, .SHRX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 3, 0xF7, 0xFF, .W1, .L0, .SHRX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x00, 0xFF, .W1, .L1, .VPERMQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x01, 0xFF, .W1, .L1, .VPERMPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x02, 0xFF, .W0, .L1, .VPBLENDD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x02, 0xFF, .W0, .L0, .VPBLENDD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x06, 0xFF, .WIG, .L1, .VPERM2F128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x08, 0xFF, .WIG, .L1, .VROUNDPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x08, 0xFF, .WIG, .L0, .VROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x09, 0xFF, .WIG, .L0, .VROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x09, 0xFF, .WIG, .L1, .VROUNDPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x0A, 0xFF, .WIG, .LIG, .VROUNDSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX}}, - {._0F3A, 1, 0x0B, 0xFF, .WIG, .LIG, .VROUNDSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX}}, - {._0F3A, 1, 0x0C, 0xFF, .WIG, .L0, .VBLENDPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x0C, 0xFF, .WIG, .L1, .VBLENDPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x0D, 0xFF, .WIG, .L1, .VBLENDPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x0D, 0xFF, .WIG, .L0, .VBLENDPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x0E, 0xFF, .WIG, .L1, .VPBLENDW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x0E, 0xFF, .WIG, .L0, .VPBLENDW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x0F, 0xFF, .WIG, .L1, .VPALIGNR, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x0F, 0xFF, .WIG, .L0, .VPALIGNR, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x14, 0xFF, .WIG, .L0, .VPEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x15, 0xFF, .WIG, .L0, .VPEXTRW, {.RM16, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x16, 0xFF, .WIG, .L0, .VPEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x16, 0xFF, .W1, .L0, .VPEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x17, 0xFF, .WIG, .L0, .VEXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x18, 0xFF, .WIG, .L1, .VINSERTF128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x19, 0xFF, .WIG, .L1, .VEXTRACTF128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x1D, 0xFF, .WIG, .L1, .VCVTPS2PH, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x1D, 0xFF, .WIG, .L0, .VCVTPS2PH, {.XMM_M64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x20, 0xFF, .WIG, .L0, .VPINSRB, {.XMM, .XMM, .RM8, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x21, 0xFF, .WIG, .L0, .VINSERTPS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x22, 0xFF, .WIG, .L0, .VPINSRD, {.XMM, .XMM, .RM32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x22, 0xFF, .W1, .L0, .VPINSRQ, {.XMM, .XMM, .RM64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x30, 0xFF, .W0, .L0, .KSHIFTRB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x30, 0xFF, .W1, .L0, .KSHIFTRW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x31, 0xFF, .W0, .L0, .KSHIFTRD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x31, 0xFF, .W1, .L0, .KSHIFTRQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x32, 0xFF, .W1, .L0, .KSHIFTLW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x32, 0xFF, .W0, .L0, .KSHIFTLB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x33, 0xFF, .W0, .L0, .KSHIFTLD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x33, 0xFF, .W1, .L0, .KSHIFTLQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x38, 0xFF, .WIG, .L1, .VINSERTI128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x39, 0xFF, .WIG, .L1, .VEXTRACTI128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x40, 0xFF, .WIG, .L1, .VDPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x40, 0xFF, .WIG, .L0, .VDPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x41, 0xFF, .WIG, .L0, .VDPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x42, 0xFF, .WIG, .L0, .VMPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x42, 0xFF, .WIG, .L1, .VMPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x44, 0xFF, .WIG, .L0, .VPCLMULQDQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 1, 0x44, 0xFF, .WIG, .L1, .VPCLMULQDQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x46, 0xFF, .WIG, .L1, .VPERM2I128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1}}, - {._0F3A, 1, 0x4A, 0xFF, .W0, .L0, .VBLENDVPS, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x4A, 0xFF, .W0, .L1, .VBLENDVPS, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x4B, 0xFF, .W0, .L1, .VBLENDVPD, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x4B, 0xFF, .W0, .L0, .VBLENDVPD, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x4C, 0xFF, .W0, .L1, .VPBLENDVB, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x4C, 0xFF, .W0, .L0, .VPBLENDVB, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0xDF, 0xFF, .WIG, .L0, .VAESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0}}, - {._0F3A, 3, 0xF0, 0xFF, .W0, .L0, .RORX, {.R32, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 3, 0xF0, 0xFF, .W1, .L0, .RORX, {.R64, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {._0F, 0, 0x90, 0xFF, .W1, .L0, .KMOVQ, {.K, .K_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x90, 0xFF, .W0, .L0, .KMOVW, {.K, .K_M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x91, 0xFF, .W1, .L0, .KMOVQ, {.M64, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x91, 0xFF, .W0, .L0, .KMOVW, {.M16, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x92, 0xFF, .W0, .L0, .KMOVW, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x93, 0xFF, .W0, .L0, .KMOVW, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x98, 0xFF, .W0, .L0, .KORTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x98, 0xFF, .W1, .L0, .KORTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x99, 0xFF, .W1, .L0, .KTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x99, 0xFF, .W0, .L0, .KTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xC2, 0xFF, .WIG, .L0, .VCMPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F, 0, 0xC2, 0xFF, .WIG, .L1, .VCMPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F, 0, 0xC6, 0xFF, .WIG, .L1, .VSHUFPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F, 0, 0xC6, 0xFF, .WIG, .L0, .VSHUFPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F, 1, 0x10, 0xFF, .WIG, .L0, .VMOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x10, 0xFF, .WIG, .L1, .VMOVUPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x11, 0xFF, .WIG, .L1, .VMOVUPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x11, 0xFF, .WIG, .L0, .VMOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x12, 0xFF, .WIG, .L0, .VMOVLPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x13, 0xFF, .WIG, .L0, .VMOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x14, 0xFF, .WIG, .L0, .VUNPCKLPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x14, 0xFF, .WIG, .L1, .VUNPCKLPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x15, 0xFF, .WIG, .L1, .VUNPCKHPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x15, 0xFF, .WIG, .L0, .VUNPCKHPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x16, 0xFF, .WIG, .L0, .VMOVHPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x17, 0xFF, .WIG, .L0, .VMOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x28, 0xFF, .WIG, .L0, .VMOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x28, 0xFF, .WIG, .L1, .VMOVAPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x29, 0xFF, .WIG, .L1, .VMOVAPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x29, 0xFF, .WIG, .L0, .VMOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x2B, 0xFF, .WIG, .L0, .VMOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x2B, 0xFF, .WIG, .L1, .VMOVNTPD, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x2E, 0xFF, .WIG, .LIG, .VUCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x2F, 0xFF, .WIG, .LIG, .VCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x41, 0xFF, .W1, .L1, .KANDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x41, 0xFF, .W0, .L1, .KANDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x42, 0xFF, .W0, .L1, .KANDNB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x42, 0xFF, .W1, .L1, .KANDND, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x44, 0xFF, .W1, .L0, .KNOTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x44, 0xFF, .W0, .L0, .KNOTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x45, 0xFF, .W0, .L1, .KORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x45, 0xFF, .W1, .L1, .KORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x46, 0xFF, .W1, .L1, .KXNORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x46, 0xFF, .W0, .L1, .KXNORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x47, 0xFF, .W1, .L1, .KXORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x47, 0xFF, .W0, .L1, .KXORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x4A, 0xFF, .W0, .L1, .KADDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x4A, 0xFF, .W1, .L1, .KADDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x4B, 0xFF, .W0, .L1, .KUNPCKBW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x50, 0xFF, .WIG, .L0, .VMOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x50, 0xFF, .WIG, .L1, .VMOVMSKPD, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x51, 0xFF, .WIG, .L1, .VSQRTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x51, 0xFF, .WIG, .L0, .VSQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x54, 0xFF, .WIG, .L1, .VANDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x54, 0xFF, .WIG, .L0, .VANDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x55, 0xFF, .WIG, .L0, .VANDNPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x55, 0xFF, .WIG, .L1, .VANDNPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x56, 0xFF, .WIG, .L1, .VORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x56, 0xFF, .WIG, .L0, .VORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x57, 0xFF, .WIG, .L0, .VXORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x57, 0xFF, .WIG, .L1, .VXORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x58, 0xFF, .WIG, .L0, .VADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x58, 0xFF, .WIG, .L1, .VADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x59, 0xFF, .WIG, .L1, .VMULPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x59, 0xFF, .WIG, .L0, .VMULPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x5A, 0xFF, .WIG, .L0, .VCVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x5A, 0xFF, .WIG, .L1, .VCVTPD2PS, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x5B, 0xFF, .WIG, .L0, .VCVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x5B, 0xFF, .WIG, .L1, .VCVTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x5C, 0xFF, .WIG, .L1, .VSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x5C, 0xFF, .WIG, .L0, .VSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x5D, 0xFF, .WIG, .L0, .VMINPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x5D, 0xFF, .WIG, .L1, .VMINPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x5E, 0xFF, .WIG, .L1, .VDIVPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x5E, 0xFF, .WIG, .L0, .VDIVPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x5F, 0xFF, .WIG, .L0, .VMAXPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x5F, 0xFF, .WIG, .L1, .VMAXPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x60, 0xFF, .WIG, .L1, .VPUNPCKLBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x60, 0xFF, .WIG, .L0, .VPUNPCKLBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x61, 0xFF, .WIG, .L0, .VPUNPCKLWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x61, 0xFF, .WIG, .L1, .VPUNPCKLWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x62, 0xFF, .WIG, .L1, .VPUNPCKLDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x62, 0xFF, .WIG, .L0, .VPUNPCKLDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x63, 0xFF, .WIG, .L0, .VPACKSSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x63, 0xFF, .WIG, .L1, .VPACKSSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x64, 0xFF, .WIG, .L1, .VPCMPGTB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x64, 0xFF, .WIG, .L0, .VPCMPGTB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x65, 0xFF, .WIG, .L1, .VPCMPGTW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x65, 0xFF, .WIG, .L0, .VPCMPGTW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x66, 0xFF, .WIG, .L1, .VPCMPGTD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x66, 0xFF, .WIG, .L0, .VPCMPGTD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x67, 0xFF, .WIG, .L0, .VPACKUSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x67, 0xFF, .WIG, .L1, .VPACKUSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x68, 0xFF, .WIG, .L1, .VPUNPCKHBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x68, 0xFF, .WIG, .L0, .VPUNPCKHBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x69, 0xFF, .WIG, .L1, .VPUNPCKHWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x69, 0xFF, .WIG, .L0, .VPUNPCKHWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x6A, 0xFF, .WIG, .L0, .VPUNPCKHDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x6A, 0xFF, .WIG, .L1, .VPUNPCKHDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x6B, 0xFF, .WIG, .L0, .VPACKSSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x6B, 0xFF, .WIG, .L1, .VPACKSSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x6C, 0xFF, .WIG, .L0, .VPUNPCKLQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x6C, 0xFF, .WIG, .L1, .VPUNPCKLQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x6D, 0xFF, .WIG, .L0, .VPUNPCKHQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x6D, 0xFF, .WIG, .L1, .VPUNPCKHQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x6E, 0xFF, .WIG, .L0, .VMOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6E, 0xFF, .W1, .L0, .VMOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6F, 0xFF, .WIG, .L1, .VMOVDQA, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6F, 0xFF, .WIG, .L0, .VMOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x70, 0xFF, .WIG, .L0, .VPSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x70, 0xFF, .WIG, .L1, .VPSHUFD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x71, 0x02, .WIG, .L1, .VPSRLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x71, 0x02, .WIG, .L0, .VPSRLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x71, 0x04, .WIG, .L1, .VPSRAW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x71, 0x04, .WIG, .L0, .VPSRAW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x71, 0x06, .WIG, .L1, .VPSLLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x71, 0x06, .WIG, .L0, .VPSLLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x02, .WIG, .L0, .VPSRLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x02, .WIG, .L1, .VPSRLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x04, .WIG, .L0, .VPSRAD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x04, .WIG, .L1, .VPSRAD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x06, .WIG, .L1, .VPSLLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x06, .WIG, .L0, .VPSLLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x73, 0x02, .WIG, .L0, .VPSRLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x73, 0x02, .WIG, .L1, .VPSRLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x73, 0x06, .WIG, .L1, .VPSLLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x73, 0x06, .WIG, .L0, .VPSLLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x74, 0xFF, .WIG, .L0, .VPCMPEQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x74, 0xFF, .WIG, .L1, .VPCMPEQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x75, 0xFF, .WIG, .L0, .VPCMPEQW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x75, 0xFF, .WIG, .L1, .VPCMPEQW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x76, 0xFF, .WIG, .L0, .VPCMPEQD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x76, 0xFF, .WIG, .L1, .VPCMPEQD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x7E, 0xFF, .WIG, .L0, .VMOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7E, 0xFF, .W1, .L0, .VMOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7F, 0xFF, .WIG, .L1, .VMOVDQA, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7F, 0xFF, .WIG, .L0, .VMOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x90, 0xFF, .W1, .L0, .KMOVD, {.K, .K_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x90, 0xFF, .W0, .L0, .KMOVB, {.K, .K_M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x91, 0xFF, .W0, .L0, .KMOVB, {.M8, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x91, 0xFF, .W1, .L0, .KMOVD, {.M32, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x92, 0xFF, .W0, .L0, .KMOVB, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x93, 0xFF, .W0, .L0, .KMOVB, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x98, 0xFF, .W0, .L0, .KORTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x98, 0xFF, .W1, .L0, .KORTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x99, 0xFF, .W1, .L0, .KTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x99, 0xFF, .W0, .L0, .KTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xC2, 0xFF, .WIG, .L1, .VCMPPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F, 1, 0xC2, 0xFF, .WIG, .L0, .VCMPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F, 1, 0xC4, 0xFF, .WIG, .L0, .VPINSRW, {.XMM, .XMM, .RM16, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F, 1, 0xC5, 0xFF, .WIG, .L0, .VPEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xC6, 0xFF, .WIG, .L0, .VSHUFPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F, 1, 0xC6, 0xFF, .WIG, .L1, .VSHUFPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F, 1, 0xD1, 0xFF, .WIG, .L1, .VPSRLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD1, 0xFF, .WIG, .L0, .VPSRLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD2, 0xFF, .WIG, .L0, .VPSRLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD2, 0xFF, .WIG, .L1, .VPSRLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD3, 0xFF, .WIG, .L1, .VPSRLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD3, 0xFF, .WIG, .L0, .VPSRLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD4, 0xFF, .WIG, .L0, .VPADDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD4, 0xFF, .WIG, .L1, .VPADDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD5, 0xFF, .WIG, .L0, .VPMULLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD5, 0xFF, .WIG, .L1, .VPMULLW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xD6, 0xFF, .WIG, .L0, .VMOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD7, 0xFF, .WIG, .L0, .VPMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xD7, 0xFF, .WIG, .L1, .VPMOVMSKB, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xDB, 0xFF, .WIG, .L1, .VPAND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xDB, 0xFF, .WIG, .L0, .VPAND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xDF, 0xFF, .WIG, .L1, .VPANDN, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xDF, 0xFF, .WIG, .L0, .VPANDN, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xE1, 0xFF, .WIG, .L1, .VPSRAW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xE1, 0xFF, .WIG, .L0, .VPSRAW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xE2, 0xFF, .WIG, .L1, .VPSRAD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xE2, 0xFF, .WIG, .L0, .VPSRAD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xE4, 0xFF, .WIG, .L0, .VPMULHUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xE4, 0xFF, .WIG, .L1, .VPMULHUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xE5, 0xFF, .WIG, .L1, .VPMULHW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xE5, 0xFF, .WIG, .L0, .VPMULHW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xE6, 0xFF, .WIG, .L1, .VCVTTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE6, 0xFF, .WIG, .L0, .VCVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE7, 0xFF, .WIG, .L1, .VMOVNTDQ, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xE7, 0xFF, .WIG, .L0, .VMOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xEB, 0xFF, .WIG, .L1, .VPOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xEB, 0xFF, .WIG, .L0, .VPOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xEF, 0xFF, .WIG, .L0, .VPXOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xEF, 0xFF, .WIG, .L1, .VPXOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF1, 0xFF, .WIG, .L0, .VPSLLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF1, 0xFF, .WIG, .L1, .VPSLLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF2, 0xFF, .WIG, .L0, .VPSLLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF2, 0xFF, .WIG, .L1, .VPSLLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF3, 0xFF, .WIG, .L1, .VPSLLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF3, 0xFF, .WIG, .L0, .VPSLLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF4, 0xFF, .WIG, .L0, .VPMULUDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF4, 0xFF, .WIG, .L1, .VPMULUDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF5, 0xFF, .WIG, .L1, .VPMADDWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF5, 0xFF, .WIG, .L0, .VPMADDWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF7, 0xFF, .WIG, .L0, .VMASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0xF8, 0xFF, .WIG, .L1, .VPSUBB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF8, 0xFF, .WIG, .L0, .VPSUBB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF9, 0xFF, .WIG, .L1, .VPSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xF9, 0xFF, .WIG, .L0, .VPSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFA, 0xFF, .WIG, .L0, .VPSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFA, 0xFF, .WIG, .L1, .VPSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFB, 0xFF, .WIG, .L1, .VPSUBQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFB, 0xFF, .WIG, .L0, .VPSUBQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFC, 0xFF, .WIG, .L0, .VPADDB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFC, 0xFF, .WIG, .L1, .VPADDB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFD, 0xFF, .WIG, .L0, .VPADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFD, 0xFF, .WIG, .L1, .VPADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFE, 0xFF, .WIG, .L0, .VPADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xFE, 0xFF, .WIG, .L1, .VPADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x10, 0xFF, .WIG, .LIG, .VMOVSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x10, 0xFF, .WIG, .LIG, .VMOVSS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x11, 0xFF, .WIG, .LIG, .VMOVSS, {.M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2A, 0xFF, .W1, .LIG, .VCVTSI2SS, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x2A, 0xFF, .WIG, .LIG, .VCVTSI2SS, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x2C, 0xFF, .WIG, .LIG, .VCVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2C, 0xFF, .W1, .LIG, .VCVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2D, 0xFF, .WIG, .LIG, .VCVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2D, 0xFF, .W1, .LIG, .VCVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x51, 0xFF, .WIG, .LIG, .VSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x52, 0xFF, .WIG, .LIG, .VRSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x53, 0xFF, .WIG, .LIG, .VRCPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x58, 0xFF, .WIG, .LIG, .VADDSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x59, 0xFF, .WIG, .LIG, .VMULSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x5A, 0xFF, .WIG, .LIG, .VCVTSS2SD, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x5B, 0xFF, .WIG, .L1, .VCVTTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x5B, 0xFF, .WIG, .L0, .VCVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x5C, 0xFF, .WIG, .LIG, .VSUBSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x5D, 0xFF, .WIG, .LIG, .VMINSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x5E, 0xFF, .WIG, .LIG, .VDIVSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x5F, 0xFF, .WIG, .LIG, .VMAXSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x6F, 0xFF, .WIG, .L1, .VMOVDQU, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x6F, 0xFF, .WIG, .L0, .VMOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x70, 0xFF, .WIG, .L1, .VPSHUFHW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x70, 0xFF, .WIG, .L0, .VPSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 2, 0x7E, 0xFF, .WIG, .L0, .VMOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x7F, 0xFF, .WIG, .L1, .VMOVDQU, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x7F, 0xFF, .WIG, .L0, .VMOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xC2, 0xFF, .WIG, .LIG, .VCMPSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=2, vex_type=.VEX, op_count=4, needs_modrm=true}}, + {._0F, 2, 0xE6, 0xFF, .WIG, .L1, .VCVTDQ2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xE6, 0xFF, .WIG, .L0, .VCVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x10, 0xFF, .WIG, .LIG, .VMOVSD, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x10, 0xFF, .WIG, .LIG, .VMOVSD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x11, 0xFF, .WIG, .LIG, .VMOVSD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2A, 0xFF, .WIG, .LIG, .VCVTSI2SD, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x2A, 0xFF, .W1, .LIG, .VCVTSI2SD, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x2C, 0xFF, .W1, .LIG, .VCVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2C, 0xFF, .WIG, .LIG, .VCVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2D, 0xFF, .WIG, .LIG, .VCVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2D, 0xFF, .W1, .LIG, .VCVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x51, 0xFF, .WIG, .LIG, .VSQRTSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x58, 0xFF, .WIG, .LIG, .VADDSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x59, 0xFF, .WIG, .LIG, .VMULSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x5A, 0xFF, .WIG, .LIG, .VCVTSD2SS, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x5C, 0xFF, .WIG, .LIG, .VSUBSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x5D, 0xFF, .WIG, .LIG, .VMINSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x5E, 0xFF, .WIG, .LIG, .VDIVSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x5F, 0xFF, .WIG, .LIG, .VMAXSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x70, 0xFF, .WIG, .L1, .VPSHUFLW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x70, 0xFF, .WIG, .L0, .VPSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 3, 0x92, 0xFF, .W1, .L0, .KMOVQ, {.K, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x92, 0xFF, .W0, .L0, .KMOVD, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x93, 0xFF, .W0, .L0, .KMOVD, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x93, 0xFF, .W1, .L0, .KMOVQ, {.R64, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0xC2, 0xFF, .WIG, .LIG, .VCMPSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F, prefix=3, vex_type=.VEX, op_count=4, needs_modrm=true}}, + {._0F, 3, 0xE6, 0xFF, .WIG, .L1, .VCVTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 3, 0xE6, 0xFF, .WIG, .L0, .VCVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF2, 0xFF, .W1, .L0, .ANDN, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 0, 0xF2, 0xFF, .W0, .L0, .ANDN, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 0, 0xF3, 0x01, .W1, .L0, .BLSR, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF3, 0x01, .W0, .L0, .BLSR, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF3, 0x02, .W0, .L0, .BLSMSK, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF3, 0x02, .W1, .L0, .BLSMSK, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF3, 0x03, .W1, .L0, .BLSI, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF3, 0x03, .W0, .L0, .BLSI, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF5, 0xFF, .W0, .L0, .BZHI, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 0, 0xF5, 0xFF, .W1, .L0, .BZHI, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 0, 0xF7, 0xFF, .W1, .L0, .BEXTR, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 0, 0xF7, 0xFF, .W0, .L0, .BEXTR, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x00, 0xFF, .WIG, .L0, .VPSHUFB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x00, 0xFF, .WIG, .L1, .VPSHUFB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x01, 0xFF, .WIG, .L0, .VPHADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x01, 0xFF, .WIG, .L1, .VPHADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x02, 0xFF, .WIG, .L1, .VPHADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x02, 0xFF, .WIG, .L0, .VPHADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x03, 0xFF, .WIG, .L0, .VPHADDSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x03, 0xFF, .WIG, .L1, .VPHADDSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x04, 0xFF, .WIG, .L0, .VPMADDUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x04, 0xFF, .WIG, .L1, .VPMADDUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x05, 0xFF, .WIG, .L0, .VPHSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x05, 0xFF, .WIG, .L1, .VPHSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x06, 0xFF, .WIG, .L1, .VPHSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x06, 0xFF, .WIG, .L0, .VPHSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x07, 0xFF, .WIG, .L1, .VPHSUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x07, 0xFF, .WIG, .L0, .VPHSUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x08, 0xFF, .WIG, .L1, .VPSIGNB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x08, 0xFF, .WIG, .L0, .VPSIGNB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x09, 0xFF, .WIG, .L0, .VPSIGNW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x09, 0xFF, .WIG, .L1, .VPSIGNW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x0A, 0xFF, .WIG, .L0, .VPSIGND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x0A, 0xFF, .WIG, .L1, .VPSIGND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x0B, 0xFF, .WIG, .L1, .VPMULHRSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x0B, 0xFF, .WIG, .L0, .VPMULHRSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x0E, 0xFF, .WIG, .L1, .VTESTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x0E, 0xFF, .WIG, .L0, .VTESTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x0F, 0xFF, .WIG, .L0, .VTESTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x0F, 0xFF, .WIG, .L1, .VTESTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x13, 0xFF, .WIG, .L0, .VCVTPH2PS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x13, 0xFF, .WIG, .L1, .VCVTPH2PS, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x16, 0xFF, .W0, .L1, .VPERMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x17, 0xFF, .WIG, .L0, .VPTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x17, 0xFF, .WIG, .L1, .VPTEST, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x18, 0xFF, .WIG, .L1, .VBROADCASTSS, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x18, 0xFF, .WIG, .L0, .VBROADCASTSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x18, 0xFF, .WIG, .L1, .VBROADCASTSS, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x18, 0xFF, .WIG, .L0, .VBROADCASTSS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x19, 0xFF, .WIG, .L1, .VBROADCASTSD, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x19, 0xFF, .WIG, .L1, .VBROADCASTSD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1A, 0xFF, .WIG, .L1, .VBROADCASTF128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1C, 0xFF, .WIG, .L1, .VPABSB, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1C, 0xFF, .WIG, .L0, .VPABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1D, 0xFF, .WIG, .L0, .VPABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1D, 0xFF, .WIG, .L1, .VPABSW, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1E, 0xFF, .WIG, .L0, .VPABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x1E, 0xFF, .WIG, .L1, .VPABSD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x20, 0xFF, .WIG, .L1, .VPMOVSXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x20, 0xFF, .WIG, .L0, .VPMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x21, 0xFF, .WIG, .L0, .VPMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x21, 0xFF, .WIG, .L1, .VPMOVSXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x22, 0xFF, .WIG, .L1, .VPMOVSXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x22, 0xFF, .WIG, .L0, .VPMOVSXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x23, 0xFF, .WIG, .L0, .VPMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x23, 0xFF, .WIG, .L1, .VPMOVSXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x24, 0xFF, .WIG, .L0, .VPMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x24, 0xFF, .WIG, .L1, .VPMOVSXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x25, 0xFF, .WIG, .L1, .VPMOVSXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x25, 0xFF, .WIG, .L0, .VPMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x28, 0xFF, .WIG, .L1, .VPMULDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x28, 0xFF, .WIG, .L0, .VPMULDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x29, 0xFF, .WIG, .L1, .VPCMPEQQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x29, 0xFF, .WIG, .L0, .VPCMPEQQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2A, 0xFF, .WIG, .L0, .VMOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x2A, 0xFF, .WIG, .L1, .VMOVNTDQA, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x2B, 0xFF, .WIG, .L1, .VPACKUSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2B, 0xFF, .WIG, .L0, .VPACKUSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2C, 0xFF, .WIG, .L0, .VMASKMOVPS, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2C, 0xFF, .WIG, .L1, .VMASKMOVPS, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2D, 0xFF, .WIG, .L1, .VMASKMOVPD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2D, 0xFF, .WIG, .L0, .VMASKMOVPD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2E, 0xFF, .WIG, .L0, .VMASKMOVPS, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2E, 0xFF, .WIG, .L1, .VMASKMOVPS, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2F, 0xFF, .WIG, .L1, .VMASKMOVPD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2F, 0xFF, .WIG, .L0, .VMASKMOVPD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x30, 0xFF, .WIG, .L1, .VPMOVZXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x30, 0xFF, .WIG, .L0, .VPMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x31, 0xFF, .WIG, .L1, .VPMOVZXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x31, 0xFF, .WIG, .L0, .VPMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x32, 0xFF, .WIG, .L1, .VPMOVZXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x32, 0xFF, .WIG, .L0, .VPMOVZXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x33, 0xFF, .WIG, .L0, .VPMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x33, 0xFF, .WIG, .L1, .VPMOVZXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x34, 0xFF, .WIG, .L0, .VPMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x34, 0xFF, .WIG, .L1, .VPMOVZXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x35, 0xFF, .WIG, .L1, .VPMOVZXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x35, 0xFF, .WIG, .L0, .VPMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x36, 0xFF, .W0, .L1, .VPERMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x37, 0xFF, .WIG, .L0, .VPCMPGTQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x37, 0xFF, .WIG, .L1, .VPCMPGTQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x38, 0xFF, .WIG, .L0, .VPMINSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x38, 0xFF, .WIG, .L1, .VPMINSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x39, 0xFF, .WIG, .L0, .VPMINSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x39, 0xFF, .WIG, .L1, .VPMINSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3A, 0xFF, .WIG, .L0, .VPMINUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3A, 0xFF, .WIG, .L1, .VPMINUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3B, 0xFF, .WIG, .L0, .VPMINUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3B, 0xFF, .WIG, .L1, .VPMINUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3C, 0xFF, .WIG, .L1, .VPMAXSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3C, 0xFF, .WIG, .L0, .VPMAXSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3D, 0xFF, .WIG, .L0, .VPMAXSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3D, 0xFF, .WIG, .L1, .VPMAXSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3E, 0xFF, .WIG, .L1, .VPMAXUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3E, 0xFF, .WIG, .L0, .VPMAXUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3F, 0xFF, .WIG, .L0, .VPMAXUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x3F, 0xFF, .WIG, .L1, .VPMAXUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x40, 0xFF, .WIG, .L1, .VPMULLD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x40, 0xFF, .WIG, .L0, .VPMULLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x41, 0xFF, .WIG, .L0, .VPHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x45, 0xFF, .W1, .L0, .VPSRLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x45, 0xFF, .W0, .L1, .VPSRLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x45, 0xFF, .W1, .L1, .VPSRLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x45, 0xFF, .W0, .L0, .VPSRLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x46, 0xFF, .W0, .L0, .VPSRAVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x46, 0xFF, .W0, .L1, .VPSRAVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x47, 0xFF, .W1, .L1, .VPSLLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x47, 0xFF, .W1, .L0, .VPSLLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x47, 0xFF, .W0, .L0, .VPSLLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x47, 0xFF, .W0, .L1, .VPSLLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x5A, 0xFF, .WIG, .L1, .VBROADCASTI128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8C, 0xFF, .W1, .L1, .VPMASKMOVQ, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8C, 0xFF, .W0, .L0, .VPMASKMOVD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8C, 0xFF, .W0, .L1, .VPMASKMOVD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8C, 0xFF, .W1, .L0, .VPMASKMOVQ, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8E, 0xFF, .W0, .L0, .VPMASKMOVD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8E, 0xFF, .W1, .L1, .VPMASKMOVQ, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8E, 0xFF, .W1, .L0, .VPMASKMOVQ, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8E, 0xFF, .W0, .L1, .VPMASKMOVD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x90, 0xFF, .W0, .L1, .VPGATHERDD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x90, 0xFF, .W0, .L0, .VPGATHERDD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x90, 0xFF, .W1, .L1, .VPGATHERDQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x90, 0xFF, .W1, .L0, .VPGATHERDQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x91, 0xFF, .W1, .L1, .VPGATHERQQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x91, 0xFF, .W0, .L1, .VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x91, 0xFF, .W1, .L0, .VPGATHERQQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x91, 0xFF, .W0, .L0, .VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x92, 0xFF, .W1, .L0, .VGATHERDPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x92, 0xFF, .W0, .L0, .VGATHERDPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x92, 0xFF, .W0, .L1, .VGATHERDPS, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x92, 0xFF, .W1, .L1, .VGATHERDPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x93, 0xFF, .W1, .L0, .VGATHERQPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x93, 0xFF, .W0, .L0, .VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x93, 0xFF, .W1, .L1, .VGATHERQPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x93, 0xFF, .W0, .L1, .VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x96, 0xFF, .W1, .L0, .VFMADDSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x96, 0xFF, .W0, .L1, .VFMADDSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x96, 0xFF, .W1, .L1, .VFMADDSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x96, 0xFF, .W0, .L0, .VFMADDSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x97, 0xFF, .W1, .L0, .VFMSUBADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x97, 0xFF, .W1, .L1, .VFMSUBADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x97, 0xFF, .W0, .L1, .VFMSUBADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x97, 0xFF, .W0, .L0, .VFMSUBADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x98, 0xFF, .W1, .L0, .VFMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x98, 0xFF, .W1, .L1, .VFMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x98, 0xFF, .W0, .L0, .VFMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x98, 0xFF, .W0, .L1, .VFMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x99, 0xFF, .W1, .LIG, .VFMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x99, 0xFF, .W0, .LIG, .VFMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9A, 0xFF, .W1, .L0, .VFMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9A, 0xFF, .W0, .L1, .VFMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9A, 0xFF, .W1, .L1, .VFMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9A, 0xFF, .W0, .L0, .VFMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9B, 0xFF, .W0, .LIG, .VFMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9B, 0xFF, .W1, .LIG, .VFMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9C, 0xFF, .W0, .L0, .VFNMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9C, 0xFF, .W1, .L1, .VFNMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9C, 0xFF, .W0, .L1, .VFNMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9C, 0xFF, .W1, .L0, .VFNMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9D, 0xFF, .W1, .LIG, .VFNMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9D, 0xFF, .W0, .LIG, .VFNMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9E, 0xFF, .W0, .L1, .VFNMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9E, 0xFF, .W0, .L0, .VFNMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9E, 0xFF, .W1, .L0, .VFNMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9E, 0xFF, .W1, .L1, .VFNMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9F, 0xFF, .W0, .LIG, .VFNMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x9F, 0xFF, .W1, .LIG, .VFNMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA6, 0xFF, .W1, .L1, .VFMADDSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA6, 0xFF, .W0, .L0, .VFMADDSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA6, 0xFF, .W1, .L0, .VFMADDSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA6, 0xFF, .W0, .L1, .VFMADDSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA7, 0xFF, .W1, .L0, .VFMSUBADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA7, 0xFF, .W1, .L1, .VFMSUBADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA7, 0xFF, .W0, .L0, .VFMSUBADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA7, 0xFF, .W0, .L1, .VFMSUBADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA8, 0xFF, .W1, .L0, .VFMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA8, 0xFF, .W1, .L1, .VFMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA8, 0xFF, .W0, .L1, .VFMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA8, 0xFF, .W0, .L0, .VFMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA9, 0xFF, .W0, .LIG, .VFMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA9, 0xFF, .W1, .LIG, .VFMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAA, 0xFF, .W1, .L0, .VFMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAA, 0xFF, .W0, .L0, .VFMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAA, 0xFF, .W0, .L1, .VFMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAA, 0xFF, .W1, .L1, .VFMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAB, 0xFF, .W1, .LIG, .VFMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAB, 0xFF, .W0, .LIG, .VFMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAC, 0xFF, .W0, .L1, .VFNMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAC, 0xFF, .W1, .L1, .VFNMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAC, 0xFF, .W0, .L0, .VFNMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAC, 0xFF, .W1, .L0, .VFNMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAD, 0xFF, .W1, .LIG, .VFNMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAD, 0xFF, .W0, .LIG, .VFNMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAE, 0xFF, .W0, .L1, .VFNMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAE, 0xFF, .W1, .L0, .VFNMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAE, 0xFF, .W1, .L1, .VFNMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAE, 0xFF, .W0, .L0, .VFNMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAF, 0xFF, .W0, .LIG, .VFNMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xAF, 0xFF, .W1, .LIG, .VFNMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB6, 0xFF, .W0, .L1, .VFMADDSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB6, 0xFF, .W0, .L0, .VFMADDSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB6, 0xFF, .W1, .L0, .VFMADDSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB6, 0xFF, .W1, .L1, .VFMADDSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB7, 0xFF, .W1, .L0, .VFMSUBADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB7, 0xFF, .W0, .L1, .VFMSUBADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB7, 0xFF, .W0, .L0, .VFMSUBADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB7, 0xFF, .W1, .L1, .VFMSUBADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB8, 0xFF, .W1, .L1, .VFMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB8, 0xFF, .W0, .L1, .VFMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB8, 0xFF, .W0, .L0, .VFMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB8, 0xFF, .W1, .L0, .VFMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB9, 0xFF, .W1, .LIG, .VFMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xB9, 0xFF, .W0, .LIG, .VFMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBA, 0xFF, .W1, .L1, .VFMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBA, 0xFF, .W1, .L0, .VFMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBA, 0xFF, .W0, .L1, .VFMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBA, 0xFF, .W0, .L0, .VFMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBB, 0xFF, .W1, .LIG, .VFMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBB, 0xFF, .W0, .LIG, .VFMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBC, 0xFF, .W1, .L0, .VFNMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBC, 0xFF, .W1, .L1, .VFNMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBC, 0xFF, .W0, .L0, .VFNMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBC, 0xFF, .W0, .L1, .VFNMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBD, 0xFF, .W1, .LIG, .VFNMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBD, 0xFF, .W0, .LIG, .VFNMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBE, 0xFF, .W1, .L1, .VFNMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBE, 0xFF, .W1, .L0, .VFNMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBE, 0xFF, .W0, .L1, .VFNMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBE, 0xFF, .W0, .L0, .VFNMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBF, 0xFF, .W1, .LIG, .VFNMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xBF, 0xFF, .W0, .LIG, .VFNMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xDB, 0xFF, .WIG, .L0, .VAESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xDC, 0xFF, .WIG, .L0, .VAESENC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xDD, 0xFF, .WIG, .L0, .VAESENCLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xDE, 0xFF, .WIG, .L0, .VAESDEC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xDF, 0xFF, .WIG, .L0, .VAESDECLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xF7, 0xFF, .W1, .L0, .SHLX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xF7, 0xFF, .W0, .L0, .SHLX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0xF5, 0xFF, .W1, .L0, .PEXT, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0xF5, 0xFF, .W0, .L0, .PEXT, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0xF7, 0xFF, .W0, .L0, .SARX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0xF7, 0xFF, .W1, .L0, .SARX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=2, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 3, 0xF5, 0xFF, .W0, .L0, .PDEP, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 3, 0xF5, 0xFF, .W1, .L0, .PDEP, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 3, 0xF6, 0xFF, .W1, .L0, .MULX, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 3, 0xF6, 0xFF, .W0, .L0, .MULX, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 3, 0xF7, 0xFF, .W0, .L0, .SHRX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 3, 0xF7, 0xFF, .W1, .L0, .SHRX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, {esc=._0F38, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x00, 0xFF, .W1, .L1, .VPERMQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x01, 0xFF, .W1, .L1, .VPERMPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x02, 0xFF, .W0, .L1, .VPBLENDD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x02, 0xFF, .W0, .L0, .VPBLENDD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x06, 0xFF, .WIG, .L1, .VPERM2F128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x08, 0xFF, .WIG, .L1, .VROUNDPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x08, 0xFF, .WIG, .L0, .VROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x09, 0xFF, .WIG, .L0, .VROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x09, 0xFF, .WIG, .L1, .VROUNDPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x0A, 0xFF, .WIG, .LIG, .VROUNDSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x0B, 0xFF, .WIG, .LIG, .VROUNDSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x0C, 0xFF, .WIG, .L0, .VBLENDPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x0C, 0xFF, .WIG, .L1, .VBLENDPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x0D, 0xFF, .WIG, .L1, .VBLENDPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x0D, 0xFF, .WIG, .L0, .VBLENDPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x0E, 0xFF, .WIG, .L1, .VPBLENDW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x0E, 0xFF, .WIG, .L0, .VPBLENDW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x0F, 0xFF, .WIG, .L1, .VPALIGNR, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x0F, 0xFF, .WIG, .L0, .VPALIGNR, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x14, 0xFF, .WIG, .L0, .VPEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x15, 0xFF, .WIG, .L0, .VPEXTRW, {.RM16, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x16, 0xFF, .WIG, .L0, .VPEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x16, 0xFF, .W1, .L0, .VPEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x17, 0xFF, .WIG, .L0, .VEXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x18, 0xFF, .WIG, .L1, .VINSERTF128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x19, 0xFF, .WIG, .L1, .VEXTRACTF128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x1D, 0xFF, .WIG, .L1, .VCVTPS2PH, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x1D, 0xFF, .WIG, .L0, .VCVTPS2PH, {.XMM_M64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x20, 0xFF, .WIG, .L0, .VPINSRB, {.XMM, .XMM, .RM8, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x21, 0xFF, .WIG, .L0, .VINSERTPS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x22, 0xFF, .WIG, .L0, .VPINSRD, {.XMM, .XMM, .RM32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x22, 0xFF, .W1, .L0, .VPINSRQ, {.XMM, .XMM, .RM64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x30, 0xFF, .W0, .L0, .KSHIFTRB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x30, 0xFF, .W1, .L0, .KSHIFTRW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x31, 0xFF, .W0, .L0, .KSHIFTRD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x31, 0xFF, .W1, .L0, .KSHIFTRQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x32, 0xFF, .W1, .L0, .KSHIFTLW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x32, 0xFF, .W0, .L0, .KSHIFTLB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x33, 0xFF, .W0, .L0, .KSHIFTLD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x33, 0xFF, .W1, .L0, .KSHIFTLQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x38, 0xFF, .WIG, .L1, .VINSERTI128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x39, 0xFF, .WIG, .L1, .VEXTRACTI128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x40, 0xFF, .WIG, .L1, .VDPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x40, 0xFF, .WIG, .L0, .VDPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x41, 0xFF, .WIG, .L0, .VDPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x42, 0xFF, .WIG, .L0, .VMPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x42, 0xFF, .WIG, .L1, .VMPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x44, 0xFF, .WIG, .L0, .VPCLMULQDQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x44, 0xFF, .WIG, .L1, .VPCLMULQDQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x46, 0xFF, .WIG, .L1, .VPERM2I128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x4A, 0xFF, .W0, .L0, .VBLENDVPS, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x4A, 0xFF, .W0, .L1, .VBLENDVPS, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x4B, 0xFF, .W0, .L1, .VBLENDVPD, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x4B, 0xFF, .W0, .L0, .VBLENDVPD, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x4C, 0xFF, .W0, .L1, .VPBLENDVB, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x4C, 0xFF, .W0, .L0, .VPBLENDVB, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0xDF, 0xFF, .WIG, .L0, .VAESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.VEX, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 3, 0xF0, 0xFF, .W0, .L0, .RORX, {.R32, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 3, 0xF0, 0xFF, .W1, .L0, .RORX, {.R64, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=3, vex_type=.VEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, } @(rodata) EVEX_DECODE_ENTRIES := [418]lib.VEX_Decode_Entry{ - {._0F, 1, 0x6F, 0xFF, .W0, .L1, .VMOVDQA32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 1, 0x6F, 0xFF, .W0, .L0, .VMOVDQA32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 1, 0x6F, 0xFF, .W1, .L0, .VMOVDQA64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 1, 0x6F, 0xFF, .W1, .L2, .VMOVDQA64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F, 1, 0x6F, 0xFF, .W1, .L1, .VMOVDQA64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 1, 0x6F, 0xFF, .W0, .L2, .VMOVDQA32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F, 1, 0x72, 0x01, .W0, .L2, .VPROLD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x01, .W0, .L0, .VPROLD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x01, .W0, .L1, .VPROLD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x01, .W1, .L2, .VPROLQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x01, .W1, .L0, .VPROLQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0x01, .W1, .L1, .VPROLQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, modrm_reg_ext=true}}, - {._0F, 1, 0x72, 0xFF, .W0, .L2, .VPRORD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F, 1, 0x72, 0xFF, .W1, .L0, .VPRORQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 1, 0x72, 0xFF, .W1, .L2, .VPRORQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F, 1, 0x72, 0xFF, .W0, .L0, .VPRORD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 1, 0x72, 0xFF, .W0, .L1, .VPRORD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 1, 0x72, 0xFF, .W1, .L1, .VPRORQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 1, 0x7F, 0xFF, .W1, .L0, .VMOVDQA64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 1, 0x7F, 0xFF, .W1, .L1, .VMOVDQA64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 1, 0x7F, 0xFF, .W1, .L2, .VMOVDQA64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F, 1, 0x7F, 0xFF, .W0, .L1, .VMOVDQA32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 1, 0x7F, 0xFF, .W0, .L2, .VMOVDQA32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F, 1, 0x7F, 0xFF, .W0, .L0, .VMOVDQA32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 2, 0x6F, 0xFF, .W1, .L1, .VMOVDQU64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 2, 0x6F, 0xFF, .W0, .L0, .VMOVDQU32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 2, 0x6F, 0xFF, .W1, .L2, .VMOVDQU64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F, 2, 0x6F, 0xFF, .W0, .L2, .VMOVDQU32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F, 2, 0x6F, 0xFF, .W0, .L1, .VMOVDQU32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 2, 0x6F, 0xFF, .W1, .L0, .VMOVDQU64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 2, 0x7F, 0xFF, .W1, .L0, .VMOVDQU64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 2, 0x7F, 0xFF, .W0, .L1, .VMOVDQU32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 2, 0x7F, 0xFF, .W1, .L1, .VMOVDQU64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 2, 0x7F, 0xFF, .W0, .L2, .VMOVDQU32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F, 2, 0x7F, 0xFF, .W0, .L0, .VMOVDQU32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 2, 0x7F, 0xFF, .W1, .L2, .VMOVDQU64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F, 3, 0x6F, 0xFF, .W1, .L1, .VMOVDQU16, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F, 3, 0x6F, 0xFF, .W1, .L0, .VMOVDQU16, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 3, 0x6F, 0xFF, .W0, .L2, .VMOVDQU8, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F, 3, 0x6F, 0xFF, .W0, .L1, .VMOVDQU8, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 3, 0x6F, 0xFF, .W0, .L0, .VMOVDQU8, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 3, 0x6F, 0xFF, .W1, .L2, .VMOVDQU16, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F, 3, 0x7F, 0xFF, .W1, .L2, .VMOVDQU16, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F, 3, 0x7F, 0xFF, .W1, .L0, .VMOVDQU16, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F, 3, 0x7F, 0xFF, .W0, .L0, .VMOVDQU8, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F, 3, 0x7F, 0xFF, .W0, .L1, .VMOVDQU8, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F, 3, 0x7F, 0xFF, .W0, .L2, .VMOVDQU8, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F, 3, 0x7F, 0xFF, .W1, .L1, .VMOVDQU16, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x10, 0xFF, .W1, .L2, .VPSRLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x10, 0xFF, .W1, .L0, .VPSRLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x10, 0xFF, .W1, .L1, .VPSRLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x11, 0xFF, .W1, .L2, .VPSRAVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x11, 0xFF, .W1, .L0, .VPSRAVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x11, 0xFF, .W1, .L1, .VPSRAVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x12, 0xFF, .W1, .L1, .VPSLLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x12, 0xFF, .W1, .L2, .VPSLLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x12, 0xFF, .W1, .L0, .VPSLLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x13, 0xFF, .WIG, .L2, .VCVTPH2PS, {.ZMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_l=.L2}}, - {._0F38, 1, 0x14, 0xFF, .W0, .L0, .VPRORVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x14, 0xFF, .W1, .L0, .VPRORVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x14, 0xFF, .W0, .L2, .VPRORVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x14, 0xFF, .W1, .L2, .VPRORVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x14, 0xFF, .W0, .L1, .VPRORVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x14, 0xFF, .W1, .L1, .VPRORVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x15, 0xFF, .W0, .L1, .VPROLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x15, 0xFF, .W1, .L1, .VPROLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x15, 0xFF, .W1, .L0, .VPROLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x15, 0xFF, .W0, .L0, .VPROLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x15, 0xFF, .W0, .L2, .VPROLVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x15, 0xFF, .W1, .L2, .VPROLVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x26, 0xFF, .W1, .L1, .VPTESTMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x26, 0xFF, .W1, .L2, .VPTESTMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x26, 0xFF, .W0, .L2, .VPTESTMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x26, 0xFF, .W0, .L1, .VPTESTMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x26, 0xFF, .W1, .L0, .VPTESTMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x26, 0xFF, .W0, .L0, .VPTESTMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x27, 0xFF, .W0, .L0, .VPTESTMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x27, 0xFF, .W0, .L2, .VPTESTMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x27, 0xFF, .W1, .L2, .VPTESTMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x27, 0xFF, .W1, .L0, .VPTESTMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x27, 0xFF, .W1, .L1, .VPTESTMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x27, 0xFF, .W0, .L1, .VPTESTMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x2C, 0xFF, .W0, .L1, .VSCALEFPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x2C, 0xFF, .W1, .L1, .VSCALEFPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x2C, 0xFF, .W0, .L0, .VSCALEFPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x2C, 0xFF, .W1, .L0, .VSCALEFPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x2C, 0xFF, .W1, .L2, .VSCALEFPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x2C, 0xFF, .W0, .L2, .VSCALEFPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x2D, 0xFF, .W1, .LIG, .VSCALEFSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}}, - {._0F38, 1, 0x2D, 0xFF, .W0, .LIG, .VSCALEFSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}}, - {._0F38, 1, 0x42, 0xFF, .W0, .L2, .VGETEXPPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x42, 0xFF, .W0, .L0, .VGETEXPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x42, 0xFF, .W1, .L1, .VGETEXPPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x42, 0xFF, .W0, .L1, .VGETEXPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x42, 0xFF, .W1, .L0, .VGETEXPPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x42, 0xFF, .W1, .L2, .VGETEXPPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x43, 0xFF, .W1, .LIG, .VGETEXPSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}}, - {._0F38, 1, 0x43, 0xFF, .W0, .LIG, .VGETEXPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}}, - {._0F38, 1, 0x44, 0xFF, .W0, .L0, .VPLZCNTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x44, 0xFF, .W0, .L2, .VPLZCNTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x44, 0xFF, .W1, .L0, .VPLZCNTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x44, 0xFF, .W0, .L1, .VPLZCNTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x44, 0xFF, .W1, .L1, .VPLZCNTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x44, 0xFF, .W1, .L2, .VPLZCNTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x46, 0xFF, .W1, .L0, .VPSRAVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x46, 0xFF, .W1, .L2, .VPSRAVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x46, 0xFF, .W1, .L1, .VPSRAVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x4C, 0xFF, .W1, .L0, .VRCP14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x4C, 0xFF, .W0, .L2, .VRCP14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x4C, 0xFF, .W1, .L2, .VRCP14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x4C, 0xFF, .W0, .L1, .VRCP14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x4C, 0xFF, .W0, .L0, .VRCP14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x4C, 0xFF, .W1, .L1, .VRCP14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x4D, 0xFF, .W0, .LIG, .VRCP14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}}, - {._0F38, 1, 0x4D, 0xFF, .W1, .LIG, .VRCP14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}}, - {._0F38, 1, 0x4E, 0xFF, .W1, .L0, .VRSQRT14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x4E, 0xFF, .W1, .L2, .VRSQRT14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x4E, 0xFF, .W1, .L1, .VRSQRT14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x4E, 0xFF, .W0, .L1, .VRSQRT14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x4E, 0xFF, .W0, .L2, .VRSQRT14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x4E, 0xFF, .W0, .L0, .VRSQRT14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x4F, 0xFF, .W1, .LIG, .VRSQRT14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1}}, - {._0F38, 1, 0x4F, 0xFF, .W0, .LIG, .VRSQRT14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0}}, - {._0F38, 1, 0x64, 0xFF, .W1, .L0, .VPBLENDMQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x64, 0xFF, .W0, .L2, .VPBLENDMD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x64, 0xFF, .W1, .L1, .VPBLENDMQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x64, 0xFF, .W0, .L0, .VPBLENDMD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x64, 0xFF, .W1, .L2, .VPBLENDMQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x64, 0xFF, .W0, .L1, .VPBLENDMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x65, 0xFF, .W1, .L0, .VBLENDMPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x65, 0xFF, .W0, .L1, .VBLENDMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x65, 0xFF, .W0, .L0, .VBLENDMPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x65, 0xFF, .W0, .L2, .VBLENDMPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x65, 0xFF, .W1, .L1, .VBLENDMPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x65, 0xFF, .W1, .L2, .VBLENDMPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x66, 0xFF, .W1, .L1, .VPBLENDMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x66, 0xFF, .W1, .L0, .VPBLENDMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x66, 0xFF, .W1, .L2, .VPBLENDMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x66, 0xFF, .W0, .L0, .VPBLENDMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x66, 0xFF, .W0, .L1, .VPBLENDMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x66, 0xFF, .W0, .L2, .VPBLENDMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x75, 0xFF, .W0, .L0, .VPERMI2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x75, 0xFF, .W0, .L1, .VPERMI2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x75, 0xFF, .W0, .L2, .VPERMI2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x75, 0xFF, .W1, .L1, .VPERMI2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x75, 0xFF, .W1, .L0, .VPERMI2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x75, 0xFF, .W1, .L2, .VPERMI2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x76, 0xFF, .W0, .L0, .VPERMI2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x76, 0xFF, .W0, .L1, .VPERMI2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x76, 0xFF, .W0, .L2, .VPERMI2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x76, 0xFF, .W1, .L0, .VPERMI2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x76, 0xFF, .W1, .L2, .VPERMI2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x76, 0xFF, .W1, .L1, .VPERMI2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x77, 0xFF, .W0, .L1, .VPERMI2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x77, 0xFF, .W0, .L0, .VPERMI2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x77, 0xFF, .W1, .L0, .VPERMI2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x77, 0xFF, .W1, .L1, .VPERMI2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x77, 0xFF, .W1, .L2, .VPERMI2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x77, 0xFF, .W0, .L2, .VPERMI2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x7D, 0xFF, .W0, .L1, .VPERMT2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x7D, 0xFF, .W0, .L2, .VPERMT2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x7D, 0xFF, .W1, .L0, .VPERMT2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x7D, 0xFF, .W1, .L1, .VPERMT2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x7D, 0xFF, .W1, .L2, .VPERMT2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x7D, 0xFF, .W0, .L0, .VPERMT2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x7E, 0xFF, .W0, .L0, .VPERMT2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x7E, 0xFF, .W0, .L2, .VPERMT2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x7E, 0xFF, .W0, .L1, .VPERMT2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x7E, 0xFF, .W1, .L1, .VPERMT2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x7E, 0xFF, .W1, .L0, .VPERMT2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x7E, 0xFF, .W1, .L2, .VPERMT2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x7F, 0xFF, .W0, .L1, .VPERMT2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x7F, 0xFF, .W0, .L0, .VPERMT2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x7F, 0xFF, .W0, .L2, .VPERMT2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x7F, 0xFF, .W1, .L0, .VPERMT2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x7F, 0xFF, .W1, .L1, .VPERMT2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x7F, 0xFF, .W1, .L2, .VPERMT2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x83, 0xFF, .W1, .L1, .VPMULTISHIFTQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x83, 0xFF, .W1, .L0, .VPMULTISHIFTQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x83, 0xFF, .W1, .L2, .VPMULTISHIFTQB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x88, 0xFF, .W1, .L2, .VEXPANDPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x88, 0xFF, .W1, .L0, .VEXPANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x88, 0xFF, .W0, .L2, .VEXPANDPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x88, 0xFF, .W1, .L1, .VEXPANDPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x88, 0xFF, .W0, .L0, .VEXPANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x88, 0xFF, .W0, .L1, .VEXPANDPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x89, 0xFF, .W1, .L2, .VPEXPANDQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x89, 0xFF, .W1, .L0, .VPEXPANDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x89, 0xFF, .W0, .L2, .VPEXPANDD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x89, 0xFF, .W1, .L1, .VPEXPANDQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x89, 0xFF, .W0, .L0, .VPEXPANDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x89, 0xFF, .W0, .L1, .VPEXPANDD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x8A, 0xFF, .W1, .L2, .VCOMPRESSPD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x8A, 0xFF, .W1, .L1, .VCOMPRESSPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x8A, 0xFF, .W0, .L2, .VCOMPRESSPS, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x8A, 0xFF, .W0, .L0, .VCOMPRESSPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x8A, 0xFF, .W0, .L1, .VCOMPRESSPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x8A, 0xFF, .W1, .L0, .VCOMPRESSPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x8B, 0xFF, .W1, .L2, .VPCOMPRESSQ, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0x8B, 0xFF, .W0, .L0, .VPCOMPRESSD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x8B, 0xFF, .W0, .L1, .VPCOMPRESSD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x8B, 0xFF, .W0, .L2, .VPCOMPRESSD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x8B, 0xFF, .W1, .L0, .VPCOMPRESSQ, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x8B, 0xFF, .W1, .L1, .VPCOMPRESSQ, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x8D, 0xFF, .W0, .L0, .VPERMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0x8D, 0xFF, .W1, .L1, .VPERMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0x8D, 0xFF, .W0, .L2, .VPERMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0x8D, 0xFF, .W0, .L1, .VPERMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0x8D, 0xFF, .W1, .L0, .VPERMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0x8D, 0xFF, .W1, .L2, .VPERMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0xA0, 0xFF, .W1, .L2, .VPSCATTERDQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0xA0, 0xFF, .W1, .L0, .VPSCATTERDQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xA0, 0xFF, .W1, .L1, .VPSCATTERDQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xA0, 0xFF, .W0, .L2, .VPSCATTERDD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0xA0, 0xFF, .W0, .L1, .VPSCATTERDD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xA0, 0xFF, .W0, .L0, .VPSCATTERDD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xA1, 0xFF, .W0, .L0, .VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xA1, 0xFF, .W1, .L0, .VPSCATTERQQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xA1, 0xFF, .W0, .L1, .VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xA1, 0xFF, .W1, .L1, .VPSCATTERQQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xA1, 0xFF, .W1, .L2, .VPSCATTERQQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0xA1, 0xFF, .W0, .L2, .VPSCATTERQD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0xA2, 0xFF, .W1, .L2, .VSCATTERDPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0xA2, 0xFF, .W0, .L1, .VSCATTERDPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xA2, 0xFF, .W0, .L0, .VSCATTERDPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xA2, 0xFF, .W0, .L2, .VSCATTERDPS, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0xA2, 0xFF, .W1, .L0, .VSCATTERDPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xA2, 0xFF, .W1, .L1, .VSCATTERDPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xA3, 0xFF, .W0, .L0, .VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xA3, 0xFF, .W1, .L2, .VSCATTERQPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 1, 0xA3, 0xFF, .W0, .L1, .VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xA3, 0xFF, .W1, .L0, .VSCATTERQPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xA3, 0xFF, .W1, .L1, .VSCATTERQPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xA3, 0xFF, .W0, .L2, .VSCATTERQPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0xC4, 0xFF, .W0, .L2, .VPCONFLICTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 1, 0xC4, 0xFF, .W0, .L1, .VPCONFLICTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 1, 0xC4, 0xFF, .W1, .L0, .VPCONFLICTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 1, 0xC4, 0xFF, .W0, .L0, .VPCONFLICTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 1, 0xC4, 0xFF, .W1, .L1, .VPCONFLICTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 1, 0xC4, 0xFF, .W1, .L2, .VPCONFLICTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 2, 0x10, 0xFF, .W0, .L2, .VPMOVUSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x10, 0xFF, .W0, .L1, .VPMOVUSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x10, 0xFF, .W0, .L0, .VPMOVUSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x11, 0xFF, .W0, .L0, .VPMOVUSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x11, 0xFF, .W0, .L1, .VPMOVUSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x11, 0xFF, .W0, .L2, .VPMOVUSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x12, 0xFF, .W0, .L2, .VPMOVUSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x12, 0xFF, .W0, .L0, .VPMOVUSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x12, 0xFF, .W0, .L1, .VPMOVUSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x13, 0xFF, .W0, .L0, .VPMOVUSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x13, 0xFF, .W0, .L2, .VPMOVUSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x13, 0xFF, .W0, .L1, .VPMOVUSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x14, 0xFF, .W0, .L2, .VPMOVUSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x14, 0xFF, .W0, .L0, .VPMOVUSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x14, 0xFF, .W0, .L1, .VPMOVUSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x15, 0xFF, .W0, .L0, .VPMOVUSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x15, 0xFF, .W0, .L1, .VPMOVUSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x15, 0xFF, .W0, .L2, .VPMOVUSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x20, 0xFF, .W0, .L1, .VPMOVSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x20, 0xFF, .W0, .L2, .VPMOVSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x20, 0xFF, .W0, .L0, .VPMOVSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x21, 0xFF, .W0, .L2, .VPMOVSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x21, 0xFF, .W0, .L0, .VPMOVSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x21, 0xFF, .W0, .L1, .VPMOVSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x22, 0xFF, .W0, .L2, .VPMOVSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x22, 0xFF, .W0, .L0, .VPMOVSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x22, 0xFF, .W0, .L1, .VPMOVSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x23, 0xFF, .W0, .L1, .VPMOVSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x23, 0xFF, .W0, .L0, .VPMOVSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x23, 0xFF, .W0, .L2, .VPMOVSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x24, 0xFF, .W0, .L1, .VPMOVSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x24, 0xFF, .W0, .L0, .VPMOVSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x24, 0xFF, .W0, .L2, .VPMOVSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x25, 0xFF, .W0, .L2, .VPMOVSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x25, 0xFF, .W0, .L0, .VPMOVSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x25, 0xFF, .W0, .L1, .VPMOVSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x26, 0xFF, .W1, .L2, .VPTESTNMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 2, 0x26, 0xFF, .W1, .L0, .VPTESTNMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 2, 0x26, 0xFF, .W0, .L1, .VPTESTNMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x26, 0xFF, .W0, .L0, .VPTESTNMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x26, 0xFF, .W0, .L2, .VPTESTNMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x26, 0xFF, .W1, .L1, .VPTESTNMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 2, 0x27, 0xFF, .W1, .L1, .VPTESTNMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 2, 0x27, 0xFF, .W1, .L0, .VPTESTNMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 2, 0x27, 0xFF, .W1, .L2, .VPTESTNMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 2, 0x27, 0xFF, .W0, .L0, .VPTESTNMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x27, 0xFF, .W0, .L1, .VPTESTNMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x27, 0xFF, .W0, .L2, .VPTESTNMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x28, 0xFF, .W1, .L1, .VPMOVM2W, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 2, 0x28, 0xFF, .W1, .L0, .VPMOVM2W, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 2, 0x28, 0xFF, .W1, .L2, .VPMOVM2W, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 2, 0x28, 0xFF, .W0, .L1, .VPMOVM2B, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x28, 0xFF, .W0, .L2, .VPMOVM2B, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x28, 0xFF, .W0, .L0, .VPMOVM2B, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x29, 0xFF, .W1, .L2, .VPMOVW2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 2, 0x29, 0xFF, .W1, .L1, .VPMOVW2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 2, 0x29, 0xFF, .W0, .L1, .VPMOVB2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x29, 0xFF, .W0, .L0, .VPMOVB2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x29, 0xFF, .W0, .L2, .VPMOVB2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x29, 0xFF, .W1, .L0, .VPMOVW2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 2, 0x30, 0xFF, .W0, .L2, .VPMOVWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x30, 0xFF, .W0, .L0, .VPMOVWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x30, 0xFF, .W0, .L1, .VPMOVWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x31, 0xFF, .W0, .L1, .VPMOVDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x31, 0xFF, .W0, .L0, .VPMOVDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x31, 0xFF, .W0, .L2, .VPMOVDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x32, 0xFF, .W0, .L2, .VPMOVQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x32, 0xFF, .W0, .L1, .VPMOVQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x32, 0xFF, .W0, .L0, .VPMOVQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x33, 0xFF, .W0, .L2, .VPMOVDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x33, 0xFF, .W0, .L0, .VPMOVDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x33, 0xFF, .W0, .L1, .VPMOVDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x34, 0xFF, .W0, .L0, .VPMOVQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x34, 0xFF, .W0, .L1, .VPMOVQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x34, 0xFF, .W0, .L2, .VPMOVQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x35, 0xFF, .W0, .L0, .VPMOVQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x35, 0xFF, .W0, .L1, .VPMOVQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x35, 0xFF, .W0, .L2, .VPMOVQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x38, 0xFF, .W1, .L2, .VPMOVM2Q, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 2, 0x38, 0xFF, .W1, .L0, .VPMOVM2Q, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F38, 2, 0x38, 0xFF, .W0, .L2, .VPMOVM2D, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x38, 0xFF, .W1, .L1, .VPMOVM2Q, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 2, 0x38, 0xFF, .W0, .L0, .VPMOVM2D, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x38, 0xFF, .W0, .L1, .VPMOVM2D, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x39, 0xFF, .W1, .L2, .VPMOVQ2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F38, 2, 0x39, 0xFF, .W1, .L1, .VPMOVQ2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F38, 2, 0x39, 0xFF, .W0, .L1, .VPMOVD2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F38, 2, 0x39, 0xFF, .W0, .L0, .VPMOVD2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F38, 2, 0x39, 0xFF, .W0, .L2, .VPMOVD2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F38, 2, 0x39, 0xFF, .W1, .L0, .VPMOVQ2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x03, 0xFF, .W1, .L0, .VALIGNQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x03, 0xFF, .W0, .L0, .VALIGND, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x03, 0xFF, .W1, .L1, .VALIGNQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x03, 0xFF, .W0, .L1, .VALIGND, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x03, 0xFF, .W0, .L2, .VALIGND, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x03, 0xFF, .W1, .L2, .VALIGNQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x08, 0xFF, .W0, .L0, .VRNDSCALEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x08, 0xFF, .W0, .L1, .VRNDSCALEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x08, 0xFF, .W0, .L2, .VRNDSCALEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x09, 0xFF, .W1, .L0, .VRNDSCALEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x09, 0xFF, .W1, .L1, .VRNDSCALEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x09, 0xFF, .W1, .L2, .VRNDSCALEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x0A, 0xFF, .W0, .LIG, .VRNDSCALESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, - {._0F3A, 1, 0x0B, 0xFF, .W1, .LIG, .VRNDSCALESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, - {._0F3A, 1, 0x1D, 0xFF, .WIG, .L2, .VCVTPS2PH, {.YMM_M256, .ZMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_l=.L2}}, - {._0F3A, 1, 0x1E, 0xFF, .W1, .L2, .VPCMPUQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x1E, 0xFF, .W1, .L0, .VPCMPUQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x1E, 0xFF, .W1, .L1, .VPCMPUQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x1E, 0xFF, .W0, .L2, .VPCMPUD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x1E, 0xFF, .W0, .L1, .VPCMPUD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x1E, 0xFF, .W0, .L0, .VPCMPUD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x1F, 0xFF, .W1, .L2, .VPCMPQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x1F, 0xFF, .W1, .L0, .VPCMPQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x1F, 0xFF, .W0, .L2, .VPCMPD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x1F, 0xFF, .W0, .L0, .VPCMPD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x1F, 0xFF, .W0, .L1, .VPCMPD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x1F, 0xFF, .W1, .L1, .VPCMPQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x25, 0xFF, .W0, .L0, .VPTERNLOGD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x25, 0xFF, .W0, .L1, .VPTERNLOGD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x25, 0xFF, .W1, .L0, .VPTERNLOGQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x25, 0xFF, .W1, .L1, .VPTERNLOGQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x25, 0xFF, .W0, .L2, .VPTERNLOGD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x25, 0xFF, .W1, .L2, .VPTERNLOGQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x26, 0xFF, .W1, .L0, .VGETMANTPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x26, 0xFF, .W1, .L1, .VGETMANTPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x26, 0xFF, .W0, .L1, .VGETMANTPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x26, 0xFF, .W0, .L0, .VGETMANTPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x26, 0xFF, .W1, .L2, .VGETMANTPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x26, 0xFF, .W0, .L2, .VGETMANTPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x27, 0xFF, .W1, .LIG, .VGETMANTSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, - {._0F3A, 1, 0x27, 0xFF, .W0, .LIG, .VGETMANTSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, - {._0F3A, 1, 0x3E, 0xFF, .W1, .L2, .VPCMPUW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x3E, 0xFF, .W0, .L2, .VPCMPUB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x3E, 0xFF, .W0, .L0, .VPCMPUB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x3E, 0xFF, .W1, .L0, .VPCMPUW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x3E, 0xFF, .W0, .L1, .VPCMPUB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x3E, 0xFF, .W1, .L1, .VPCMPUW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x3F, 0xFF, .W1, .L0, .VPCMPW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x3F, 0xFF, .W1, .L1, .VPCMPW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x3F, 0xFF, .W0, .L1, .VPCMPB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x3F, 0xFF, .W0, .L0, .VPCMPB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x3F, 0xFF, .W0, .L2, .VPCMPB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x3F, 0xFF, .W1, .L2, .VPCMPW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x42, 0xFF, .W0, .L0, .VDBPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x42, 0xFF, .W0, .L1, .VDBPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x42, 0xFF, .W0, .L2, .VDBPSADBW, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x50, 0xFF, .W1, .L1, .VRANGEPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x50, 0xFF, .W0, .L2, .VRANGEPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x50, 0xFF, .W0, .L1, .VRANGEPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x50, 0xFF, .W1, .L0, .VRANGEPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x50, 0xFF, .W1, .L2, .VRANGEPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x50, 0xFF, .W0, .L0, .VRANGEPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x51, 0xFF, .W0, .LIG, .VRANGESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, - {._0F3A, 1, 0x51, 0xFF, .W1, .LIG, .VRANGESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, - {._0F3A, 1, 0x54, 0xFF, .W1, .L2, .VFIXUPIMMPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x54, 0xFF, .W1, .L1, .VFIXUPIMMPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x54, 0xFF, .W0, .L1, .VFIXUPIMMPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x54, 0xFF, .W0, .L0, .VFIXUPIMMPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x54, 0xFF, .W0, .L2, .VFIXUPIMMPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x54, 0xFF, .W1, .L0, .VFIXUPIMMPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x55, 0xFF, .W1, .LIG, .VFIXUPIMMSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, - {._0F3A, 1, 0x55, 0xFF, .W0, .LIG, .VFIXUPIMMSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, - {._0F3A, 1, 0x56, 0xFF, .W1, .L2, .VREDUCEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x56, 0xFF, .W1, .L0, .VREDUCEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x56, 0xFF, .W0, .L1, .VREDUCEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x56, 0xFF, .W0, .L0, .VREDUCEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x56, 0xFF, .W0, .L2, .VREDUCEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x56, 0xFF, .W1, .L1, .VREDUCEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x57, 0xFF, .W0, .LIG, .VREDUCESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, - {._0F3A, 1, 0x57, 0xFF, .W1, .LIG, .VREDUCESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, - {._0F3A, 1, 0x66, 0xFF, .W0, .L0, .VFPCLASSPS, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, - {._0F3A, 1, 0x66, 0xFF, .W0, .L1, .VFPCLASSPS, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, - {._0F3A, 1, 0x66, 0xFF, .W0, .L2, .VFPCLASSPS, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, - {._0F3A, 1, 0x66, 0xFF, .W1, .L0, .VFPCLASSPD, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, - {._0F3A, 1, 0x66, 0xFF, .W1, .L2, .VFPCLASSPD, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, - {._0F3A, 1, 0x66, 0xFF, .W1, .L1, .VFPCLASSPD, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, - {._0F3A, 1, 0x67, 0xFF, .W1, .LIG, .VFPCLASSSD, {.K, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1}}, - {._0F3A, 1, 0x67, 0xFF, .W0, .LIG, .VFPCLASSSS, {.K, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0}}, + {._0F, 1, 0x6F, 0xFF, .W0, .L1, .VMOVDQA32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6F, 0xFF, .W0, .L0, .VMOVDQA32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6F, 0xFF, .W1, .L0, .VMOVDQA64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6F, 0xFF, .W1, .L2, .VMOVDQA64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6F, 0xFF, .W1, .L1, .VMOVDQA64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6F, 0xFF, .W0, .L2, .VMOVDQA32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x72, 0x01, .W0, .L2, .VPROLD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x01, .W0, .L0, .VPROLD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x01, .W0, .L1, .VPROLD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x01, .W1, .L2, .VPROLQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x01, .W1, .L0, .VPROLQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0x01, .W1, .L1, .VPROLQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, modrm_reg_ext=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0xFF, .W0, .L2, .VPRORD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0xFF, .W1, .L0, .VPRORQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0xFF, .W1, .L2, .VPRORQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0xFF, .W0, .L0, .VPRORD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0xFF, .W0, .L1, .VPRORD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x72, 0xFF, .W1, .L1, .VPRORQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F, 1, 0x7F, 0xFF, .W1, .L0, .VMOVDQA64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7F, 0xFF, .W1, .L1, .VMOVDQA64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7F, 0xFF, .W1, .L2, .VMOVDQA64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7F, 0xFF, .W0, .L1, .VMOVDQA32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7F, 0xFF, .W0, .L2, .VMOVDQA32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7F, 0xFF, .W0, .L0, .VMOVDQA32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x6F, 0xFF, .W1, .L1, .VMOVDQU64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x6F, 0xFF, .W0, .L0, .VMOVDQU32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x6F, 0xFF, .W1, .L2, .VMOVDQU64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x6F, 0xFF, .W0, .L2, .VMOVDQU32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x6F, 0xFF, .W0, .L1, .VMOVDQU32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x6F, 0xFF, .W1, .L0, .VMOVDQU64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x7F, 0xFF, .W1, .L0, .VMOVDQU64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x7F, 0xFF, .W0, .L1, .VMOVDQU32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x7F, 0xFF, .W1, .L1, .VMOVDQU64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x7F, 0xFF, .W0, .L2, .VMOVDQU32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x7F, 0xFF, .W0, .L0, .VMOVDQU32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x7F, 0xFF, .W1, .L2, .VMOVDQU64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x6F, 0xFF, .W1, .L1, .VMOVDQU16, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x6F, 0xFF, .W1, .L0, .VMOVDQU16, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x6F, 0xFF, .W0, .L2, .VMOVDQU8, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x6F, 0xFF, .W0, .L1, .VMOVDQU8, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x6F, 0xFF, .W0, .L0, .VMOVDQU8, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x6F, 0xFF, .W1, .L2, .VMOVDQU16, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x7F, 0xFF, .W1, .L2, .VMOVDQU16, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x7F, 0xFF, .W1, .L0, .VMOVDQU16, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x7F, 0xFF, .W0, .L0, .VMOVDQU8, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x7F, 0xFF, .W0, .L1, .VMOVDQU8, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x7F, 0xFF, .W0, .L2, .VMOVDQU8, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x7F, 0xFF, .W1, .L1, .VMOVDQU16, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x10, 0xFF, .W1, .L2, .VPSRLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x10, 0xFF, .W1, .L0, .VPSRLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x10, 0xFF, .W1, .L1, .VPSRLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x11, 0xFF, .W1, .L2, .VPSRAVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x11, 0xFF, .W1, .L0, .VPSRAVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x11, 0xFF, .W1, .L1, .VPSRAVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x12, 0xFF, .W1, .L1, .VPSLLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x12, 0xFF, .W1, .L2, .VPSLLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x12, 0xFF, .W1, .L0, .VPSLLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x13, 0xFF, .WIG, .L2, .VCVTPH2PS, {.ZMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x14, 0xFF, .W0, .L0, .VPRORVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x14, 0xFF, .W1, .L0, .VPRORVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x14, 0xFF, .W0, .L2, .VPRORVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x14, 0xFF, .W1, .L2, .VPRORVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x14, 0xFF, .W0, .L1, .VPRORVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x14, 0xFF, .W1, .L1, .VPRORVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x15, 0xFF, .W0, .L1, .VPROLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x15, 0xFF, .W1, .L1, .VPROLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x15, 0xFF, .W1, .L0, .VPROLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x15, 0xFF, .W0, .L0, .VPROLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x15, 0xFF, .W0, .L2, .VPROLVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x15, 0xFF, .W1, .L2, .VPROLVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x26, 0xFF, .W1, .L1, .VPTESTMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x26, 0xFF, .W1, .L2, .VPTESTMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x26, 0xFF, .W0, .L2, .VPTESTMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x26, 0xFF, .W0, .L1, .VPTESTMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x26, 0xFF, .W1, .L0, .VPTESTMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x26, 0xFF, .W0, .L0, .VPTESTMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x27, 0xFF, .W0, .L0, .VPTESTMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x27, 0xFF, .W0, .L2, .VPTESTMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x27, 0xFF, .W1, .L2, .VPTESTMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x27, 0xFF, .W1, .L0, .VPTESTMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x27, 0xFF, .W1, .L1, .VPTESTMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x27, 0xFF, .W0, .L1, .VPTESTMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2C, 0xFF, .W0, .L1, .VSCALEFPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2C, 0xFF, .W1, .L1, .VSCALEFPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2C, 0xFF, .W0, .L0, .VSCALEFPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2C, 0xFF, .W1, .L0, .VSCALEFPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2C, 0xFF, .W1, .L2, .VSCALEFPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2C, 0xFF, .W0, .L2, .VSCALEFPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2D, 0xFF, .W1, .LIG, .VSCALEFSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x2D, 0xFF, .W0, .LIG, .VSCALEFSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x42, 0xFF, .W0, .L2, .VGETEXPPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x42, 0xFF, .W0, .L0, .VGETEXPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x42, 0xFF, .W1, .L1, .VGETEXPPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x42, 0xFF, .W0, .L1, .VGETEXPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x42, 0xFF, .W1, .L0, .VGETEXPPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x42, 0xFF, .W1, .L2, .VGETEXPPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x43, 0xFF, .W1, .LIG, .VGETEXPSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x43, 0xFF, .W0, .LIG, .VGETEXPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x44, 0xFF, .W0, .L0, .VPLZCNTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x44, 0xFF, .W0, .L2, .VPLZCNTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x44, 0xFF, .W1, .L0, .VPLZCNTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x44, 0xFF, .W0, .L1, .VPLZCNTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x44, 0xFF, .W1, .L1, .VPLZCNTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x44, 0xFF, .W1, .L2, .VPLZCNTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x46, 0xFF, .W1, .L0, .VPSRAVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x46, 0xFF, .W1, .L2, .VPSRAVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x46, 0xFF, .W1, .L1, .VPSRAVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x4C, 0xFF, .W1, .L0, .VRCP14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4C, 0xFF, .W0, .L2, .VRCP14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4C, 0xFF, .W1, .L2, .VRCP14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4C, 0xFF, .W0, .L1, .VRCP14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4C, 0xFF, .W0, .L0, .VRCP14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4C, 0xFF, .W1, .L1, .VRCP14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4D, 0xFF, .W0, .LIG, .VRCP14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x4D, 0xFF, .W1, .LIG, .VRCP14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x4E, 0xFF, .W1, .L0, .VRSQRT14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4E, 0xFF, .W1, .L2, .VRSQRT14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4E, 0xFF, .W1, .L1, .VRSQRT14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4E, 0xFF, .W0, .L1, .VRSQRT14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4E, 0xFF, .W0, .L2, .VRSQRT14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4E, 0xFF, .W0, .L0, .VRSQRT14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x4F, 0xFF, .W1, .LIG, .VRSQRT14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x4F, 0xFF, .W0, .LIG, .VRSQRT14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x64, 0xFF, .W1, .L0, .VPBLENDMQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x64, 0xFF, .W0, .L2, .VPBLENDMD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x64, 0xFF, .W1, .L1, .VPBLENDMQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x64, 0xFF, .W0, .L0, .VPBLENDMD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x64, 0xFF, .W1, .L2, .VPBLENDMQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x64, 0xFF, .W0, .L1, .VPBLENDMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x65, 0xFF, .W1, .L0, .VBLENDMPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x65, 0xFF, .W0, .L1, .VBLENDMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x65, 0xFF, .W0, .L0, .VBLENDMPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x65, 0xFF, .W0, .L2, .VBLENDMPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x65, 0xFF, .W1, .L1, .VBLENDMPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x65, 0xFF, .W1, .L2, .VBLENDMPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x66, 0xFF, .W1, .L1, .VPBLENDMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x66, 0xFF, .W1, .L0, .VPBLENDMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x66, 0xFF, .W1, .L2, .VPBLENDMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x66, 0xFF, .W0, .L0, .VPBLENDMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x66, 0xFF, .W0, .L1, .VPBLENDMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x66, 0xFF, .W0, .L2, .VPBLENDMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x75, 0xFF, .W0, .L0, .VPERMI2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x75, 0xFF, .W0, .L1, .VPERMI2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x75, 0xFF, .W0, .L2, .VPERMI2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x75, 0xFF, .W1, .L1, .VPERMI2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x75, 0xFF, .W1, .L0, .VPERMI2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x75, 0xFF, .W1, .L2, .VPERMI2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x76, 0xFF, .W0, .L0, .VPERMI2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x76, 0xFF, .W0, .L1, .VPERMI2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x76, 0xFF, .W0, .L2, .VPERMI2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x76, 0xFF, .W1, .L0, .VPERMI2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x76, 0xFF, .W1, .L2, .VPERMI2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x76, 0xFF, .W1, .L1, .VPERMI2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x77, 0xFF, .W0, .L1, .VPERMI2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x77, 0xFF, .W0, .L0, .VPERMI2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x77, 0xFF, .W1, .L0, .VPERMI2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x77, 0xFF, .W1, .L1, .VPERMI2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x77, 0xFF, .W1, .L2, .VPERMI2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x77, 0xFF, .W0, .L2, .VPERMI2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7D, 0xFF, .W0, .L1, .VPERMT2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7D, 0xFF, .W0, .L2, .VPERMT2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7D, 0xFF, .W1, .L0, .VPERMT2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7D, 0xFF, .W1, .L1, .VPERMT2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7D, 0xFF, .W1, .L2, .VPERMT2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7D, 0xFF, .W0, .L0, .VPERMT2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7E, 0xFF, .W0, .L0, .VPERMT2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7E, 0xFF, .W0, .L2, .VPERMT2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7E, 0xFF, .W0, .L1, .VPERMT2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7E, 0xFF, .W1, .L1, .VPERMT2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7E, 0xFF, .W1, .L0, .VPERMT2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7E, 0xFF, .W1, .L2, .VPERMT2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7F, 0xFF, .W0, .L1, .VPERMT2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7F, 0xFF, .W0, .L0, .VPERMT2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7F, 0xFF, .W0, .L2, .VPERMT2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7F, 0xFF, .W1, .L0, .VPERMT2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7F, 0xFF, .W1, .L1, .VPERMT2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x7F, 0xFF, .W1, .L2, .VPERMT2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x83, 0xFF, .W1, .L1, .VPMULTISHIFTQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x83, 0xFF, .W1, .L0, .VPMULTISHIFTQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x83, 0xFF, .W1, .L2, .VPMULTISHIFTQB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x88, 0xFF, .W1, .L2, .VEXPANDPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x88, 0xFF, .W1, .L0, .VEXPANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x88, 0xFF, .W0, .L2, .VEXPANDPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x88, 0xFF, .W1, .L1, .VEXPANDPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x88, 0xFF, .W0, .L0, .VEXPANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x88, 0xFF, .W0, .L1, .VEXPANDPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x89, 0xFF, .W1, .L2, .VPEXPANDQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x89, 0xFF, .W1, .L0, .VPEXPANDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x89, 0xFF, .W0, .L2, .VPEXPANDD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x89, 0xFF, .W1, .L1, .VPEXPANDQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x89, 0xFF, .W0, .L0, .VPEXPANDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x89, 0xFF, .W0, .L1, .VPEXPANDD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8A, 0xFF, .W1, .L2, .VCOMPRESSPD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8A, 0xFF, .W1, .L1, .VCOMPRESSPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8A, 0xFF, .W0, .L2, .VCOMPRESSPS, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8A, 0xFF, .W0, .L0, .VCOMPRESSPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8A, 0xFF, .W0, .L1, .VCOMPRESSPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8A, 0xFF, .W1, .L0, .VCOMPRESSPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8B, 0xFF, .W1, .L2, .VPCOMPRESSQ, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8B, 0xFF, .W0, .L0, .VPCOMPRESSD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8B, 0xFF, .W0, .L1, .VPCOMPRESSD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8B, 0xFF, .W0, .L2, .VPCOMPRESSD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8B, 0xFF, .W1, .L0, .VPCOMPRESSQ, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8B, 0xFF, .W1, .L1, .VPCOMPRESSQ, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x8D, 0xFF, .W0, .L0, .VPERMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8D, 0xFF, .W1, .L1, .VPERMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8D, 0xFF, .W0, .L2, .VPERMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8D, 0xFF, .W0, .L1, .VPERMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8D, 0xFF, .W1, .L0, .VPERMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0x8D, 0xFF, .W1, .L2, .VPERMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 1, 0xA0, 0xFF, .W1, .L2, .VPSCATTERDQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA0, 0xFF, .W1, .L0, .VPSCATTERDQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA0, 0xFF, .W1, .L1, .VPSCATTERDQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA0, 0xFF, .W0, .L2, .VPSCATTERDD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA0, 0xFF, .W0, .L1, .VPSCATTERDD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA0, 0xFF, .W0, .L0, .VPSCATTERDD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA1, 0xFF, .W0, .L0, .VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA1, 0xFF, .W1, .L0, .VPSCATTERQQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA1, 0xFF, .W0, .L1, .VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA1, 0xFF, .W1, .L1, .VPSCATTERQQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA1, 0xFF, .W1, .L2, .VPSCATTERQQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA1, 0xFF, .W0, .L2, .VPSCATTERQD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA2, 0xFF, .W1, .L2, .VSCATTERDPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA2, 0xFF, .W0, .L1, .VSCATTERDPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA2, 0xFF, .W0, .L0, .VSCATTERDPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA2, 0xFF, .W0, .L2, .VSCATTERDPS, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA2, 0xFF, .W1, .L0, .VSCATTERDPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA2, 0xFF, .W1, .L1, .VSCATTERDPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA3, 0xFF, .W0, .L0, .VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA3, 0xFF, .W1, .L2, .VSCATTERQPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA3, 0xFF, .W0, .L1, .VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA3, 0xFF, .W1, .L0, .VSCATTERQPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA3, 0xFF, .W1, .L1, .VSCATTERQPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xA3, 0xFF, .W0, .L2, .VSCATTERQPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xC4, 0xFF, .W0, .L2, .VPCONFLICTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xC4, 0xFF, .W0, .L1, .VPCONFLICTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xC4, 0xFF, .W1, .L0, .VPCONFLICTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xC4, 0xFF, .W0, .L0, .VPCONFLICTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xC4, 0xFF, .W1, .L1, .VPCONFLICTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0xC4, 0xFF, .W1, .L2, .VPCONFLICTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x10, 0xFF, .W0, .L2, .VPMOVUSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x10, 0xFF, .W0, .L1, .VPMOVUSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x10, 0xFF, .W0, .L0, .VPMOVUSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x11, 0xFF, .W0, .L0, .VPMOVUSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x11, 0xFF, .W0, .L1, .VPMOVUSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x11, 0xFF, .W0, .L2, .VPMOVUSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x12, 0xFF, .W0, .L2, .VPMOVUSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x12, 0xFF, .W0, .L0, .VPMOVUSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x12, 0xFF, .W0, .L1, .VPMOVUSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x13, 0xFF, .W0, .L0, .VPMOVUSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x13, 0xFF, .W0, .L2, .VPMOVUSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x13, 0xFF, .W0, .L1, .VPMOVUSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x14, 0xFF, .W0, .L2, .VPMOVUSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x14, 0xFF, .W0, .L0, .VPMOVUSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x14, 0xFF, .W0, .L1, .VPMOVUSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x15, 0xFF, .W0, .L0, .VPMOVUSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x15, 0xFF, .W0, .L1, .VPMOVUSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x15, 0xFF, .W0, .L2, .VPMOVUSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x20, 0xFF, .W0, .L1, .VPMOVSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x20, 0xFF, .W0, .L2, .VPMOVSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x20, 0xFF, .W0, .L0, .VPMOVSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x21, 0xFF, .W0, .L2, .VPMOVSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x21, 0xFF, .W0, .L0, .VPMOVSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x21, 0xFF, .W0, .L1, .VPMOVSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x22, 0xFF, .W0, .L2, .VPMOVSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x22, 0xFF, .W0, .L0, .VPMOVSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x22, 0xFF, .W0, .L1, .VPMOVSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x23, 0xFF, .W0, .L1, .VPMOVSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x23, 0xFF, .W0, .L0, .VPMOVSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x23, 0xFF, .W0, .L2, .VPMOVSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x24, 0xFF, .W0, .L1, .VPMOVSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x24, 0xFF, .W0, .L0, .VPMOVSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x24, 0xFF, .W0, .L2, .VPMOVSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x25, 0xFF, .W0, .L2, .VPMOVSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x25, 0xFF, .W0, .L0, .VPMOVSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x25, 0xFF, .W0, .L1, .VPMOVSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x26, 0xFF, .W1, .L2, .VPTESTNMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x26, 0xFF, .W1, .L0, .VPTESTNMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x26, 0xFF, .W0, .L1, .VPTESTNMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x26, 0xFF, .W0, .L0, .VPTESTNMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x26, 0xFF, .W0, .L2, .VPTESTNMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x26, 0xFF, .W1, .L1, .VPTESTNMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x27, 0xFF, .W1, .L1, .VPTESTNMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x27, 0xFF, .W1, .L0, .VPTESTNMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x27, 0xFF, .W1, .L2, .VPTESTNMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x27, 0xFF, .W0, .L0, .VPTESTNMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x27, 0xFF, .W0, .L1, .VPTESTNMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x27, 0xFF, .W0, .L2, .VPTESTNMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F38, 2, 0x28, 0xFF, .W1, .L1, .VPMOVM2W, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x28, 0xFF, .W1, .L0, .VPMOVM2W, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x28, 0xFF, .W1, .L2, .VPMOVM2W, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x28, 0xFF, .W0, .L1, .VPMOVM2B, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x28, 0xFF, .W0, .L2, .VPMOVM2B, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x28, 0xFF, .W0, .L0, .VPMOVM2B, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x29, 0xFF, .W1, .L2, .VPMOVW2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x29, 0xFF, .W1, .L1, .VPMOVW2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x29, 0xFF, .W0, .L1, .VPMOVB2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x29, 0xFF, .W0, .L0, .VPMOVB2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x29, 0xFF, .W0, .L2, .VPMOVB2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x29, 0xFF, .W1, .L0, .VPMOVW2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x30, 0xFF, .W0, .L2, .VPMOVWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x30, 0xFF, .W0, .L0, .VPMOVWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x30, 0xFF, .W0, .L1, .VPMOVWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x31, 0xFF, .W0, .L1, .VPMOVDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x31, 0xFF, .W0, .L0, .VPMOVDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x31, 0xFF, .W0, .L2, .VPMOVDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x32, 0xFF, .W0, .L2, .VPMOVQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x32, 0xFF, .W0, .L1, .VPMOVQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x32, 0xFF, .W0, .L0, .VPMOVQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x33, 0xFF, .W0, .L2, .VPMOVDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x33, 0xFF, .W0, .L0, .VPMOVDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x33, 0xFF, .W0, .L1, .VPMOVDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x34, 0xFF, .W0, .L0, .VPMOVQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x34, 0xFF, .W0, .L1, .VPMOVQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x34, 0xFF, .W0, .L2, .VPMOVQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x35, 0xFF, .W0, .L0, .VPMOVQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x35, 0xFF, .W0, .L1, .VPMOVQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x35, 0xFF, .W0, .L2, .VPMOVQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x38, 0xFF, .W1, .L2, .VPMOVM2Q, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x38, 0xFF, .W1, .L0, .VPMOVM2Q, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x38, 0xFF, .W0, .L2, .VPMOVM2D, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x38, 0xFF, .W1, .L1, .VPMOVM2Q, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x38, 0xFF, .W0, .L0, .VPMOVM2D, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x38, 0xFF, .W0, .L1, .VPMOVM2D, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x39, 0xFF, .W1, .L2, .VPMOVQ2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x39, 0xFF, .W1, .L1, .VPMOVQ2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x39, 0xFF, .W0, .L1, .VPMOVD2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x39, 0xFF, .W0, .L0, .VPMOVD2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x39, 0xFF, .W0, .L2, .VPMOVD2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=2, needs_modrm=true}}, + {._0F38, 2, 0x39, 0xFF, .W1, .L0, .VPMOVQ2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=2, needs_modrm=true}}, + {._0F3A, 1, 0x03, 0xFF, .W1, .L0, .VALIGNQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x03, 0xFF, .W0, .L0, .VALIGND, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x03, 0xFF, .W1, .L1, .VALIGNQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x03, 0xFF, .W0, .L1, .VALIGND, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x03, 0xFF, .W0, .L2, .VALIGND, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x03, 0xFF, .W1, .L2, .VALIGNQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x08, 0xFF, .W0, .L0, .VRNDSCALEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x08, 0xFF, .W0, .L1, .VRNDSCALEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x08, 0xFF, .W0, .L2, .VRNDSCALEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x09, 0xFF, .W1, .L0, .VRNDSCALEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x09, 0xFF, .W1, .L1, .VRNDSCALEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x09, 0xFF, .W1, .L2, .VRNDSCALEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x0A, 0xFF, .W0, .LIG, .VRNDSCALESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x0B, 0xFF, .W1, .LIG, .VRNDSCALESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1D, 0xFF, .WIG, .L2, .VCVTPS2PH, {.YMM_M256, .ZMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x1E, 0xFF, .W1, .L2, .VPCMPUQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1E, 0xFF, .W1, .L0, .VPCMPUQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1E, 0xFF, .W1, .L1, .VPCMPUQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1E, 0xFF, .W0, .L2, .VPCMPUD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1E, 0xFF, .W0, .L1, .VPCMPUD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1E, 0xFF, .W0, .L0, .VPCMPUD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1F, 0xFF, .W1, .L2, .VPCMPQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1F, 0xFF, .W1, .L0, .VPCMPQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1F, 0xFF, .W0, .L2, .VPCMPD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1F, 0xFF, .W0, .L0, .VPCMPD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1F, 0xFF, .W0, .L1, .VPCMPD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x1F, 0xFF, .W1, .L1, .VPCMPQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x25, 0xFF, .W0, .L0, .VPTERNLOGD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x25, 0xFF, .W0, .L1, .VPTERNLOGD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x25, 0xFF, .W1, .L0, .VPTERNLOGQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x25, 0xFF, .W1, .L1, .VPTERNLOGQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x25, 0xFF, .W0, .L2, .VPTERNLOGD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x25, 0xFF, .W1, .L2, .VPTERNLOGQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x26, 0xFF, .W1, .L0, .VGETMANTPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x26, 0xFF, .W1, .L1, .VGETMANTPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x26, 0xFF, .W0, .L1, .VGETMANTPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x26, 0xFF, .W0, .L0, .VGETMANTPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x26, 0xFF, .W1, .L2, .VGETMANTPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x26, 0xFF, .W0, .L2, .VGETMANTPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x27, 0xFF, .W1, .LIG, .VGETMANTSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x27, 0xFF, .W0, .LIG, .VGETMANTSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3E, 0xFF, .W1, .L2, .VPCMPUW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3E, 0xFF, .W0, .L2, .VPCMPUB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3E, 0xFF, .W0, .L0, .VPCMPUB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3E, 0xFF, .W1, .L0, .VPCMPUW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3E, 0xFF, .W0, .L1, .VPCMPUB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3E, 0xFF, .W1, .L1, .VPCMPUW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3F, 0xFF, .W1, .L0, .VPCMPW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3F, 0xFF, .W1, .L1, .VPCMPW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3F, 0xFF, .W0, .L1, .VPCMPB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3F, 0xFF, .W0, .L0, .VPCMPB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3F, 0xFF, .W0, .L2, .VPCMPB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x3F, 0xFF, .W1, .L2, .VPCMPW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x42, 0xFF, .W0, .L0, .VDBPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x42, 0xFF, .W0, .L1, .VDBPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x42, 0xFF, .W0, .L2, .VDBPSADBW, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x50, 0xFF, .W1, .L1, .VRANGEPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x50, 0xFF, .W0, .L2, .VRANGEPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x50, 0xFF, .W0, .L1, .VRANGEPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x50, 0xFF, .W1, .L0, .VRANGEPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x50, 0xFF, .W1, .L2, .VRANGEPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x50, 0xFF, .W0, .L0, .VRANGEPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x51, 0xFF, .W0, .LIG, .VRANGESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x51, 0xFF, .W1, .LIG, .VRANGESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x54, 0xFF, .W1, .L2, .VFIXUPIMMPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x54, 0xFF, .W1, .L1, .VFIXUPIMMPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x54, 0xFF, .W0, .L1, .VFIXUPIMMPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x54, 0xFF, .W0, .L0, .VFIXUPIMMPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x54, 0xFF, .W0, .L2, .VFIXUPIMMPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x54, 0xFF, .W1, .L0, .VFIXUPIMMPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x55, 0xFF, .W1, .LIG, .VFIXUPIMMSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x55, 0xFF, .W0, .LIG, .VFIXUPIMMSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x56, 0xFF, .W1, .L2, .VREDUCEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x56, 0xFF, .W1, .L0, .VREDUCEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x56, 0xFF, .W0, .L1, .VREDUCEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x56, 0xFF, .W0, .L0, .VREDUCEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x56, 0xFF, .W0, .L2, .VREDUCEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x56, 0xFF, .W1, .L1, .VREDUCEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x57, 0xFF, .W0, .LIG, .VREDUCESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x57, 0xFF, .W1, .LIG, .VREDUCESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=4, needs_modrm=true}}, + {._0F3A, 1, 0x66, 0xFF, .W0, .L0, .VFPCLASSPS, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x66, 0xFF, .W0, .L1, .VFPCLASSPS, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x66, 0xFF, .W0, .L2, .VFPCLASSPS, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x66, 0xFF, .W1, .L0, .VFPCLASSPD, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x66, 0xFF, .W1, .L2, .VFPCLASSPD, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x66, 0xFF, .W1, .L1, .VFPCLASSPD, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x67, 0xFF, .W1, .LIG, .VFPCLASSSD, {.K, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W1, op_count=3, needs_modrm=true}}, + {._0F3A, 1, 0x67, 0xFF, .W0, .LIG, .VFPCLASSSS, {.K, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F3A, prefix=1, vex_type=.EVEX, vex_w=.W0, op_count=3, needs_modrm=true}}, } @(rodata) From 0e90e5babf657c186b83c0c8a34183ebbb303e0c Mon Sep 17 00:00:00 2001 From: gingerBill Date: Mon, 15 Jun 2026 23:02:19 +0100 Subject: [PATCH 14/27] Update the binary tables --- core/rexcode/x86/encoding_types.odin | 4 +- core/rexcode/x86/tablegen/gen.odin | 8 +- .../x86/tablegen/generated/encode_tables.odin | 306 +++++++++--------- core/rexcode/x86/tables/x86.encode_forms.bin | Bin 37680 -> 37680 bytes core/rexcode/x86/tables/x86.evex.bin | Bin 8360 -> 8360 bytes core/rexcode/x86/tables/x86.legacy.bin | Bin 25400 -> 25400 bytes core/rexcode/x86/tables/x86.vex.bin | Bin 13340 -> 13340 bytes 7 files changed, 159 insertions(+), 159 deletions(-) diff --git a/core/rexcode/x86/encoding_types.odin b/core/rexcode/x86/encoding_types.odin index fe6ad9ac4..ea537b6f4 100644 --- a/core/rexcode/x86/encoding_types.odin +++ b/core/rexcode/x86/encoding_types.odin @@ -259,10 +259,10 @@ Encoding_Flags :: bit_field u32 { modrm_reg_ext: bool | 1, // ModR/M reg field is opcode extension (use ext field) mode_32_only: bool | 1, // only valid in Mode._32 (e.g. short-form INC/DEC at 0x40-0x4F) - explicit_count: u8 | 2, // 0..<4 non-implicit operands + explicit_count: u8 | 3, // 0..<4 non-implicit operands has_implicit: bool | 1, // any implicit operand - op_count: u8 | 2, // total operands including implicit (0..<4) + op_count: u8 | 3, // total operands including implicit (0..<4) needs_modrm: bool | 1, // any enc is .MR/.REG/.VVVV } diff --git a/core/rexcode/x86/tablegen/gen.odin b/core/rexcode/x86/tablegen/gen.odin index 303d9f206..0a9ccc038 100644 --- a/core/rexcode/x86/tablegen/gen.odin +++ b/core/rexcode/x86/tablegen/gen.odin @@ -385,11 +385,11 @@ write_flags :: proc(sb: ^strings.Builder, enc: union{lib.Encoding, Collected_Ent switch e in enc { case lib.Encoding: encoding_operand_count: u8 = 0 - has_implict := false + has_implicit := false for op_type in e.ops { if op_type == .NONE { break } if lib.is_implicit_op_inline(op_type) { - has_implict = true + has_implicit = true } else { encoding_operand_count += 1 } @@ -397,8 +397,8 @@ write_flags :: proc(sb: ^strings.Builder, enc: union{lib.Encoding, Collected_Ent if encoding_operand_count > 0 { append(&parts, fmt.tprintf("explicit_count=%d", encoding_operand_count)) } - if has_implict { - append(&parts, "has_implict=true") + if has_implicit { + append(&parts, "has_implicit=true") } case Collected_Entry: diff --git a/core/rexcode/x86/tablegen/generated/encode_tables.odin b/core/rexcode/x86/tablegen/generated/encode_tables.odin index 5acf93a23..11d45ce67 100644 --- a/core/rexcode/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/x86/tablegen/generated/encode_tables.odin @@ -26,14 +26,14 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.MOV, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true, explicit_count=2}}, {.MOV, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true, explicit_count=2}}, {.MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, - {.MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {explicit_count=1, has_implict=true}}, - {.MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}}, - {.MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}}, - {.MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, - {.MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {explicit_count=1, has_implict=true}}, - {.MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}}, - {.MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}}, - {.MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {explicit_count=1, has_implicit=true}}, + {.MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implicit=true}}, + {.MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implicit=true}}, + {.MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, + {.MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {explicit_count=1, has_implicit=true}}, + {.MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implicit=true}}, + {.MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implicit=true}}, + {.MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, {.MOV, {.RM16, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {explicit_count=2}}, {.MOV, {.RM64, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {force_rex_w=true, explicit_count=2}}, {.MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {explicit_count=2}}, @@ -44,14 +44,14 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.MOV, {.DR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F, explicit_count=2}}, // .MOVABS {.MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, 0xB8, 0, {force_rex_w=true, explicit_count=2}}, - {.MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {explicit_count=1, has_implict=true}}, - {.MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}}, - {.MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implict=true}}, - {.MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, - {.MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {explicit_count=1, has_implict=true}}, - {.MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}}, - {.MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implict=true}}, - {.MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {explicit_count=1, has_implicit=true}}, + {.MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implicit=true}}, + {.MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {explicit_count=1, has_implicit=true}}, + {.MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, + {.MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {explicit_count=1, has_implicit=true}}, + {.MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implicit=true}}, + {.MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {explicit_count=1, has_implicit=true}}, + {.MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, // .MOVZX {.MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F, explicit_count=2}}, {.MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F, explicit_count=2}}, @@ -67,9 +67,9 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .MOVSXD {.MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x63, 0, {force_rex_w=true, explicit_count=2}}, // .XCHG - {.XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {explicit_count=1, has_implict=true}}, - {.XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {explicit_count=1, has_implict=true}}, - {.XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {explicit_count=1, has_implicit=true}}, + {.XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {explicit_count=1, has_implicit=true}}, + {.XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, {.XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x86, 0, {lock_ok=true, explicit_count=2}}, {.XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true, explicit_count=2}}, {.XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true, explicit_count=2}}, @@ -104,10 +104,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {explicit_count=2}}, {.ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {explicit_count=2}}, {.ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {force_rex_w=true, explicit_count=2}}, - {.ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x04, 0, {explicit_count=1, has_implict=true}}, - {.ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x05, 0, {explicit_count=1, has_implict=true}}, - {.ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {explicit_count=1, has_implict=true}}, - {.ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x04, 0, {explicit_count=1, has_implicit=true}}, + {.ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x05, 0, {explicit_count=1, has_implicit=true}}, + {.ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {explicit_count=1, has_implicit=true}}, + {.ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, {.ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 0, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, @@ -124,10 +124,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {explicit_count=2}}, {.ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {explicit_count=2}}, {.ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {force_rex_w=true, explicit_count=2}}, - {.ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x14, 0, {explicit_count=1, has_implict=true}}, - {.ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x15, 0, {explicit_count=1, has_implict=true}}, - {.ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {explicit_count=1, has_implict=true}}, - {.ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x14, 0, {explicit_count=1, has_implicit=true}}, + {.ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x15, 0, {explicit_count=1, has_implicit=true}}, + {.ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {explicit_count=1, has_implicit=true}}, + {.ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, {.ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 2, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, @@ -144,10 +144,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {explicit_count=2}}, {.SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {explicit_count=2}}, {.SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {force_rex_w=true, explicit_count=2}}, - {.SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x2C, 0, {explicit_count=1, has_implict=true}}, - {.SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x2D, 0, {explicit_count=1, has_implict=true}}, - {.SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {explicit_count=1, has_implict=true}}, - {.SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x2C, 0, {explicit_count=1, has_implicit=true}}, + {.SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x2D, 0, {explicit_count=1, has_implicit=true}}, + {.SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {explicit_count=1, has_implicit=true}}, + {.SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, {.SUB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 5, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 5, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 5, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, @@ -164,10 +164,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {explicit_count=2}}, {.SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {explicit_count=2}}, {.SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {force_rex_w=true, explicit_count=2}}, - {.SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x1C, 0, {explicit_count=1, has_implict=true}}, - {.SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x1D, 0, {explicit_count=1, has_implict=true}}, - {.SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {explicit_count=1, has_implict=true}}, - {.SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x1C, 0, {explicit_count=1, has_implicit=true}}, + {.SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x1D, 0, {explicit_count=1, has_implicit=true}}, + {.SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {explicit_count=1, has_implicit=true}}, + {.SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, {.SBB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 3, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, @@ -232,10 +232,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {explicit_count=2}}, {.CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {explicit_count=2}}, {.CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {force_rex_w=true, explicit_count=2}}, - {.CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x3C, 0, {explicit_count=1, has_implict=true}}, - {.CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x3D, 0, {explicit_count=1, has_implict=true}}, - {.CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {explicit_count=1, has_implict=true}}, - {.CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x3C, 0, {explicit_count=1, has_implicit=true}}, + {.CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x3D, 0, {explicit_count=1, has_implicit=true}}, + {.CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {explicit_count=1, has_implicit=true}}, + {.CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, {.CMP, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 7, {modrm_reg_ext=true, explicit_count=2}}, {.CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true, explicit_count=2}}, {.CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true, explicit_count=2}}, @@ -252,10 +252,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {explicit_count=2}}, {.AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {explicit_count=2}}, {.AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {force_rex_w=true, explicit_count=2}}, - {.AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x24, 0, {explicit_count=1, has_implict=true}}, - {.AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x25, 0, {explicit_count=1, has_implict=true}}, - {.AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {explicit_count=1, has_implict=true}}, - {.AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x24, 0, {explicit_count=1, has_implicit=true}}, + {.AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x25, 0, {explicit_count=1, has_implicit=true}}, + {.AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {explicit_count=1, has_implicit=true}}, + {.AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, {.AND, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 4, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 4, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 4, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, @@ -272,10 +272,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {explicit_count=2}}, {.OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {explicit_count=2}}, {.OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {force_rex_w=true, explicit_count=2}}, - {.OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x0C, 0, {explicit_count=1, has_implict=true}}, - {.OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x0D, 0, {explicit_count=1, has_implict=true}}, - {.OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {explicit_count=1, has_implict=true}}, - {.OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x0C, 0, {explicit_count=1, has_implicit=true}}, + {.OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x0D, 0, {explicit_count=1, has_implicit=true}}, + {.OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {explicit_count=1, has_implicit=true}}, + {.OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, {.OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 1, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, @@ -292,10 +292,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {explicit_count=2}}, {.XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {explicit_count=2}}, {.XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {force_rex_w=true, explicit_count=2}}, - {.XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x34, 0, {explicit_count=1, has_implict=true}}, - {.XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x35, 0, {explicit_count=1, has_implict=true}}, - {.XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {explicit_count=1, has_implict=true}}, - {.XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x34, 0, {explicit_count=1, has_implicit=true}}, + {.XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x35, 0, {explicit_count=1, has_implicit=true}}, + {.XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {explicit_count=1, has_implicit=true}}, + {.XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, {.XOR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 6, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 6, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, {.XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 6, {lock_ok=true, modrm_reg_ext=true, explicit_count=2}}, @@ -313,119 +313,119 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {explicit_count=2}}, {.TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {explicit_count=2}}, {.TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {force_rex_w=true, explicit_count=2}}, - {.TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0xA8, 0, {explicit_count=1, has_implict=true}}, - {.TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0xA9, 0, {explicit_count=1, has_implict=true}}, - {.TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {explicit_count=1, has_implict=true}}, - {.TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {force_rex_w=true, explicit_count=1, has_implict=true}}, + {.TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0xA8, 0, {explicit_count=1, has_implicit=true}}, + {.TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0xA9, 0, {explicit_count=1, has_implicit=true}}, + {.TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {explicit_count=1, has_implicit=true}}, + {.TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {force_rex_w=true, explicit_count=1, has_implicit=true}}, {.TEST, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xF6, 0, {modrm_reg_ext=true, explicit_count=2}}, {.TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true, explicit_count=2}}, {.TEST, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true, explicit_count=2}}, {.TEST, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .SHL - {.SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 4, {modrm_reg_ext=true, explicit_count=2}}, - {.SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true, explicit_count=2}}, - {.SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true, explicit_count=2}}, - {.SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .SHR - {.SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 5, {modrm_reg_ext=true, explicit_count=2}}, - {.SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true, explicit_count=2}}, - {.SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true, explicit_count=2}}, - {.SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .SAR - {.SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 7, {modrm_reg_ext=true, explicit_count=2}}, - {.SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true, explicit_count=2}}, - {.SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true, explicit_count=2}}, - {.SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .ROL - {.ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.ROL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 0, {modrm_reg_ext=true, explicit_count=2}}, - {.ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true, explicit_count=2}}, - {.ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true, explicit_count=2}}, - {.ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .ROR - {.ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.ROR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 1, {modrm_reg_ext=true, explicit_count=2}}, - {.ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true, explicit_count=2}}, - {.ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true, explicit_count=2}}, - {.ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .RCL - {.RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 2, {modrm_reg_ext=true, explicit_count=2}}, - {.RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true, explicit_count=2}}, - {.RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true, explicit_count=2}}, - {.RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .RCR - {.RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 3, {modrm_reg_ext=true, explicit_count=2}}, - {.RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true, explicit_count=2}}, - {.RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true, explicit_count=2}}, - {.RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, - {.RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implict=true}}, + {.RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, + {.RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=1, has_implicit=true}}, {.RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {force_rex_w=true, modrm_reg_ext=true, explicit_count=2}}, // .SHLD {.SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, explicit_count=3}}, {.SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, explicit_count=3}}, {.SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, force_rex_w=true, explicit_count=3}}, - {.SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, explicit_count=2, has_implict=true}}, - {.SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, explicit_count=2, has_implict=true}}, - {.SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, force_rex_w=true, explicit_count=2, has_implict=true}}, + {.SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, explicit_count=2, has_implicit=true}}, + {.SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, explicit_count=2, has_implicit=true}}, + {.SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, force_rex_w=true, explicit_count=2, has_implicit=true}}, // .SHRD {.SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, explicit_count=3}}, {.SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, explicit_count=3}}, {.SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, force_rex_w=true, explicit_count=3}}, - {.SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, explicit_count=2, has_implict=true}}, - {.SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, explicit_count=2, has_implict=true}}, - {.SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, force_rex_w=true, explicit_count=2, has_implict=true}}, + {.SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, explicit_count=2, has_implicit=true}}, + {.SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, explicit_count=2, has_implicit=true}}, + {.SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, force_rex_w=true, explicit_count=2, has_implicit=true}}, // .BT {.BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F, explicit_count=2}}, {.BT, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F, explicit_count=2}}, @@ -1378,13 +1378,13 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .BLENDPD {.BLENDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0D, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .BLENDVPS - {.BLENDVPS, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implict=true}}, + {.BLENDVPS, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x14, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implicit=true}}, // .BLENDVPD - {.BLENDVPD, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implict=true}}, + {.BLENDVPD, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x15, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implicit=true}}, // .PBLENDW {.PBLENDW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0E, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .PBLENDVB - {.PBLENDVB, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x10, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implict=true}}, + {.PBLENDVB, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x10, 0, {esc=._0F38, prefix=1, explicit_count=2, has_implicit=true}}, // .DPPS {.DPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x40, 0, {esc=._0F3A, prefix=1, explicit_count=3}}, // .DPPD @@ -1510,7 +1510,7 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .SHA256MSG2 {.SHA256MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCD, 0, {esc=._0F38, explicit_count=2}}, // .SHA256RNDS2 - {.SHA256RNDS2, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0xCB, 0, {esc=._0F38, explicit_count=2, has_implict=true}}, + {.SHA256RNDS2, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0xCB, 0, {esc=._0F38, explicit_count=2, has_implicit=true}}, // .VADDPS {.VADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, explicit_count=3}}, {.VADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, explicit_count=3}}, @@ -3080,10 +3080,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .FADD {.FADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 0, {explicit_count=1}}, {.FADD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 0, {explicit_count=1}}, - {.FADD, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 192, {explicit_count=1, has_implict=true}}, - {.FADD, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 192, {explicit_count=1, has_implict=true}}, + {.FADD, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 192, {explicit_count=1, has_implicit=true}}, + {.FADD, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 192, {explicit_count=1, has_implicit=true}}, // .FADDP - {.FADDP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 192, {explicit_count=1, has_implict=true}}, + {.FADDP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 192, {explicit_count=1, has_implicit=true}}, {.FADDP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 193, {}}, // .FIADD {.FIADD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 0, {explicit_count=1}}, @@ -3091,10 +3091,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .FSUB {.FSUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 4, {modrm_reg_ext=true, explicit_count=1}}, {.FSUB, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 4, {modrm_reg_ext=true, explicit_count=1}}, - {.FSUB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 224, {explicit_count=1, has_implict=true}}, - {.FSUB, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 232, {explicit_count=1, has_implict=true}}, + {.FSUB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 224, {explicit_count=1, has_implicit=true}}, + {.FSUB, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 232, {explicit_count=1, has_implicit=true}}, // .FSUBP - {.FSUBP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 232, {explicit_count=1, has_implict=true}}, + {.FSUBP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 232, {explicit_count=1, has_implicit=true}}, {.FSUBP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 233, {}}, // .FISUB {.FISUB, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 4, {modrm_reg_ext=true, explicit_count=1}}, @@ -3102,10 +3102,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .FSUBR {.FSUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 5, {modrm_reg_ext=true, explicit_count=1}}, {.FSUBR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 5, {modrm_reg_ext=true, explicit_count=1}}, - {.FSUBR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 232, {explicit_count=1, has_implict=true}}, - {.FSUBR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 224, {explicit_count=1, has_implict=true}}, + {.FSUBR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 232, {explicit_count=1, has_implicit=true}}, + {.FSUBR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 224, {explicit_count=1, has_implicit=true}}, // .FSUBRP - {.FSUBRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 224, {explicit_count=1, has_implict=true}}, + {.FSUBRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 224, {explicit_count=1, has_implicit=true}}, {.FSUBRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 225, {}}, // .FISUBR {.FISUBR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 5, {modrm_reg_ext=true, explicit_count=1}}, @@ -3113,10 +3113,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .FMUL {.FMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 1, {modrm_reg_ext=true, explicit_count=1}}, {.FMUL, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 1, {modrm_reg_ext=true, explicit_count=1}}, - {.FMUL, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 200, {explicit_count=1, has_implict=true}}, - {.FMUL, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 200, {explicit_count=1, has_implict=true}}, + {.FMUL, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 200, {explicit_count=1, has_implicit=true}}, + {.FMUL, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 200, {explicit_count=1, has_implicit=true}}, // .FMULP - {.FMULP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 200, {explicit_count=1, has_implict=true}}, + {.FMULP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 200, {explicit_count=1, has_implicit=true}}, {.FMULP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 201, {}}, // .FIMUL {.FIMUL, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 1, {modrm_reg_ext=true, explicit_count=1}}, @@ -3124,10 +3124,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .FDIV {.FDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 6, {modrm_reg_ext=true, explicit_count=1}}, {.FDIV, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 6, {modrm_reg_ext=true, explicit_count=1}}, - {.FDIV, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 240, {explicit_count=1, has_implict=true}}, - {.FDIV, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 248, {explicit_count=1, has_implict=true}}, + {.FDIV, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 240, {explicit_count=1, has_implicit=true}}, + {.FDIV, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 248, {explicit_count=1, has_implicit=true}}, // .FDIVP - {.FDIVP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 248, {explicit_count=1, has_implict=true}}, + {.FDIVP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 248, {explicit_count=1, has_implicit=true}}, {.FDIVP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 249, {}}, // .FIDIV {.FIDIV, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 6, {modrm_reg_ext=true, explicit_count=1}}, @@ -3135,10 +3135,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ // .FDIVR {.FDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 7, {modrm_reg_ext=true, explicit_count=1}}, {.FDIVR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 7, {modrm_reg_ext=true, explicit_count=1}}, - {.FDIVR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 248, {explicit_count=1, has_implict=true}}, - {.FDIVR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 240, {explicit_count=1, has_implict=true}}, + {.FDIVR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 248, {explicit_count=1, has_implicit=true}}, + {.FDIVR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 240, {explicit_count=1, has_implicit=true}}, // .FDIVRP - {.FDIVRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 240, {explicit_count=1, has_implict=true}}, + {.FDIVRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 240, {explicit_count=1, has_implicit=true}}, {.FDIVRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 241, {}}, // .FIDIVR {.FIDIVR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 7, {modrm_reg_ext=true, explicit_count=1}}, @@ -3198,21 +3198,21 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD9, 200, {explicit_count=1}}, {.FXCH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 201, {}}, // .FCMOVB - {.FCMOVB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 192, {explicit_count=1, has_implict=true}}, + {.FCMOVB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 192, {explicit_count=1, has_implicit=true}}, // .FCMOVE - {.FCMOVE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 200, {explicit_count=1, has_implict=true}}, + {.FCMOVE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 200, {explicit_count=1, has_implicit=true}}, // .FCMOVBE - {.FCMOVBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 208, {explicit_count=1, has_implict=true}}, + {.FCMOVBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 208, {explicit_count=1, has_implicit=true}}, // .FCMOVU - {.FCMOVU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 216, {explicit_count=1, has_implict=true}}, + {.FCMOVU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 216, {explicit_count=1, has_implicit=true}}, // .FCMOVNB - {.FCMOVNB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 192, {explicit_count=1, has_implict=true}}, + {.FCMOVNB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 192, {explicit_count=1, has_implicit=true}}, // .FCMOVNE - {.FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 200, {explicit_count=1, has_implict=true}}, + {.FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 200, {explicit_count=1, has_implicit=true}}, // .FCMOVNBE - {.FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 208, {explicit_count=1, has_implict=true}}, + {.FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 208, {explicit_count=1, has_implicit=true}}, // .FCMOVNU - {.FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 216, {explicit_count=1, has_implict=true}}, + {.FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 216, {explicit_count=1, has_implicit=true}}, // .FCOM {.FCOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 2, {modrm_reg_ext=true, explicit_count=1}}, {.FCOM, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 2, {modrm_reg_ext=true, explicit_count=1}}, @@ -3232,13 +3232,13 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.FICOMP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 3, {modrm_reg_ext=true, explicit_count=1}}, {.FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 3, {modrm_reg_ext=true, explicit_count=1}}, // .FCOMI - {.FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 240, {explicit_count=1, has_implict=true}}, + {.FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 240, {explicit_count=1, has_implicit=true}}, // .FCOMIP - {.FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 240, {explicit_count=1, has_implict=true}}, + {.FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 240, {explicit_count=1, has_implicit=true}}, // .FUCOMI - {.FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 232, {explicit_count=1, has_implict=true}}, + {.FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 232, {explicit_count=1, has_implicit=true}}, // .FUCOMIP - {.FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 232, {explicit_count=1, has_implict=true}}, + {.FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 232, {explicit_count=1, has_implicit=true}}, // .FUCOM {.FUCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 224, {explicit_count=1}}, {.FUCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDD, 225, {}}, @@ -3319,10 +3319,10 @@ ENCODE_FORMS := [2355]lib.Encoding{ {.FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 4, {modrm_reg_ext=true, explicit_count=1}}, // .FSTSW {.FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7, {modrm_reg_ext=true, explicit_count=1}}, - {.FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {has_implict=true}}, + {.FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {has_implicit=true}}, // .FNSTSW {.FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7, {modrm_reg_ext=true, explicit_count=1}}, - {.FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {has_implict=true}}, + {.FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 224, {has_implicit=true}}, // .FXSAVE {.FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true, explicit_count=1}}, // .FXSAVE64 diff --git a/core/rexcode/x86/tables/x86.encode_forms.bin b/core/rexcode/x86/tables/x86.encode_forms.bin index f5d461a38f200d4946796911b1b56519cdbe1f1a..0dd6a2e4ec68fe08a43d551504fd38669a1965e6 100644 GIT binary patch literal 37680 zcmZQ%U}a=rU}R!o=wM)AU}0cnU}J*tJE44bW>h{03!KjZQqRcBz`(@Fz|aL%&%_4d zcSHHi?5KPe4mcm8UxS*+m!_7}*hg4g|jgq+ZgLfq|2Qfnfmy1A`C) zBZHI~guf8Vmo`V`%UHnq93b_kk_-$SoD2+$pz6(}ApFHpzPU6i-$Dk?2kU23fP`lc z)V~}EKG=T>(D3Yo$}2#_uMg^f7Db4D1qMcN{3)_P!dD5(XHkO4D?<57PHO$>1i9-easBZXnasw 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zx&CKjJP%hl4V*7Qb7<$_=0V~TG>3K`E;bFE7hL}{GMTl&CyVfh@Qw-0OwtUQ3&(FfKGQwP_} zbdd?B4r0fI|BOu6nN&Dc!0kl17~^#&Wlm*?7&uHPfY#2y)j{k4jj7&%tAp4v@jnyO zEi`o#|1&b(gsX$t0a_by3oZuJ%gBhN4s0)|A8-Xt9cb+JGF%K229rQ@ns9p|c1-%u z#B>EN266LbP#YMo7h*4{4{;SP1~G5)ed=H*>A?D5a&%|^Oo^~N_0gY4NhO2|=Wn{VyR|m0U=6@!JC!l^5 zxPF_)0ID}<{%2%(2|?5~lP2Gcj;5!}{ltuwV9{iHRRg@3Q}lj685VAoec%&&0?N7lYWl z>^~zD4_q%K43__AViZMFxBNd7lPFvr#C^;EGcpRn)j{l7{-2Ra2(Aud-irTBjQ8PT z0I_$)eH`<4Hh7@nfV(W?JUjIZH( zA@;8N&&c=!E(S4g)qh5&7ijjb`p?Al8ZHKL-|GKN3?I?#SpA=o;T@V=*8FE=`U2Mr z@yD9~OibV5Vi5Dz{AXnRg65Vr|Ct!S!^I$OUi+Vk;V+uKYyUGc{6e#L-G4?V2DGqW z_n(Q886HOv^Va=mVq%7?gSchge?~?IxH?F;6zJ*+x{~$@xsl6 z_;=fXMn+yV^S1qGVibUjLEN(KKNFJxTrb2e+y65$ilM37{-2Ra7_JUt$M*k>jKXkr z5I1lC&%`7KR|hd~$A2cK2WVlx<3A(QUAP#;ydD1;8Slcw9%9~(|4fVz;9?Lr@BGii z@C+?JcK&B%c#IYwyZ$pVy@A^Sam%j%OpI^P%-i*!k?AE|9mFlW{xdSZgsX$NW%qw3 zhEHhr?*7ln@E*>+a35g;Ve-5g$Xn^cLzRB7zGvs>AeTn3ln2v zya%@ftd|+2_cmN_97r!S$d21^JLZAKzWrxne25{&$oLRVFUZ~paC;%$AQJcdO>4k3YcO{3TS${{xdKrg3=_|UU3GHz1;s97?eP1 z7fFogKLevA+XgmNus%r_df%Z6s8!X6q;VpSlU!Hb)d1dsc7o>|1&U6K~o1B zUz>uaPUJrWV>J`2vJe9!6DtG6eWKubdo~m?&>GEJCU!J2CdN7@4yf34aQK17*ObxJ zfyT&oGpVR(K*9waAE2?XT}&D(P{yr2O5K_XHr&Xg_sAn z7c>T?f`|{Wn9_d+#zxSb2$DLb|4fWcpgB3P7{tv6p#B!KfdOQlLO58j!G9*k({M3} zIzv$34=x5#X9()Q!NnlzjQ%q*9>)-4WIO>EgXlH>&&YTRLyU>>BwP$)9%x+PC|dY| z#sH3>g&(L-EQ=QB4*wY#Wzpgs)F+lh6Lb2{z&IUKjA=TWc`pAM7&oA)bNSD}v;j?> z+kXb8V`ySt{}~yjL3)*$m>IbsVE|e~Dh*Pn0u}?O1MmNgOfr~aj526?ef~2tO+!=X u^PiD%8k#y#8M_TNPcwf2)xQkP?2tH*2gNz_hyP5BcNthXAY$_w85jTrp|u_W From df133c007b1c514e7758bc7de686b8bcfe304640 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 16 Jun 2026 14:11:15 +0100 Subject: [PATCH 15/27] Begin work on `core:rexcode/wasm` --- core/rexcode/wasm/decoder.odin | 258 ++++++++ core/rexcode/wasm/decoding_tables.odin | 560 ++++++++++++++++++ core/rexcode/wasm/encoder.odin | 203 +++++++ core/rexcode/wasm/encoding_table.odin | 502 ++++++++++++++++ core/rexcode/wasm/encoding_types.odin | 203 +++++++ core/rexcode/wasm/instructions.odin | 151 +++++ core/rexcode/wasm/mnemonics.odin | 469 +++++++++++++++ core/rexcode/wasm/operands.odin | 197 ++++++ core/rexcode/wasm/printer.odin | 406 +++++++++++++ core/rexcode/wasm/registers.odin | 76 +++ core/rexcode/wasm/reloc.odin | 44 ++ core/rexcode/wasm/tests/pipeline_smoke.odin | 148 +++++ core/rexcode/wasm/tests/smoke.odin | 86 +++ .../rexcode/wasm/tools/dump_verify_input.odin | 111 ++++ 14 files changed, 3414 insertions(+) create mode 100644 core/rexcode/wasm/decoder.odin create mode 100644 core/rexcode/wasm/decoding_tables.odin create mode 100644 core/rexcode/wasm/encoder.odin create mode 100644 core/rexcode/wasm/encoding_table.odin create mode 100644 core/rexcode/wasm/encoding_types.odin create mode 100644 core/rexcode/wasm/instructions.odin create mode 100644 core/rexcode/wasm/mnemonics.odin create mode 100644 core/rexcode/wasm/operands.odin create mode 100644 core/rexcode/wasm/printer.odin create mode 100644 core/rexcode/wasm/registers.odin create mode 100644 core/rexcode/wasm/reloc.odin create mode 100644 core/rexcode/wasm/tests/pipeline_smoke.odin create mode 100644 core/rexcode/wasm/tests/smoke.odin create mode 100644 core/rexcode/wasm/tools/dump_verify_input.odin diff --git a/core/rexcode/wasm/decoder.odin b/core/rexcode/wasm/decoder.odin new file mode 100644 index 000000000..d7ca165a4 --- /dev/null +++ b/core/rexcode/wasm/decoder.odin @@ -0,0 +1,258 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm + +import "base:runtime" + +// ============================================================================= +// WebAssembly DECODER +// ============================================================================= +// +// Single forward pass, mirroring the encoder. Each step: +// +// 1. Read the opcode. A leading 0xFC switches to the misc group, whose +// sub-opcode is an unsigned LEB128 read next; otherwise the single byte +// is the opcode. The byte (or sub-opcode) indexes the DECODE_MAIN / +// DECODE_MISC tables built from ENCODING_TABLE at package init. +// 2. Look the resulting Mnemonic's form back up in ENCODING_TABLE and read +// its immediates in declaration order, reconstructing Operands. +// +// WASM control flow is structured (branches carry relative label depths, not +// byte offsets), so there is no PC-relative label inference -- `label_defs` +// is part of the universal signature but left untouched. Object-file index +// relocations *are* re-attached: when an input relocation lands on a decoded +// index field, that operand is marked `symbolic` and carries the label id. +// +// `br_table`'s case-label vector is materialised into a freshly allocated +// `[]u32` (caller owns it, like the rest of the decoded output). + +Instruction_Info :: struct { + offset: u32, + decode_entry: u16, + _: u16, +} +#assert(size_of(Instruction_Info) == 8) + +decode :: proc( + data: []u8, + relocs: []Relocation, + instructions: ^[dynamic]Instruction, + inst_info: ^[dynamic]Instruction_Info, + label_defs: ^[dynamic]Label_Definition, + errors: ^[dynamic]Error, + targets_allocator := context.allocator, +) -> (byte_count: u32, ok: bool) { + errors_start := u32(len(errors)) + n := u32(len(data)) + + for byte_count < n { + inst, info, next, dok := decode_one(data, relocs, byte_count, targets_allocator) + if !dok { + append(errors, Error{inst_idx = byte_count, code = .INVALID_OPCODE}) + inst = Instruction{mnemonic = .INVALID, length = 1} + info = Instruction_Info{offset = byte_count} + append(instructions, inst) + append(inst_info, info) + byte_count += 1 + continue + } + inst.length = u8(min(next - byte_count, 255)) + append(instructions, inst) + append(inst_info, info) + byte_count = next + } + + ok = u32(len(errors)) == errors_start + return +} + +// ============================================================================= +// Internal +// ============================================================================= + +@(private="file") +decode_one :: proc( + data: []u8, + relocs: []Relocation, + pc: u32, + targets_allocator: runtime.Allocator, +) -> (inst: Instruction, info: Instruction_Info, next: u32, ok: bool) { + off := pc + if off >= u32(len(data)) { + next = pc + return + } + + // --- opcode (and optional misc sub-opcode) ------------------------------ + b0 := data[off] + off += 1 + + m: Mnemonic = .INVALID + switch b0 { + case PREFIX_MISC: + sub := read_uleb(data, &off) or_return + if sub < u64(DECODE_MISC_COUNT) { + m = DECODE_MISC[sub] + } + case PREFIX_SIMD: + sub := read_uleb(data, &off) or_return + if sub < u64(DECODE_SIMD_COUNT) { + m = DECODE_SIMD[sub] + } + case PREFIX_ATOM: + sub := read_uleb(data, &off) or_return + if sub < u64(DECODE_ATOMIC_COUNT) { + m = DECODE_ATOMIC[sub] + } + case: + m = DECODE_MAIN[b0] + } + if m == .INVALID { + next = pc + return + } + + form := encoding_form(m) + inst.mnemonic = m + inst.flags = {} + + // --- immediates --------------------------------------------------------- + slot := 0 + for k, ki in form.imm { + switch k { + case .NONE: + // nothing + + case .BLOCKTYPE: + v := read_sleb(data, &off) or_return + inst.ops[slot] = Operand{immediate = v, kind = .BLOCK_TYPE} + slot += 1 + + case .I32: + v := read_sleb(data, &off) or_return + inst.ops[slot] = Operand{immediate = v, kind = .IMMEDIATE, size = 4} + slot += 1 + + case .I64: + v := read_sleb(data, &off) or_return + inst.ops[slot] = Operand{immediate = v, kind = .IMMEDIATE, size = 8} + slot += 1 + + case .F32: + bits := read_u32le(data, &off) or_return + inst.ops[slot] = Operand{ + immediate = i64(bits), kind = .IMMEDIATE, size = 4, flags = {is_float = true}, + } + slot += 1 + + case .F64: + bits := read_u64le(data, &off) or_return + inst.ops[slot] = Operand{ + immediate = i64(bits), kind = .IMMEDIATE, size = 8, flags = {is_float = true}, + } + slot += 1 + + case .IDX: + field := off + raw := read_uleb(data, &off) or_return + op := Operand{index = u32(raw), kind = .INDEX, idx_kind = idx_kind_for(m, ki)} + if lid, sym := reloc_label_at(relocs, field); sym { + op.index = lid + op.flags.symbolic = true + op.size = 5 + } + inst.ops[slot] = op + slot += 1 + + case .MEMARG: + align := read_uleb(data, &off) or_return + offset := read_uleb(data, &off) or_return + inst.ops[slot] = Operand{ + memarg = Memarg{align = u32(align), offset = u32(offset)}, kind = .MEMARG, + } + slot += 1 + + case .REFTYPE: + if off >= u32(len(data)) { + next = pc + return + } + t := data[off]; off += 1 + inst.ops[slot] = Operand{immediate = i64(t), kind = .IMMEDIATE, size = 1} + slot += 1 + + case .BR_TABLE: + count := read_uleb(data, &off) or_return + targets := make([]u32, int(count), targets_allocator) + for i in 0..= u32(len(data)) { + next = pc + return + } + off += 1 // reserved 0x00, consumes no operand + + case .LANE: + if off >= u32(len(data)) { + next = pc + return + } + l := data[off]; off += 1 + inst.ops[slot] = Operand{immediate = i64(l), kind = .IMMEDIATE, size = 1} + slot += 1 + + case .LANES16: + if off + 16 > u32(len(data)) { + next = pc + return + } + copy(inst.bytes[:], data[off:off + 16]) + off += 16 // value lives in inst.bytes, no operand + } + } + + inst.operand_count = u8(slot) + info.offset = pc + info.decode_entry = u16(m) + next = off + ok = true + return +} + +// Which index space the IDX immediate in operand slot `which` addresses, by +// mnemonic. Mirrors how the builders in instructions.odin tag each operand. +@(private="file") +idx_kind_for :: #force_inline proc "contextless" (m: Mnemonic, which: int) -> Index_Kind { + #partial switch m { + case .BR, .BR_IF: return .LABEL + case .CALL, .REF_FUNC: return .FUNC + case .CALL_INDIRECT: return which == 0 ? .TYPE : .TABLE + case .LOCAL_GET, .LOCAL_SET, .LOCAL_TEE: return .LOCAL + case .GLOBAL_GET, .GLOBAL_SET: return .GLOBAL + case .MEMORY_INIT, .DATA_DROP: return .DATA + case .TABLE_INIT: return which == 0 ? .ELEM : .TABLE + case .ELEM_DROP: return .ELEM + case .TABLE_COPY: return .TABLE + case .TABLE_GROW, .TABLE_SIZE, .TABLE_FILL: return .TABLE + } + return .NONE +} + +@(private="file") +reloc_label_at :: #force_inline proc "contextless" (relocs: []Relocation, offset: u32) -> (label_id: u32, found: bool) { + for r in relocs { + if r.offset == offset { + return r.label_id, true + } + } + return 0, false +} diff --git a/core/rexcode/wasm/decoding_tables.odin b/core/rexcode/wasm/decoding_tables.odin new file mode 100644 index 000000000..751676186 --- /dev/null +++ b/core/rexcode/wasm/decoding_tables.odin @@ -0,0 +1,560 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm + +// ============================================================================= +// WebAssembly DECODE DISPATCH TABLES +// ============================================================================= +// +// Reverse maps from wire opcode to Mnemonic. Dispatch is two-level: +// +// * core opcodes (prefix 0x00): DECODE_MAIN[opcode_byte] +// * 0xFC misc group: DECODE_MISC[sub_opcode] +// +// These mirror ENCODING_TABLE (the single source of truth) entry-for-entry; +// unlisted slots default to .INVALID. Four dispatch arrays cover the four +// opcode spaces: core (DECODE_MAIN), 0xFC misc (DECODE_MISC), 0xFD SIMD +// (DECODE_SIMD), and 0xFE threads/atomics (DECODE_ATOMIC). + +DECODE_MAIN_COUNT :: 256 // (0..=0xD2) +DECODE_MISC_COUNT :: 32 // 0xFC sub-opcodes (0..=17) +DECODE_SIMD_COUNT :: 0x114 // 0xFD sub-opcodes (0..=0x113) +DECODE_ATOMIC_COUNT :: 0x4F // 0xFE sub-opcodes (0..=0x4E) + +@(rodata) +DECODE_MAIN := [DECODE_MAIN_COUNT]Mnemonic{ + 0x00 = .UNREACHABLE, + 0x01 = .NOP, + 0x02 = .BLOCK, + 0x03 = .LOOP, + 0x04 = .IF, + 0x05 = .ELSE, + 0x0B = .END, + 0x0C = .BR, + 0x0D = .BR_IF, + 0x0E = .BR_TABLE, + 0x0F = .RETURN, + 0x10 = .CALL, + 0x11 = .CALL_INDIRECT, + 0x1A = .DROP, + 0x1B = .SELECT, + 0x20 = .LOCAL_GET, + 0x21 = .LOCAL_SET, + 0x22 = .LOCAL_TEE, + 0x23 = .GLOBAL_GET, + 0x24 = .GLOBAL_SET, + 0x28 = .I32_LOAD, + 0x29 = .I64_LOAD, + 0x2A = .F32_LOAD, + 0x2B = .F64_LOAD, + 0x2C = .I32_LOAD8_S, + 0x2D = .I32_LOAD8_U, + 0x2E = .I32_LOAD16_S, + 0x2F = .I32_LOAD16_U, + 0x30 = .I64_LOAD8_S, + 0x31 = .I64_LOAD8_U, + 0x32 = .I64_LOAD16_S, + 0x33 = .I64_LOAD16_U, + 0x34 = .I64_LOAD32_S, + 0x35 = .I64_LOAD32_U, + 0x36 = .I32_STORE, + 0x37 = .I64_STORE, + 0x38 = .F32_STORE, + 0x39 = .F64_STORE, + 0x3A = .I32_STORE8, + 0x3B = .I32_STORE16, + 0x3C = .I64_STORE8, + 0x3D = .I64_STORE16, + 0x3E = .I64_STORE32, + 0x3F = .MEMORY_SIZE, + 0x40 = .MEMORY_GROW, + 0x41 = .I32_CONST, + 0x42 = .I64_CONST, + 0x43 = .F32_CONST, + 0x44 = .F64_CONST, + 0x45 = .I32_EQZ, + 0x46 = .I32_EQ, + 0x47 = .I32_NE, + 0x48 = .I32_LT_S, + 0x49 = .I32_LT_U, + 0x4A = .I32_GT_S, + 0x4B = .I32_GT_U, + 0x4C = .I32_LE_S, + 0x4D = .I32_LE_U, + 0x4E = .I32_GE_S, + 0x4F = .I32_GE_U, + 0x50 = .I64_EQZ, + 0x51 = .I64_EQ, + 0x52 = .I64_NE, + 0x53 = .I64_LT_S, + 0x54 = .I64_LT_U, + 0x55 = .I64_GT_S, + 0x56 = .I64_GT_U, + 0x57 = .I64_LE_S, + 0x58 = .I64_LE_U, + 0x59 = .I64_GE_S, + 0x5A = .I64_GE_U, + 0x5B = .F32_EQ, + 0x5C = .F32_NE, + 0x5D = .F32_LT, + 0x5E = .F32_GT, + 0x5F = .F32_LE, + 0x60 = .F32_GE, + 0x61 = .F64_EQ, + 0x62 = .F64_NE, + 0x63 = .F64_LT, + 0x64 = .F64_GT, + 0x65 = .F64_LE, + 0x66 = .F64_GE, + 0x67 = .I32_CLZ, + 0x68 = .I32_CTZ, + 0x69 = .I32_POPCNT, + 0x6A = .I32_ADD, + 0x6B = .I32_SUB, + 0x6C = .I32_MUL, + 0x6D = .I32_DIV_S, + 0x6E = .I32_DIV_U, + 0x6F = .I32_REM_S, + 0x70 = .I32_REM_U, + 0x71 = .I32_AND, + 0x72 = .I32_OR, + 0x73 = .I32_XOR, + 0x74 = .I32_SHL, + 0x75 = .I32_SHR_S, + 0x76 = .I32_SHR_U, + 0x77 = .I32_ROTL, + 0x78 = .I32_ROTR, + 0x79 = .I64_CLZ, + 0x7A = .I64_CTZ, + 0x7B = .I64_POPCNT, + 0x7C = .I64_ADD, + 0x7D = .I64_SUB, + 0x7E = .I64_MUL, + 0x7F = .I64_DIV_S, + 0x80 = .I64_DIV_U, + 0x81 = .I64_REM_S, + 0x82 = .I64_REM_U, + 0x83 = .I64_AND, + 0x84 = .I64_OR, + 0x85 = .I64_XOR, + 0x86 = .I64_SHL, + 0x87 = .I64_SHR_S, + 0x88 = .I64_SHR_U, + 0x89 = .I64_ROTL, + 0x8A = .I64_ROTR, + 0x8B = .F32_ABS, + 0x8C = .F32_NEG, + 0x8D = .F32_CEIL, + 0x8E = .F32_FLOOR, + 0x8F = .F32_TRUNC, + 0x90 = .F32_NEAREST, + 0x91 = .F32_SQRT, + 0x92 = .F32_ADD, + 0x93 = .F32_SUB, + 0x94 = .F32_MUL, + 0x95 = .F32_DIV, + 0x96 = .F32_MIN, + 0x97 = .F32_MAX, + 0x98 = .F32_COPYSIGN, + 0x99 = .F64_ABS, + 0x9A = .F64_NEG, + 0x9B = .F64_CEIL, + 0x9C = .F64_FLOOR, + 0x9D = .F64_TRUNC, + 0x9E = .F64_NEAREST, + 0x9F = .F64_SQRT, + 0xA0 = .F64_ADD, + 0xA1 = .F64_SUB, + 0xA2 = .F64_MUL, + 0xA3 = .F64_DIV, + 0xA4 = .F64_MIN, + 0xA5 = .F64_MAX, + 0xA6 = .F64_COPYSIGN, + 0xA7 = .I32_WRAP_I64, + 0xA8 = .I32_TRUNC_F32_S, + 0xA9 = .I32_TRUNC_F32_U, + 0xAA = .I32_TRUNC_F64_S, + 0xAB = .I32_TRUNC_F64_U, + 0xAC = .I64_EXTEND_I32_S, + 0xAD = .I64_EXTEND_I32_U, + 0xAE = .I64_TRUNC_F32_S, + 0xAF = .I64_TRUNC_F32_U, + 0xB0 = .I64_TRUNC_F64_S, + 0xB1 = .I64_TRUNC_F64_U, + 0xB2 = .F32_CONVERT_I32_S, + 0xB3 = .F32_CONVERT_I32_U, + 0xB4 = .F32_CONVERT_I64_S, + 0xB5 = .F32_CONVERT_I64_U, + 0xB6 = .F32_DEMOTE_F64, + 0xB7 = .F64_CONVERT_I32_S, + 0xB8 = .F64_CONVERT_I32_U, + 0xB9 = .F64_CONVERT_I64_S, + 0xBA = .F64_CONVERT_I64_U, + 0xBB = .F64_PROMOTE_F32, + 0xBC = .I32_REINTERPRET_F32, + 0xBD = .I64_REINTERPRET_F64, + 0xBE = .F32_REINTERPRET_I32, + 0xBF = .F64_REINTERPRET_I64, + 0xC0 = .I32_EXTEND8_S, + 0xC1 = .I32_EXTEND16_S, + 0xC2 = .I64_EXTEND8_S, + 0xC3 = .I64_EXTEND16_S, + 0xC4 = .I64_EXTEND32_S, + 0xD0 = .REF_NULL, + 0xD1 = .REF_IS_NULL, + 0xD2 = .REF_FUNC, +} + +@(rodata) +DECODE_MISC := [DECODE_MISC_COUNT]Mnemonic{ + 0 = .I32_TRUNC_SAT_F32_S, + 1 = .I32_TRUNC_SAT_F32_U, + 2 = .I32_TRUNC_SAT_F64_S, + 3 = .I32_TRUNC_SAT_F64_U, + 4 = .I64_TRUNC_SAT_F32_S, + 5 = .I64_TRUNC_SAT_F32_U, + 6 = .I64_TRUNC_SAT_F64_S, + 7 = .I64_TRUNC_SAT_F64_U, + 8 = .MEMORY_INIT, + 9 = .DATA_DROP, + 10 = .MEMORY_COPY, + 11 = .MEMORY_FILL, + 12 = .TABLE_INIT, + 13 = .ELEM_DROP, + 14 = .TABLE_COPY, + 15 = .TABLE_GROW, + 16 = .TABLE_SIZE, + 17 = .TABLE_FILL, +} + +@(rodata) +DECODE_SIMD := [DECODE_SIMD_COUNT]Mnemonic{ + 0x00 = .V128_LOAD, + 0x01 = .V128_LOAD8X8_S, + 0x02 = .V128_LOAD8X8_U, + 0x03 = .V128_LOAD16X4_S, + 0x04 = .V128_LOAD16X4_U, + 0x05 = .V128_LOAD32X2_S, + 0x06 = .V128_LOAD32X2_U, + 0x07 = .V128_LOAD8_SPLAT, + 0x08 = .V128_LOAD16_SPLAT, + 0x09 = .V128_LOAD32_SPLAT, + 0x0A = .V128_LOAD64_SPLAT, + 0x0B = .V128_STORE, + 0x0C = .V128_CONST, + 0x0D = .I8X16_SHUFFLE, + 0x0E = .I8X16_SWIZZLE, + 0x0F = .I8X16_SPLAT, + 0x10 = .I16X8_SPLAT, + 0x11 = .I32X4_SPLAT, + 0x12 = .I64X2_SPLAT, + 0x13 = .F32X4_SPLAT, + 0x14 = .F64X2_SPLAT, + 0x15 = .I8X16_EXTRACT_LANE_S, + 0x16 = .I8X16_EXTRACT_LANE_U, + 0x17 = .I8X16_REPLACE_LANE, + 0x18 = .I16X8_EXTRACT_LANE_S, + 0x19 = .I16X8_EXTRACT_LANE_U, + 0x1A = .I16X8_REPLACE_LANE, + 0x1B = .I32X4_EXTRACT_LANE, + 0x1C = .I32X4_REPLACE_LANE, + 0x1D = .I64X2_EXTRACT_LANE, + 0x1E = .I64X2_REPLACE_LANE, + 0x1F = .F32X4_EXTRACT_LANE, + 0x20 = .F32X4_REPLACE_LANE, + 0x21 = .F64X2_EXTRACT_LANE, + 0x22 = .F64X2_REPLACE_LANE, + 0x23 = .I8X16_EQ, + 0x24 = .I8X16_NE, + 0x25 = .I8X16_LT_S, + 0x26 = .I8X16_LT_U, + 0x27 = .I8X16_GT_S, + 0x28 = .I8X16_GT_U, + 0x29 = .I8X16_LE_S, + 0x2A = .I8X16_LE_U, + 0x2B = .I8X16_GE_S, + 0x2C = .I8X16_GE_U, + 0x2D = .I16X8_EQ, + 0x2E = .I16X8_NE, + 0x2F = .I16X8_LT_S, + 0x30 = .I16X8_LT_U, + 0x31 = .I16X8_GT_S, + 0x32 = .I16X8_GT_U, + 0x33 = .I16X8_LE_S, + 0x34 = .I16X8_LE_U, + 0x35 = .I16X8_GE_S, + 0x36 = .I16X8_GE_U, + 0x37 = .I32X4_EQ, + 0x38 = .I32X4_NE, + 0x39 = .I32X4_LT_S, + 0x3A = .I32X4_LT_U, + 0x3B = .I32X4_GT_S, + 0x3C = .I32X4_GT_U, + 0x3D = .I32X4_LE_S, + 0x3E = .I32X4_LE_U, + 0x3F = .I32X4_GE_S, + 0x40 = .I32X4_GE_U, + 0x41 = .F32X4_EQ, + 0x42 = .F32X4_NE, + 0x43 = .F32X4_LT, + 0x44 = .F32X4_GT, + 0x45 = .F32X4_LE, + 0x46 = .F32X4_GE, + 0x47 = .F64X2_EQ, + 0x48 = .F64X2_NE, + 0x49 = .F64X2_LT, + 0x4A = .F64X2_GT, + 0x4B = .F64X2_LE, + 0x4C = .F64X2_GE, + 0x4D = .V128_NOT, + 0x4E = .V128_AND, + 0x4F = .V128_ANDNOT, + 0x50 = .V128_OR, + 0x51 = .V128_XOR, + 0x52 = .V128_BITSELECT, + 0x53 = .V128_ANY_TRUE, + 0x54 = .V128_LOAD8_LANE, + 0x55 = .V128_LOAD16_LANE, + 0x56 = .V128_LOAD32_LANE, + 0x57 = .V128_LOAD64_LANE, + 0x58 = .V128_STORE8_LANE, + 0x59 = .V128_STORE16_LANE, + 0x5A = .V128_STORE32_LANE, + 0x5B = .V128_STORE64_LANE, + 0x5C = .V128_LOAD32_ZERO, + 0x5D = .V128_LOAD64_ZERO, + 0x5E = .F32X4_DEMOTE_F64X2_ZERO, + 0x5F = .F64X2_PROMOTE_LOW_F32X4, + 0x60 = .I8X16_ABS, + 0x61 = .I8X16_NEG, + 0x62 = .I8X16_POPCNT, + 0x63 = .I8X16_ALL_TRUE, + 0x64 = .I8X16_BITMASK, + 0x65 = .I8X16_NARROW_I16X8_S, + 0x66 = .I8X16_NARROW_I16X8_U, + 0x67 = .F32X4_CEIL, + 0x68 = .F32X4_FLOOR, + 0x69 = .F32X4_TRUNC, + 0x6A = .F32X4_NEAREST, + 0x6B = .I8X16_SHL, + 0x6C = .I8X16_SHR_S, + 0x6D = .I8X16_SHR_U, + 0x6E = .I8X16_ADD, + 0x6F = .I8X16_ADD_SAT_S, + 0x70 = .I8X16_ADD_SAT_U, + 0x71 = .I8X16_SUB, + 0x72 = .I8X16_SUB_SAT_S, + 0x73 = .I8X16_SUB_SAT_U, + 0x74 = .F64X2_CEIL, + 0x75 = .F64X2_FLOOR, + 0x76 = .I8X16_MIN_S, + 0x77 = .I8X16_MIN_U, + 0x78 = .I8X16_MAX_S, + 0x79 = .I8X16_MAX_U, + 0x7A = .F64X2_TRUNC, + 0x7B = .I8X16_AVGR_U, + 0x7C = .I16X8_EXTADD_PAIRWISE_I8X16_S, + 0x7D = .I16X8_EXTADD_PAIRWISE_I8X16_U, + 0x7E = .I32X4_EXTADD_PAIRWISE_I16X8_S, + 0x7F = .I32X4_EXTADD_PAIRWISE_I16X8_U, + 0x80 = .I16X8_ABS, + 0x81 = .I16X8_NEG, + 0x82 = .I16X8_Q15MULR_SAT_S, + 0x83 = .I16X8_ALL_TRUE, + 0x84 = .I16X8_BITMASK, + 0x85 = .I16X8_NARROW_I32X4_S, + 0x86 = .I16X8_NARROW_I32X4_U, + 0x87 = .I16X8_EXTEND_LOW_I8X16_S, + 0x88 = .I16X8_EXTEND_HIGH_I8X16_S, + 0x89 = .I16X8_EXTEND_LOW_I8X16_U, + 0x8A = .I16X8_EXTEND_HIGH_I8X16_U, + 0x8B = .I16X8_SHL, + 0x8C = .I16X8_SHR_S, + 0x8D = .I16X8_SHR_U, + 0x8E = .I16X8_ADD, + 0x8F = .I16X8_ADD_SAT_S, + 0x90 = .I16X8_ADD_SAT_U, + 0x91 = .I16X8_SUB, + 0x92 = .I16X8_SUB_SAT_S, + 0x93 = .I16X8_SUB_SAT_U, + 0x94 = .F64X2_NEAREST, + 0x95 = .I16X8_MUL, + 0x96 = .I16X8_MIN_S, + 0x97 = .I16X8_MIN_U, + 0x98 = .I16X8_MAX_S, + 0x99 = .I16X8_MAX_U, + 0x9B = .I16X8_AVGR_U, + 0x9C = .I16X8_EXTMUL_LOW_I8X16_S, + 0x9D = .I16X8_EXTMUL_HIGH_I8X16_S, + 0x9E = .I16X8_EXTMUL_LOW_I8X16_U, + 0x9F = .I16X8_EXTMUL_HIGH_I8X16_U, + 0xA0 = .I32X4_ABS, + 0xA1 = .I32X4_NEG, + 0xA3 = .I32X4_ALL_TRUE, + 0xA4 = .I32X4_BITMASK, + 0xA7 = .I32X4_EXTEND_LOW_I16X8_S, + 0xA8 = .I32X4_EXTEND_HIGH_I16X8_S, + 0xA9 = .I32X4_EXTEND_LOW_I16X8_U, + 0xAA = .I32X4_EXTEND_HIGH_I16X8_U, + 0xAB = .I32X4_SHL, + 0xAC = .I32X4_SHR_S, + 0xAD = .I32X4_SHR_U, + 0xAE = .I32X4_ADD, + 0xB1 = .I32X4_SUB, + 0xB5 = .I32X4_MUL, + 0xB6 = .I32X4_MIN_S, + 0xB7 = .I32X4_MIN_U, + 0xB8 = .I32X4_MAX_S, + 0xB9 = .I32X4_MAX_U, + 0xBA = .I32X4_DOT_I16X8_S, + 0xBC = .I32X4_EXTMUL_LOW_I16X8_S, + 0xBD = .I32X4_EXTMUL_HIGH_I16X8_S, + 0xBE = .I32X4_EXTMUL_LOW_I16X8_U, + 0xBF = .I32X4_EXTMUL_HIGH_I16X8_U, + 0xC0 = .I64X2_ABS, + 0xC1 = .I64X2_NEG, + 0xC3 = .I64X2_ALL_TRUE, + 0xC4 = .I64X2_BITMASK, + 0xC7 = .I64X2_EXTEND_LOW_I32X4_S, + 0xC8 = .I64X2_EXTEND_HIGH_I32X4_S, + 0xC9 = .I64X2_EXTEND_LOW_I32X4_U, + 0xCA = .I64X2_EXTEND_HIGH_I32X4_U, + 0xCB = .I64X2_SHL, + 0xCC = .I64X2_SHR_S, + 0xCD = .I64X2_SHR_U, + 0xCE = .I64X2_ADD, + 0xD1 = .I64X2_SUB, + 0xD5 = .I64X2_MUL, + 0xD6 = .I64X2_EQ, + 0xD7 = .I64X2_NE, + 0xD8 = .I64X2_LT_S, + 0xD9 = .I64X2_GT_S, + 0xDA = .I64X2_LE_S, + 0xDB = .I64X2_GE_S, + 0xDC = .I64X2_EXTMUL_LOW_I32X4_S, + 0xDD = .I64X2_EXTMUL_HIGH_I32X4_S, + 0xDE = .I64X2_EXTMUL_LOW_I32X4_U, + 0xDF = .I64X2_EXTMUL_HIGH_I32X4_U, + 0xE0 = .F32X4_ABS, + 0xE1 = .F32X4_NEG, + 0xE3 = .F32X4_SQRT, + 0xE4 = .F32X4_ADD, + 0xE5 = .F32X4_SUB, + 0xE6 = .F32X4_MUL, + 0xE7 = .F32X4_DIV, + 0xE8 = .F32X4_MIN, + 0xE9 = .F32X4_MAX, + 0xEA = .F32X4_PMIN, + 0xEB = .F32X4_PMAX, + 0xEC = .F64X2_ABS, + 0xED = .F64X2_NEG, + 0xEF = .F64X2_SQRT, + 0xF0 = .F64X2_ADD, + 0xF1 = .F64X2_SUB, + 0xF2 = .F64X2_MUL, + 0xF3 = .F64X2_DIV, + 0xF4 = .F64X2_MIN, + 0xF5 = .F64X2_MAX, + 0xF6 = .F64X2_PMIN, + 0xF7 = .F64X2_PMAX, + 0xF8 = .I32X4_TRUNC_SAT_F32X4_S, + 0xF9 = .I32X4_TRUNC_SAT_F32X4_U, + 0xFA = .F32X4_CONVERT_I32X4_S, + 0xFB = .F32X4_CONVERT_I32X4_U, + 0xFC = .I32X4_TRUNC_SAT_F64X2_S_ZERO, + 0xFD = .I32X4_TRUNC_SAT_F64X2_U_ZERO, + 0xFE = .F64X2_CONVERT_LOW_I32X4_S, + 0xFF = .F64X2_CONVERT_LOW_I32X4_U, + 0x100 = .I8X16_RELAXED_SWIZZLE, + 0x101 = .I32X4_RELAXED_TRUNC_F32X4_S, + 0x102 = .I32X4_RELAXED_TRUNC_F32X4_U, + 0x103 = .I32X4_RELAXED_TRUNC_F64X2_S_ZERO, + 0x104 = .I32X4_RELAXED_TRUNC_F64X2_U_ZERO, + 0x105 = .F32X4_RELAXED_MADD, + 0x106 = .F32X4_RELAXED_NMADD, + 0x107 = .F64X2_RELAXED_MADD, + 0x108 = .F64X2_RELAXED_NMADD, + 0x109 = .I8X16_RELAXED_LANESELECT, + 0x10A = .I16X8_RELAXED_LANESELECT, + 0x10B = .I32X4_RELAXED_LANESELECT, + 0x10C = .I64X2_RELAXED_LANESELECT, + 0x10D = .F32X4_RELAXED_MIN, + 0x10E = .F32X4_RELAXED_MAX, + 0x10F = .F64X2_RELAXED_MIN, + 0x110 = .F64X2_RELAXED_MAX, + 0x111 = .I16X8_RELAXED_Q15MULR_S, + 0x112 = .I16X8_RELAXED_DOT_I8X16_I7X16_S, + 0x113 = .I32X4_RELAXED_DOT_I8X16_I7X16_ADD_S, +} + +@(rodata) +DECODE_ATOMIC := [DECODE_ATOMIC_COUNT]Mnemonic{ + 0x00 = .MEMORY_ATOMIC_NOTIFY, + 0x01 = .MEMORY_ATOMIC_WAIT32, + 0x02 = .MEMORY_ATOMIC_WAIT64, + 0x03 = .ATOMIC_FENCE, + 0x10 = .I32_ATOMIC_LOAD, + 0x11 = .I64_ATOMIC_LOAD, + 0x12 = .I32_ATOMIC_LOAD8_U, + 0x13 = .I32_ATOMIC_LOAD16_U, + 0x14 = .I64_ATOMIC_LOAD8_U, + 0x15 = .I64_ATOMIC_LOAD16_U, + 0x16 = .I64_ATOMIC_LOAD32_U, + 0x17 = .I32_ATOMIC_STORE, + 0x18 = .I64_ATOMIC_STORE, + 0x19 = .I32_ATOMIC_STORE8, + 0x1A = .I32_ATOMIC_STORE16, + 0x1B = .I64_ATOMIC_STORE8, + 0x1C = .I64_ATOMIC_STORE16, + 0x1D = .I64_ATOMIC_STORE32, + 0x1E = .I32_ATOMIC_RMW_ADD, + 0x1F = .I64_ATOMIC_RMW_ADD, + 0x20 = .I32_ATOMIC_RMW8_ADD_U, + 0x21 = .I32_ATOMIC_RMW16_ADD_U, + 0x22 = .I64_ATOMIC_RMW8_ADD_U, + 0x23 = .I64_ATOMIC_RMW16_ADD_U, + 0x24 = .I64_ATOMIC_RMW32_ADD_U, + 0x25 = .I32_ATOMIC_RMW_SUB, + 0x26 = .I64_ATOMIC_RMW_SUB, + 0x27 = .I32_ATOMIC_RMW8_SUB_U, + 0x28 = .I32_ATOMIC_RMW16_SUB_U, + 0x29 = .I64_ATOMIC_RMW8_SUB_U, + 0x2A = .I64_ATOMIC_RMW16_SUB_U, + 0x2B = .I64_ATOMIC_RMW32_SUB_U, + 0x2C = .I32_ATOMIC_RMW_AND, + 0x2D = .I64_ATOMIC_RMW_AND, + 0x2E = .I32_ATOMIC_RMW8_AND_U, + 0x2F = .I32_ATOMIC_RMW16_AND_U, + 0x30 = .I64_ATOMIC_RMW8_AND_U, + 0x31 = .I64_ATOMIC_RMW16_AND_U, + 0x32 = .I64_ATOMIC_RMW32_AND_U, + 0x33 = .I32_ATOMIC_RMW_OR, + 0x34 = .I64_ATOMIC_RMW_OR, + 0x35 = .I32_ATOMIC_RMW8_OR_U, + 0x36 = .I32_ATOMIC_RMW16_OR_U, + 0x37 = .I64_ATOMIC_RMW8_OR_U, + 0x38 = .I64_ATOMIC_RMW16_OR_U, + 0x39 = .I64_ATOMIC_RMW32_OR_U, + 0x3A = .I32_ATOMIC_RMW_XOR, + 0x3B = .I64_ATOMIC_RMW_XOR, + 0x3C = .I32_ATOMIC_RMW8_XOR_U, + 0x3D = .I32_ATOMIC_RMW16_XOR_U, + 0x3E = .I64_ATOMIC_RMW8_XOR_U, + 0x3F = .I64_ATOMIC_RMW16_XOR_U, + 0x40 = .I64_ATOMIC_RMW32_XOR_U, + 0x41 = .I32_ATOMIC_RMW_XCHG, + 0x42 = .I64_ATOMIC_RMW_XCHG, + 0x43 = .I32_ATOMIC_RMW8_XCHG_U, + 0x44 = .I32_ATOMIC_RMW16_XCHG_U, + 0x45 = .I64_ATOMIC_RMW8_XCHG_U, + 0x46 = .I64_ATOMIC_RMW16_XCHG_U, + 0x47 = .I64_ATOMIC_RMW32_XCHG_U, + 0x48 = .I32_ATOMIC_RMW_CMPXCHG, + 0x49 = .I64_ATOMIC_RMW_CMPXCHG, + 0x4A = .I32_ATOMIC_RMW8_CMPXCHG_U, + 0x4B = .I32_ATOMIC_RMW16_CMPXCHG_U, + 0x4C = .I64_ATOMIC_RMW8_CMPXCHG_U, + 0x4D = .I64_ATOMIC_RMW16_CMPXCHG_U, + 0x4E = .I64_ATOMIC_RMW32_CMPXCHG_U, +} diff --git a/core/rexcode/wasm/encoder.odin b/core/rexcode/wasm/encoder.odin new file mode 100644 index 000000000..bb3f182c9 --- /dev/null +++ b/core/rexcode/wasm/encoder.odin @@ -0,0 +1,203 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm + +// ============================================================================= +// WebAssembly ENCODER +// ============================================================================= +// +// Variable-length, byte-oriented, LEB128-heavy. Because LEB fields are not a +// fixed width, encoding is sequential: a single forward pass writes each +// instruction's opcode (a byte, or a prefix byte plus an unsigned-LEB +// sub-opcode) followed by its immediates, advancing a byte cursor. +// +// WASM has no PC-relative branches (control flow uses structured label +// depths), so there is no second resolution pass and no rewrite of +// `label_defs`: those parameters are part of the universal signature but are +// inert here. Relocations *are* produced -- for symbolic index references +// (see op_label) -- and returned for a linker to patch; symbolic indices are +// laid down as fixed-width 5-byte LEB placeholders so the patched value fits. + +MAX_OPCODE_SIZE :: 3 // prefix byte + two-byte unsigned-LEB sub-opcode (SIMD reaches 0x113) + +@(require_results) +encode_max_code_size :: #force_inline proc "contextless" (n: int) -> int { + // Worst case per instruction without a br_table: a 3-byte opcode plus the + // largest single immediate, which is v128.const's 16 raw bytes (a memarg+ + // lane pair is smaller). br_table is unbounded in its target count; + // callers encoding tables should size from the target totals. + return n * 24 +} +@(require_results) +encode_max_relocation_count :: #force_inline proc "contextless" (n: int) -> int { + return n +} + +encode :: proc( + instructions: []Instruction, + label_defs: []Label_Definition, + code: []u8, + relocs: ^[dynamic]Relocation, + errors: ^[dynamic]Error, + resolve: bool = true, + base_address: u64 = 0, +) -> (byte_count: u32, ok: bool) { + errors_start := u32(len(errors)) + + for i in 0.. (size: u32, ok: bool) { + if inst.mnemonic == .INVALID { + append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) + return 0, false + } + form := encoding_form(inst.mnemonic) + + need := encoded_size(inst, form) + if pc + need > u32(len(code)) { + append(errors, Error{inst_idx = u32(inst_idx), code = .BUFFER_OVERFLOW}) + return 0, false + } + + off := pc + + // Opcode (and prefix sub-opcode). + if form.prefix == PREFIX_NONE { + code[off] = u8(form.opcode) + off += 1 + } else { + code[off] = form.prefix + off += 1 + write_uleb(code, &off, u64(form.opcode)) + } + + // Immediates, walked in declaration order with an operand cursor. + opi := 0 + for k in form.imm { + switch k { + case .NONE: + // nothing + case .BLOCKTYPE, .I32, .I64: + write_sleb(code, &off, inst.ops[opi].immediate) + opi += 1 + case .F32: + write_u32le(code, &off, u32(inst.ops[opi].immediate)) + opi += 1 + case .F64: + write_u64le(code, &off, u64(inst.ops[opi].immediate)) + opi += 1 + case .IDX: + op := &inst.ops[opi] + if op.flags.symbolic { + append(relocs, Relocation{ + offset = off, label_id = op.index, addend = 0, + type = reloc_type_for(op.idx_kind), size = 5, inst_idx = inst_idx, + }) + write_uleb_padded5(code, &off, u64(op.index)) + } else { + write_uleb(code, &off, u64(op.index)) + } + opi += 1 + case .MEMARG: + ma := inst.ops[opi].memarg + write_uleb(code, &off, u64(ma.align)) + write_uleb(code, &off, u64(ma.offset)) + opi += 1 + case .REFTYPE: + code[off] = u8(inst.ops[opi].immediate) + off += 1 + opi += 1 + case .BR_TABLE: + write_uleb(code, &off, u64(len(inst.targets))) + for t in inst.targets { + write_uleb(code, &off, u64(t)) + } + write_uleb(code, &off, u64(inst.ops[opi].index)) // default depth + opi += 1 + case .ZERO_BYTE: + code[off] = 0x00 + off += 1 + case .LANE: + code[off] = u8(inst.ops[opi].immediate) + off += 1 + opi += 1 + case .LANES16: + for bb in inst.bytes { + code[off] = bb + off += 1 + } + } + } + + return off - pc, true +} + +@(private="file") +encoded_size :: proc(inst: ^Instruction, form: ^Encoding) -> u32 { + size: u32 = form.prefix == PREFIX_NONE ? 1 : 1 + uleb_size(u64(form.opcode)) + opi := 0 + for k in form.imm { + switch k { + case .NONE: + case .BLOCKTYPE, .I32, .I64: + size += sleb_size(inst.ops[opi].immediate); opi += 1 + case .F32: + size += 4; opi += 1 + case .F64: + size += 8; opi += 1 + case .IDX: + op := &inst.ops[opi] + size += op.flags.symbolic ? 5 : uleb_size(u64(op.index)) + opi += 1 + case .MEMARG: + ma := inst.ops[opi].memarg + size += uleb_size(u64(ma.align)) + uleb_size(u64(ma.offset)); opi += 1 + case .REFTYPE: + size += 1; opi += 1 + case .BR_TABLE: + size += uleb_size(u64(len(inst.targets))) + for t in inst.targets { size += uleb_size(u64(t)) } + size += uleb_size(u64(inst.ops[opi].index)); opi += 1 + case .ZERO_BYTE: + size += 1 + case .LANE: + size += 1; opi += 1 + case .LANES16: + size += 16 + } + } + return size +} + +@(private="file") +reloc_type_for :: #force_inline proc "contextless" (k: Index_Kind) -> Relocation_Type { + #partial switch k { + case .FUNC: return .FUNCTION_INDEX_LEB + case .TYPE: return .TYPE_INDEX_LEB + case .GLOBAL: return .GLOBAL_INDEX_LEB + case .TABLE: return .TABLE_NUMBER_LEB + } + return .FUNCTION_INDEX_LEB +} diff --git a/core/rexcode/wasm/encoding_table.odin b/core/rexcode/wasm/encoding_table.odin new file mode 100644 index 000000000..caf4e927d --- /dev/null +++ b/core/rexcode/wasm/encoding_table.odin @@ -0,0 +1,502 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm + +// ============================================================================= +// WebAssembly ENCODING TABLE (single source of truth) +// ============================================================================= +// +// One form per mnemonic, indexed directly by the Mnemonic enum. Each entry +// records the prefix byte, the (sub-)opcode, and the immediate layout. The +// decode dispatch in decoding_tables.odin is derived from this table at +// package init, so opcode bytes are written down exactly once. +// +// The `mnemonic` field of each Encoding is left at INVALID here: the table +// index already identifies the mnemonic and the encoder never reads it back. + +@(private="file") CTRL :: Encoding_Flags{control = true} +@(private="file") MEM :: Encoding_Flags{memory = true} + +@(rodata) +ENCODING_TABLE := [Mnemonic]Encoding{ + .INVALID = {}, + + // ------------------------------------------------------------------ control + .UNREACHABLE = Encoding{prefix = PREFIX_NONE, opcode = 0x00, flags = CTRL}, + .NOP = Encoding{prefix = PREFIX_NONE, opcode = 0x01}, + .BLOCK = Encoding{prefix = PREFIX_NONE, opcode = 0x02, imm = {.BLOCKTYPE, .NONE}, flags = CTRL}, + .LOOP = Encoding{prefix = PREFIX_NONE, opcode = 0x03, imm = {.BLOCKTYPE, .NONE}, flags = CTRL}, + .IF = Encoding{prefix = PREFIX_NONE, opcode = 0x04, imm = {.BLOCKTYPE, .NONE}, flags = CTRL}, + .ELSE = Encoding{prefix = PREFIX_NONE, opcode = 0x05, flags = CTRL}, + .END = Encoding{prefix = PREFIX_NONE, opcode = 0x0B, flags = CTRL}, + .BR = Encoding{prefix = PREFIX_NONE, opcode = 0x0C, imm = {.IDX, .NONE}, flags = CTRL}, + .BR_IF = Encoding{prefix = PREFIX_NONE, opcode = 0x0D, imm = {.IDX, .NONE}, flags = CTRL}, + .BR_TABLE = Encoding{prefix = PREFIX_NONE, opcode = 0x0E, imm = {.BR_TABLE, .NONE}, flags = CTRL}, + .RETURN = Encoding{prefix = PREFIX_NONE, opcode = 0x0F, flags = CTRL}, + .CALL = Encoding{prefix = PREFIX_NONE, opcode = 0x10, imm = {.IDX, .NONE}, flags = CTRL}, + .CALL_INDIRECT = Encoding{prefix = PREFIX_NONE, opcode = 0x11, imm = {.IDX, .IDX}, flags = CTRL}, + + // -------------------------------------------------------------- parametric + .DROP = Encoding{prefix = PREFIX_NONE, opcode = 0x1A}, + .SELECT = Encoding{prefix = PREFIX_NONE, opcode = 0x1B}, + + // ---------------------------------------------------------------- variable + .LOCAL_GET = Encoding{prefix = PREFIX_NONE, opcode = 0x20, imm = {.IDX, .NONE}}, + .LOCAL_SET = Encoding{prefix = PREFIX_NONE, opcode = 0x21, imm = {.IDX, .NONE}}, + .LOCAL_TEE = Encoding{prefix = PREFIX_NONE, opcode = 0x22, imm = {.IDX, .NONE}}, + .GLOBAL_GET = Encoding{prefix = PREFIX_NONE, opcode = 0x23, imm = {.IDX, .NONE}}, + .GLOBAL_SET = Encoding{prefix = PREFIX_NONE, opcode = 0x24, imm = {.IDX, .NONE}}, + + // ------------------------------------------------------------------- memory + .I32_LOAD = Encoding{prefix = PREFIX_NONE, opcode = 0x28, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD = Encoding{prefix = PREFIX_NONE, opcode = 0x29, imm = {.MEMARG, .NONE}, flags = MEM}, + .F32_LOAD = Encoding{prefix = PREFIX_NONE, opcode = 0x2A, imm = {.MEMARG, .NONE}, flags = MEM}, + .F64_LOAD = Encoding{prefix = PREFIX_NONE, opcode = 0x2B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_LOAD8_S = Encoding{prefix = PREFIX_NONE, opcode = 0x2C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_LOAD8_U = Encoding{prefix = PREFIX_NONE, opcode = 0x2D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_LOAD16_S = Encoding{prefix = PREFIX_NONE, opcode = 0x2E, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_LOAD16_U = Encoding{prefix = PREFIX_NONE, opcode = 0x2F, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD8_S = Encoding{prefix = PREFIX_NONE, opcode = 0x30, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD8_U = Encoding{prefix = PREFIX_NONE, opcode = 0x31, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD16_S = Encoding{prefix = PREFIX_NONE, opcode = 0x32, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD16_U = Encoding{prefix = PREFIX_NONE, opcode = 0x33, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD32_S = Encoding{prefix = PREFIX_NONE, opcode = 0x34, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD32_U = Encoding{prefix = PREFIX_NONE, opcode = 0x35, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_STORE = Encoding{prefix = PREFIX_NONE, opcode = 0x36, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_STORE = Encoding{prefix = PREFIX_NONE, opcode = 0x37, imm = {.MEMARG, .NONE}, flags = MEM}, + .F32_STORE = Encoding{prefix = PREFIX_NONE, opcode = 0x38, imm = {.MEMARG, .NONE}, flags = MEM}, + .F64_STORE = Encoding{prefix = PREFIX_NONE, opcode = 0x39, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_STORE8 = Encoding{prefix = PREFIX_NONE, opcode = 0x3A, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_STORE16 = Encoding{prefix = PREFIX_NONE, opcode = 0x3B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_STORE8 = Encoding{prefix = PREFIX_NONE, opcode = 0x3C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_STORE16 = Encoding{prefix = PREFIX_NONE, opcode = 0x3D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_STORE32 = Encoding{prefix = PREFIX_NONE, opcode = 0x3E, imm = {.MEMARG, .NONE}, flags = MEM}, + .MEMORY_SIZE = Encoding{prefix = PREFIX_NONE, opcode = 0x3F, imm = {.ZERO_BYTE, .NONE}, flags = MEM}, + .MEMORY_GROW = Encoding{prefix = PREFIX_NONE, opcode = 0x40, imm = {.ZERO_BYTE, .NONE}, flags = MEM}, + + // ----------------------------------------------------------------- numeric + .I32_CONST = Encoding{prefix = PREFIX_NONE, opcode = 0x41, imm = {.I32, .NONE}}, + .I64_CONST = Encoding{prefix = PREFIX_NONE, opcode = 0x42, imm = {.I64, .NONE}}, + .F32_CONST = Encoding{prefix = PREFIX_NONE, opcode = 0x43, imm = {.F32, .NONE}}, + .F64_CONST = Encoding{prefix = PREFIX_NONE, opcode = 0x44, imm = {.F64, .NONE}}, + + .I32_EQZ = Encoding{prefix = PREFIX_NONE, opcode = 0x45}, .I32_EQ = Encoding{prefix = PREFIX_NONE, opcode = 0x46}, .I32_NE = Encoding{prefix = PREFIX_NONE, opcode = 0x47}, + .I32_LT_S = Encoding{prefix = PREFIX_NONE, opcode = 0x48}, .I32_LT_U = Encoding{prefix = PREFIX_NONE, opcode = 0x49}, + .I32_GT_S = Encoding{prefix = PREFIX_NONE, opcode = 0x4A}, .I32_GT_U = Encoding{prefix = PREFIX_NONE, opcode = 0x4B}, + .I32_LE_S = Encoding{prefix = PREFIX_NONE, opcode = 0x4C}, .I32_LE_U = Encoding{prefix = PREFIX_NONE, opcode = 0x4D}, + .I32_GE_S = Encoding{prefix = PREFIX_NONE, opcode = 0x4E}, .I32_GE_U = Encoding{prefix = PREFIX_NONE, opcode = 0x4F}, + + .I64_EQZ = Encoding{prefix = PREFIX_NONE, opcode = 0x50}, .I64_EQ = Encoding{prefix = PREFIX_NONE, opcode = 0x51}, .I64_NE = Encoding{prefix = PREFIX_NONE, opcode = 0x52}, + .I64_LT_S = Encoding{prefix = PREFIX_NONE, opcode = 0x53}, .I64_LT_U = Encoding{prefix = PREFIX_NONE, opcode = 0x54}, + .I64_GT_S = Encoding{prefix = PREFIX_NONE, opcode = 0x55}, .I64_GT_U = Encoding{prefix = PREFIX_NONE, opcode = 0x56}, + .I64_LE_S = Encoding{prefix = PREFIX_NONE, opcode = 0x57}, .I64_LE_U = Encoding{prefix = PREFIX_NONE, opcode = 0x58}, + .I64_GE_S = Encoding{prefix = PREFIX_NONE, opcode = 0x59}, .I64_GE_U = Encoding{prefix = PREFIX_NONE, opcode = 0x5A}, + + .F32_EQ = Encoding{prefix = PREFIX_NONE, opcode = 0x5B}, .F32_NE = Encoding{prefix = PREFIX_NONE, opcode = 0x5C}, + .F32_LT = Encoding{prefix = PREFIX_NONE, opcode = 0x5D}, .F32_GT = Encoding{prefix = PREFIX_NONE, opcode = 0x5E}, + .F32_LE = Encoding{prefix = PREFIX_NONE, opcode = 0x5F}, .F32_GE = Encoding{prefix = PREFIX_NONE, opcode = 0x60}, + + .F64_EQ = Encoding{prefix = PREFIX_NONE, opcode = 0x61}, .F64_NE = Encoding{prefix = PREFIX_NONE, opcode = 0x62}, + .F64_LT = Encoding{prefix = PREFIX_NONE, opcode = 0x63}, .F64_GT = Encoding{prefix = PREFIX_NONE, opcode = 0x64}, + .F64_LE = Encoding{prefix = PREFIX_NONE, opcode = 0x65}, .F64_GE = Encoding{prefix = PREFIX_NONE, opcode = 0x66}, + + .I32_CLZ = Encoding{prefix = PREFIX_NONE, opcode = 0x67}, .I32_CTZ = Encoding{prefix = PREFIX_NONE, opcode = 0x68}, .I32_POPCNT = Encoding{prefix = PREFIX_NONE, opcode = 0x69}, + .I32_ADD = Encoding{prefix = PREFIX_NONE, opcode = 0x6A}, .I32_SUB = Encoding{prefix = PREFIX_NONE, opcode = 0x6B}, .I32_MUL = Encoding{prefix = PREFIX_NONE, opcode = 0x6C}, + .I32_DIV_S = Encoding{prefix = PREFIX_NONE, opcode = 0x6D}, .I32_DIV_U = Encoding{prefix = PREFIX_NONE, opcode = 0x6E}, + .I32_REM_S = Encoding{prefix = PREFIX_NONE, opcode = 0x6F}, .I32_REM_U = Encoding{prefix = PREFIX_NONE, opcode = 0x70}, + .I32_AND = Encoding{prefix = PREFIX_NONE, opcode = 0x71}, .I32_OR = Encoding{prefix = PREFIX_NONE, opcode = 0x72}, .I32_XOR = Encoding{prefix = PREFIX_NONE, opcode = 0x73}, + .I32_SHL = Encoding{prefix = PREFIX_NONE, opcode = 0x74}, .I32_SHR_S = Encoding{prefix = PREFIX_NONE, opcode = 0x75}, .I32_SHR_U = Encoding{prefix = PREFIX_NONE, opcode = 0x76}, + .I32_ROTL = Encoding{prefix = PREFIX_NONE, opcode = 0x77}, .I32_ROTR = Encoding{prefix = PREFIX_NONE, opcode = 0x78}, + + .I64_CLZ = Encoding{prefix = PREFIX_NONE, opcode = 0x79}, .I64_CTZ = Encoding{prefix = PREFIX_NONE, opcode = 0x7A}, .I64_POPCNT = Encoding{prefix = PREFIX_NONE, opcode = 0x7B}, + .I64_ADD = Encoding{prefix = PREFIX_NONE, opcode = 0x7C}, .I64_SUB = Encoding{prefix = PREFIX_NONE, opcode = 0x7D}, .I64_MUL = Encoding{prefix = PREFIX_NONE, opcode = 0x7E}, + .I64_DIV_S = Encoding{prefix = PREFIX_NONE, opcode = 0x7F}, .I64_DIV_U = Encoding{prefix = PREFIX_NONE, opcode = 0x80}, + .I64_REM_S = Encoding{prefix = PREFIX_NONE, opcode = 0x81}, .I64_REM_U = Encoding{prefix = PREFIX_NONE, opcode = 0x82}, + .I64_AND = Encoding{prefix = PREFIX_NONE, opcode = 0x83}, .I64_OR = Encoding{prefix = PREFIX_NONE, opcode = 0x84}, .I64_XOR = Encoding{prefix = PREFIX_NONE, opcode = 0x85}, + .I64_SHL = Encoding{prefix = PREFIX_NONE, opcode = 0x86}, .I64_SHR_S = Encoding{prefix = PREFIX_NONE, opcode = 0x87}, .I64_SHR_U = Encoding{prefix = PREFIX_NONE, opcode = 0x88}, + .I64_ROTL = Encoding{prefix = PREFIX_NONE, opcode = 0x89}, .I64_ROTR = Encoding{prefix = PREFIX_NONE, opcode = 0x8A}, + + .F32_ABS = Encoding{prefix = PREFIX_NONE, opcode = 0x8B}, .F32_NEG = Encoding{prefix = PREFIX_NONE, opcode = 0x8C}, .F32_CEIL = Encoding{prefix = PREFIX_NONE, opcode = 0x8D}, + .F32_FLOOR = Encoding{prefix = PREFIX_NONE, opcode = 0x8E}, .F32_TRUNC = Encoding{prefix = PREFIX_NONE, opcode = 0x8F}, .F32_NEAREST = Encoding{prefix = PREFIX_NONE, opcode = 0x90}, + .F32_SQRT = Encoding{prefix = PREFIX_NONE, opcode = 0x91}, .F32_ADD = Encoding{prefix = PREFIX_NONE, opcode = 0x92}, .F32_SUB = Encoding{prefix = PREFIX_NONE, opcode = 0x93}, + .F32_MUL = Encoding{prefix = PREFIX_NONE, opcode = 0x94}, .F32_DIV = Encoding{prefix = PREFIX_NONE, opcode = 0x95}, .F32_MIN = Encoding{prefix = PREFIX_NONE, opcode = 0x96}, + .F32_MAX = Encoding{prefix = PREFIX_NONE, opcode = 0x97}, .F32_COPYSIGN = Encoding{prefix = PREFIX_NONE, opcode = 0x98}, + + .F64_ABS = Encoding{prefix = PREFIX_NONE, opcode = 0x99}, .F64_NEG = Encoding{prefix = PREFIX_NONE, opcode = 0x9A}, .F64_CEIL = Encoding{prefix = PREFIX_NONE, opcode = 0x9B}, + .F64_FLOOR = Encoding{prefix = PREFIX_NONE, opcode = 0x9C}, .F64_TRUNC = Encoding{prefix = PREFIX_NONE, opcode = 0x9D}, .F64_NEAREST = Encoding{prefix = PREFIX_NONE, opcode = 0x9E}, + .F64_SQRT = Encoding{prefix = PREFIX_NONE, opcode = 0x9F}, .F64_ADD = Encoding{prefix = PREFIX_NONE, opcode = 0xA0}, .F64_SUB = Encoding{prefix = PREFIX_NONE, opcode = 0xA1}, + .F64_MUL = Encoding{prefix = PREFIX_NONE, opcode = 0xA2}, .F64_DIV = Encoding{prefix = PREFIX_NONE, opcode = 0xA3}, .F64_MIN = Encoding{prefix = PREFIX_NONE, opcode = 0xA4}, + .F64_MAX = Encoding{prefix = PREFIX_NONE, opcode = 0xA5}, .F64_COPYSIGN = Encoding{prefix = PREFIX_NONE, opcode = 0xA6}, + + .I32_WRAP_I64 = Encoding{prefix = PREFIX_NONE, opcode = 0xA7}, + .I32_TRUNC_F32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xA8}, .I32_TRUNC_F32_U = Encoding{prefix = PREFIX_NONE, opcode = 0xA9}, + .I32_TRUNC_F64_S = Encoding{prefix = PREFIX_NONE, opcode = 0xAA}, .I32_TRUNC_F64_U = Encoding{prefix = PREFIX_NONE, opcode = 0xAB}, + .I64_EXTEND_I32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xAC}, .I64_EXTEND_I32_U = Encoding{prefix = PREFIX_NONE, opcode = 0xAD}, + .I64_TRUNC_F32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xAE}, .I64_TRUNC_F32_U = Encoding{prefix = PREFIX_NONE, opcode = 0xAF}, + .I64_TRUNC_F64_S = Encoding{prefix = PREFIX_NONE, opcode = 0xB0}, .I64_TRUNC_F64_U = Encoding{prefix = PREFIX_NONE, opcode = 0xB1}, + .F32_CONVERT_I32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xB2}, .F32_CONVERT_I32_U = Encoding{prefix = PREFIX_NONE, opcode = 0xB3}, + .F32_CONVERT_I64_S = Encoding{prefix = PREFIX_NONE, opcode = 0xB4}, .F32_CONVERT_I64_U = Encoding{prefix = PREFIX_NONE, opcode = 0xB5}, + .F32_DEMOTE_F64 = Encoding{prefix = PREFIX_NONE, opcode = 0xB6}, + .F64_CONVERT_I32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xB7}, .F64_CONVERT_I32_U = Encoding{prefix = PREFIX_NONE, opcode = 0xB8}, + .F64_CONVERT_I64_S = Encoding{prefix = PREFIX_NONE, opcode = 0xB9}, .F64_CONVERT_I64_U = Encoding{prefix = PREFIX_NONE, opcode = 0xBA}, + .F64_PROMOTE_F32 = Encoding{prefix = PREFIX_NONE, opcode = 0xBB}, + .I32_REINTERPRET_F32 = Encoding{prefix = PREFIX_NONE, opcode = 0xBC}, .I64_REINTERPRET_F64 = Encoding{prefix = PREFIX_NONE, opcode = 0xBD}, + .F32_REINTERPRET_I32 = Encoding{prefix = PREFIX_NONE, opcode = 0xBE}, .F64_REINTERPRET_I64 = Encoding{prefix = PREFIX_NONE, opcode = 0xBF}, + + .I32_EXTEND8_S = Encoding{prefix = PREFIX_NONE, opcode = 0xC0}, .I32_EXTEND16_S = Encoding{prefix = PREFIX_NONE, opcode = 0xC1}, + .I64_EXTEND8_S = Encoding{prefix = PREFIX_NONE, opcode = 0xC2}, .I64_EXTEND16_S = Encoding{prefix = PREFIX_NONE, opcode = 0xC3}, .I64_EXTEND32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xC4}, + + .REF_NULL = Encoding{prefix = PREFIX_NONE, opcode = 0xD0, imm = {.REFTYPE, .NONE}}, + .REF_IS_NULL = Encoding{prefix = PREFIX_NONE, opcode = 0xD1}, + .REF_FUNC = Encoding{prefix = PREFIX_NONE, opcode = 0xD2, imm = {.IDX, .NONE}}, + + // ------------------------------------------------------- 0xFC misc prefix + .I32_TRUNC_SAT_F32_S = Encoding{prefix = PREFIX_MISC, opcode = 0}, .I32_TRUNC_SAT_F32_U = Encoding{prefix = PREFIX_MISC, opcode = 1}, + .I32_TRUNC_SAT_F64_S = Encoding{prefix = PREFIX_MISC, opcode = 2}, .I32_TRUNC_SAT_F64_U = Encoding{prefix = PREFIX_MISC, opcode = 3}, + .I64_TRUNC_SAT_F32_S = Encoding{prefix = PREFIX_MISC, opcode = 4}, .I64_TRUNC_SAT_F32_U = Encoding{prefix = PREFIX_MISC, opcode = 5}, + .I64_TRUNC_SAT_F64_S = Encoding{prefix = PREFIX_MISC, opcode = 6}, .I64_TRUNC_SAT_F64_U = Encoding{prefix = PREFIX_MISC, opcode = 7}, + .MEMORY_INIT = Encoding{prefix = PREFIX_MISC, opcode = 8, imm = {.IDX, .ZERO_BYTE}, flags = MEM}, + .DATA_DROP = Encoding{prefix = PREFIX_MISC, opcode = 9, imm = {.IDX, .NONE}}, + .MEMORY_COPY = Encoding{prefix = PREFIX_MISC, opcode = 10, imm = {.ZERO_BYTE, .ZERO_BYTE}, flags = MEM}, + .MEMORY_FILL = Encoding{prefix = PREFIX_MISC, opcode = 11, imm = {.ZERO_BYTE, .NONE}, flags = MEM}, + .TABLE_INIT = Encoding{prefix = PREFIX_MISC, opcode = 12, imm = {.IDX, .IDX}}, + .ELEM_DROP = Encoding{prefix = PREFIX_MISC, opcode = 13, imm = {.IDX, .NONE}}, + .TABLE_COPY = Encoding{prefix = PREFIX_MISC, opcode = 14, imm = {.IDX, .IDX}}, + .TABLE_GROW = Encoding{prefix = PREFIX_MISC, opcode = 15, imm = {.IDX, .NONE}}, + .TABLE_SIZE = Encoding{prefix = PREFIX_MISC, opcode = 16, imm = {.IDX, .NONE}}, + .TABLE_FILL = Encoding{prefix = PREFIX_MISC, opcode = 17, imm = {.IDX, .NONE}}, + + // ----------------------------------------------- 0xFD SIMD (v128) prefix + .V128_LOAD = Encoding{prefix = PREFIX_SIMD, opcode = 0x00, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD8X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x01, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD8X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x02, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD16X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x03, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD16X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x04, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD32X2_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x05, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD32X2_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x06, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD8_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x07, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD16_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x08, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD32_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x09, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD64_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x0A, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_STORE = Encoding{prefix = PREFIX_SIMD, opcode = 0x0B, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_CONST = Encoding{prefix = PREFIX_SIMD, opcode = 0x0C, imm = {.LANES16, .NONE}}, + .I8X16_SHUFFLE = Encoding{prefix = PREFIX_SIMD, opcode = 0x0D, imm = {.LANES16, .NONE}}, + .I8X16_SWIZZLE = Encoding{prefix = PREFIX_SIMD, opcode = 0x0E}, + .I8X16_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x0F}, + .I16X8_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x10}, + .I32X4_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x11}, + .I64X2_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x12}, + .F32X4_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x13}, + .F64X2_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x14}, + .I8X16_EXTRACT_LANE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x15, imm = {.LANE, .NONE}}, + .I8X16_EXTRACT_LANE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x16, imm = {.LANE, .NONE}}, + .I8X16_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x17, imm = {.LANE, .NONE}}, + .I16X8_EXTRACT_LANE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x18, imm = {.LANE, .NONE}}, + .I16X8_EXTRACT_LANE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x19, imm = {.LANE, .NONE}}, + .I16X8_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1A, imm = {.LANE, .NONE}}, + .I32X4_EXTRACT_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1B, imm = {.LANE, .NONE}}, + .I32X4_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1C, imm = {.LANE, .NONE}}, + .I64X2_EXTRACT_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1D, imm = {.LANE, .NONE}}, + .I64X2_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1E, imm = {.LANE, .NONE}}, + .F32X4_EXTRACT_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1F, imm = {.LANE, .NONE}}, + .F32X4_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x20, imm = {.LANE, .NONE}}, + .F64X2_EXTRACT_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x21, imm = {.LANE, .NONE}}, + .F64X2_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x22, imm = {.LANE, .NONE}}, + .I8X16_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0x23}, + .I8X16_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0x24}, + .I8X16_LT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x25}, + .I8X16_LT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x26}, + .I8X16_GT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x27}, + .I8X16_GT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x28}, + .I8X16_LE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x29}, + .I8X16_LE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x2A}, + .I8X16_GE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x2B}, + .I8X16_GE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x2C}, + .I16X8_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0x2D}, + .I16X8_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0x2E}, + .I16X8_LT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x2F}, + .I16X8_LT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x30}, + .I16X8_GT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x31}, + .I16X8_GT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x32}, + .I16X8_LE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x33}, + .I16X8_LE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x34}, + .I16X8_GE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x35}, + .I16X8_GE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x36}, + .I32X4_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0x37}, + .I32X4_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0x38}, + .I32X4_LT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x39}, + .I32X4_LT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x3A}, + .I32X4_GT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x3B}, + .I32X4_GT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x3C}, + .I32X4_LE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x3D}, + .I32X4_LE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x3E}, + .I32X4_GE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x3F}, + .I32X4_GE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x40}, + .F32X4_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0x41}, + .F32X4_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0x42}, + .F32X4_LT = Encoding{prefix = PREFIX_SIMD, opcode = 0x43}, + .F32X4_GT = Encoding{prefix = PREFIX_SIMD, opcode = 0x44}, + .F32X4_LE = Encoding{prefix = PREFIX_SIMD, opcode = 0x45}, + .F32X4_GE = Encoding{prefix = PREFIX_SIMD, opcode = 0x46}, + .F64X2_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0x47}, + .F64X2_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0x48}, + .F64X2_LT = Encoding{prefix = PREFIX_SIMD, opcode = 0x49}, + .F64X2_GT = Encoding{prefix = PREFIX_SIMD, opcode = 0x4A}, + .F64X2_LE = Encoding{prefix = PREFIX_SIMD, opcode = 0x4B}, + .F64X2_GE = Encoding{prefix = PREFIX_SIMD, opcode = 0x4C}, + .V128_NOT = Encoding{prefix = PREFIX_SIMD, opcode = 0x4D}, + .V128_AND = Encoding{prefix = PREFIX_SIMD, opcode = 0x4E}, + .V128_ANDNOT = Encoding{prefix = PREFIX_SIMD, opcode = 0x4F}, + .V128_OR = Encoding{prefix = PREFIX_SIMD, opcode = 0x50}, + .V128_XOR = Encoding{prefix = PREFIX_SIMD, opcode = 0x51}, + .V128_BITSELECT = Encoding{prefix = PREFIX_SIMD, opcode = 0x52}, + .V128_ANY_TRUE = Encoding{prefix = PREFIX_SIMD, opcode = 0x53}, + .V128_LOAD8_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x54, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_LOAD16_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x55, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_LOAD32_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x56, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_LOAD64_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x57, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_STORE8_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x58, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_STORE16_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x59, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_STORE32_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x5A, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_STORE64_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x5B, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_LOAD32_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0x5C, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD64_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0x5D, imm = {.MEMARG, .NONE}, flags = MEM}, + .F32X4_DEMOTE_F64X2_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0x5E}, + .F64X2_PROMOTE_LOW_F32X4 = Encoding{prefix = PREFIX_SIMD, opcode = 0x5F}, + .I8X16_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0x60}, + .I8X16_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0x61}, + .I8X16_POPCNT = Encoding{prefix = PREFIX_SIMD, opcode = 0x62}, + .I8X16_ALL_TRUE = Encoding{prefix = PREFIX_SIMD, opcode = 0x63}, + .I8X16_BITMASK = Encoding{prefix = PREFIX_SIMD, opcode = 0x64}, + .I8X16_NARROW_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x65}, + .I8X16_NARROW_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x66}, + .F32X4_CEIL = Encoding{prefix = PREFIX_SIMD, opcode = 0x67}, + .F32X4_FLOOR = Encoding{prefix = PREFIX_SIMD, opcode = 0x68}, + .F32X4_TRUNC = Encoding{prefix = PREFIX_SIMD, opcode = 0x69}, + .F32X4_NEAREST = Encoding{prefix = PREFIX_SIMD, opcode = 0x6A}, + .I8X16_SHL = Encoding{prefix = PREFIX_SIMD, opcode = 0x6B}, + .I8X16_SHR_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x6C}, + .I8X16_SHR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x6D}, + .I8X16_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x6E}, + .I8X16_ADD_SAT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x6F}, + .I8X16_ADD_SAT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x70}, + .I8X16_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0x71}, + .I8X16_SUB_SAT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x72}, + .I8X16_SUB_SAT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x73}, + .F64X2_CEIL = Encoding{prefix = PREFIX_SIMD, opcode = 0x74}, + .F64X2_FLOOR = Encoding{prefix = PREFIX_SIMD, opcode = 0x75}, + .I8X16_MIN_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x76}, + .I8X16_MIN_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x77}, + .I8X16_MAX_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x78}, + .I8X16_MAX_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x79}, + .F64X2_TRUNC = Encoding{prefix = PREFIX_SIMD, opcode = 0x7A}, + .I8X16_AVGR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x7B}, + .I16X8_EXTADD_PAIRWISE_I8X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x7C}, + .I16X8_EXTADD_PAIRWISE_I8X16_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x7D}, + .I32X4_EXTADD_PAIRWISE_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x7E}, + .I32X4_EXTADD_PAIRWISE_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x7F}, + .I16X8_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0x80}, + .I16X8_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0x81}, + .I16X8_Q15MULR_SAT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x82}, + .I16X8_ALL_TRUE = Encoding{prefix = PREFIX_SIMD, opcode = 0x83}, + .I16X8_BITMASK = Encoding{prefix = PREFIX_SIMD, opcode = 0x84}, + .I16X8_NARROW_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x85}, + .I16X8_NARROW_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x86}, + .I16X8_EXTEND_LOW_I8X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x87}, + .I16X8_EXTEND_HIGH_I8X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x88}, + .I16X8_EXTEND_LOW_I8X16_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x89}, + .I16X8_EXTEND_HIGH_I8X16_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x8A}, + .I16X8_SHL = Encoding{prefix = PREFIX_SIMD, opcode = 0x8B}, + .I16X8_SHR_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x8C}, + .I16X8_SHR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x8D}, + .I16X8_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x8E}, + .I16X8_ADD_SAT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x8F}, + .I16X8_ADD_SAT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x90}, + .I16X8_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0x91}, + .I16X8_SUB_SAT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x92}, + .I16X8_SUB_SAT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x93}, + .F64X2_NEAREST = Encoding{prefix = PREFIX_SIMD, opcode = 0x94}, + .I16X8_MUL = Encoding{prefix = PREFIX_SIMD, opcode = 0x95}, + .I16X8_MIN_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x96}, + .I16X8_MIN_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x97}, + .I16X8_MAX_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x98}, + .I16X8_MAX_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x99}, + .I16X8_AVGR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x9B}, + .I16X8_EXTMUL_LOW_I8X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x9C}, + .I16X8_EXTMUL_HIGH_I8X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x9D}, + .I16X8_EXTMUL_LOW_I8X16_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x9E}, + .I16X8_EXTMUL_HIGH_I8X16_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x9F}, + .I32X4_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0xA0}, + .I32X4_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0xA1}, + .I32X4_ALL_TRUE = Encoding{prefix = PREFIX_SIMD, opcode = 0xA3}, + .I32X4_BITMASK = Encoding{prefix = PREFIX_SIMD, opcode = 0xA4}, + .I32X4_EXTEND_LOW_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xA7}, + .I32X4_EXTEND_HIGH_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xA8}, + .I32X4_EXTEND_LOW_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xA9}, + .I32X4_EXTEND_HIGH_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xAA}, + .I32X4_SHL = Encoding{prefix = PREFIX_SIMD, opcode = 0xAB}, + .I32X4_SHR_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xAC}, + .I32X4_SHR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xAD}, + .I32X4_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0xAE}, + .I32X4_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0xB1}, + .I32X4_MUL = Encoding{prefix = PREFIX_SIMD, opcode = 0xB5}, + .I32X4_MIN_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xB6}, + .I32X4_MIN_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xB7}, + .I32X4_MAX_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xB8}, + .I32X4_MAX_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xB9}, + .I32X4_DOT_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xBA}, + .I32X4_EXTMUL_LOW_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xBC}, + .I32X4_EXTMUL_HIGH_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xBD}, + .I32X4_EXTMUL_LOW_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xBE}, + .I32X4_EXTMUL_HIGH_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xBF}, + .I64X2_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0xC0}, + .I64X2_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0xC1}, + .I64X2_ALL_TRUE = Encoding{prefix = PREFIX_SIMD, opcode = 0xC3}, + .I64X2_BITMASK = Encoding{prefix = PREFIX_SIMD, opcode = 0xC4}, + .I64X2_EXTEND_LOW_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xC7}, + .I64X2_EXTEND_HIGH_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xC8}, + .I64X2_EXTEND_LOW_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xC9}, + .I64X2_EXTEND_HIGH_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xCA}, + .I64X2_SHL = Encoding{prefix = PREFIX_SIMD, opcode = 0xCB}, + .I64X2_SHR_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xCC}, + .I64X2_SHR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xCD}, + .I64X2_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0xCE}, + .I64X2_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0xD1}, + .I64X2_MUL = Encoding{prefix = PREFIX_SIMD, opcode = 0xD5}, + .I64X2_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0xD6}, + .I64X2_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0xD7}, + .I64X2_LT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xD8}, + .I64X2_GT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xD9}, + .I64X2_LE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xDA}, + .I64X2_GE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xDB}, + .I64X2_EXTMUL_LOW_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xDC}, + .I64X2_EXTMUL_HIGH_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xDD}, + .I64X2_EXTMUL_LOW_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xDE}, + .I64X2_EXTMUL_HIGH_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xDF}, + .F32X4_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0xE0}, + .F32X4_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0xE1}, + .F32X4_SQRT = Encoding{prefix = PREFIX_SIMD, opcode = 0xE3}, + .F32X4_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0xE4}, + .F32X4_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0xE5}, + .F32X4_MUL = Encoding{prefix = PREFIX_SIMD, opcode = 0xE6}, + .F32X4_DIV = Encoding{prefix = PREFIX_SIMD, opcode = 0xE7}, + .F32X4_MIN = Encoding{prefix = PREFIX_SIMD, opcode = 0xE8}, + .F32X4_MAX = Encoding{prefix = PREFIX_SIMD, opcode = 0xE9}, + .F32X4_PMIN = Encoding{prefix = PREFIX_SIMD, opcode = 0xEA}, + .F32X4_PMAX = Encoding{prefix = PREFIX_SIMD, opcode = 0xEB}, + .F64X2_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0xEC}, + .F64X2_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0xED}, + .F64X2_SQRT = Encoding{prefix = PREFIX_SIMD, opcode = 0xEF}, + .F64X2_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0xF0}, + .F64X2_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0xF1}, + .F64X2_MUL = Encoding{prefix = PREFIX_SIMD, opcode = 0xF2}, + .F64X2_DIV = Encoding{prefix = PREFIX_SIMD, opcode = 0xF3}, + .F64X2_MIN = Encoding{prefix = PREFIX_SIMD, opcode = 0xF4}, + .F64X2_MAX = Encoding{prefix = PREFIX_SIMD, opcode = 0xF5}, + .F64X2_PMIN = Encoding{prefix = PREFIX_SIMD, opcode = 0xF6}, + .F64X2_PMAX = Encoding{prefix = PREFIX_SIMD, opcode = 0xF7}, + .I32X4_TRUNC_SAT_F32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xF8}, + .I32X4_TRUNC_SAT_F32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xF9}, + .F32X4_CONVERT_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xFA}, + .F32X4_CONVERT_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xFB}, + .I32X4_TRUNC_SAT_F64X2_S_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0xFC}, + .I32X4_TRUNC_SAT_F64X2_U_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0xFD}, + .F64X2_CONVERT_LOW_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xFE}, + .F64X2_CONVERT_LOW_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xFF}, + .I8X16_RELAXED_SWIZZLE = Encoding{prefix = PREFIX_SIMD, opcode = 0x100}, + .I32X4_RELAXED_TRUNC_F32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x101}, + .I32X4_RELAXED_TRUNC_F32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x102}, + .I32X4_RELAXED_TRUNC_F64X2_S_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0x103}, + .I32X4_RELAXED_TRUNC_F64X2_U_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0x104}, + .F32X4_RELAXED_MADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x105}, + .F32X4_RELAXED_NMADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x106}, + .F64X2_RELAXED_MADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x107}, + .F64X2_RELAXED_NMADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x108}, + .I8X16_RELAXED_LANESELECT = Encoding{prefix = PREFIX_SIMD, opcode = 0x109}, + .I16X8_RELAXED_LANESELECT = Encoding{prefix = PREFIX_SIMD, opcode = 0x10A}, + .I32X4_RELAXED_LANESELECT = Encoding{prefix = PREFIX_SIMD, opcode = 0x10B}, + .I64X2_RELAXED_LANESELECT = Encoding{prefix = PREFIX_SIMD, opcode = 0x10C}, + .F32X4_RELAXED_MIN = Encoding{prefix = PREFIX_SIMD, opcode = 0x10D}, + .F32X4_RELAXED_MAX = Encoding{prefix = PREFIX_SIMD, opcode = 0x10E}, + .F64X2_RELAXED_MIN = Encoding{prefix = PREFIX_SIMD, opcode = 0x10F}, + .F64X2_RELAXED_MAX = Encoding{prefix = PREFIX_SIMD, opcode = 0x110}, + .I16X8_RELAXED_Q15MULR_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x111}, + .I16X8_RELAXED_DOT_I8X16_I7X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x112}, + .I32X4_RELAXED_DOT_I8X16_I7X16_ADD_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x113}, + + // ------------------------------------------ 0xFE threads / atomics prefix + .MEMORY_ATOMIC_NOTIFY = Encoding{prefix = PREFIX_ATOM, opcode = 0x00, imm = {.MEMARG, .NONE}, flags = MEM}, + .MEMORY_ATOMIC_WAIT32 = Encoding{prefix = PREFIX_ATOM, opcode = 0x01, imm = {.MEMARG, .NONE}, flags = MEM}, + .MEMORY_ATOMIC_WAIT64 = Encoding{prefix = PREFIX_ATOM, opcode = 0x02, imm = {.MEMARG, .NONE}, flags = MEM}, + .ATOMIC_FENCE = Encoding{prefix = PREFIX_ATOM, opcode = 0x03, imm = {.ZERO_BYTE, .NONE}}, + .I32_ATOMIC_LOAD = Encoding{prefix = PREFIX_ATOM, opcode = 0x10, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_LOAD = Encoding{prefix = PREFIX_ATOM, opcode = 0x11, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_LOAD8_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x12, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_LOAD16_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x13, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_LOAD8_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x14, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_LOAD16_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x15, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_LOAD32_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x16, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_STORE = Encoding{prefix = PREFIX_ATOM, opcode = 0x17, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_STORE = Encoding{prefix = PREFIX_ATOM, opcode = 0x18, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_STORE8 = Encoding{prefix = PREFIX_ATOM, opcode = 0x19, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_STORE16 = Encoding{prefix = PREFIX_ATOM, opcode = 0x1A, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_STORE8 = Encoding{prefix = PREFIX_ATOM, opcode = 0x1B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_STORE16 = Encoding{prefix = PREFIX_ATOM, opcode = 0x1C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_STORE32 = Encoding{prefix = PREFIX_ATOM, opcode = 0x1D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_ADD = Encoding{prefix = PREFIX_ATOM, opcode = 0x1E, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_ADD = Encoding{prefix = PREFIX_ATOM, opcode = 0x1F, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_ADD_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x20, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_ADD_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x21, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_ADD_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x22, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_ADD_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x23, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_ADD_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x24, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_SUB = Encoding{prefix = PREFIX_ATOM, opcode = 0x25, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_SUB = Encoding{prefix = PREFIX_ATOM, opcode = 0x26, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_SUB_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x27, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_SUB_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x28, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_SUB_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x29, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_SUB_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x2A, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_SUB_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x2B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_AND = Encoding{prefix = PREFIX_ATOM, opcode = 0x2C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_AND = Encoding{prefix = PREFIX_ATOM, opcode = 0x2D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_AND_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x2E, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_AND_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x2F, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_AND_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x30, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_AND_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x31, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_AND_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x32, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_OR = Encoding{prefix = PREFIX_ATOM, opcode = 0x33, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_OR = Encoding{prefix = PREFIX_ATOM, opcode = 0x34, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_OR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x35, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_OR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x36, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_OR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x37, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_OR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x38, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_OR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x39, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_XOR = Encoding{prefix = PREFIX_ATOM, opcode = 0x3A, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_XOR = Encoding{prefix = PREFIX_ATOM, opcode = 0x3B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_XOR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x3C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_XOR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x3D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_XOR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x3E, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_XOR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x3F, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_XOR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x40, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_XCHG = Encoding{prefix = PREFIX_ATOM, opcode = 0x41, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_XCHG = Encoding{prefix = PREFIX_ATOM, opcode = 0x42, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_XCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x43, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_XCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x44, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_XCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x45, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_XCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x46, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_XCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x47, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_CMPXCHG = Encoding{prefix = PREFIX_ATOM, opcode = 0x48, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_CMPXCHG = Encoding{prefix = PREFIX_ATOM, opcode = 0x49, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_CMPXCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x4A, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_CMPXCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x4B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_CMPXCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x4C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_CMPXCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x4D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_CMPXCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x4E, imm = {.MEMARG, .NONE}, flags = MEM}, +} + +// Per-mnemonic encode form. Returns a pointer into the rodata table. +@(private, require_results) +encoding_form :: #force_inline proc "contextless" (m: Mnemonic) -> ^Encoding { + return &ENCODING_TABLE[m] +} diff --git a/core/rexcode/wasm/encoding_types.odin b/core/rexcode/wasm/encoding_types.odin new file mode 100644 index 000000000..6a6b9c085 --- /dev/null +++ b/core/rexcode/wasm/encoding_types.odin @@ -0,0 +1,203 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm + +import "core:rexcode/isa" + +// ============================================================================= +// WebAssembly ENCODING FUNDAMENTALS +// ============================================================================= +// +// An instruction is: [prefix?] opcode immediate* +// +// * `prefix` is 0 for the single-byte core opcodes, or one of 0xFC (misc), +// 0xFD (SIMD), 0xFE (threads). When present, the *sub*-opcode that +// follows is an unsigned LEB128 (so SIMD's 0..275 fit). +// * Integer immediates use LEB128 (unsigned for indices/alignment, signed +// for i32.const/i64.const and the s33 blocktype). +// * Float constants are raw little-endian IEEE-754 (4 or 8 bytes). +// +// There is at most one encoding form per mnemonic, so dispatch is a direct +// `ENCODING_TABLE[mnemonic]` lookup (O(1)) rather than the operand-shape +// scan the variable-form arches (x86) need. The immediate layout is described +// declaratively by `imm: [2]Imm_Kind`, walked in order by the encoder and +// decoder. + +Error :: isa.Error +Label_Definition :: isa.Label_Definition +LABEL_UNDEFINED :: isa.LABEL_UNDEFINED + +// Relocation / Relocation_Type live in reloc.odin (per-arch by design). + +// Opcode-space prefix bytes. +PREFIX_NONE :: u8(0x00) +PREFIX_MISC :: u8(0xFC) // saturating truncation, bulk memory/table +PREFIX_SIMD :: u8(0xFD) // vector (v128) +PREFIX_ATOM :: u8(0xFE) // threads / atomics + +Encoding_Flags :: bit_field u8 { + control: bool | 1, // structured control flow (block/loop/if/else/end/br*) + memory: bool | 1, // touches linear memory + _: u8 | 6, +} + +// How one immediate field is laid down after the opcode. +Imm_Kind :: enum u8 { + NONE, + BLOCKTYPE, // signed LEB128 s33 (negative valtype byte, or type index) + I32, // signed LEB128 (i32.const) + I64, // signed LEB128 (i64.const) + F32, // 4 little-endian bytes + F64, // 8 little-endian bytes + IDX, // unsigned LEB128 index (space comes from the operand) + MEMARG, // unsigned LEB128 align, then unsigned LEB128 offset + REFTYPE, // single value-type byte (ref.null) + BR_TABLE, // unsigned LEB128 count, that many label depths, default depth + ZERO_BYTE, // a single reserved 0x00 byte (memidx placeholders) + LANE, // single byte lane index (SIMD extract/replace/load/store lane) + LANES16, // sixteen raw bytes (v128.const value / i8x16.shuffle mask), from Instruction.bytes +} + +Encoding :: struct #packed { + mnemonic: Mnemonic, // 2 -- redundant w/ table index, kept for parity + prefix: u8, // 1 -- PREFIX_NONE / PREFIX_MISC / PREFIX_SIMD / PREFIX_ATOM + opcode: u16, // 2 -- primary opcode, or sub-opcode within a prefix group (SIMD reaches 0x113) + imm: [2]Imm_Kind, // 2 -- immediate layout, walked in order + flags: Encoding_Flags, // 1 +} +#assert(size_of(Encoding) == 8) + +// ============================================================================= +// LEB128 + little-endian primitives (shared by encoder and decoder) +// ============================================================================= + +// Unsigned LEB128. Advances `*offset`. Caller guarantees buffer space. +write_uleb :: #force_inline proc "contextless" (code: []u8, offset: ^u32, value: u64) { + v := value + for { + b := u8(v & 0x7F) + v >>= 7 + if v != 0 { b |= 0x80 } + code[offset^] = b + offset^ += 1 + if v == 0 { break } + } +} + +// Signed LEB128. Advances `*offset`. +write_sleb :: #force_inline proc "contextless" (code: []u8, offset: ^u32, value: i64) { + v := value + for { + b := u8(v & 0x7F) + v >>= 7 // arithmetic shift on signed value sign-extends + done := (v == 0 && (b & 0x40) == 0) || (v == -1 && (b & 0x40) != 0) + if !done { b |= 0x80 } + code[offset^] = b + offset^ += 1 + if done { break } + } +} + +// Fixed 5-byte unsigned LEB128 (relocatable placeholder for 32-bit indices). +write_uleb_padded5 :: #force_inline proc "contextless" (code: []u8, offset: ^u32, value: u64) { + v := value + for i := 0; i < 5 && offset^ < u32(len(code)); i += 1 { + b := u8(v & 0x7F) + v >>= 7 + if i != 4 { b |= 0x80 } + code[offset^] = b + offset^ += 1 + } +} + +uleb_size :: #force_inline proc "contextless" (value: u64) -> u32 { + v := value + n: u32 = 1 + for v >= 0x80 { v >>= 7; n += 1 } + return n +} + +sleb_size :: #force_inline proc "contextless" (value: i64) -> u32 { + v := value + n: u32 = 0 + for { + b := u8(v & 0x7F) + v >>= 7 + n += 1 + if (v == 0 && (b & 0x40) == 0) || (v == -1 && (b & 0x40) != 0) { break } + } + return n +} + +// Read unsigned LEB128 starting at `*offset`; advances it. `ok` is false on +// truncation. Reads at most `max` bytes (10 covers u64). +read_uleb :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (value: u64, ok: bool) { + shift: uint = 0 + for i := 0; i < 10 && offset^ < u32(len(data)); i += 1 { + b := data[offset^] + offset^ += 1 + value |= u64(b & 0x7F) << shift + if b & 0x80 == 0 { return value, true } + shift += 7 + } + return 0, false +} + +// Read signed LEB128 starting at `*offset`; advances it. +read_sleb :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (value: i64, ok: bool) { + shift: uint = 0 + b: u8 = 0 + for i := 0; i < 10 && offset^ < u32(len(data)); i += 1 { + b = data[offset^] + offset^ += 1 + value |= i64(b & 0x7F) << shift + shift += 7 + if b & 0x80 == 0 { break } + } + if shift < 64 && (b & 0x40) != 0 { + value |= -(i64(1) << shift) + } + return value, true +} + +write_u32le :: #force_inline proc(code: []u8, offset: ^u32, v: u32) { + assert(offset^+ 4 <= u32(len(code))) + code[offset^+0] = u8(v) + code[offset^+1] = u8(v >> 8) + code[offset^+2] = u8(v >> 16) + code[offset^+3] = u8(v >> 24) + offset^ += 4 +} + +write_u64le :: #force_inline proc(code: []u8, offset: ^u32, v: u64) { + assert(offset^+ 8 <= u32(len(code))) + for i in u32(0)..<8 { + code[offset^+i] = u8(v >> (8 * i)) + } + offset^ += 8 +} + +read_u32le :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (u32, bool) { + if offset^ + 4 > u32(len(data)) { + return 0, false + } + v := u32(data[offset^+0]) | + u32(data[offset^+1])<<8 | + u32(data[offset^+2])<<16 | + u32(data[offset^+3])<<24 + offset^ += 4 + return v, true +} + +read_u64le :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (u64, bool) { + if offset^ + 8 > u32(len(data)) { + return 0, false + } + v: u64 = 0 + for i in u32(0)..<8 { + v |= u64(data[offset^+i]) << (8 * i) + } + offset^ += 8 + return v, true +} diff --git a/core/rexcode/wasm/instructions.odin b/core/rexcode/wasm/instructions.odin new file mode 100644 index 000000000..d2bd516b0 --- /dev/null +++ b/core/rexcode/wasm/instructions.odin @@ -0,0 +1,151 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm + +// ============================================================================= +// INSTRUCTION +// ============================================================================= +// +// WASM instructions are variable length: a single opcode byte (or a prefix +// byte 0xFC/0xFD/0xFE plus an unsigned-LEB sub-opcode) followed by zero or +// more immediate fields. Two immediate slots cover every modelled form +// (e.g. call_indirect's typeidx + tableidx, table.copy's two tableidx). +// +// `br_table` is the one operator whose immediate is a *vector* of label +// depths; its default label lives in ops[0] and the case targets in the +// `targets` slice (caller-owned, like the rest of the input). `length` is +// filled by the encoder (and by the decoder) since it is not fixed. + +Instruction_Flags :: bit_field u8 { + _: u8 | 8, +} + +Instruction :: struct { + ops: [2]Operand `fmt:"v,operand_count"`, + targets: []u32, // br_table case labels (default in ops[0]) + bytes: [16]u8, // v128.const value / i8x16.shuffle lane mask (LANES16) + mnemonic: Mnemonic, + operand_count: u8, + flags: Instruction_Flags, + length: u8, // filled by encoder/decoder (1..N) + _: [3]u8, +} +#assert(size_of(Instruction) == 48 + 2*size_of(int)) + +// ============================================================================= +// Builders (shape spelled out, comma-separated -- contract surface) +// ============================================================================= + +@(require_results) +inst_none :: #force_inline proc "contextless" (m: Mnemonic) -> Instruction { + return Instruction{mnemonic = m, operand_count = 0} +} + +// Single immediate constant (i32/i64/f32/f64.const, ref.null). +@(require_results) +inst_i :: #force_inline proc "contextless" (m: Mnemonic, o: Operand) -> Instruction { + return Instruction{mnemonic = m, operand_count = 1, ops = {o, {}}} +} + +// Single index immediate (local/global/func/.../label). +@(require_results) +inst_idx :: #force_inline proc "contextless" (m: Mnemonic, o: Operand) -> Instruction { + return Instruction{mnemonic = m, operand_count = 1, ops = {o, {}}} +} + +// Memory access: a single memarg. +@(require_results) +inst_memarg :: #force_inline proc "contextless" (m: Mnemonic, ma: Memarg) -> Instruction { + return Instruction{mnemonic = m, operand_count = 1, ops = {op_mem(ma), {}}} +} + +// Block / loop / if with a signature. +@(require_results) +inst_block :: #force_inline proc "contextless" (m: Mnemonic, bt: Block_Type = .EMPTY) -> Instruction { + return Instruction{mnemonic = m, operand_count = 1, ops = {op_blocktype(bt), {}}} +} + +// Branch with a relative label depth (br / br_if). +@(require_results) +inst_br :: #force_inline proc "contextless" (m: Mnemonic, depth: u32) -> Instruction { + return Instruction{mnemonic = m, operand_count = 1, ops = {op_labelidx(depth), {}}} +} + +// br_table: a vector of case depths plus a default depth. +@(require_results) +inst_br_table :: #force_inline proc "contextless" (targets: []u32, default_depth: u32) -> Instruction { + return Instruction{ + mnemonic = .BR_TABLE, operand_count = 1, + ops = {op_labelidx(default_depth), {}}, targets = targets, + } +} + +// call_indirect typeidx, tableidx. +@(require_results) +inst_call_indirect :: #force_inline proc "contextless" (type_index: u32, table_index: u32 = 0) -> Instruction { + return Instruction{ + mnemonic = .CALL_INDIRECT, operand_count = 2, + ops = {op_type(type_index), op_table(table_index)}, + } +} + +// Two-index operators (table.init elemidx tableidx; table.copy dst src). +@(require_results) +inst_idx_idx :: #force_inline proc "contextless" (m: Mnemonic, a, b: Operand) -> Instruction { + return Instruction{mnemonic = m, operand_count = 2, ops = {a, b}} +} + +// ----------------------------------------------------------------------------- +// SIMD (0xFD) builders +// ----------------------------------------------------------------------------- + +// v128.const: a 16-byte literal carried in `bytes` (no stack operand). +@(require_results) +inst_v128_const :: #force_inline proc "contextless" (value: [16]u8) -> Instruction { + return Instruction{mnemonic = .V128_CONST, operand_count = 0, bytes = value} +} + +// i8x16.shuffle: a 16-lane index mask carried in `bytes`. +@(require_results) +inst_shuffle :: #force_inline proc "contextless" (lanes: [16]u8) -> Instruction { + return Instruction{mnemonic = .I8X16_SHUFFLE, operand_count = 0, bytes = lanes} +} + +// extract_lane / replace_lane: a single lane index immediate. +@(require_results) +inst_lane :: #force_inline proc "contextless" (m: Mnemonic, lane: u8) -> Instruction { + return Instruction{mnemonic = m, operand_count = 1, ops = {op_lane(lane), {}}} +} + +// v128 load/store *_lane: a memarg plus a lane index. +@(require_results) +inst_mem_lane :: #force_inline proc "contextless" (m: Mnemonic, ma: Memarg, lane: u8) -> Instruction { + return Instruction{mnemonic = m, operand_count = 2, ops = {op_mem(ma), op_lane(lane)}} +} + +// ============================================================================= +// Emitters (append to a [dynamic]Instruction) +// ============================================================================= + +emit_none :: #force_inline proc(buf: ^[dynamic]Instruction, m: Mnemonic) { + append(buf, inst_none(m)) +} +emit_i :: #force_inline proc(buf: ^[dynamic]Instruction, m: Mnemonic, o: Operand) { + append(buf, inst_i(m, o)) +} +emit_idx :: #force_inline proc(buf: ^[dynamic]Instruction, m: Mnemonic, o: Operand) { + append(buf, inst_idx(m, o)) +} +emit_memarg :: #force_inline proc(buf: ^[dynamic]Instruction, m: Mnemonic, ma: Memarg) { + append(buf, inst_memarg(m, ma)) +} +emit_block :: #force_inline proc(buf: ^[dynamic]Instruction, m: Mnemonic, bt: Block_Type = .EMPTY) { + append(buf, inst_block(m, bt)) +} +emit_br :: #force_inline proc(buf: ^[dynamic]Instruction, m: Mnemonic, depth: u32) { + append(buf, inst_br(m, depth)) +} +emit_call_indirect :: #force_inline proc(buf: ^[dynamic]Instruction, type_index: u32, table_index: u32 = 0) { + append(buf, inst_call_indirect(type_index, table_index)) +} diff --git a/core/rexcode/wasm/mnemonics.odin b/core/rexcode/wasm/mnemonics.odin new file mode 100644 index 000000000..013a8363a --- /dev/null +++ b/core/rexcode/wasm/mnemonics.odin @@ -0,0 +1,469 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm + +// ============================================================================= +// WebAssembly MNEMONICS +// ============================================================================= +// +// Coverage: +// - WebAssembly 1.0 (MVP) core: control flow, parametric, variable, +// memory, numeric (i32/i64/f32/f64) and conversion instructions. +// - The sign-extension operators (0xC0..0xC4). +// - Reference types ref.null / ref.is_null / ref.func (0xD0..0xD2). +// - The 0xFC misc prefix group: saturating float->int truncation plus the +// bulk memory / table operators (memory.init/copy/fill, table.*, ...). +// - The 0xFD SIMD (fixed-width + relaxed) vector group (v128.*, i8x16.*, ...). +// - The 0xFE threads / atomics group (atomic.fence, *.atomic.load/store/rmw*, +// memory.atomic.notify/wait*). +// +// Per the cross-arch contract: `enum u16`, `INVALID = 0`. + +Mnemonic :: enum u16 { + INVALID = 0, + + // ------------------------------------------------------------------ control + UNREACHABLE, NOP, + BLOCK, LOOP, IF, ELSE, END, + BR, BR_IF, BR_TABLE, + RETURN, CALL, CALL_INDIRECT, + + // -------------------------------------------------------------- parametric + DROP, SELECT, + + // ---------------------------------------------------------------- variable + LOCAL_GET, LOCAL_SET, LOCAL_TEE, + GLOBAL_GET, GLOBAL_SET, + + // ------------------------------------------------------------------- memory + I32_LOAD, I64_LOAD, F32_LOAD, F64_LOAD, + I32_LOAD8_S, I32_LOAD8_U, I32_LOAD16_S, I32_LOAD16_U, + I64_LOAD8_S, I64_LOAD8_U, I64_LOAD16_S, I64_LOAD16_U, I64_LOAD32_S, I64_LOAD32_U, + I32_STORE, I64_STORE, F32_STORE, F64_STORE, + I32_STORE8, I32_STORE16, + I64_STORE8, I64_STORE16, I64_STORE32, + MEMORY_SIZE, MEMORY_GROW, + + // ----------------------------------------------------------------- numeric + I32_CONST, I64_CONST, F32_CONST, F64_CONST, + + // i32 comparison + I32_EQZ, I32_EQ, I32_NE, I32_LT_S, I32_LT_U, I32_GT_S, I32_GT_U, + I32_LE_S, I32_LE_U, I32_GE_S, I32_GE_U, + // i64 comparison + I64_EQZ, I64_EQ, I64_NE, I64_LT_S, I64_LT_U, I64_GT_S, I64_GT_U, + I64_LE_S, I64_LE_U, I64_GE_S, I64_GE_U, + // f32 comparison + F32_EQ, F32_NE, F32_LT, F32_GT, F32_LE, F32_GE, + // f64 comparison + F64_EQ, F64_NE, F64_LT, F64_GT, F64_LE, F64_GE, + + // i32 arithmetic + I32_CLZ, I32_CTZ, I32_POPCNT, + I32_ADD, I32_SUB, I32_MUL, I32_DIV_S, I32_DIV_U, I32_REM_S, I32_REM_U, + I32_AND, I32_OR, I32_XOR, I32_SHL, I32_SHR_S, I32_SHR_U, I32_ROTL, I32_ROTR, + // i64 arithmetic + I64_CLZ, I64_CTZ, I64_POPCNT, + I64_ADD, I64_SUB, I64_MUL, I64_DIV_S, I64_DIV_U, I64_REM_S, I64_REM_U, + I64_AND, I64_OR, I64_XOR, I64_SHL, I64_SHR_S, I64_SHR_U, I64_ROTL, I64_ROTR, + // f32 arithmetic + F32_ABS, F32_NEG, F32_CEIL, F32_FLOOR, F32_TRUNC, F32_NEAREST, F32_SQRT, + F32_ADD, F32_SUB, F32_MUL, F32_DIV, F32_MIN, F32_MAX, F32_COPYSIGN, + // f64 arithmetic + F64_ABS, F64_NEG, F64_CEIL, F64_FLOOR, F64_TRUNC, F64_NEAREST, F64_SQRT, + F64_ADD, F64_SUB, F64_MUL, F64_DIV, F64_MIN, F64_MAX, F64_COPYSIGN, + + // conversions + I32_WRAP_I64, + I32_TRUNC_F32_S, I32_TRUNC_F32_U, I32_TRUNC_F64_S, I32_TRUNC_F64_U, + I64_EXTEND_I32_S, I64_EXTEND_I32_U, + I64_TRUNC_F32_S, I64_TRUNC_F32_U, I64_TRUNC_F64_S, I64_TRUNC_F64_U, + F32_CONVERT_I32_S, F32_CONVERT_I32_U, F32_CONVERT_I64_S, F32_CONVERT_I64_U, F32_DEMOTE_F64, + F64_CONVERT_I32_S, F64_CONVERT_I32_U, F64_CONVERT_I64_S, F64_CONVERT_I64_U, F64_PROMOTE_F32, + I32_REINTERPRET_F32, I64_REINTERPRET_F64, F32_REINTERPRET_I32, F64_REINTERPRET_I64, + + // sign-extension operators (0xC0..0xC4) + I32_EXTEND8_S, I32_EXTEND16_S, + I64_EXTEND8_S, I64_EXTEND16_S, I64_EXTEND32_S, + + // reference types + REF_NULL, REF_IS_NULL, REF_FUNC, + + // ------------------------------------------------------- 0xFC misc prefix + // saturating truncation + I32_TRUNC_SAT_F32_S, I32_TRUNC_SAT_F32_U, I32_TRUNC_SAT_F64_S, I32_TRUNC_SAT_F64_U, + I64_TRUNC_SAT_F32_S, I64_TRUNC_SAT_F32_U, I64_TRUNC_SAT_F64_S, I64_TRUNC_SAT_F64_U, + // bulk memory & table + MEMORY_INIT, DATA_DROP, MEMORY_COPY, MEMORY_FILL, + TABLE_INIT, ELEM_DROP, TABLE_COPY, TABLE_GROW, TABLE_SIZE, TABLE_FILL, + + // ----------------------------------------------- 0xFD SIMD (v128) prefix + V128_LOAD, V128_LOAD8X8_S, V128_LOAD8X8_U, + V128_LOAD16X4_S, V128_LOAD16X4_U, V128_LOAD32X2_S, + V128_LOAD32X2_U, V128_LOAD8_SPLAT, V128_LOAD16_SPLAT, + V128_LOAD32_SPLAT, V128_LOAD64_SPLAT, V128_STORE, + V128_CONST, I8X16_SHUFFLE, I8X16_SWIZZLE, + I8X16_SPLAT, I16X8_SPLAT, I32X4_SPLAT, + I64X2_SPLAT, F32X4_SPLAT, F64X2_SPLAT, + I8X16_EXTRACT_LANE_S, I8X16_EXTRACT_LANE_U, I8X16_REPLACE_LANE, + I16X8_EXTRACT_LANE_S, I16X8_EXTRACT_LANE_U, I16X8_REPLACE_LANE, + I32X4_EXTRACT_LANE, I32X4_REPLACE_LANE, I64X2_EXTRACT_LANE, + I64X2_REPLACE_LANE, F32X4_EXTRACT_LANE, F32X4_REPLACE_LANE, + F64X2_EXTRACT_LANE, F64X2_REPLACE_LANE, I8X16_EQ, + I8X16_NE, I8X16_LT_S, I8X16_LT_U, + I8X16_GT_S, I8X16_GT_U, I8X16_LE_S, + I8X16_LE_U, I8X16_GE_S, I8X16_GE_U, + I16X8_EQ, I16X8_NE, I16X8_LT_S, + I16X8_LT_U, I16X8_GT_S, I16X8_GT_U, + I16X8_LE_S, I16X8_LE_U, I16X8_GE_S, + I16X8_GE_U, I32X4_EQ, I32X4_NE, + I32X4_LT_S, I32X4_LT_U, I32X4_GT_S, + I32X4_GT_U, I32X4_LE_S, I32X4_LE_U, + I32X4_GE_S, I32X4_GE_U, F32X4_EQ, + F32X4_NE, F32X4_LT, F32X4_GT, + F32X4_LE, F32X4_GE, F64X2_EQ, + F64X2_NE, F64X2_LT, F64X2_GT, + F64X2_LE, F64X2_GE, V128_NOT, + V128_AND, V128_ANDNOT, V128_OR, + V128_XOR, V128_BITSELECT, V128_ANY_TRUE, + V128_LOAD8_LANE, V128_LOAD16_LANE, V128_LOAD32_LANE, + V128_LOAD64_LANE, V128_STORE8_LANE, V128_STORE16_LANE, + V128_STORE32_LANE, V128_STORE64_LANE, V128_LOAD32_ZERO, + V128_LOAD64_ZERO, F32X4_DEMOTE_F64X2_ZERO, F64X2_PROMOTE_LOW_F32X4, + I8X16_ABS, I8X16_NEG, I8X16_POPCNT, + I8X16_ALL_TRUE, I8X16_BITMASK, I8X16_NARROW_I16X8_S, + I8X16_NARROW_I16X8_U, F32X4_CEIL, F32X4_FLOOR, + F32X4_TRUNC, F32X4_NEAREST, I8X16_SHL, + I8X16_SHR_S, I8X16_SHR_U, I8X16_ADD, + I8X16_ADD_SAT_S, I8X16_ADD_SAT_U, I8X16_SUB, + I8X16_SUB_SAT_S, I8X16_SUB_SAT_U, F64X2_CEIL, + F64X2_FLOOR, I8X16_MIN_S, I8X16_MIN_U, + I8X16_MAX_S, I8X16_MAX_U, F64X2_TRUNC, + I8X16_AVGR_U, I16X8_EXTADD_PAIRWISE_I8X16_S, I16X8_EXTADD_PAIRWISE_I8X16_U, + I32X4_EXTADD_PAIRWISE_I16X8_S, I32X4_EXTADD_PAIRWISE_I16X8_U, I16X8_ABS, + I16X8_NEG, I16X8_Q15MULR_SAT_S, I16X8_ALL_TRUE, + I16X8_BITMASK, I16X8_NARROW_I32X4_S, I16X8_NARROW_I32X4_U, + I16X8_EXTEND_LOW_I8X16_S, I16X8_EXTEND_HIGH_I8X16_S, I16X8_EXTEND_LOW_I8X16_U, + I16X8_EXTEND_HIGH_I8X16_U, I16X8_SHL, I16X8_SHR_S, + I16X8_SHR_U, I16X8_ADD, I16X8_ADD_SAT_S, + I16X8_ADD_SAT_U, I16X8_SUB, I16X8_SUB_SAT_S, + I16X8_SUB_SAT_U, F64X2_NEAREST, I16X8_MUL, + I16X8_MIN_S, I16X8_MIN_U, I16X8_MAX_S, + I16X8_MAX_U, I16X8_AVGR_U, I16X8_EXTMUL_LOW_I8X16_S, + I16X8_EXTMUL_HIGH_I8X16_S, I16X8_EXTMUL_LOW_I8X16_U, I16X8_EXTMUL_HIGH_I8X16_U, + I32X4_ABS, I32X4_NEG, I32X4_ALL_TRUE, + I32X4_BITMASK, I32X4_EXTEND_LOW_I16X8_S, I32X4_EXTEND_HIGH_I16X8_S, + I32X4_EXTEND_LOW_I16X8_U, I32X4_EXTEND_HIGH_I16X8_U, I32X4_SHL, + I32X4_SHR_S, I32X4_SHR_U, I32X4_ADD, + I32X4_SUB, I32X4_MUL, I32X4_MIN_S, + I32X4_MIN_U, I32X4_MAX_S, I32X4_MAX_U, + I32X4_DOT_I16X8_S, I32X4_EXTMUL_LOW_I16X8_S, I32X4_EXTMUL_HIGH_I16X8_S, + I32X4_EXTMUL_LOW_I16X8_U, I32X4_EXTMUL_HIGH_I16X8_U, I64X2_ABS, + I64X2_NEG, I64X2_ALL_TRUE, I64X2_BITMASK, + I64X2_EXTEND_LOW_I32X4_S, I64X2_EXTEND_HIGH_I32X4_S, I64X2_EXTEND_LOW_I32X4_U, + I64X2_EXTEND_HIGH_I32X4_U, I64X2_SHL, I64X2_SHR_S, + I64X2_SHR_U, I64X2_ADD, I64X2_SUB, + I64X2_MUL, I64X2_EQ, I64X2_NE, + I64X2_LT_S, I64X2_GT_S, I64X2_LE_S, + I64X2_GE_S, I64X2_EXTMUL_LOW_I32X4_S, I64X2_EXTMUL_HIGH_I32X4_S, + I64X2_EXTMUL_LOW_I32X4_U, I64X2_EXTMUL_HIGH_I32X4_U, F32X4_ABS, + F32X4_NEG, F32X4_SQRT, F32X4_ADD, + F32X4_SUB, F32X4_MUL, F32X4_DIV, + F32X4_MIN, F32X4_MAX, F32X4_PMIN, + F32X4_PMAX, F64X2_ABS, F64X2_NEG, + F64X2_SQRT, F64X2_ADD, F64X2_SUB, + F64X2_MUL, F64X2_DIV, F64X2_MIN, + F64X2_MAX, F64X2_PMIN, F64X2_PMAX, + I32X4_TRUNC_SAT_F32X4_S, I32X4_TRUNC_SAT_F32X4_U, F32X4_CONVERT_I32X4_S, + F32X4_CONVERT_I32X4_U, I32X4_TRUNC_SAT_F64X2_S_ZERO, I32X4_TRUNC_SAT_F64X2_U_ZERO, + F64X2_CONVERT_LOW_I32X4_S, F64X2_CONVERT_LOW_I32X4_U, I8X16_RELAXED_SWIZZLE, + I32X4_RELAXED_TRUNC_F32X4_S, I32X4_RELAXED_TRUNC_F32X4_U, I32X4_RELAXED_TRUNC_F64X2_S_ZERO, + I32X4_RELAXED_TRUNC_F64X2_U_ZERO, F32X4_RELAXED_MADD, F32X4_RELAXED_NMADD, + F64X2_RELAXED_MADD, F64X2_RELAXED_NMADD, I8X16_RELAXED_LANESELECT, + I16X8_RELAXED_LANESELECT, I32X4_RELAXED_LANESELECT, I64X2_RELAXED_LANESELECT, + F32X4_RELAXED_MIN, F32X4_RELAXED_MAX, F64X2_RELAXED_MIN, + F64X2_RELAXED_MAX, I16X8_RELAXED_Q15MULR_S, I16X8_RELAXED_DOT_I8X16_I7X16_S, + I32X4_RELAXED_DOT_I8X16_I7X16_ADD_S, + + // ------------------------------------------ 0xFE threads / atomics prefix + MEMORY_ATOMIC_NOTIFY, MEMORY_ATOMIC_WAIT32, MEMORY_ATOMIC_WAIT64, + ATOMIC_FENCE, I32_ATOMIC_LOAD, I64_ATOMIC_LOAD, + I32_ATOMIC_LOAD8_U, I32_ATOMIC_LOAD16_U, I64_ATOMIC_LOAD8_U, + I64_ATOMIC_LOAD16_U, I64_ATOMIC_LOAD32_U, I32_ATOMIC_STORE, + I64_ATOMIC_STORE, I32_ATOMIC_STORE8, I32_ATOMIC_STORE16, + I64_ATOMIC_STORE8, I64_ATOMIC_STORE16, I64_ATOMIC_STORE32, + I32_ATOMIC_RMW_ADD, I64_ATOMIC_RMW_ADD, I32_ATOMIC_RMW8_ADD_U, + I32_ATOMIC_RMW16_ADD_U, I64_ATOMIC_RMW8_ADD_U, I64_ATOMIC_RMW16_ADD_U, + I64_ATOMIC_RMW32_ADD_U, I32_ATOMIC_RMW_SUB, I64_ATOMIC_RMW_SUB, + I32_ATOMIC_RMW8_SUB_U, I32_ATOMIC_RMW16_SUB_U, I64_ATOMIC_RMW8_SUB_U, + I64_ATOMIC_RMW16_SUB_U, I64_ATOMIC_RMW32_SUB_U, I32_ATOMIC_RMW_AND, + I64_ATOMIC_RMW_AND, I32_ATOMIC_RMW8_AND_U, I32_ATOMIC_RMW16_AND_U, + I64_ATOMIC_RMW8_AND_U, I64_ATOMIC_RMW16_AND_U, I64_ATOMIC_RMW32_AND_U, + I32_ATOMIC_RMW_OR, I64_ATOMIC_RMW_OR, I32_ATOMIC_RMW8_OR_U, + I32_ATOMIC_RMW16_OR_U, I64_ATOMIC_RMW8_OR_U, I64_ATOMIC_RMW16_OR_U, + I64_ATOMIC_RMW32_OR_U, I32_ATOMIC_RMW_XOR, I64_ATOMIC_RMW_XOR, + I32_ATOMIC_RMW8_XOR_U, I32_ATOMIC_RMW16_XOR_U, I64_ATOMIC_RMW8_XOR_U, + I64_ATOMIC_RMW16_XOR_U, I64_ATOMIC_RMW32_XOR_U, I32_ATOMIC_RMW_XCHG, + I64_ATOMIC_RMW_XCHG, I32_ATOMIC_RMW8_XCHG_U, I32_ATOMIC_RMW16_XCHG_U, + I64_ATOMIC_RMW8_XCHG_U, I64_ATOMIC_RMW16_XCHG_U, I64_ATOMIC_RMW32_XCHG_U, + I32_ATOMIC_RMW_CMPXCHG, I64_ATOMIC_RMW_CMPXCHG, I32_ATOMIC_RMW8_CMPXCHG_U, + I32_ATOMIC_RMW16_CMPXCHG_U, I64_ATOMIC_RMW8_CMPXCHG_U, I64_ATOMIC_RMW16_CMPXCHG_U, + I64_ATOMIC_RMW32_CMPXCHG_U, +} + +// ----------------------------------------------------------------------------- +// Canonical WAT text names (per-arch formatting -- WASM mixes '.' and '_' in +// ways no single transform of the enum name captures, so the names are +// explicit). Indexed by Mnemonic; INVALID maps to "". +// ----------------------------------------------------------------------------- + +@(rodata) +MNEMONIC_NAMES := [Mnemonic]string{ + .INVALID = "", + + .UNREACHABLE = "unreachable", .NOP = "nop", + .BLOCK = "block", .LOOP = "loop", .IF = "if", .ELSE = "else", .END = "end", + .BR = "br", .BR_IF = "br_if", .BR_TABLE = "br_table", + .RETURN = "return", .CALL = "call", .CALL_INDIRECT = "call_indirect", + + .DROP = "drop", .SELECT = "select", + + .LOCAL_GET = "local.get", .LOCAL_SET = "local.set", .LOCAL_TEE = "local.tee", + .GLOBAL_GET = "global.get", .GLOBAL_SET = "global.set", + + .I32_LOAD = "i32.load", .I64_LOAD = "i64.load", .F32_LOAD = "f32.load", .F64_LOAD = "f64.load", + .I32_LOAD8_S = "i32.load8_s", .I32_LOAD8_U = "i32.load8_u", + .I32_LOAD16_S = "i32.load16_s", .I32_LOAD16_U = "i32.load16_u", + .I64_LOAD8_S = "i64.load8_s", .I64_LOAD8_U = "i64.load8_u", + .I64_LOAD16_S = "i64.load16_s", .I64_LOAD16_U = "i64.load16_u", + .I64_LOAD32_S = "i64.load32_s", .I64_LOAD32_U = "i64.load32_u", + .I32_STORE = "i32.store", .I64_STORE = "i64.store", .F32_STORE = "f32.store", .F64_STORE = "f64.store", + .I32_STORE8 = "i32.store8", .I32_STORE16 = "i32.store16", + .I64_STORE8 = "i64.store8", .I64_STORE16 = "i64.store16", .I64_STORE32 = "i64.store32", + .MEMORY_SIZE = "memory.size", .MEMORY_GROW = "memory.grow", + + .I32_CONST = "i32.const", .I64_CONST = "i64.const", .F32_CONST = "f32.const", .F64_CONST = "f64.const", + + .I32_EQZ = "i32.eqz", .I32_EQ = "i32.eq", .I32_NE = "i32.ne", + .I32_LT_S = "i32.lt_s", .I32_LT_U = "i32.lt_u", .I32_GT_S = "i32.gt_s", .I32_GT_U = "i32.gt_u", + .I32_LE_S = "i32.le_s", .I32_LE_U = "i32.le_u", .I32_GE_S = "i32.ge_s", .I32_GE_U = "i32.ge_u", + .I64_EQZ = "i64.eqz", .I64_EQ = "i64.eq", .I64_NE = "i64.ne", + .I64_LT_S = "i64.lt_s", .I64_LT_U = "i64.lt_u", .I64_GT_S = "i64.gt_s", .I64_GT_U = "i64.gt_u", + .I64_LE_S = "i64.le_s", .I64_LE_U = "i64.le_u", .I64_GE_S = "i64.ge_s", .I64_GE_U = "i64.ge_u", + .F32_EQ = "f32.eq", .F32_NE = "f32.ne", .F32_LT = "f32.lt", .F32_GT = "f32.gt", .F32_LE = "f32.le", .F32_GE = "f32.ge", + .F64_EQ = "f64.eq", .F64_NE = "f64.ne", .F64_LT = "f64.lt", .F64_GT = "f64.gt", .F64_LE = "f64.le", .F64_GE = "f64.ge", + + .I32_CLZ = "i32.clz", .I32_CTZ = "i32.ctz", .I32_POPCNT = "i32.popcnt", + .I32_ADD = "i32.add", .I32_SUB = "i32.sub", .I32_MUL = "i32.mul", + .I32_DIV_S = "i32.div_s", .I32_DIV_U = "i32.div_u", .I32_REM_S = "i32.rem_s", .I32_REM_U = "i32.rem_u", + .I32_AND = "i32.and", .I32_OR = "i32.or", .I32_XOR = "i32.xor", + .I32_SHL = "i32.shl", .I32_SHR_S = "i32.shr_s", .I32_SHR_U = "i32.shr_u", .I32_ROTL = "i32.rotl", .I32_ROTR = "i32.rotr", + .I64_CLZ = "i64.clz", .I64_CTZ = "i64.ctz", .I64_POPCNT = "i64.popcnt", + .I64_ADD = "i64.add", .I64_SUB = "i64.sub", .I64_MUL = "i64.mul", + .I64_DIV_S = "i64.div_s", .I64_DIV_U = "i64.div_u", .I64_REM_S = "i64.rem_s", .I64_REM_U = "i64.rem_u", + .I64_AND = "i64.and", .I64_OR = "i64.or", .I64_XOR = "i64.xor", + .I64_SHL = "i64.shl", .I64_SHR_S = "i64.shr_s", .I64_SHR_U = "i64.shr_u", .I64_ROTL = "i64.rotl", .I64_ROTR = "i64.rotr", + .F32_ABS = "f32.abs", .F32_NEG = "f32.neg", .F32_CEIL = "f32.ceil", .F32_FLOOR = "f32.floor", + .F32_TRUNC = "f32.trunc", .F32_NEAREST = "f32.nearest", .F32_SQRT = "f32.sqrt", + .F32_ADD = "f32.add", .F32_SUB = "f32.sub", .F32_MUL = "f32.mul", .F32_DIV = "f32.div", + .F32_MIN = "f32.min", .F32_MAX = "f32.max", .F32_COPYSIGN = "f32.copysign", + .F64_ABS = "f64.abs", .F64_NEG = "f64.neg", .F64_CEIL = "f64.ceil", .F64_FLOOR = "f64.floor", + .F64_TRUNC = "f64.trunc", .F64_NEAREST = "f64.nearest", .F64_SQRT = "f64.sqrt", + .F64_ADD = "f64.add", .F64_SUB = "f64.sub", .F64_MUL = "f64.mul", .F64_DIV = "f64.div", + .F64_MIN = "f64.min", .F64_MAX = "f64.max", .F64_COPYSIGN = "f64.copysign", + + .I32_WRAP_I64 = "i32.wrap_i64", + .I32_TRUNC_F32_S = "i32.trunc_f32_s", .I32_TRUNC_F32_U = "i32.trunc_f32_u", + .I32_TRUNC_F64_S = "i32.trunc_f64_s", .I32_TRUNC_F64_U = "i32.trunc_f64_u", + .I64_EXTEND_I32_S = "i64.extend_i32_s", .I64_EXTEND_I32_U = "i64.extend_i32_u", + .I64_TRUNC_F32_S = "i64.trunc_f32_s", .I64_TRUNC_F32_U = "i64.trunc_f32_u", + .I64_TRUNC_F64_S = "i64.trunc_f64_s", .I64_TRUNC_F64_U = "i64.trunc_f64_u", + .F32_CONVERT_I32_S = "f32.convert_i32_s", .F32_CONVERT_I32_U = "f32.convert_i32_u", + .F32_CONVERT_I64_S = "f32.convert_i64_s", .F32_CONVERT_I64_U = "f32.convert_i64_u", + .F32_DEMOTE_F64 = "f32.demote_f64", + .F64_CONVERT_I32_S = "f64.convert_i32_s", .F64_CONVERT_I32_U = "f64.convert_i32_u", + .F64_CONVERT_I64_S = "f64.convert_i64_s", .F64_CONVERT_I64_U = "f64.convert_i64_u", + .F64_PROMOTE_F32 = "f64.promote_f32", + .I32_REINTERPRET_F32 = "i32.reinterpret_f32", .I64_REINTERPRET_F64 = "i64.reinterpret_f64", + .F32_REINTERPRET_I32 = "f32.reinterpret_i32", .F64_REINTERPRET_I64 = "f64.reinterpret_i64", + + .I32_EXTEND8_S = "i32.extend8_s", .I32_EXTEND16_S = "i32.extend16_s", + .I64_EXTEND8_S = "i64.extend8_s", .I64_EXTEND16_S = "i64.extend16_s", .I64_EXTEND32_S = "i64.extend32_s", + + .REF_NULL = "ref.null", .REF_IS_NULL = "ref.is_null", .REF_FUNC = "ref.func", + + .I32_TRUNC_SAT_F32_S = "i32.trunc_sat_f32_s", .I32_TRUNC_SAT_F32_U = "i32.trunc_sat_f32_u", + .I32_TRUNC_SAT_F64_S = "i32.trunc_sat_f64_s", .I32_TRUNC_SAT_F64_U = "i32.trunc_sat_f64_u", + .I64_TRUNC_SAT_F32_S = "i64.trunc_sat_f32_s", .I64_TRUNC_SAT_F32_U = "i64.trunc_sat_f32_u", + .I64_TRUNC_SAT_F64_S = "i64.trunc_sat_f64_s", .I64_TRUNC_SAT_F64_U = "i64.trunc_sat_f64_u", + .MEMORY_INIT = "memory.init", .DATA_DROP = "data.drop", .MEMORY_COPY = "memory.copy", .MEMORY_FILL = "memory.fill", + .TABLE_INIT = "table.init", .ELEM_DROP = "elem.drop", .TABLE_COPY = "table.copy", + .TABLE_GROW = "table.grow", .TABLE_SIZE = "table.size", .TABLE_FILL = "table.fill", + + // SIMD (0xFD) + .V128_LOAD = "v128.load", .V128_LOAD8X8_S = "v128.load8x8_s", + .V128_LOAD8X8_U = "v128.load8x8_u", .V128_LOAD16X4_S = "v128.load16x4_s", + .V128_LOAD16X4_U = "v128.load16x4_u", .V128_LOAD32X2_S = "v128.load32x2_s", + .V128_LOAD32X2_U = "v128.load32x2_u", .V128_LOAD8_SPLAT = "v128.load8_splat", + .V128_LOAD16_SPLAT = "v128.load16_splat", .V128_LOAD32_SPLAT = "v128.load32_splat", + .V128_LOAD64_SPLAT = "v128.load64_splat", .V128_STORE = "v128.store", + .V128_CONST = "v128.const", .I8X16_SHUFFLE = "i8x16.shuffle", + .I8X16_SWIZZLE = "i8x16.swizzle", .I8X16_SPLAT = "i8x16.splat", + .I16X8_SPLAT = "i16x8.splat", .I32X4_SPLAT = "i32x4.splat", + .I64X2_SPLAT = "i64x2.splat", .F32X4_SPLAT = "f32x4.splat", + .F64X2_SPLAT = "f64x2.splat", .I8X16_EXTRACT_LANE_S = "i8x16.extract_lane_s", + .I8X16_EXTRACT_LANE_U = "i8x16.extract_lane_u", .I8X16_REPLACE_LANE = "i8x16.replace_lane", + .I16X8_EXTRACT_LANE_S = "i16x8.extract_lane_s", .I16X8_EXTRACT_LANE_U = "i16x8.extract_lane_u", + .I16X8_REPLACE_LANE = "i16x8.replace_lane", .I32X4_EXTRACT_LANE = "i32x4.extract_lane", + .I32X4_REPLACE_LANE = "i32x4.replace_lane", .I64X2_EXTRACT_LANE = "i64x2.extract_lane", + .I64X2_REPLACE_LANE = "i64x2.replace_lane", .F32X4_EXTRACT_LANE = "f32x4.extract_lane", + .F32X4_REPLACE_LANE = "f32x4.replace_lane", .F64X2_EXTRACT_LANE = "f64x2.extract_lane", + .F64X2_REPLACE_LANE = "f64x2.replace_lane", .I8X16_EQ = "i8x16.eq", + .I8X16_NE = "i8x16.ne", .I8X16_LT_S = "i8x16.lt_s", + .I8X16_LT_U = "i8x16.lt_u", .I8X16_GT_S = "i8x16.gt_s", + .I8X16_GT_U = "i8x16.gt_u", .I8X16_LE_S = "i8x16.le_s", + .I8X16_LE_U = "i8x16.le_u", .I8X16_GE_S = "i8x16.ge_s", + .I8X16_GE_U = "i8x16.ge_u", .I16X8_EQ = "i16x8.eq", + .I16X8_NE = "i16x8.ne", .I16X8_LT_S = "i16x8.lt_s", + .I16X8_LT_U = "i16x8.lt_u", .I16X8_GT_S = "i16x8.gt_s", + .I16X8_GT_U = "i16x8.gt_u", .I16X8_LE_S = "i16x8.le_s", + .I16X8_LE_U = "i16x8.le_u", .I16X8_GE_S = "i16x8.ge_s", + .I16X8_GE_U = "i16x8.ge_u", .I32X4_EQ = "i32x4.eq", + .I32X4_NE = "i32x4.ne", .I32X4_LT_S = "i32x4.lt_s", + .I32X4_LT_U = "i32x4.lt_u", .I32X4_GT_S = "i32x4.gt_s", + .I32X4_GT_U = "i32x4.gt_u", .I32X4_LE_S = "i32x4.le_s", + .I32X4_LE_U = "i32x4.le_u", .I32X4_GE_S = "i32x4.ge_s", + .I32X4_GE_U = "i32x4.ge_u", .F32X4_EQ = "f32x4.eq", + .F32X4_NE = "f32x4.ne", .F32X4_LT = "f32x4.lt", + .F32X4_GT = "f32x4.gt", .F32X4_LE = "f32x4.le", + .F32X4_GE = "f32x4.ge", .F64X2_EQ = "f64x2.eq", + .F64X2_NE = "f64x2.ne", .F64X2_LT = "f64x2.lt", + .F64X2_GT = "f64x2.gt", .F64X2_LE = "f64x2.le", + .F64X2_GE = "f64x2.ge", .V128_NOT = "v128.not", + .V128_AND = "v128.and", .V128_ANDNOT = "v128.andnot", + .V128_OR = "v128.or", .V128_XOR = "v128.xor", + .V128_BITSELECT = "v128.bitselect", .V128_ANY_TRUE = "v128.any_true", + .V128_LOAD8_LANE = "v128.load8_lane", .V128_LOAD16_LANE = "v128.load16_lane", + .V128_LOAD32_LANE = "v128.load32_lane", .V128_LOAD64_LANE = "v128.load64_lane", + .V128_STORE8_LANE = "v128.store8_lane", .V128_STORE16_LANE = "v128.store16_lane", + .V128_STORE32_LANE = "v128.store32_lane", .V128_STORE64_LANE = "v128.store64_lane", + .V128_LOAD32_ZERO = "v128.load32_zero", .V128_LOAD64_ZERO = "v128.load64_zero", + .F32X4_DEMOTE_F64X2_ZERO = "f32x4.demote_f64x2_zero", .F64X2_PROMOTE_LOW_F32X4 = "f64x2.promote_low_f32x4", + .I8X16_ABS = "i8x16.abs", .I8X16_NEG = "i8x16.neg", + .I8X16_POPCNT = "i8x16.popcnt", .I8X16_ALL_TRUE = "i8x16.all_true", + .I8X16_BITMASK = "i8x16.bitmask", .I8X16_NARROW_I16X8_S = "i8x16.narrow_i16x8_s", + .I8X16_NARROW_I16X8_U = "i8x16.narrow_i16x8_u", .F32X4_CEIL = "f32x4.ceil", + .F32X4_FLOOR = "f32x4.floor", .F32X4_TRUNC = "f32x4.trunc", + .F32X4_NEAREST = "f32x4.nearest", .I8X16_SHL = "i8x16.shl", + .I8X16_SHR_S = "i8x16.shr_s", .I8X16_SHR_U = "i8x16.shr_u", + .I8X16_ADD = "i8x16.add", .I8X16_ADD_SAT_S = "i8x16.add_sat_s", + .I8X16_ADD_SAT_U = "i8x16.add_sat_u", .I8X16_SUB = "i8x16.sub", + .I8X16_SUB_SAT_S = "i8x16.sub_sat_s", .I8X16_SUB_SAT_U = "i8x16.sub_sat_u", + .F64X2_CEIL = "f64x2.ceil", .F64X2_FLOOR = "f64x2.floor", + .I8X16_MIN_S = "i8x16.min_s", .I8X16_MIN_U = "i8x16.min_u", + .I8X16_MAX_S = "i8x16.max_s", .I8X16_MAX_U = "i8x16.max_u", + .F64X2_TRUNC = "f64x2.trunc", .I8X16_AVGR_U = "i8x16.avgr_u", + .I16X8_EXTADD_PAIRWISE_I8X16_S = "i16x8.extadd_pairwise_i8x16_s", .I16X8_EXTADD_PAIRWISE_I8X16_U = "i16x8.extadd_pairwise_i8x16_u", + .I32X4_EXTADD_PAIRWISE_I16X8_S = "i32x4.extadd_pairwise_i16x8_s", .I32X4_EXTADD_PAIRWISE_I16X8_U = "i32x4.extadd_pairwise_i16x8_u", + .I16X8_ABS = "i16x8.abs", .I16X8_NEG = "i16x8.neg", + .I16X8_Q15MULR_SAT_S = "i16x8.q15mulr_sat_s", .I16X8_ALL_TRUE = "i16x8.all_true", + .I16X8_BITMASK = "i16x8.bitmask", .I16X8_NARROW_I32X4_S = "i16x8.narrow_i32x4_s", + .I16X8_NARROW_I32X4_U = "i16x8.narrow_i32x4_u", .I16X8_EXTEND_LOW_I8X16_S = "i16x8.extend_low_i8x16_s", + .I16X8_EXTEND_HIGH_I8X16_S = "i16x8.extend_high_i8x16_s", .I16X8_EXTEND_LOW_I8X16_U = "i16x8.extend_low_i8x16_u", + .I16X8_EXTEND_HIGH_I8X16_U = "i16x8.extend_high_i8x16_u", .I16X8_SHL = "i16x8.shl", + .I16X8_SHR_S = "i16x8.shr_s", .I16X8_SHR_U = "i16x8.shr_u", + .I16X8_ADD = "i16x8.add", .I16X8_ADD_SAT_S = "i16x8.add_sat_s", + .I16X8_ADD_SAT_U = "i16x8.add_sat_u", .I16X8_SUB = "i16x8.sub", + .I16X8_SUB_SAT_S = "i16x8.sub_sat_s", .I16X8_SUB_SAT_U = "i16x8.sub_sat_u", + .F64X2_NEAREST = "f64x2.nearest", .I16X8_MUL = "i16x8.mul", + .I16X8_MIN_S = "i16x8.min_s", .I16X8_MIN_U = "i16x8.min_u", + .I16X8_MAX_S = "i16x8.max_s", .I16X8_MAX_U = "i16x8.max_u", + .I16X8_AVGR_U = "i16x8.avgr_u", .I16X8_EXTMUL_LOW_I8X16_S = "i16x8.extmul_low_i8x16_s", + .I16X8_EXTMUL_HIGH_I8X16_S = "i16x8.extmul_high_i8x16_s", .I16X8_EXTMUL_LOW_I8X16_U = "i16x8.extmul_low_i8x16_u", + .I16X8_EXTMUL_HIGH_I8X16_U = "i16x8.extmul_high_i8x16_u", .I32X4_ABS = "i32x4.abs", + .I32X4_NEG = "i32x4.neg", .I32X4_ALL_TRUE = "i32x4.all_true", + .I32X4_BITMASK = "i32x4.bitmask", .I32X4_EXTEND_LOW_I16X8_S = "i32x4.extend_low_i16x8_s", + .I32X4_EXTEND_HIGH_I16X8_S = "i32x4.extend_high_i16x8_s", .I32X4_EXTEND_LOW_I16X8_U = "i32x4.extend_low_i16x8_u", + .I32X4_EXTEND_HIGH_I16X8_U = "i32x4.extend_high_i16x8_u", .I32X4_SHL = "i32x4.shl", + .I32X4_SHR_S = "i32x4.shr_s", .I32X4_SHR_U = "i32x4.shr_u", + .I32X4_ADD = "i32x4.add", .I32X4_SUB = "i32x4.sub", + .I32X4_MUL = "i32x4.mul", .I32X4_MIN_S = "i32x4.min_s", + .I32X4_MIN_U = "i32x4.min_u", .I32X4_MAX_S = "i32x4.max_s", + .I32X4_MAX_U = "i32x4.max_u", .I32X4_DOT_I16X8_S = "i32x4.dot_i16x8_s", + .I32X4_EXTMUL_LOW_I16X8_S = "i32x4.extmul_low_i16x8_s", .I32X4_EXTMUL_HIGH_I16X8_S = "i32x4.extmul_high_i16x8_s", + .I32X4_EXTMUL_LOW_I16X8_U = "i32x4.extmul_low_i16x8_u", .I32X4_EXTMUL_HIGH_I16X8_U = "i32x4.extmul_high_i16x8_u", + .I64X2_ABS = "i64x2.abs", .I64X2_NEG = "i64x2.neg", + .I64X2_ALL_TRUE = "i64x2.all_true", .I64X2_BITMASK = "i64x2.bitmask", + .I64X2_EXTEND_LOW_I32X4_S = "i64x2.extend_low_i32x4_s", .I64X2_EXTEND_HIGH_I32X4_S = "i64x2.extend_high_i32x4_s", + .I64X2_EXTEND_LOW_I32X4_U = "i64x2.extend_low_i32x4_u", .I64X2_EXTEND_HIGH_I32X4_U = "i64x2.extend_high_i32x4_u", + .I64X2_SHL = "i64x2.shl", .I64X2_SHR_S = "i64x2.shr_s", + .I64X2_SHR_U = "i64x2.shr_u", .I64X2_ADD = "i64x2.add", + .I64X2_SUB = "i64x2.sub", .I64X2_MUL = "i64x2.mul", + .I64X2_EQ = "i64x2.eq", .I64X2_NE = "i64x2.ne", + .I64X2_LT_S = "i64x2.lt_s", .I64X2_GT_S = "i64x2.gt_s", + .I64X2_LE_S = "i64x2.le_s", .I64X2_GE_S = "i64x2.ge_s", + .I64X2_EXTMUL_LOW_I32X4_S = "i64x2.extmul_low_i32x4_s", .I64X2_EXTMUL_HIGH_I32X4_S = "i64x2.extmul_high_i32x4_s", + .I64X2_EXTMUL_LOW_I32X4_U = "i64x2.extmul_low_i32x4_u", .I64X2_EXTMUL_HIGH_I32X4_U = "i64x2.extmul_high_i32x4_u", + .F32X4_ABS = "f32x4.abs", .F32X4_NEG = "f32x4.neg", + .F32X4_SQRT = "f32x4.sqrt", .F32X4_ADD = "f32x4.add", + .F32X4_SUB = "f32x4.sub", .F32X4_MUL = "f32x4.mul", + .F32X4_DIV = "f32x4.div", .F32X4_MIN = "f32x4.min", + .F32X4_MAX = "f32x4.max", .F32X4_PMIN = "f32x4.pmin", + .F32X4_PMAX = "f32x4.pmax", .F64X2_ABS = "f64x2.abs", + .F64X2_NEG = "f64x2.neg", .F64X2_SQRT = "f64x2.sqrt", + .F64X2_ADD = "f64x2.add", .F64X2_SUB = "f64x2.sub", + .F64X2_MUL = "f64x2.mul", .F64X2_DIV = "f64x2.div", + .F64X2_MIN = "f64x2.min", .F64X2_MAX = "f64x2.max", + .F64X2_PMIN = "f64x2.pmin", .F64X2_PMAX = "f64x2.pmax", + .I32X4_TRUNC_SAT_F32X4_S = "i32x4.trunc_sat_f32x4_s", .I32X4_TRUNC_SAT_F32X4_U = "i32x4.trunc_sat_f32x4_u", + .F32X4_CONVERT_I32X4_S = "f32x4.convert_i32x4_s", .F32X4_CONVERT_I32X4_U = "f32x4.convert_i32x4_u", + .I32X4_TRUNC_SAT_F64X2_S_ZERO = "i32x4.trunc_sat_f64x2_s_zero", .I32X4_TRUNC_SAT_F64X2_U_ZERO = "i32x4.trunc_sat_f64x2_u_zero", + .F64X2_CONVERT_LOW_I32X4_S = "f64x2.convert_low_i32x4_s", .F64X2_CONVERT_LOW_I32X4_U = "f64x2.convert_low_i32x4_u", + .I8X16_RELAXED_SWIZZLE = "i8x16.relaxed_swizzle", .I32X4_RELAXED_TRUNC_F32X4_S = "i32x4.relaxed_trunc_f32x4_s", + .I32X4_RELAXED_TRUNC_F32X4_U = "i32x4.relaxed_trunc_f32x4_u", .I32X4_RELAXED_TRUNC_F64X2_S_ZERO = "i32x4.relaxed_trunc_f64x2_s_zero", + .I32X4_RELAXED_TRUNC_F64X2_U_ZERO = "i32x4.relaxed_trunc_f64x2_u_zero", .F32X4_RELAXED_MADD = "f32x4.relaxed_madd", + .F32X4_RELAXED_NMADD = "f32x4.relaxed_nmadd", .F64X2_RELAXED_MADD = "f64x2.relaxed_madd", + .F64X2_RELAXED_NMADD = "f64x2.relaxed_nmadd", .I8X16_RELAXED_LANESELECT = "i8x16.relaxed_laneselect", + .I16X8_RELAXED_LANESELECT = "i16x8.relaxed_laneselect", .I32X4_RELAXED_LANESELECT = "i32x4.relaxed_laneselect", + .I64X2_RELAXED_LANESELECT = "i64x2.relaxed_laneselect", .F32X4_RELAXED_MIN = "f32x4.relaxed_min", + .F32X4_RELAXED_MAX = "f32x4.relaxed_max", .F64X2_RELAXED_MIN = "f64x2.relaxed_min", + .F64X2_RELAXED_MAX = "f64x2.relaxed_max", .I16X8_RELAXED_Q15MULR_S = "i16x8.relaxed_q15mulr_s", + .I16X8_RELAXED_DOT_I8X16_I7X16_S = "i16x8.relaxed_dot_i8x16_i7x16_s", .I32X4_RELAXED_DOT_I8X16_I7X16_ADD_S = "i32x4.relaxed_dot_i8x16_i7x16_add_s", + + // threads / atomics (0xFE) + .MEMORY_ATOMIC_NOTIFY = "memory.atomic.notify", .MEMORY_ATOMIC_WAIT32 = "memory.atomic.wait32", + .MEMORY_ATOMIC_WAIT64 = "memory.atomic.wait64", .ATOMIC_FENCE = "atomic.fence", + .I32_ATOMIC_LOAD = "i32.atomic.load", .I64_ATOMIC_LOAD = "i64.atomic.load", + .I32_ATOMIC_LOAD8_U = "i32.atomic.load8_u", .I32_ATOMIC_LOAD16_U = "i32.atomic.load16_u", + .I64_ATOMIC_LOAD8_U = "i64.atomic.load8_u", .I64_ATOMIC_LOAD16_U = "i64.atomic.load16_u", + .I64_ATOMIC_LOAD32_U = "i64.atomic.load32_u", .I32_ATOMIC_STORE = "i32.atomic.store", + .I64_ATOMIC_STORE = "i64.atomic.store", .I32_ATOMIC_STORE8 = "i32.atomic.store8", + .I32_ATOMIC_STORE16 = "i32.atomic.store16", .I64_ATOMIC_STORE8 = "i64.atomic.store8", + .I64_ATOMIC_STORE16 = "i64.atomic.store16", .I64_ATOMIC_STORE32 = "i64.atomic.store32", + .I32_ATOMIC_RMW_ADD = "i32.atomic.rmw.add", .I64_ATOMIC_RMW_ADD = "i64.atomic.rmw.add", + .I32_ATOMIC_RMW8_ADD_U = "i32.atomic.rmw8.add_u", .I32_ATOMIC_RMW16_ADD_U = "i32.atomic.rmw16.add_u", + .I64_ATOMIC_RMW8_ADD_U = "i64.atomic.rmw8.add_u", .I64_ATOMIC_RMW16_ADD_U = "i64.atomic.rmw16.add_u", + .I64_ATOMIC_RMW32_ADD_U = "i64.atomic.rmw32.add_u", .I32_ATOMIC_RMW_SUB = "i32.atomic.rmw.sub", + .I64_ATOMIC_RMW_SUB = "i64.atomic.rmw.sub", .I32_ATOMIC_RMW8_SUB_U = "i32.atomic.rmw8.sub_u", + .I32_ATOMIC_RMW16_SUB_U = "i32.atomic.rmw16.sub_u", .I64_ATOMIC_RMW8_SUB_U = "i64.atomic.rmw8.sub_u", + .I64_ATOMIC_RMW16_SUB_U = "i64.atomic.rmw16.sub_u", .I64_ATOMIC_RMW32_SUB_U = "i64.atomic.rmw32.sub_u", + .I32_ATOMIC_RMW_AND = "i32.atomic.rmw.and", .I64_ATOMIC_RMW_AND = "i64.atomic.rmw.and", + .I32_ATOMIC_RMW8_AND_U = "i32.atomic.rmw8.and_u", .I32_ATOMIC_RMW16_AND_U = "i32.atomic.rmw16.and_u", + .I64_ATOMIC_RMW8_AND_U = "i64.atomic.rmw8.and_u", .I64_ATOMIC_RMW16_AND_U = "i64.atomic.rmw16.and_u", + .I64_ATOMIC_RMW32_AND_U = "i64.atomic.rmw32.and_u", .I32_ATOMIC_RMW_OR = "i32.atomic.rmw.or", + .I64_ATOMIC_RMW_OR = "i64.atomic.rmw.or", .I32_ATOMIC_RMW8_OR_U = "i32.atomic.rmw8.or_u", + .I32_ATOMIC_RMW16_OR_U = "i32.atomic.rmw16.or_u", .I64_ATOMIC_RMW8_OR_U = "i64.atomic.rmw8.or_u", + .I64_ATOMIC_RMW16_OR_U = "i64.atomic.rmw16.or_u", .I64_ATOMIC_RMW32_OR_U = "i64.atomic.rmw32.or_u", + .I32_ATOMIC_RMW_XOR = "i32.atomic.rmw.xor", .I64_ATOMIC_RMW_XOR = "i64.atomic.rmw.xor", + .I32_ATOMIC_RMW8_XOR_U = "i32.atomic.rmw8.xor_u", .I32_ATOMIC_RMW16_XOR_U = "i32.atomic.rmw16.xor_u", + .I64_ATOMIC_RMW8_XOR_U = "i64.atomic.rmw8.xor_u", .I64_ATOMIC_RMW16_XOR_U = "i64.atomic.rmw16.xor_u", + .I64_ATOMIC_RMW32_XOR_U = "i64.atomic.rmw32.xor_u", .I32_ATOMIC_RMW_XCHG = "i32.atomic.rmw.xchg", + .I64_ATOMIC_RMW_XCHG = "i64.atomic.rmw.xchg", .I32_ATOMIC_RMW8_XCHG_U = "i32.atomic.rmw8.xchg_u", + .I32_ATOMIC_RMW16_XCHG_U = "i32.atomic.rmw16.xchg_u", .I64_ATOMIC_RMW8_XCHG_U = "i64.atomic.rmw8.xchg_u", + .I64_ATOMIC_RMW16_XCHG_U = "i64.atomic.rmw16.xchg_u", .I64_ATOMIC_RMW32_XCHG_U = "i64.atomic.rmw32.xchg_u", + .I32_ATOMIC_RMW_CMPXCHG = "i32.atomic.rmw.cmpxchg", .I64_ATOMIC_RMW_CMPXCHG = "i64.atomic.rmw.cmpxchg", + .I32_ATOMIC_RMW8_CMPXCHG_U = "i32.atomic.rmw8.cmpxchg_u", .I32_ATOMIC_RMW16_CMPXCHG_U = "i32.atomic.rmw16.cmpxchg_u", + .I64_ATOMIC_RMW8_CMPXCHG_U = "i64.atomic.rmw8.cmpxchg_u", .I64_ATOMIC_RMW16_CMPXCHG_U = "i64.atomic.rmw16.cmpxchg_u", + .I64_ATOMIC_RMW32_CMPXCHG_U = "i64.atomic.rmw32.cmpxchg_u", +} diff --git a/core/rexcode/wasm/operands.odin b/core/rexcode/wasm/operands.odin new file mode 100644 index 000000000..90215b0ad --- /dev/null +++ b/core/rexcode/wasm/operands.odin @@ -0,0 +1,197 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm + +// ============================================================================= +// WebAssembly OPERANDS +// ============================================================================= +// +// WASM operands are not registers or addressing modes; they are *immediates* +// that follow the opcode in the byte stream: +// +// i32.const 42 IMMEDIATE immediate = 42 (signed LEB128) +// f64.const 3.14 IMMEDIATE immediate = bits(3.14) (8 LE bytes) +// local.get 0 INDEX index = 0, idx_kind = LOCAL (unsigned LEB128) +// call $f INDEX index = funcidx, idx_kind = FUNC +// br 1 INDEX index = 1, idx_kind = LABEL (branch depth) +// i32.load align=2 off=8 MEMARG memarg = {align = 2, offset = 8} +// block (result i32) BLOCK_TYPE block_type = .I32 +// +// Branching in WASM is *structured*: `br`/`br_if`/`br_table` take a relative +// label depth (an unsigned immediate), not a PC-relative byte offset. There +// are therefore no PC-relative relocations and the isa label-inference path is +// not used; the array-index `Label_Definition` machinery is re-exported for +// contract parity but WASM control flow does not consume it. +// +// Relocations *are* real, but for the object-file index spaces (function / +// global / table / type / data / elem indices that a linker fixes up). An +// INDEX operand flagged `symbolic` carries a label id and is emitted as a +// fixed-width 5-byte LEB placeholder plus a Relocation entry. `op_label` +// (required by the contract) produces exactly such a symbolic function index. + +Operand_Kind :: enum u8 { + NONE, + REGISTER, // vestigial -- WASM is register-less (never produced) + IMMEDIATE, // i32/i64/f32/f64 constant (floats stored as raw bits) + INDEX, // LEB128 unsigned index into one of the index spaces + MEMARG, // load/store alignment + offset pair + BLOCK_TYPE, // block / loop / if signature +} + +// Which index space an INDEX operand addresses. Drives matching, relocation +// type selection, and printer annotation. +Index_Kind :: enum u8 { + NONE, + LOCAL, + GLOBAL, + FUNC, + TYPE, + TABLE, + MEMORY, + LABEL, // br / br_if / br_table relative depth + DATA, + ELEM, +} + +Operand_Flags :: bit_field u8 { + symbolic: bool | 1, // INDEX value is a label id needing a relocation + is_float: bool | 1, // IMMEDIATE holds float bits (vs a signed integer) + _: u8 | 6, +} + +// Load/store immediate: alignment hint (log2 bytes) + static offset. +Memarg :: struct #packed { + offset: u32, + align: u32, +} +#assert(size_of(Memarg) == 8) + +// Block signature. Negative sentinels are the s33 single-byte forms; a +// non-negative value is a type index encoded as a positive signed LEB128. +Block_Type :: enum i64 { + EMPTY = -64, // 0x40 + I32 = -1, // 0x7F + I64 = -2, // 0x7E + F32 = -3, // 0x7D + F64 = -4, // 0x7C + V128 = -5, // 0x7B + FUNCREF = -16, // 0x70 + EXTERNREF = -17, // 0x6F +} + +Operand :: struct #packed { + using _: struct #raw_union { + reg: Register, // REGISTER (vestigial) + memarg: Memarg, // MEMARG + immediate: i64, // IMMEDIATE (int value or float bits) / BLOCK_TYPE (s33) + index: u32, // INDEX (value, or label id when symbolic) + }, + kind: Operand_Kind, + idx_kind: Index_Kind, + size: u8, // value width in bytes where meaningful (4/8) + flags: Operand_Flags, +} +#assert(size_of(Operand) == 12) + +// ----------------------------------------------------------------------------- +// Generic constructors (contract surface) +// ----------------------------------------------------------------------------- + +@(require_results) +op_reg :: #force_inline proc "contextless" (r: Register) -> Operand { + return Operand{reg = r, kind = .REGISTER} +} + +@(require_results) +op_imm :: #force_inline proc "contextless" (v: i64, size: u8) -> Operand { + return Operand{immediate = v, kind = .IMMEDIATE, size = size} +} + +@(require_results) +op_mem :: #force_inline proc "contextless" (m: Memarg, size: u8 = 0) -> Operand { + return Operand{memarg = m, kind = .MEMARG, size = size} +} + +// Symbolic function reference: emitted as a relocatable funcidx placeholder. +@(require_results) +op_label :: #force_inline proc "contextless" (label_id: u32, size: u8 = 5) -> Operand { + return Operand{index = label_id, kind = .INDEX, idx_kind = .FUNC, size = size, flags = {symbolic = true}} +} + +// ----------------------------------------------------------------------------- +// Numeric constants +// ----------------------------------------------------------------------------- + +@(require_results) +op_i32 :: #force_inline proc "contextless" (v: i32) -> Operand { + return Operand{immediate = i64(v), kind = .IMMEDIATE, size = 4} +} +@(require_results) +op_i64 :: #force_inline proc "contextless" (v: i64) -> Operand { + return Operand{immediate = v, kind = .IMMEDIATE, size = 8} +} +@(require_results) +op_f32 :: #force_inline proc "contextless" (v: f32) -> Operand { + return Operand{immediate = i64(transmute(u32)v), kind = .IMMEDIATE, size = 4, flags = {is_float = true}} +} +@(require_results) +op_f64 :: #force_inline proc "contextless" (v: f64) -> Operand { + return Operand{immediate = transmute(i64)v, kind = .IMMEDIATE, size = 8, flags = {is_float = true}} +} + +// ----------------------------------------------------------------------------- +// Memory argument + block type +// ----------------------------------------------------------------------------- + +@(require_results) +memarg :: #force_inline proc "contextless" (align, offset: u32) -> Memarg { + return Memarg{align = align, offset = offset} +} +@(require_results) +op_memarg :: #force_inline proc "contextless" (align, offset: u32) -> Operand { + return Operand{memarg = Memarg{align = align, offset = offset}, kind = .MEMARG} +} + +@(require_results) +op_blocktype :: #force_inline proc "contextless" (bt: Block_Type) -> Operand { + return Operand{immediate = i64(bt), kind = .BLOCK_TYPE} +} +@(require_results) +op_block_typeidx :: #force_inline proc "contextless" (type_index: u32) -> Operand { + return Operand{immediate = i64(type_index), kind = .BLOCK_TYPE} +} + +// ----------------------------------------------------------------------------- +// Index-space constructors (one per space; all unsigned LEB128 on the wire) +// ----------------------------------------------------------------------------- + +@(require_results) +op_index :: #force_inline proc "contextless" (kind: Index_Kind, value: u32) -> Operand { + return Operand{index = value, kind = .INDEX, idx_kind = kind} +} + +@(require_results) op_local :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.LOCAL, n) } +@(require_results) op_global :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.GLOBAL, n) } +@(require_results) op_func :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.FUNC, n) } +@(require_results) op_type :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.TYPE, n) } +@(require_results) op_table :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.TABLE, n) } +@(require_results) op_memory :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.MEMORY, n) } +@(require_results) op_data :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.DATA, n) } +@(require_results) op_elem :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.ELEM, n) } + +// Branch label depth (number of enclosing blocks to break out of). +@(require_results) op_labelidx :: #force_inline proc "contextless" (depth: u32) -> Operand { return op_index(.LABEL, depth) } + +// ref.null heap type (encoded as a single value-type byte). +@(require_results) +op_reftype :: #force_inline proc "contextless" (t: Value_Type) -> Operand { + return Operand{immediate = i64(t), kind = .IMMEDIATE, size = 1} +} + +// SIMD lane index (single byte) for extract_lane / replace_lane / load_lane / +// store_lane operators. +@(require_results) +op_lane :: #force_inline proc "contextless" (n: u8) -> Operand { + return Operand{immediate = i64(n), kind = .IMMEDIATE, size = 1} +} diff --git a/core/rexcode/wasm/printer.odin b/core/rexcode/wasm/printer.odin new file mode 100644 index 000000000..cf7b5f176 --- /dev/null +++ b/core/rexcode/wasm/printer.odin @@ -0,0 +1,406 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm + +import "core:strings" +import "core:strconv" +import "core:os" +import "core:io" +import "core:rexcode/isa" + +// ============================================================================= +// WebAssembly PRINTER +// ============================================================================= +// +// Emits WebAssembly text-format (WAT) instruction syntax: the folded-stack +// form is not reconstructed (that needs structure the linear stream does not +// carry); instead each instruction prints on its own line as +// +// * +// +// Examples: +// +// i32.const 42 +// local.get 0 +// i32.add +// call 3 +// block (result i32) +// i32.load offset=8 align=2 +// br_table 0 1 2 ; cases 0 1, default 2 +// ref.null func +// f64.const 3.14 +// +// Mnemonic spelling comes from the explicit MNEMONIC_NAMES table (WASM mixes +// '.' and '_' irregularly, e.g. `local.get` vs `i32.trunc_f32_s`). WASM has +// no register file, so register printing is vestigial. + +Token :: isa.Token +Token_Kind :: isa.Token_Kind +Print_Options :: isa.Print_Options +Print_Result :: isa.Print_Result +DEFAULT_PRINT_OPTIONS :: isa.DEFAULT_PRINT_OPTIONS + +mnemonic_to_string :: proc(m: Mnemonic, lowercase: bool = true, allocator := context.temp_allocator) -> string { + sb := strings.builder_make(allocator) + write_mnemonic(&sb, m, !lowercase) + return strings.to_string(sb) +} + +// Vestigial -- WASM is register-less; provided for contract parity only. +register_name :: proc(r: Register, lowercase: bool = true, allocator := context.temp_allocator) -> string { + _ = r + _ = lowercase + return "" +} + +// ============================================================================= +// Core sbprint +// ============================================================================= + +sbprint :: proc( + sb: ^strings.Builder, + instructions: []Instruction, + inst_info: []Instruction_Info, + label_defs: []Label_Definition, + tokens: ^[dynamic]Token = nil, + options: ^Print_Options = nil, + label_names: ^map[u32]string = nil, +) { + opts := options + if opts == nil { + @(static) defaults := DEFAULT_PRINT_OPTIONS + opts = &defaults + } + + running: u32 = 0 + for i in 0.. 0 { + for slot in 0.. string { + sb := strings.builder_make(allocator) + sbprint(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + return strings.to_string(sb) +} + +aprintln :: proc( + instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, + tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, + allocator := context.allocator, +) -> string { + sb := strings.builder_make(allocator) + sbprintln(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + return strings.to_string(sb) +} + +tprint :: proc( + instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, + tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, +) -> string { + sb := strings.builder_make(context.temp_allocator) + sbprint(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + return strings.to_string(sb) +} + +tprintln :: proc( + instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, + tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, +) -> string { + sb := strings.builder_make(context.temp_allocator) + sbprintln(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + return strings.to_string(sb) +} + +bprint :: proc( + buf: []u8, + instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, + tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, +) -> string { + sb := strings.builder_from_bytes(buf) + sbprint(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + return strings.to_string(sb) +} + +bprintln :: proc( + buf: []u8, + instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, + tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, +) -> string { + sb := strings.builder_from_bytes(buf) + sbprintln(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + return strings.to_string(sb) +} + +fprint :: proc( + fd: ^os.File, + instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, + tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, +) { + sb := strings.builder_make(context.temp_allocator) + sbprint(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + os.write_string(fd, strings.to_string(sb)) +} + +fprintln :: proc( + fd: ^os.File, + instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, + tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, +) { + sb := strings.builder_make(context.temp_allocator) + sbprintln(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + os.write_string(fd, strings.to_string(sb)) +} + +wprint :: proc( + w: io.Writer, + instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, + tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, +) { + sb := strings.builder_make(context.temp_allocator) + sbprint(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + io.write_string(w, strings.to_string(sb)) +} + +wprintln :: proc( + w: io.Writer, + instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, + tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, +) { + sb := strings.builder_make(context.temp_allocator) + sbprintln(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + io.write_string(w, strings.to_string(sb)) +} + +// ============================================================================= +// Internal writers +// ============================================================================= + +@(private="file") +write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { + name := MNEMONIC_NAMES[m] + if name == "" { strings.write_string(sb, ""); return } + if uppercase { + for i in 0..= 'a' && c <= 'z' { strings.write_byte(sb, c - 32) } else { strings.write_byte(sb, c) } + } + } else { + strings.write_string(sb, name) + } +} + +@(private="file") +write_operand :: proc( + sb: ^strings.Builder, + op: ^Operand, + mnemonic: Mnemonic, + label_names: ^map[u32]string, + opts: ^Print_Options, +) { + switch op.kind { + case .NONE: + + case .REGISTER: + strings.write_string(sb, "") // vestigial + + case .IMMEDIATE: + if mnemonic == .REF_NULL { + write_heap_type(sb, u8(op.immediate)) + } else if op.flags.is_float { + write_float(sb, op) + } else { + write_signed_decimal(sb, op.immediate) + } + + case .INDEX: + if op.flags.symbolic { + write_label(sb, op.index, label_names, opts) + } else { + write_decimal_u32(sb, op.index) + } + + case .MEMARG: + // WAT prints non-trivial memargs as `offset=N align=N` (omitting either + // when it is the natural default is a refinement; we print both). + strings.write_string(sb, "offset=") + write_decimal_u32(sb, op.memarg.offset) + strings.write_string(sb, " align=") + write_decimal_u32(sb, op.memarg.align) + + case .BLOCK_TYPE: + write_block_type(sb, op.immediate) + } +} + +@(private="file") +write_block_type :: proc(sb: ^strings.Builder, v: i64) { + switch Block_Type(v) { + case .EMPTY: // no result annotation + case .I32: strings.write_string(sb, "(result i32)") + case .I64: strings.write_string(sb, "(result i64)") + case .F32: strings.write_string(sb, "(result f32)") + case .F64: strings.write_string(sb, "(result f64)") + case .V128: strings.write_string(sb, "(result v128)") + case .FUNCREF: strings.write_string(sb, "(result funcref)") + case .EXTERNREF: strings.write_string(sb, "(result externref)") + case: + // non-negative: a type index + strings.write_string(sb, "(type ") + write_decimal_u32(sb, u32(v)) + strings.write_byte(sb, ')') + } +} + +@(private="file") +write_heap_type :: proc(sb: ^strings.Builder, b: u8) { + #partial switch Value_Type(b) { + case .FUNCREF: strings.write_string(sb, "func") + case .EXTERNREF: strings.write_string(sb, "extern") + case: + write_decimal_u32(sb, u32(b)) + } +} + +@(private="file") +write_float :: proc(sb: ^strings.Builder, op: ^Operand) { + buf: [40]u8 + if op.size == 4 { + f := transmute(f32)u32(op.immediate) + s := strconv.write_float(buf[:], f64(f), 'g', -1, 32) + strings.write_string(sb, s) + } else { + f := transmute(f64)u64(op.immediate) + s := strconv.write_float(buf[:], f, 'g', -1, 64) + strings.write_string(sb, s) + } +} + +@(private="file") +write_label :: proc( + sb: ^strings.Builder, + label_id: u32, + label_names: ^map[u32]string, + opts: ^Print_Options, +) { + if label_names != nil { + if name, has := label_names^[label_id]; has { + strings.write_string(sb, name) + return + } + } + strings.write_string(sb, opts.label_prefix) + write_decimal_u32(sb, label_id) +} + +@(private="file") +write_decimal_u32 :: proc(sb: ^strings.Builder, v: u32) { + if v == 0 { strings.write_byte(sb, '0'); return } + buf: [10]u8 + i := 0 + n := v + for n > 0 { buf[i] = '0' + u8(n % 10); n /= 10; i += 1 } + for j := i - 1; j >= 0; j -= 1 { strings.write_byte(sb, buf[j]) } +} + +@(private="file") +write_signed_decimal :: proc(sb: ^strings.Builder, v: i64) { + if v < 0 { + strings.write_byte(sb, '-') + write_decimal_u64(sb, u64(-(v + 1)) + 1) + } else { + write_decimal_u64(sb, u64(v)) + } +} + +@(private="file") +write_decimal_u64 :: proc(sb: ^strings.Builder, v: u64) { + if v == 0 { strings.write_byte(sb, '0'); return } + buf: [20]u8 + i := 0 + n := v + for n > 0 { buf[i] = '0' + u8(n % 10); n /= 10; i += 1 } + for j := i - 1; j >= 0; j -= 1 { strings.write_byte(sb, buf[j]) } +} diff --git a/core/rexcode/wasm/registers.odin b/core/rexcode/wasm/registers.odin new file mode 100644 index 000000000..062417d1e --- /dev/null +++ b/core/rexcode/wasm/registers.odin @@ -0,0 +1,76 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm + +// ============================================================================= +// WebAssembly "REGISTERS" +// ============================================================================= +// +// WebAssembly is a stack machine: it has no general-purpose register file. +// Operands live on an implicit value stack and instructions reference locals, +// globals, and various index spaces by LEB128 immediate -- never by register. +// +// The cross-arch naming contract still asks every package for a `Register` +// type plus `reg_hw` / `reg_class` accessors, so we keep the same packed +// `distinct u16` scheme (class in the high byte, index in the low byte) used +// by the register-machine arches. It is *vestigial* here: the REGISTER +// operand kind is never produced by the encoder or decoder, and the value +// stack is modelled implicitly. The real per-arch content WASM cares about -- +// value types and the index spaces -- lives below and in operands.odin. + +Register :: distinct u16 + +REG_NONE :: 0x0000 + +NONE :: Register(0xFFFF) + +@(require_results) +reg_hw :: #force_inline proc "contextless" (r: Register) -> u8 { + return u8(r) & 0xFF +} + +@(require_results) +reg_class :: #force_inline proc "contextless" (r: Register) -> u16 { + return u16(r) & 0xFF00 +} + +@(require_results) +reg_size :: #force_inline proc "contextless" (_: Register) -> u8 { + return 0 // no fixed width: the value stack is implicit +} + +// ----------------------------------------------------------------------------- +// Value types (the bytes WASM actually uses where a register would otherwise +// appear: block result/param types, ref.null heap types, select t* types). +// +// The numeric byte is the WASM binary encoding; the same byte sign-extends to +// the negative s33 value used inside a blocktype. See operands.odin / +// Block_Type for how these participate in block / loop / if. +// ----------------------------------------------------------------------------- + +Value_Type :: enum u8 { + I32 = 0x7F, + I64 = 0x7E, + F32 = 0x7D, + F64 = 0x7C, + V128 = 0x7B, + FUNCREF = 0x70, + EXTERNREF = 0x6F, +} + +@(require_results) +value_type_is_num :: #force_inline proc "contextless" (t: Value_Type) -> bool { + #partial switch t { + case .I32, .I64, .F32, .F64: return true + } + return false +} + +@(require_results) +value_type_is_ref :: #force_inline proc "contextless" (t: Value_Type) -> bool { + #partial switch t { + case .FUNCREF, .EXTERNREF: return true + } + return false +} diff --git a/core/rexcode/wasm/reloc.odin b/core/rexcode/wasm/reloc.odin new file mode 100644 index 000000000..685986080 --- /dev/null +++ b/core/rexcode/wasm/reloc.odin @@ -0,0 +1,44 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) +// Ginger Bill (gingerBill@github) + +package rexcode_wasm + +// ============================================================================= +// WebAssembly RELOCATIONS +// ============================================================================= +// +// Per the cross-arch design (§2.4) each arch owns its Relocation_Type. WASM's +// relocations are the object-file ("linking") relocations: symbolic index +// references the linker fixes up. They are emitted, never PC-relative -- WASM +// control flow uses structured label depths, not byte offsets, so the encoder +// does not resolve these in a pass 2; it records them and leaves the patching +// to the linker. The relocatable LEB encodings are written as fixed-width +// 5-byte placeholders so the patched value always fits. +// +// The subset modelled mirrors the names from the tool-conventions linking +// spec used by LLVM / wasm-ld. + +Relocation_Type :: enum u8 { + NONE = 0, + + FUNCTION_INDEX_LEB, // funcidx, 5-byte ULEB (call, ref.func) + TABLE_INDEX_SLEB, // 5-byte SLEB table element index + TABLE_INDEX_I32, // 4-byte LE table element index + MEMORY_ADDR_LEB, // linear-memory address, 5-byte ULEB + MEMORY_ADDR_SLEB, // linear-memory address, 5-byte SLEB + MEMORY_ADDR_I32, // linear-memory address, 4-byte LE + TYPE_INDEX_LEB, // typeidx, 5-byte ULEB (call_indirect) + GLOBAL_INDEX_LEB, // globalidx, 5-byte ULEB + TABLE_NUMBER_LEB, // tableidx, 5-byte ULEB +} + +Relocation :: struct #packed { + offset: u32, // byte offset of the relocatable field + label_id: u32, // symbol / target label id + addend: i32, + type: Relocation_Type, + size: u8, // bytes occupied by the field (5 for LEB, 4 for I32) + inst_idx: u16, +} +#assert(size_of(Relocation) == 16) diff --git a/core/rexcode/wasm/tests/pipeline_smoke.odin b/core/rexcode/wasm/tests/pipeline_smoke.odin new file mode 100644 index 000000000..3333bfef3 --- /dev/null +++ b/core/rexcode/wasm/tests/pipeline_smoke.odin @@ -0,0 +1,148 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm_tests + +// End-to-end WASM pipeline: build a short instruction sequence, encode it, +// assert the exact byte stream against hand-computed LEB128 encodings, then +// decode the bytes back and confirm the mnemonics/operands round-trip, and +// finally print the decoded form and check the WAT text. +// +// Covers: nullary ops, signed-LEB constants, index immediates, a blocktype, +// a memarg, and the br_table vector form. +// +// Run with: odin run wasm/tests + +import "core:fmt" +import "core:os" +import wasm "../" + +@(private="file") rpasses := 0 +@(private="file") rfailures := 0 + +@(private="file") +ok :: proc(name: string, cond: bool) { + if cond { + fmt.printfln(" [ok] %s", name) + rpasses += 1 + } else { + fmt.printfln(" [FAIL] %s", name) + rfailures += 1 + } +} + +@(private="file") +eq_bytes :: proc(name: string, got, want: []u8) { + same := len(got) == len(want) + if same { + for i in 0.. 0 { os.exit(1) } +} diff --git a/core/rexcode/wasm/tests/smoke.odin b/core/rexcode/wasm/tests/smoke.odin new file mode 100644 index 000000000..f81226b96 --- /dev/null +++ b/core/rexcode/wasm/tests/smoke.odin @@ -0,0 +1,86 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author +// Ginger Bill (gingerBill@github) + +package rexcode_wasm_tests + +// Spot-check ENCODING_TABLE entries against the canonical opcode bytes from +// the WebAssembly core specification (binary format, §5.4). One or two +// representatives from each opcode region, plus both 0xFC misc endpoints. +// +// Run with: odin run wasm/tests + +import "core:fmt" +import "core:os" +import wasm "../" + +@(private="file") passes := 0 +@(private="file") failures := 0 + +@(private="file") +check :: proc(name: string, m: wasm.Mnemonic, want_prefix: u8, want_opcode: u16) { + e := wasm.ENCODING_TABLE[m] + if e.prefix != want_prefix || e.opcode != want_opcode { + fmt.printfln(" [FAIL] %-22s got prefix=%02x op=%02x want prefix=%02x op=%02x", + name, e.prefix, e.opcode, want_prefix, want_opcode) + failures += 1 + return + } + fmt.printfln(" [ok] %-22s prefix=%02x op=%02x", name, e.prefix, e.opcode) + passes += 1 +} + +main :: proc() { + fmt.println("== wasm encoding-table spot checks ==") + + // control + check("unreachable", .UNREACHABLE, 0x00, 0x00) + check("block", .BLOCK, 0x00, 0x02) + check("br_table", .BR_TABLE, 0x00, 0x0E) + check("call", .CALL, 0x00, 0x10) + check("call_indirect", .CALL_INDIRECT, 0x00, 0x11) + + // parametric / variable + check("drop", .DROP, 0x00, 0x1A) + check("local.get", .LOCAL_GET, 0x00, 0x20) + check("global.set", .GLOBAL_SET, 0x00, 0x24) + + // memory + check("i32.load", .I32_LOAD, 0x00, 0x28) + check("i64.store32", .I64_STORE32, 0x00, 0x3E) + check("memory.size", .MEMORY_SIZE, 0x00, 0x3F) + check("memory.grow", .MEMORY_GROW, 0x00, 0x40) + + // numeric + check("i32.const", .I32_CONST, 0x00, 0x41) + check("f64.const", .F64_CONST, 0x00, 0x44) + check("i32.add", .I32_ADD, 0x00, 0x6A) + check("i64.mul", .I64_MUL, 0x00, 0x7E) + check("f32.add", .F32_ADD, 0x00, 0x92) + check("f64.sqrt", .F64_SQRT, 0x00, 0x9F) + + // conversions / sign-extension / reftypes + check("i32.wrap_i64", .I32_WRAP_I64, 0x00, 0xA7) + check("i32.extend8_s", .I32_EXTEND8_S, 0x00, 0xC0) + check("ref.null", .REF_NULL, 0x00, 0xD0) + check("ref.func", .REF_FUNC, 0x00, 0xD2) + + // 0xFC misc group endpoints + check("i32.trunc_sat_f32_s", .I32_TRUNC_SAT_F32_S, 0xFC, 0) + check("memory.init", .MEMORY_INIT, 0xFC, 8) + check("table.fill", .TABLE_FILL, 0xFC, 17) + + // 0xFD SIMD group + check("v128.load", .V128_LOAD, 0xFD, 0x00) + check("v128.const", .V128_CONST, 0xFD, 0x0C) + check("i8x16.shuffle", .I8X16_SHUFFLE, 0xFD, 0x0D) + check("i32x4.add", .I32X4_ADD, 0xFD, 0xAE) + check("simd hi (relaxed)", .I32X4_RELAXED_DOT_I8X16_I7X16_ADD_S, 0xFD, 0x113) + + // 0xFE threads / atomics group + check("memory.atomic.notify", .MEMORY_ATOMIC_NOTIFY, 0xFE, 0x00) + check("atomic.fence", .ATOMIC_FENCE, 0xFE, 0x03) + check("i32.atomic.load", .I32_ATOMIC_LOAD, 0xFE, 0x10) + + fmt.printfln("\n%d passed, %d failed", passes, failures) + if failures > 0 { os.exit(1) } +} diff --git a/core/rexcode/wasm/tools/dump_verify_input.odin b/core/rexcode/wasm/tools/dump_verify_input.odin new file mode 100644 index 000000000..f835bb10b --- /dev/null +++ b/core/rexcode/wasm/tools/dump_verify_input.odin @@ -0,0 +1,111 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package main + +// ============================================================================= +// WebAssembly verification manifest dumper +// ============================================================================= +// +// Encodes one representative instruction per mnemonic (synthesising operands +// that fit the entry's immediate layout) and writes: +// +// /tmp/rexcode_wasm_input.hex -- comma-separated LE hex bytes, one row each +// /tmp/rexcode_wasm_meta.txt -- "\t\t\t" +// +// The canonical external oracle for cross-checking these bytes is wabt's +// `wasm-objdump` / `wasm2wat`, or LLVM's `llvm-mc -triple=wasm32`. Feed the +// hex rows through the disassembler and diff its mnemonics against the meta +// file. +// +// Run: cd wasm && odin run tools/dump_verify_input.odin -file + +import "core:fmt" +import "core:os" +import "core:strings" + +import w "../" + +main :: proc() { + fmt.println("Dumping WASM verification manifest...") + + hex_buf, meta_buf: strings.Builder + strings.builder_init(&hex_buf) + strings.builder_init(&meta_buf) + defer strings.builder_destroy(&hex_buf) + defer strings.builder_destroy(&meta_buf) + + code: [32]u8 + count := 0 + + for mn in w.Mnemonic { + if mn == .INVALID { continue } + form := w.ENCODING_TABLE[mn] + + inst := synth(mn, form) + one := []w.Instruction{inst} + + relocs: [dynamic]w.Relocation + errors: [dynamic]w.Error + defer delete(relocs) + defer delete(errors) + + n, ok := w.encode(one, nil, code[:], &relocs, &errors) + if !ok { continue } + + for i in 0.. 0 { strings.write_byte(&hex_buf, ',') } + fmt.sbprintf(&hex_buf, "0x%02x", code[i]) + } + strings.write_byte(&hex_buf, '\n') + + fmt.sbprintf(&meta_buf, "%v\t0x%02x\t0x%02x\t%d\n", mn, form.prefix, form.opcode, n) + count += 1 + } + + _ = os.write_entire_file("/tmp/rexcode_wasm_input.hex", hex_buf.buf[:]) + _ = os.write_entire_file("/tmp/rexcode_wasm_meta.txt", meta_buf.buf[:]) + + fmt.printf("Wrote %d entries.\n", count) +} + +// Build a minimal valid instruction for `mn` whose operands satisfy the +// immediate layout in `form`. +synth :: proc(mn: w.Mnemonic, form: w.Encoding) -> w.Instruction { + if mn == .BR_TABLE { + @(static) tbl := [1]u32{0} + return w.inst_br_table(tbl[:], 0) + } + + inst := w.Instruction{mnemonic = mn} + slot := 0 + for k in form.imm { + switch k { + case .NONE, .ZERO_BYTE: + // no operand + case .BLOCKTYPE: + inst.ops[slot] = w.op_blocktype(.EMPTY); slot += 1 + case .I32: + inst.ops[slot] = w.op_i32(1); slot += 1 + case .I64: + inst.ops[slot] = w.op_i64(1); slot += 1 + case .F32: + inst.ops[slot] = w.op_f32(1); slot += 1 + case .F64: + inst.ops[slot] = w.op_f64(1); slot += 1 + case .IDX: + inst.ops[slot] = w.op_func(0); slot += 1 + case .MEMARG: + inst.ops[slot] = w.op_memarg(0, 0); slot += 1 + case .REFTYPE: + inst.ops[slot] = w.op_reftype(.FUNCREF); slot += 1 + case .LANE: + inst.ops[slot] = w.op_lane(0); slot += 1 + case .LANES16: + // 16-byte value lives in inst.bytes (left zero), no operand + case .BR_TABLE: + // handled above + } + } + inst.operand_count = u8(slot) + return inst +} From eab637f2491ceb5fa2cb42155006f4b8998a1b9c Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 16 Jun 2026 14:21:09 +0100 Subject: [PATCH 16/27] Improve formatting --- core/rexcode/wasm/decoder.odin | 4 +-- core/rexcode/wasm/encoding_types.odin | 20 ++++++++--- core/rexcode/wasm/operands.odin | 24 +++++-------- core/rexcode/wasm/printer.odin | 36 +++++++------------ core/rexcode/wasm/tests/pipeline_smoke.odin | 8 +---- .../rexcode/wasm/tools/dump_verify_input.odin | 36 +++++++------------ 6 files changed, 52 insertions(+), 76 deletions(-) diff --git a/core/rexcode/wasm/decoder.odin b/core/rexcode/wasm/decoder.odin index d7ca165a4..ee98bf6e6 100644 --- a/core/rexcode/wasm/decoder.odin +++ b/core/rexcode/wasm/decoder.odin @@ -185,9 +185,9 @@ decode_one :: proc( case .BR_TABLE: count := read_uleb(data, &off) or_return targets := make([]u32, int(count), targets_allocator) - for i in 0.. u32 { b := u8(v & 0x7F) v >>= 7 n += 1 - if (v == 0 && (b & 0x40) == 0) || (v == -1 && (b & 0x40) != 0) { break } + if (v == 0 && (b & 0x40) == 0) || (v == -1 && (b & 0x40) != 0) { + break + } } return n } @@ -138,7 +144,9 @@ read_uleb :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (val b := data[offset^] offset^ += 1 value |= u64(b & 0x7F) << shift - if b & 0x80 == 0 { return value, true } + if b & 0x80 == 0 { + return value, true + } shift += 7 } return 0, false @@ -153,7 +161,9 @@ read_sleb :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (val offset^ += 1 value |= i64(b & 0x7F) << shift shift += 7 - if b & 0x80 == 0 { break } + if b & 0x80 == 0 { + break + } } if shift < 64 && (b & 0x40) != 0 { value |= -(i64(1) << shift) diff --git a/core/rexcode/wasm/operands.odin b/core/rexcode/wasm/operands.odin index 90215b0ad..a1ea49db1 100644 --- a/core/rexcode/wasm/operands.odin +++ b/core/rexcode/wasm/operands.odin @@ -32,9 +32,8 @@ package rexcode_wasm Operand_Kind :: enum u8 { NONE, - REGISTER, // vestigial -- WASM is register-less (never produced) IMMEDIATE, // i32/i64/f32/f64 constant (floats stored as raw bits) - INDEX, // LEB128 unsigned index into one of the index spaces + INDEX, // LEB128 unsigned index into one of the index spaces MEMARG, // load/store alignment + offset pair BLOCK_TYPE, // block / loop / if signature } @@ -98,11 +97,6 @@ Operand :: struct #packed { // Generic constructors (contract surface) // ----------------------------------------------------------------------------- -@(require_results) -op_reg :: #force_inline proc "contextless" (r: Register) -> Operand { - return Operand{reg = r, kind = .REGISTER} -} - @(require_results) op_imm :: #force_inline proc "contextless" (v: i64, size: u8) -> Operand { return Operand{immediate = v, kind = .IMMEDIATE, size = size} @@ -171,14 +165,14 @@ op_index :: #force_inline proc "contextless" (kind: Index_Kind, value: u32) -> O return Operand{index = value, kind = .INDEX, idx_kind = kind} } -@(require_results) op_local :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.LOCAL, n) } -@(require_results) op_global :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.GLOBAL, n) } -@(require_results) op_func :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.FUNC, n) } -@(require_results) op_type :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.TYPE, n) } -@(require_results) op_table :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.TABLE, n) } -@(require_results) op_memory :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.MEMORY, n) } -@(require_results) op_data :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.DATA, n) } -@(require_results) op_elem :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.ELEM, n) } +@(require_results) op_local :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.LOCAL, n) } +@(require_results) op_global :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.GLOBAL, n) } +@(require_results) op_func :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.FUNC, n) } +@(require_results) op_type :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.TYPE, n) } +@(require_results) op_table :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.TABLE, n) } +@(require_results) op_memory :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.MEMORY, n) } +@(require_results) op_data :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.DATA, n) } +@(require_results) op_elem :: #force_inline proc "contextless" (n: u32) -> Operand { return op_index(.ELEM, n) } // Branch label depth (number of enclosing blocks to break out of). @(require_results) op_labelidx :: #force_inline proc "contextless" (depth: u32) -> Operand { return op_index(.LABEL, depth) } diff --git a/core/rexcode/wasm/printer.odin b/core/rexcode/wasm/printer.odin index cf7b5f176..a6e382b2c 100644 --- a/core/rexcode/wasm/printer.odin +++ b/core/rexcode/wasm/printer.odin @@ -47,13 +47,6 @@ mnemonic_to_string :: proc(m: Mnemonic, lowercase: bool = true, allocator := con return strings.to_string(sb) } -// Vestigial -- WASM is register-less; provided for contract parity only. -register_name :: proc(r: Register, lowercase: bool = true, allocator := context.temp_allocator) -> string { - _ = r - _ = lowercase - return "" -} - // ============================================================================= // Core sbprint // ============================================================================= @@ -73,13 +66,8 @@ sbprint :: proc( opts = &defaults } - running: u32 = 0 - for i in 0.. 0 { + case: for slot in 0.."); return } if uppercase { for i in 0..= 'a' && c <= 'z' { strings.write_byte(sb, c - 32) } else { strings.write_byte(sb, c) } + c := name[i] // to force ASCII + if 'a' <= c && c <= 'z' { + strings.write_byte(sb, c - 32) + } else { + strings.write_byte(sb, c) + } } } else { strings.write_string(sb, name) @@ -283,9 +276,6 @@ write_operand :: proc( switch op.kind { case .NONE: - case .REGISTER: - strings.write_string(sb, "") // vestigial - case .IMMEDIATE: if mnemonic == .REF_NULL { write_heap_type(sb, u8(op.immediate)) diff --git a/core/rexcode/wasm/tests/pipeline_smoke.odin b/core/rexcode/wasm/tests/pipeline_smoke.odin index 3333bfef3..ee68a9355 100644 --- a/core/rexcode/wasm/tests/pipeline_smoke.odin +++ b/core/rexcode/wasm/tests/pipeline_smoke.odin @@ -33,13 +33,7 @@ ok :: proc(name: string, cond: bool) { @(private="file") eq_bytes :: proc(name: string, got, want: []u8) { - same := len(got) == len(want) - if same { - for i in 0.. 0 { strings.write_byte(&hex_buf, ',') } @@ -82,28 +81,17 @@ synth :: proc(mn: w.Mnemonic, form: w.Encoding) -> w.Instruction { switch k { case .NONE, .ZERO_BYTE: // no operand - case .BLOCKTYPE: - inst.ops[slot] = w.op_blocktype(.EMPTY); slot += 1 - case .I32: - inst.ops[slot] = w.op_i32(1); slot += 1 - case .I64: - inst.ops[slot] = w.op_i64(1); slot += 1 - case .F32: - inst.ops[slot] = w.op_f32(1); slot += 1 - case .F64: - inst.ops[slot] = w.op_f64(1); slot += 1 - case .IDX: - inst.ops[slot] = w.op_func(0); slot += 1 - case .MEMARG: - inst.ops[slot] = w.op_memarg(0, 0); slot += 1 - case .REFTYPE: - inst.ops[slot] = w.op_reftype(.FUNCREF); slot += 1 - case .LANE: - inst.ops[slot] = w.op_lane(0); slot += 1 - case .LANES16: - // 16-byte value lives in inst.bytes (left zero), no operand - case .BR_TABLE: - // handled above + case .BLOCKTYPE: inst.ops[slot] = w.op_blocktype(.EMPTY); slot += 1 + case .I32: inst.ops[slot] = w.op_i32(1); slot += 1 + case .I64: inst.ops[slot] = w.op_i64(1); slot += 1 + case .F32: inst.ops[slot] = w.op_f32(1); slot += 1 + case .F64: inst.ops[slot] = w.op_f64(1); slot += 1 + case .IDX: inst.ops[slot] = w.op_func(0); slot += 1 + case .MEMARG: inst.ops[slot] = w.op_memarg(0, 0); slot += 1 + case .REFTYPE: inst.ops[slot] = w.op_reftype(.FUNCREF); slot += 1 + case .LANE: inst.ops[slot] = w.op_lane(0); slot += 1 + case .LANES16: // 16-byte value lives in inst.bytes (left zero), no operand + case .BR_TABLE: // handled above } } inst.operand_count = u8(slot) From 4029702af00913a4a994b7a1a1ea4c5e49e7d424 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 16 Jun 2026 14:24:48 +0100 Subject: [PATCH 17/27] Improve formatting of the `ENCODING_TABLE` --- core/rexcode/wasm/encoding_table.odin | 890 +++++++++++++------------- 1 file changed, 445 insertions(+), 445 deletions(-) diff --git a/core/rexcode/wasm/encoding_table.odin b/core/rexcode/wasm/encoding_table.odin index caf4e927d..674ce318b 100644 --- a/core/rexcode/wasm/encoding_table.odin +++ b/core/rexcode/wasm/encoding_table.odin @@ -23,476 +23,476 @@ ENCODING_TABLE := [Mnemonic]Encoding{ .INVALID = {}, // ------------------------------------------------------------------ control - .UNREACHABLE = Encoding{prefix = PREFIX_NONE, opcode = 0x00, flags = CTRL}, - .NOP = Encoding{prefix = PREFIX_NONE, opcode = 0x01}, - .BLOCK = Encoding{prefix = PREFIX_NONE, opcode = 0x02, imm = {.BLOCKTYPE, .NONE}, flags = CTRL}, - .LOOP = Encoding{prefix = PREFIX_NONE, opcode = 0x03, imm = {.BLOCKTYPE, .NONE}, flags = CTRL}, - .IF = Encoding{prefix = PREFIX_NONE, opcode = 0x04, imm = {.BLOCKTYPE, .NONE}, flags = CTRL}, - .ELSE = Encoding{prefix = PREFIX_NONE, opcode = 0x05, flags = CTRL}, - .END = Encoding{prefix = PREFIX_NONE, opcode = 0x0B, flags = CTRL}, - .BR = Encoding{prefix = PREFIX_NONE, opcode = 0x0C, imm = {.IDX, .NONE}, flags = CTRL}, - .BR_IF = Encoding{prefix = PREFIX_NONE, opcode = 0x0D, imm = {.IDX, .NONE}, flags = CTRL}, - .BR_TABLE = Encoding{prefix = PREFIX_NONE, opcode = 0x0E, imm = {.BR_TABLE, .NONE}, flags = CTRL}, - .RETURN = Encoding{prefix = PREFIX_NONE, opcode = 0x0F, flags = CTRL}, - .CALL = Encoding{prefix = PREFIX_NONE, opcode = 0x10, imm = {.IDX, .NONE}, flags = CTRL}, - .CALL_INDIRECT = Encoding{prefix = PREFIX_NONE, opcode = 0x11, imm = {.IDX, .IDX}, flags = CTRL}, + .UNREACHABLE = {prefix = PREFIX_NONE, opcode = 0x00, flags = CTRL}, + .NOP = {prefix = PREFIX_NONE, opcode = 0x01}, + .BLOCK = {prefix = PREFIX_NONE, opcode = 0x02, imm = {.BLOCKTYPE, .NONE}, flags = CTRL}, + .LOOP = {prefix = PREFIX_NONE, opcode = 0x03, imm = {.BLOCKTYPE, .NONE}, flags = CTRL}, + .IF = {prefix = PREFIX_NONE, opcode = 0x04, imm = {.BLOCKTYPE, .NONE}, flags = CTRL}, + .ELSE = {prefix = PREFIX_NONE, opcode = 0x05, flags = CTRL}, + .END = {prefix = PREFIX_NONE, opcode = 0x0B, flags = CTRL}, + .BR = {prefix = PREFIX_NONE, opcode = 0x0C, imm = {.IDX, .NONE}, flags = CTRL}, + .BR_IF = {prefix = PREFIX_NONE, opcode = 0x0D, imm = {.IDX, .NONE}, flags = CTRL}, + .BR_TABLE = {prefix = PREFIX_NONE, opcode = 0x0E, imm = {.BR_TABLE, .NONE}, flags = CTRL}, + .RETURN = {prefix = PREFIX_NONE, opcode = 0x0F, flags = CTRL}, + .CALL = {prefix = PREFIX_NONE, opcode = 0x10, imm = {.IDX, .NONE}, flags = CTRL}, + .CALL_INDIRECT = {prefix = PREFIX_NONE, opcode = 0x11, imm = {.IDX, .IDX}, flags = CTRL}, // -------------------------------------------------------------- parametric - .DROP = Encoding{prefix = PREFIX_NONE, opcode = 0x1A}, - .SELECT = Encoding{prefix = PREFIX_NONE, opcode = 0x1B}, + .DROP = {prefix = PREFIX_NONE, opcode = 0x1A}, + .SELECT = {prefix = PREFIX_NONE, opcode = 0x1B}, // ---------------------------------------------------------------- variable - .LOCAL_GET = Encoding{prefix = PREFIX_NONE, opcode = 0x20, imm = {.IDX, .NONE}}, - .LOCAL_SET = Encoding{prefix = PREFIX_NONE, opcode = 0x21, imm = {.IDX, .NONE}}, - .LOCAL_TEE = Encoding{prefix = PREFIX_NONE, opcode = 0x22, imm = {.IDX, .NONE}}, - .GLOBAL_GET = Encoding{prefix = PREFIX_NONE, opcode = 0x23, imm = {.IDX, .NONE}}, - .GLOBAL_SET = Encoding{prefix = PREFIX_NONE, opcode = 0x24, imm = {.IDX, .NONE}}, + .LOCAL_GET = {prefix = PREFIX_NONE, opcode = 0x20, imm = {.IDX, .NONE}}, + .LOCAL_SET = {prefix = PREFIX_NONE, opcode = 0x21, imm = {.IDX, .NONE}}, + .LOCAL_TEE = {prefix = PREFIX_NONE, opcode = 0x22, imm = {.IDX, .NONE}}, + .GLOBAL_GET = {prefix = PREFIX_NONE, opcode = 0x23, imm = {.IDX, .NONE}}, + .GLOBAL_SET = {prefix = PREFIX_NONE, opcode = 0x24, imm = {.IDX, .NONE}}, // ------------------------------------------------------------------- memory - .I32_LOAD = Encoding{prefix = PREFIX_NONE, opcode = 0x28, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_LOAD = Encoding{prefix = PREFIX_NONE, opcode = 0x29, imm = {.MEMARG, .NONE}, flags = MEM}, - .F32_LOAD = Encoding{prefix = PREFIX_NONE, opcode = 0x2A, imm = {.MEMARG, .NONE}, flags = MEM}, - .F64_LOAD = Encoding{prefix = PREFIX_NONE, opcode = 0x2B, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_LOAD8_S = Encoding{prefix = PREFIX_NONE, opcode = 0x2C, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_LOAD8_U = Encoding{prefix = PREFIX_NONE, opcode = 0x2D, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_LOAD16_S = Encoding{prefix = PREFIX_NONE, opcode = 0x2E, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_LOAD16_U = Encoding{prefix = PREFIX_NONE, opcode = 0x2F, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_LOAD8_S = Encoding{prefix = PREFIX_NONE, opcode = 0x30, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_LOAD8_U = Encoding{prefix = PREFIX_NONE, opcode = 0x31, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_LOAD16_S = Encoding{prefix = PREFIX_NONE, opcode = 0x32, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_LOAD16_U = Encoding{prefix = PREFIX_NONE, opcode = 0x33, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_LOAD32_S = Encoding{prefix = PREFIX_NONE, opcode = 0x34, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_LOAD32_U = Encoding{prefix = PREFIX_NONE, opcode = 0x35, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_STORE = Encoding{prefix = PREFIX_NONE, opcode = 0x36, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_STORE = Encoding{prefix = PREFIX_NONE, opcode = 0x37, imm = {.MEMARG, .NONE}, flags = MEM}, - .F32_STORE = Encoding{prefix = PREFIX_NONE, opcode = 0x38, imm = {.MEMARG, .NONE}, flags = MEM}, - .F64_STORE = Encoding{prefix = PREFIX_NONE, opcode = 0x39, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_STORE8 = Encoding{prefix = PREFIX_NONE, opcode = 0x3A, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_STORE16 = Encoding{prefix = PREFIX_NONE, opcode = 0x3B, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_STORE8 = Encoding{prefix = PREFIX_NONE, opcode = 0x3C, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_STORE16 = Encoding{prefix = PREFIX_NONE, opcode = 0x3D, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_STORE32 = Encoding{prefix = PREFIX_NONE, opcode = 0x3E, imm = {.MEMARG, .NONE}, flags = MEM}, - .MEMORY_SIZE = Encoding{prefix = PREFIX_NONE, opcode = 0x3F, imm = {.ZERO_BYTE, .NONE}, flags = MEM}, - .MEMORY_GROW = Encoding{prefix = PREFIX_NONE, opcode = 0x40, imm = {.ZERO_BYTE, .NONE}, flags = MEM}, + .I32_LOAD = {prefix = PREFIX_NONE, opcode = 0x28, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD = {prefix = PREFIX_NONE, opcode = 0x29, imm = {.MEMARG, .NONE}, flags = MEM}, + .F32_LOAD = {prefix = PREFIX_NONE, opcode = 0x2A, imm = {.MEMARG, .NONE}, flags = MEM}, + .F64_LOAD = {prefix = PREFIX_NONE, opcode = 0x2B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_LOAD8_S = {prefix = PREFIX_NONE, opcode = 0x2C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_LOAD8_U = {prefix = PREFIX_NONE, opcode = 0x2D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_LOAD16_S = {prefix = PREFIX_NONE, opcode = 0x2E, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_LOAD16_U = {prefix = PREFIX_NONE, opcode = 0x2F, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD8_S = {prefix = PREFIX_NONE, opcode = 0x30, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD8_U = {prefix = PREFIX_NONE, opcode = 0x31, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD16_S = {prefix = PREFIX_NONE, opcode = 0x32, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD16_U = {prefix = PREFIX_NONE, opcode = 0x33, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD32_S = {prefix = PREFIX_NONE, opcode = 0x34, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_LOAD32_U = {prefix = PREFIX_NONE, opcode = 0x35, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_STORE = {prefix = PREFIX_NONE, opcode = 0x36, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_STORE = {prefix = PREFIX_NONE, opcode = 0x37, imm = {.MEMARG, .NONE}, flags = MEM}, + .F32_STORE = {prefix = PREFIX_NONE, opcode = 0x38, imm = {.MEMARG, .NONE}, flags = MEM}, + .F64_STORE = {prefix = PREFIX_NONE, opcode = 0x39, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_STORE8 = {prefix = PREFIX_NONE, opcode = 0x3A, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_STORE16 = {prefix = PREFIX_NONE, opcode = 0x3B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_STORE8 = {prefix = PREFIX_NONE, opcode = 0x3C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_STORE16 = {prefix = PREFIX_NONE, opcode = 0x3D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_STORE32 = {prefix = PREFIX_NONE, opcode = 0x3E, imm = {.MEMARG, .NONE}, flags = MEM}, + .MEMORY_SIZE = {prefix = PREFIX_NONE, opcode = 0x3F, imm = {.ZERO_BYTE, .NONE}, flags = MEM}, + .MEMORY_GROW = {prefix = PREFIX_NONE, opcode = 0x40, imm = {.ZERO_BYTE, .NONE}, flags = MEM}, // ----------------------------------------------------------------- numeric - .I32_CONST = Encoding{prefix = PREFIX_NONE, opcode = 0x41, imm = {.I32, .NONE}}, - .I64_CONST = Encoding{prefix = PREFIX_NONE, opcode = 0x42, imm = {.I64, .NONE}}, - .F32_CONST = Encoding{prefix = PREFIX_NONE, opcode = 0x43, imm = {.F32, .NONE}}, - .F64_CONST = Encoding{prefix = PREFIX_NONE, opcode = 0x44, imm = {.F64, .NONE}}, + .I32_CONST = {prefix = PREFIX_NONE, opcode = 0x41, imm = {.I32, .NONE}}, + .I64_CONST = {prefix = PREFIX_NONE, opcode = 0x42, imm = {.I64, .NONE}}, + .F32_CONST = {prefix = PREFIX_NONE, opcode = 0x43, imm = {.F32, .NONE}}, + .F64_CONST = {prefix = PREFIX_NONE, opcode = 0x44, imm = {.F64, .NONE}}, - .I32_EQZ = Encoding{prefix = PREFIX_NONE, opcode = 0x45}, .I32_EQ = Encoding{prefix = PREFIX_NONE, opcode = 0x46}, .I32_NE = Encoding{prefix = PREFIX_NONE, opcode = 0x47}, - .I32_LT_S = Encoding{prefix = PREFIX_NONE, opcode = 0x48}, .I32_LT_U = Encoding{prefix = PREFIX_NONE, opcode = 0x49}, - .I32_GT_S = Encoding{prefix = PREFIX_NONE, opcode = 0x4A}, .I32_GT_U = Encoding{prefix = PREFIX_NONE, opcode = 0x4B}, - .I32_LE_S = Encoding{prefix = PREFIX_NONE, opcode = 0x4C}, .I32_LE_U = Encoding{prefix = PREFIX_NONE, opcode = 0x4D}, - .I32_GE_S = Encoding{prefix = PREFIX_NONE, opcode = 0x4E}, .I32_GE_U = Encoding{prefix = PREFIX_NONE, opcode = 0x4F}, + .I32_EQZ = {prefix = PREFIX_NONE, opcode = 0x45}, .I32_EQ = {prefix = PREFIX_NONE, opcode = 0x46}, .I32_NE = {prefix = PREFIX_NONE, opcode = 0x47}, + .I32_LT_S = {prefix = PREFIX_NONE, opcode = 0x48}, .I32_LT_U = {prefix = PREFIX_NONE, opcode = 0x49}, + .I32_GT_S = {prefix = PREFIX_NONE, opcode = 0x4A}, .I32_GT_U = {prefix = PREFIX_NONE, opcode = 0x4B}, + .I32_LE_S = {prefix = PREFIX_NONE, opcode = 0x4C}, .I32_LE_U = {prefix = PREFIX_NONE, opcode = 0x4D}, + .I32_GE_S = {prefix = PREFIX_NONE, opcode = 0x4E}, .I32_GE_U = {prefix = PREFIX_NONE, opcode = 0x4F}, - .I64_EQZ = Encoding{prefix = PREFIX_NONE, opcode = 0x50}, .I64_EQ = Encoding{prefix = PREFIX_NONE, opcode = 0x51}, .I64_NE = Encoding{prefix = PREFIX_NONE, opcode = 0x52}, - .I64_LT_S = Encoding{prefix = PREFIX_NONE, opcode = 0x53}, .I64_LT_U = Encoding{prefix = PREFIX_NONE, opcode = 0x54}, - .I64_GT_S = Encoding{prefix = PREFIX_NONE, opcode = 0x55}, .I64_GT_U = Encoding{prefix = PREFIX_NONE, opcode = 0x56}, - .I64_LE_S = Encoding{prefix = PREFIX_NONE, opcode = 0x57}, .I64_LE_U = Encoding{prefix = PREFIX_NONE, opcode = 0x58}, - .I64_GE_S = Encoding{prefix = PREFIX_NONE, opcode = 0x59}, .I64_GE_U = Encoding{prefix = PREFIX_NONE, opcode = 0x5A}, + .I64_EQZ = {prefix = PREFIX_NONE, opcode = 0x50}, .I64_EQ = {prefix = PREFIX_NONE, opcode = 0x51}, .I64_NE = {prefix = PREFIX_NONE, opcode = 0x52}, + .I64_LT_S = {prefix = PREFIX_NONE, opcode = 0x53}, .I64_LT_U = {prefix = PREFIX_NONE, opcode = 0x54}, + .I64_GT_S = {prefix = PREFIX_NONE, opcode = 0x55}, .I64_GT_U = {prefix = PREFIX_NONE, opcode = 0x56}, + .I64_LE_S = {prefix = PREFIX_NONE, opcode = 0x57}, .I64_LE_U = {prefix = PREFIX_NONE, opcode = 0x58}, + .I64_GE_S = {prefix = PREFIX_NONE, opcode = 0x59}, .I64_GE_U = {prefix = PREFIX_NONE, opcode = 0x5A}, - .F32_EQ = Encoding{prefix = PREFIX_NONE, opcode = 0x5B}, .F32_NE = Encoding{prefix = PREFIX_NONE, opcode = 0x5C}, - .F32_LT = Encoding{prefix = PREFIX_NONE, opcode = 0x5D}, .F32_GT = Encoding{prefix = PREFIX_NONE, opcode = 0x5E}, - .F32_LE = Encoding{prefix = PREFIX_NONE, opcode = 0x5F}, .F32_GE = Encoding{prefix = PREFIX_NONE, opcode = 0x60}, + .F32_EQ = {prefix = PREFIX_NONE, opcode = 0x5B}, .F32_NE = {prefix = PREFIX_NONE, opcode = 0x5C}, + .F32_LT = {prefix = PREFIX_NONE, opcode = 0x5D}, .F32_GT = {prefix = PREFIX_NONE, opcode = 0x5E}, + .F32_LE = {prefix = PREFIX_NONE, opcode = 0x5F}, .F32_GE = {prefix = PREFIX_NONE, opcode = 0x60}, - .F64_EQ = Encoding{prefix = PREFIX_NONE, opcode = 0x61}, .F64_NE = Encoding{prefix = PREFIX_NONE, opcode = 0x62}, - .F64_LT = Encoding{prefix = PREFIX_NONE, opcode = 0x63}, .F64_GT = Encoding{prefix = PREFIX_NONE, opcode = 0x64}, - .F64_LE = Encoding{prefix = PREFIX_NONE, opcode = 0x65}, .F64_GE = Encoding{prefix = PREFIX_NONE, opcode = 0x66}, + .F64_EQ = {prefix = PREFIX_NONE, opcode = 0x61}, .F64_NE = {prefix = PREFIX_NONE, opcode = 0x62}, + .F64_LT = {prefix = PREFIX_NONE, opcode = 0x63}, .F64_GT = {prefix = PREFIX_NONE, opcode = 0x64}, + .F64_LE = {prefix = PREFIX_NONE, opcode = 0x65}, .F64_GE = {prefix = PREFIX_NONE, opcode = 0x66}, - .I32_CLZ = Encoding{prefix = PREFIX_NONE, opcode = 0x67}, .I32_CTZ = Encoding{prefix = PREFIX_NONE, opcode = 0x68}, .I32_POPCNT = Encoding{prefix = PREFIX_NONE, opcode = 0x69}, - .I32_ADD = Encoding{prefix = PREFIX_NONE, opcode = 0x6A}, .I32_SUB = Encoding{prefix = PREFIX_NONE, opcode = 0x6B}, .I32_MUL = Encoding{prefix = PREFIX_NONE, opcode = 0x6C}, - .I32_DIV_S = Encoding{prefix = PREFIX_NONE, opcode = 0x6D}, .I32_DIV_U = Encoding{prefix = PREFIX_NONE, opcode = 0x6E}, - .I32_REM_S = Encoding{prefix = PREFIX_NONE, opcode = 0x6F}, .I32_REM_U = Encoding{prefix = PREFIX_NONE, opcode = 0x70}, - .I32_AND = Encoding{prefix = PREFIX_NONE, opcode = 0x71}, .I32_OR = Encoding{prefix = PREFIX_NONE, opcode = 0x72}, .I32_XOR = Encoding{prefix = PREFIX_NONE, opcode = 0x73}, - .I32_SHL = Encoding{prefix = PREFIX_NONE, opcode = 0x74}, .I32_SHR_S = Encoding{prefix = PREFIX_NONE, opcode = 0x75}, .I32_SHR_U = Encoding{prefix = PREFIX_NONE, opcode = 0x76}, - .I32_ROTL = Encoding{prefix = PREFIX_NONE, opcode = 0x77}, .I32_ROTR = Encoding{prefix = PREFIX_NONE, opcode = 0x78}, + .I32_CLZ = {prefix = PREFIX_NONE, opcode = 0x67}, .I32_CTZ = {prefix = PREFIX_NONE, opcode = 0x68}, .I32_POPCNT = {prefix = PREFIX_NONE, opcode = 0x69}, + .I32_ADD = {prefix = PREFIX_NONE, opcode = 0x6A}, .I32_SUB = {prefix = PREFIX_NONE, opcode = 0x6B}, .I32_MUL = {prefix = PREFIX_NONE, opcode = 0x6C}, + .I32_DIV_S = {prefix = PREFIX_NONE, opcode = 0x6D}, .I32_DIV_U = {prefix = PREFIX_NONE, opcode = 0x6E}, + .I32_REM_S = {prefix = PREFIX_NONE, opcode = 0x6F}, .I32_REM_U = {prefix = PREFIX_NONE, opcode = 0x70}, + .I32_AND = {prefix = PREFIX_NONE, opcode = 0x71}, .I32_OR = {prefix = PREFIX_NONE, opcode = 0x72}, .I32_XOR = {prefix = PREFIX_NONE, opcode = 0x73}, + .I32_SHL = {prefix = PREFIX_NONE, opcode = 0x74}, .I32_SHR_S = {prefix = PREFIX_NONE, opcode = 0x75}, .I32_SHR_U = {prefix = PREFIX_NONE, opcode = 0x76}, + .I32_ROTL = {prefix = PREFIX_NONE, opcode = 0x77}, .I32_ROTR = {prefix = PREFIX_NONE, opcode = 0x78}, - .I64_CLZ = Encoding{prefix = PREFIX_NONE, opcode = 0x79}, .I64_CTZ = Encoding{prefix = PREFIX_NONE, opcode = 0x7A}, .I64_POPCNT = Encoding{prefix = PREFIX_NONE, opcode = 0x7B}, - .I64_ADD = Encoding{prefix = PREFIX_NONE, opcode = 0x7C}, .I64_SUB = Encoding{prefix = PREFIX_NONE, opcode = 0x7D}, .I64_MUL = Encoding{prefix = PREFIX_NONE, opcode = 0x7E}, - .I64_DIV_S = Encoding{prefix = PREFIX_NONE, opcode = 0x7F}, .I64_DIV_U = Encoding{prefix = PREFIX_NONE, opcode = 0x80}, - .I64_REM_S = Encoding{prefix = PREFIX_NONE, opcode = 0x81}, .I64_REM_U = Encoding{prefix = PREFIX_NONE, opcode = 0x82}, - .I64_AND = Encoding{prefix = PREFIX_NONE, opcode = 0x83}, .I64_OR = Encoding{prefix = PREFIX_NONE, opcode = 0x84}, .I64_XOR = Encoding{prefix = PREFIX_NONE, opcode = 0x85}, - .I64_SHL = Encoding{prefix = PREFIX_NONE, opcode = 0x86}, .I64_SHR_S = Encoding{prefix = PREFIX_NONE, opcode = 0x87}, .I64_SHR_U = Encoding{prefix = PREFIX_NONE, opcode = 0x88}, - .I64_ROTL = Encoding{prefix = PREFIX_NONE, opcode = 0x89}, .I64_ROTR = Encoding{prefix = PREFIX_NONE, opcode = 0x8A}, + .I64_CLZ = {prefix = PREFIX_NONE, opcode = 0x79}, .I64_CTZ = {prefix = PREFIX_NONE, opcode = 0x7A}, .I64_POPCNT = {prefix = PREFIX_NONE, opcode = 0x7B}, + .I64_ADD = {prefix = PREFIX_NONE, opcode = 0x7C}, .I64_SUB = {prefix = PREFIX_NONE, opcode = 0x7D}, .I64_MUL = {prefix = PREFIX_NONE, opcode = 0x7E}, + .I64_DIV_S = {prefix = PREFIX_NONE, opcode = 0x7F}, .I64_DIV_U = {prefix = PREFIX_NONE, opcode = 0x80}, + .I64_REM_S = {prefix = PREFIX_NONE, opcode = 0x81}, .I64_REM_U = {prefix = PREFIX_NONE, opcode = 0x82}, + .I64_AND = {prefix = PREFIX_NONE, opcode = 0x83}, .I64_OR = {prefix = PREFIX_NONE, opcode = 0x84}, .I64_XOR = {prefix = PREFIX_NONE, opcode = 0x85}, + .I64_SHL = {prefix = PREFIX_NONE, opcode = 0x86}, .I64_SHR_S = {prefix = PREFIX_NONE, opcode = 0x87}, .I64_SHR_U = {prefix = PREFIX_NONE, opcode = 0x88}, + .I64_ROTL = {prefix = PREFIX_NONE, opcode = 0x89}, .I64_ROTR = {prefix = PREFIX_NONE, opcode = 0x8A}, - .F32_ABS = Encoding{prefix = PREFIX_NONE, opcode = 0x8B}, .F32_NEG = Encoding{prefix = PREFIX_NONE, opcode = 0x8C}, .F32_CEIL = Encoding{prefix = PREFIX_NONE, opcode = 0x8D}, - .F32_FLOOR = Encoding{prefix = PREFIX_NONE, opcode = 0x8E}, .F32_TRUNC = Encoding{prefix = PREFIX_NONE, opcode = 0x8F}, .F32_NEAREST = Encoding{prefix = PREFIX_NONE, opcode = 0x90}, - .F32_SQRT = Encoding{prefix = PREFIX_NONE, opcode = 0x91}, .F32_ADD = Encoding{prefix = PREFIX_NONE, opcode = 0x92}, .F32_SUB = Encoding{prefix = PREFIX_NONE, opcode = 0x93}, - .F32_MUL = Encoding{prefix = PREFIX_NONE, opcode = 0x94}, .F32_DIV = Encoding{prefix = PREFIX_NONE, opcode = 0x95}, .F32_MIN = Encoding{prefix = PREFIX_NONE, opcode = 0x96}, - .F32_MAX = Encoding{prefix = PREFIX_NONE, opcode = 0x97}, .F32_COPYSIGN = Encoding{prefix = PREFIX_NONE, opcode = 0x98}, + .F32_ABS = {prefix = PREFIX_NONE, opcode = 0x8B}, .F32_NEG = {prefix = PREFIX_NONE, opcode = 0x8C}, .F32_CEIL = {prefix = PREFIX_NONE, opcode = 0x8D}, + .F32_FLOOR = {prefix = PREFIX_NONE, opcode = 0x8E}, .F32_TRUNC = {prefix = PREFIX_NONE, opcode = 0x8F}, .F32_NEAREST = {prefix = PREFIX_NONE, opcode = 0x90}, + .F32_SQRT = {prefix = PREFIX_NONE, opcode = 0x91}, .F32_ADD = {prefix = PREFIX_NONE, opcode = 0x92}, .F32_SUB = {prefix = PREFIX_NONE, opcode = 0x93}, + .F32_MUL = {prefix = PREFIX_NONE, opcode = 0x94}, .F32_DIV = {prefix = PREFIX_NONE, opcode = 0x95}, .F32_MIN = {prefix = PREFIX_NONE, opcode = 0x96}, + .F32_MAX = {prefix = PREFIX_NONE, opcode = 0x97}, .F32_COPYSIGN = {prefix = PREFIX_NONE, opcode = 0x98}, - .F64_ABS = Encoding{prefix = PREFIX_NONE, opcode = 0x99}, .F64_NEG = Encoding{prefix = PREFIX_NONE, opcode = 0x9A}, .F64_CEIL = Encoding{prefix = PREFIX_NONE, opcode = 0x9B}, - .F64_FLOOR = Encoding{prefix = PREFIX_NONE, opcode = 0x9C}, .F64_TRUNC = Encoding{prefix = PREFIX_NONE, opcode = 0x9D}, .F64_NEAREST = Encoding{prefix = PREFIX_NONE, opcode = 0x9E}, - .F64_SQRT = Encoding{prefix = PREFIX_NONE, opcode = 0x9F}, .F64_ADD = Encoding{prefix = PREFIX_NONE, opcode = 0xA0}, .F64_SUB = Encoding{prefix = PREFIX_NONE, opcode = 0xA1}, - .F64_MUL = Encoding{prefix = PREFIX_NONE, opcode = 0xA2}, .F64_DIV = Encoding{prefix = PREFIX_NONE, opcode = 0xA3}, .F64_MIN = Encoding{prefix = PREFIX_NONE, opcode = 0xA4}, - .F64_MAX = Encoding{prefix = PREFIX_NONE, opcode = 0xA5}, .F64_COPYSIGN = Encoding{prefix = PREFIX_NONE, opcode = 0xA6}, + .F64_ABS = {prefix = PREFIX_NONE, opcode = 0x99}, .F64_NEG = {prefix = PREFIX_NONE, opcode = 0x9A}, .F64_CEIL = {prefix = PREFIX_NONE, opcode = 0x9B}, + .F64_FLOOR = {prefix = PREFIX_NONE, opcode = 0x9C}, .F64_TRUNC = {prefix = PREFIX_NONE, opcode = 0x9D}, .F64_NEAREST = {prefix = PREFIX_NONE, opcode = 0x9E}, + .F64_SQRT = {prefix = PREFIX_NONE, opcode = 0x9F}, .F64_ADD = {prefix = PREFIX_NONE, opcode = 0xA0}, .F64_SUB = {prefix = PREFIX_NONE, opcode = 0xA1}, + .F64_MUL = {prefix = PREFIX_NONE, opcode = 0xA2}, .F64_DIV = {prefix = PREFIX_NONE, opcode = 0xA3}, .F64_MIN = {prefix = PREFIX_NONE, opcode = 0xA4}, + .F64_MAX = {prefix = PREFIX_NONE, opcode = 0xA5}, .F64_COPYSIGN = {prefix = PREFIX_NONE, opcode = 0xA6}, - .I32_WRAP_I64 = Encoding{prefix = PREFIX_NONE, opcode = 0xA7}, - .I32_TRUNC_F32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xA8}, .I32_TRUNC_F32_U = Encoding{prefix = PREFIX_NONE, opcode = 0xA9}, - .I32_TRUNC_F64_S = Encoding{prefix = PREFIX_NONE, opcode = 0xAA}, .I32_TRUNC_F64_U = Encoding{prefix = PREFIX_NONE, opcode = 0xAB}, - .I64_EXTEND_I32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xAC}, .I64_EXTEND_I32_U = Encoding{prefix = PREFIX_NONE, opcode = 0xAD}, - .I64_TRUNC_F32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xAE}, .I64_TRUNC_F32_U = Encoding{prefix = PREFIX_NONE, opcode = 0xAF}, - .I64_TRUNC_F64_S = Encoding{prefix = PREFIX_NONE, opcode = 0xB0}, .I64_TRUNC_F64_U = Encoding{prefix = PREFIX_NONE, opcode = 0xB1}, - .F32_CONVERT_I32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xB2}, .F32_CONVERT_I32_U = Encoding{prefix = PREFIX_NONE, opcode = 0xB3}, - .F32_CONVERT_I64_S = Encoding{prefix = PREFIX_NONE, opcode = 0xB4}, .F32_CONVERT_I64_U = Encoding{prefix = PREFIX_NONE, opcode = 0xB5}, - .F32_DEMOTE_F64 = Encoding{prefix = PREFIX_NONE, opcode = 0xB6}, - .F64_CONVERT_I32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xB7}, .F64_CONVERT_I32_U = Encoding{prefix = PREFIX_NONE, opcode = 0xB8}, - .F64_CONVERT_I64_S = Encoding{prefix = PREFIX_NONE, opcode = 0xB9}, .F64_CONVERT_I64_U = Encoding{prefix = PREFIX_NONE, opcode = 0xBA}, - .F64_PROMOTE_F32 = Encoding{prefix = PREFIX_NONE, opcode = 0xBB}, - .I32_REINTERPRET_F32 = Encoding{prefix = PREFIX_NONE, opcode = 0xBC}, .I64_REINTERPRET_F64 = Encoding{prefix = PREFIX_NONE, opcode = 0xBD}, - .F32_REINTERPRET_I32 = Encoding{prefix = PREFIX_NONE, opcode = 0xBE}, .F64_REINTERPRET_I64 = Encoding{prefix = PREFIX_NONE, opcode = 0xBF}, + .I32_WRAP_I64 = {prefix = PREFIX_NONE, opcode = 0xA7}, + .I32_TRUNC_F32_S = {prefix = PREFIX_NONE, opcode = 0xA8}, .I32_TRUNC_F32_U = {prefix = PREFIX_NONE, opcode = 0xA9}, + .I32_TRUNC_F64_S = {prefix = PREFIX_NONE, opcode = 0xAA}, .I32_TRUNC_F64_U = {prefix = PREFIX_NONE, opcode = 0xAB}, + .I64_EXTEND_I32_S = {prefix = PREFIX_NONE, opcode = 0xAC}, .I64_EXTEND_I32_U = {prefix = PREFIX_NONE, opcode = 0xAD}, + .I64_TRUNC_F32_S = {prefix = PREFIX_NONE, opcode = 0xAE}, .I64_TRUNC_F32_U = {prefix = PREFIX_NONE, opcode = 0xAF}, + .I64_TRUNC_F64_S = {prefix = PREFIX_NONE, opcode = 0xB0}, .I64_TRUNC_F64_U = {prefix = PREFIX_NONE, opcode = 0xB1}, + .F32_CONVERT_I32_S = {prefix = PREFIX_NONE, opcode = 0xB2}, .F32_CONVERT_I32_U = {prefix = PREFIX_NONE, opcode = 0xB3}, + .F32_CONVERT_I64_S = {prefix = PREFIX_NONE, opcode = 0xB4}, .F32_CONVERT_I64_U = {prefix = PREFIX_NONE, opcode = 0xB5}, + .F32_DEMOTE_F64 = {prefix = PREFIX_NONE, opcode = 0xB6}, + .F64_CONVERT_I32_S = {prefix = PREFIX_NONE, opcode = 0xB7}, .F64_CONVERT_I32_U = {prefix = PREFIX_NONE, opcode = 0xB8}, + .F64_CONVERT_I64_S = {prefix = PREFIX_NONE, opcode = 0xB9}, .F64_CONVERT_I64_U = {prefix = PREFIX_NONE, opcode = 0xBA}, + .F64_PROMOTE_F32 = {prefix = PREFIX_NONE, opcode = 0xBB}, + .I32_REINTERPRET_F32 = {prefix = PREFIX_NONE, opcode = 0xBC}, .I64_REINTERPRET_F64 = {prefix = PREFIX_NONE, opcode = 0xBD}, + .F32_REINTERPRET_I32 = {prefix = PREFIX_NONE, opcode = 0xBE}, .F64_REINTERPRET_I64 = {prefix = PREFIX_NONE, opcode = 0xBF}, - .I32_EXTEND8_S = Encoding{prefix = PREFIX_NONE, opcode = 0xC0}, .I32_EXTEND16_S = Encoding{prefix = PREFIX_NONE, opcode = 0xC1}, - .I64_EXTEND8_S = Encoding{prefix = PREFIX_NONE, opcode = 0xC2}, .I64_EXTEND16_S = Encoding{prefix = PREFIX_NONE, opcode = 0xC3}, .I64_EXTEND32_S = Encoding{prefix = PREFIX_NONE, opcode = 0xC4}, + .I32_EXTEND8_S = {prefix = PREFIX_NONE, opcode = 0xC0}, .I32_EXTEND16_S = {prefix = PREFIX_NONE, opcode = 0xC1}, + .I64_EXTEND8_S = {prefix = PREFIX_NONE, opcode = 0xC2}, .I64_EXTEND16_S = {prefix = PREFIX_NONE, opcode = 0xC3}, .I64_EXTEND32_S = {prefix = PREFIX_NONE, opcode = 0xC4}, - .REF_NULL = Encoding{prefix = PREFIX_NONE, opcode = 0xD0, imm = {.REFTYPE, .NONE}}, - .REF_IS_NULL = Encoding{prefix = PREFIX_NONE, opcode = 0xD1}, - .REF_FUNC = Encoding{prefix = PREFIX_NONE, opcode = 0xD2, imm = {.IDX, .NONE}}, + .REF_NULL = {prefix = PREFIX_NONE, opcode = 0xD0, imm = {.REFTYPE, .NONE}}, + .REF_IS_NULL = {prefix = PREFIX_NONE, opcode = 0xD1}, + .REF_FUNC = {prefix = PREFIX_NONE, opcode = 0xD2, imm = {.IDX, .NONE}}, // ------------------------------------------------------- 0xFC misc prefix - .I32_TRUNC_SAT_F32_S = Encoding{prefix = PREFIX_MISC, opcode = 0}, .I32_TRUNC_SAT_F32_U = Encoding{prefix = PREFIX_MISC, opcode = 1}, - .I32_TRUNC_SAT_F64_S = Encoding{prefix = PREFIX_MISC, opcode = 2}, .I32_TRUNC_SAT_F64_U = Encoding{prefix = PREFIX_MISC, opcode = 3}, - .I64_TRUNC_SAT_F32_S = Encoding{prefix = PREFIX_MISC, opcode = 4}, .I64_TRUNC_SAT_F32_U = Encoding{prefix = PREFIX_MISC, opcode = 5}, - .I64_TRUNC_SAT_F64_S = Encoding{prefix = PREFIX_MISC, opcode = 6}, .I64_TRUNC_SAT_F64_U = Encoding{prefix = PREFIX_MISC, opcode = 7}, - .MEMORY_INIT = Encoding{prefix = PREFIX_MISC, opcode = 8, imm = {.IDX, .ZERO_BYTE}, flags = MEM}, - .DATA_DROP = Encoding{prefix = PREFIX_MISC, opcode = 9, imm = {.IDX, .NONE}}, - .MEMORY_COPY = Encoding{prefix = PREFIX_MISC, opcode = 10, imm = {.ZERO_BYTE, .ZERO_BYTE}, flags = MEM}, - .MEMORY_FILL = Encoding{prefix = PREFIX_MISC, opcode = 11, imm = {.ZERO_BYTE, .NONE}, flags = MEM}, - .TABLE_INIT = Encoding{prefix = PREFIX_MISC, opcode = 12, imm = {.IDX, .IDX}}, - .ELEM_DROP = Encoding{prefix = PREFIX_MISC, opcode = 13, imm = {.IDX, .NONE}}, - .TABLE_COPY = Encoding{prefix = PREFIX_MISC, opcode = 14, imm = {.IDX, .IDX}}, - .TABLE_GROW = Encoding{prefix = PREFIX_MISC, opcode = 15, imm = {.IDX, .NONE}}, - .TABLE_SIZE = Encoding{prefix = PREFIX_MISC, opcode = 16, imm = {.IDX, .NONE}}, - .TABLE_FILL = Encoding{prefix = PREFIX_MISC, opcode = 17, imm = {.IDX, .NONE}}, + .I32_TRUNC_SAT_F32_S = {prefix = PREFIX_MISC, opcode = 0}, .I32_TRUNC_SAT_F32_U = {prefix = PREFIX_MISC, opcode = 1}, + .I32_TRUNC_SAT_F64_S = {prefix = PREFIX_MISC, opcode = 2}, .I32_TRUNC_SAT_F64_U = {prefix = PREFIX_MISC, opcode = 3}, + .I64_TRUNC_SAT_F32_S = {prefix = PREFIX_MISC, opcode = 4}, .I64_TRUNC_SAT_F32_U = {prefix = PREFIX_MISC, opcode = 5}, + .I64_TRUNC_SAT_F64_S = {prefix = PREFIX_MISC, opcode = 6}, .I64_TRUNC_SAT_F64_U = {prefix = PREFIX_MISC, opcode = 7}, + .MEMORY_INIT = {prefix = PREFIX_MISC, opcode = 8, imm = {.IDX, .ZERO_BYTE}, flags = MEM}, + .DATA_DROP = {prefix = PREFIX_MISC, opcode = 9, imm = {.IDX, .NONE}}, + .MEMORY_COPY = {prefix = PREFIX_MISC, opcode = 10, imm = {.ZERO_BYTE, .ZERO_BYTE}, flags = MEM}, + .MEMORY_FILL = {prefix = PREFIX_MISC, opcode = 11, imm = {.ZERO_BYTE, .NONE}, flags = MEM}, + .TABLE_INIT = {prefix = PREFIX_MISC, opcode = 12, imm = {.IDX, .IDX}}, + .ELEM_DROP = {prefix = PREFIX_MISC, opcode = 13, imm = {.IDX, .NONE}}, + .TABLE_COPY = {prefix = PREFIX_MISC, opcode = 14, imm = {.IDX, .IDX}}, + .TABLE_GROW = {prefix = PREFIX_MISC, opcode = 15, imm = {.IDX, .NONE}}, + .TABLE_SIZE = {prefix = PREFIX_MISC, opcode = 16, imm = {.IDX, .NONE}}, + .TABLE_FILL = {prefix = PREFIX_MISC, opcode = 17, imm = {.IDX, .NONE}}, // ----------------------------------------------- 0xFD SIMD (v128) prefix - .V128_LOAD = Encoding{prefix = PREFIX_SIMD, opcode = 0x00, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_LOAD8X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x01, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_LOAD8X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x02, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_LOAD16X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x03, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_LOAD16X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x04, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_LOAD32X2_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x05, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_LOAD32X2_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x06, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_LOAD8_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x07, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_LOAD16_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x08, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_LOAD32_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x09, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_LOAD64_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x0A, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_STORE = Encoding{prefix = PREFIX_SIMD, opcode = 0x0B, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_CONST = Encoding{prefix = PREFIX_SIMD, opcode = 0x0C, imm = {.LANES16, .NONE}}, - .I8X16_SHUFFLE = Encoding{prefix = PREFIX_SIMD, opcode = 0x0D, imm = {.LANES16, .NONE}}, - .I8X16_SWIZZLE = Encoding{prefix = PREFIX_SIMD, opcode = 0x0E}, - .I8X16_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x0F}, - .I16X8_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x10}, - .I32X4_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x11}, - .I64X2_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x12}, - .F32X4_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x13}, - .F64X2_SPLAT = Encoding{prefix = PREFIX_SIMD, opcode = 0x14}, - .I8X16_EXTRACT_LANE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x15, imm = {.LANE, .NONE}}, - .I8X16_EXTRACT_LANE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x16, imm = {.LANE, .NONE}}, - .I8X16_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x17, imm = {.LANE, .NONE}}, - .I16X8_EXTRACT_LANE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x18, imm = {.LANE, .NONE}}, - .I16X8_EXTRACT_LANE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x19, imm = {.LANE, .NONE}}, - .I16X8_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1A, imm = {.LANE, .NONE}}, - .I32X4_EXTRACT_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1B, imm = {.LANE, .NONE}}, - .I32X4_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1C, imm = {.LANE, .NONE}}, - .I64X2_EXTRACT_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1D, imm = {.LANE, .NONE}}, - .I64X2_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1E, imm = {.LANE, .NONE}}, - .F32X4_EXTRACT_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x1F, imm = {.LANE, .NONE}}, - .F32X4_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x20, imm = {.LANE, .NONE}}, - .F64X2_EXTRACT_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x21, imm = {.LANE, .NONE}}, - .F64X2_REPLACE_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x22, imm = {.LANE, .NONE}}, - .I8X16_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0x23}, - .I8X16_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0x24}, - .I8X16_LT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x25}, - .I8X16_LT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x26}, - .I8X16_GT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x27}, - .I8X16_GT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x28}, - .I8X16_LE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x29}, - .I8X16_LE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x2A}, - .I8X16_GE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x2B}, - .I8X16_GE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x2C}, - .I16X8_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0x2D}, - .I16X8_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0x2E}, - .I16X8_LT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x2F}, - .I16X8_LT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x30}, - .I16X8_GT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x31}, - .I16X8_GT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x32}, - .I16X8_LE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x33}, - .I16X8_LE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x34}, - .I16X8_GE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x35}, - .I16X8_GE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x36}, - .I32X4_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0x37}, - .I32X4_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0x38}, - .I32X4_LT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x39}, - .I32X4_LT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x3A}, - .I32X4_GT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x3B}, - .I32X4_GT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x3C}, - .I32X4_LE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x3D}, - .I32X4_LE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x3E}, - .I32X4_GE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x3F}, - .I32X4_GE_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x40}, - .F32X4_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0x41}, - .F32X4_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0x42}, - .F32X4_LT = Encoding{prefix = PREFIX_SIMD, opcode = 0x43}, - .F32X4_GT = Encoding{prefix = PREFIX_SIMD, opcode = 0x44}, - .F32X4_LE = Encoding{prefix = PREFIX_SIMD, opcode = 0x45}, - .F32X4_GE = Encoding{prefix = PREFIX_SIMD, opcode = 0x46}, - .F64X2_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0x47}, - .F64X2_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0x48}, - .F64X2_LT = Encoding{prefix = PREFIX_SIMD, opcode = 0x49}, - .F64X2_GT = Encoding{prefix = PREFIX_SIMD, opcode = 0x4A}, - .F64X2_LE = Encoding{prefix = PREFIX_SIMD, opcode = 0x4B}, - .F64X2_GE = Encoding{prefix = PREFIX_SIMD, opcode = 0x4C}, - .V128_NOT = Encoding{prefix = PREFIX_SIMD, opcode = 0x4D}, - .V128_AND = Encoding{prefix = PREFIX_SIMD, opcode = 0x4E}, - .V128_ANDNOT = Encoding{prefix = PREFIX_SIMD, opcode = 0x4F}, - .V128_OR = Encoding{prefix = PREFIX_SIMD, opcode = 0x50}, - .V128_XOR = Encoding{prefix = PREFIX_SIMD, opcode = 0x51}, - .V128_BITSELECT = Encoding{prefix = PREFIX_SIMD, opcode = 0x52}, - .V128_ANY_TRUE = Encoding{prefix = PREFIX_SIMD, opcode = 0x53}, - .V128_LOAD8_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x54, imm = {.MEMARG, .LANE}, flags = MEM}, - .V128_LOAD16_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x55, imm = {.MEMARG, .LANE}, flags = MEM}, - .V128_LOAD32_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x56, imm = {.MEMARG, .LANE}, flags = MEM}, - .V128_LOAD64_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x57, imm = {.MEMARG, .LANE}, flags = MEM}, - .V128_STORE8_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x58, imm = {.MEMARG, .LANE}, flags = MEM}, - .V128_STORE16_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x59, imm = {.MEMARG, .LANE}, flags = MEM}, - .V128_STORE32_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x5A, imm = {.MEMARG, .LANE}, flags = MEM}, - .V128_STORE64_LANE = Encoding{prefix = PREFIX_SIMD, opcode = 0x5B, imm = {.MEMARG, .LANE}, flags = MEM}, - .V128_LOAD32_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0x5C, imm = {.MEMARG, .NONE}, flags = MEM}, - .V128_LOAD64_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0x5D, imm = {.MEMARG, .NONE}, flags = MEM}, - .F32X4_DEMOTE_F64X2_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0x5E}, - .F64X2_PROMOTE_LOW_F32X4 = Encoding{prefix = PREFIX_SIMD, opcode = 0x5F}, - .I8X16_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0x60}, - .I8X16_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0x61}, - .I8X16_POPCNT = Encoding{prefix = PREFIX_SIMD, opcode = 0x62}, - .I8X16_ALL_TRUE = Encoding{prefix = PREFIX_SIMD, opcode = 0x63}, - .I8X16_BITMASK = Encoding{prefix = PREFIX_SIMD, opcode = 0x64}, - .I8X16_NARROW_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x65}, - .I8X16_NARROW_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x66}, - .F32X4_CEIL = Encoding{prefix = PREFIX_SIMD, opcode = 0x67}, - .F32X4_FLOOR = Encoding{prefix = PREFIX_SIMD, opcode = 0x68}, - .F32X4_TRUNC = Encoding{prefix = PREFIX_SIMD, opcode = 0x69}, - .F32X4_NEAREST = Encoding{prefix = PREFIX_SIMD, opcode = 0x6A}, - .I8X16_SHL = Encoding{prefix = PREFIX_SIMD, opcode = 0x6B}, - .I8X16_SHR_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x6C}, - .I8X16_SHR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x6D}, - .I8X16_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x6E}, - .I8X16_ADD_SAT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x6F}, - .I8X16_ADD_SAT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x70}, - .I8X16_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0x71}, - .I8X16_SUB_SAT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x72}, - .I8X16_SUB_SAT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x73}, - .F64X2_CEIL = Encoding{prefix = PREFIX_SIMD, opcode = 0x74}, - .F64X2_FLOOR = Encoding{prefix = PREFIX_SIMD, opcode = 0x75}, - .I8X16_MIN_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x76}, - .I8X16_MIN_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x77}, - .I8X16_MAX_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x78}, - .I8X16_MAX_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x79}, - .F64X2_TRUNC = Encoding{prefix = PREFIX_SIMD, opcode = 0x7A}, - .I8X16_AVGR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x7B}, - .I16X8_EXTADD_PAIRWISE_I8X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x7C}, - .I16X8_EXTADD_PAIRWISE_I8X16_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x7D}, - .I32X4_EXTADD_PAIRWISE_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x7E}, - .I32X4_EXTADD_PAIRWISE_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x7F}, - .I16X8_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0x80}, - .I16X8_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0x81}, - .I16X8_Q15MULR_SAT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x82}, - .I16X8_ALL_TRUE = Encoding{prefix = PREFIX_SIMD, opcode = 0x83}, - .I16X8_BITMASK = Encoding{prefix = PREFIX_SIMD, opcode = 0x84}, - .I16X8_NARROW_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x85}, - .I16X8_NARROW_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x86}, - .I16X8_EXTEND_LOW_I8X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x87}, - .I16X8_EXTEND_HIGH_I8X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x88}, - .I16X8_EXTEND_LOW_I8X16_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x89}, - .I16X8_EXTEND_HIGH_I8X16_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x8A}, - .I16X8_SHL = Encoding{prefix = PREFIX_SIMD, opcode = 0x8B}, - .I16X8_SHR_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x8C}, - .I16X8_SHR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x8D}, - .I16X8_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x8E}, - .I16X8_ADD_SAT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x8F}, - .I16X8_ADD_SAT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x90}, - .I16X8_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0x91}, - .I16X8_SUB_SAT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x92}, - .I16X8_SUB_SAT_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x93}, - .F64X2_NEAREST = Encoding{prefix = PREFIX_SIMD, opcode = 0x94}, - .I16X8_MUL = Encoding{prefix = PREFIX_SIMD, opcode = 0x95}, - .I16X8_MIN_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x96}, - .I16X8_MIN_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x97}, - .I16X8_MAX_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x98}, - .I16X8_MAX_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x99}, - .I16X8_AVGR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x9B}, - .I16X8_EXTMUL_LOW_I8X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x9C}, - .I16X8_EXTMUL_HIGH_I8X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x9D}, - .I16X8_EXTMUL_LOW_I8X16_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x9E}, - .I16X8_EXTMUL_HIGH_I8X16_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x9F}, - .I32X4_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0xA0}, - .I32X4_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0xA1}, - .I32X4_ALL_TRUE = Encoding{prefix = PREFIX_SIMD, opcode = 0xA3}, - .I32X4_BITMASK = Encoding{prefix = PREFIX_SIMD, opcode = 0xA4}, - .I32X4_EXTEND_LOW_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xA7}, - .I32X4_EXTEND_HIGH_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xA8}, - .I32X4_EXTEND_LOW_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xA9}, - .I32X4_EXTEND_HIGH_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xAA}, - .I32X4_SHL = Encoding{prefix = PREFIX_SIMD, opcode = 0xAB}, - .I32X4_SHR_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xAC}, - .I32X4_SHR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xAD}, - .I32X4_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0xAE}, - .I32X4_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0xB1}, - .I32X4_MUL = Encoding{prefix = PREFIX_SIMD, opcode = 0xB5}, - .I32X4_MIN_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xB6}, - .I32X4_MIN_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xB7}, - .I32X4_MAX_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xB8}, - .I32X4_MAX_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xB9}, - .I32X4_DOT_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xBA}, - .I32X4_EXTMUL_LOW_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xBC}, - .I32X4_EXTMUL_HIGH_I16X8_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xBD}, - .I32X4_EXTMUL_LOW_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xBE}, - .I32X4_EXTMUL_HIGH_I16X8_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xBF}, - .I64X2_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0xC0}, - .I64X2_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0xC1}, - .I64X2_ALL_TRUE = Encoding{prefix = PREFIX_SIMD, opcode = 0xC3}, - .I64X2_BITMASK = Encoding{prefix = PREFIX_SIMD, opcode = 0xC4}, - .I64X2_EXTEND_LOW_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xC7}, - .I64X2_EXTEND_HIGH_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xC8}, - .I64X2_EXTEND_LOW_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xC9}, - .I64X2_EXTEND_HIGH_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xCA}, - .I64X2_SHL = Encoding{prefix = PREFIX_SIMD, opcode = 0xCB}, - .I64X2_SHR_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xCC}, - .I64X2_SHR_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xCD}, - .I64X2_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0xCE}, - .I64X2_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0xD1}, - .I64X2_MUL = Encoding{prefix = PREFIX_SIMD, opcode = 0xD5}, - .I64X2_EQ = Encoding{prefix = PREFIX_SIMD, opcode = 0xD6}, - .I64X2_NE = Encoding{prefix = PREFIX_SIMD, opcode = 0xD7}, - .I64X2_LT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xD8}, - .I64X2_GT_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xD9}, - .I64X2_LE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xDA}, - .I64X2_GE_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xDB}, - .I64X2_EXTMUL_LOW_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xDC}, - .I64X2_EXTMUL_HIGH_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xDD}, - .I64X2_EXTMUL_LOW_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xDE}, - .I64X2_EXTMUL_HIGH_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xDF}, - .F32X4_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0xE0}, - .F32X4_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0xE1}, - .F32X4_SQRT = Encoding{prefix = PREFIX_SIMD, opcode = 0xE3}, - .F32X4_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0xE4}, - .F32X4_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0xE5}, - .F32X4_MUL = Encoding{prefix = PREFIX_SIMD, opcode = 0xE6}, - .F32X4_DIV = Encoding{prefix = PREFIX_SIMD, opcode = 0xE7}, - .F32X4_MIN = Encoding{prefix = PREFIX_SIMD, opcode = 0xE8}, - .F32X4_MAX = Encoding{prefix = PREFIX_SIMD, opcode = 0xE9}, - .F32X4_PMIN = Encoding{prefix = PREFIX_SIMD, opcode = 0xEA}, - .F32X4_PMAX = Encoding{prefix = PREFIX_SIMD, opcode = 0xEB}, - .F64X2_ABS = Encoding{prefix = PREFIX_SIMD, opcode = 0xEC}, - .F64X2_NEG = Encoding{prefix = PREFIX_SIMD, opcode = 0xED}, - .F64X2_SQRT = Encoding{prefix = PREFIX_SIMD, opcode = 0xEF}, - .F64X2_ADD = Encoding{prefix = PREFIX_SIMD, opcode = 0xF0}, - .F64X2_SUB = Encoding{prefix = PREFIX_SIMD, opcode = 0xF1}, - .F64X2_MUL = Encoding{prefix = PREFIX_SIMD, opcode = 0xF2}, - .F64X2_DIV = Encoding{prefix = PREFIX_SIMD, opcode = 0xF3}, - .F64X2_MIN = Encoding{prefix = PREFIX_SIMD, opcode = 0xF4}, - .F64X2_MAX = Encoding{prefix = PREFIX_SIMD, opcode = 0xF5}, - .F64X2_PMIN = Encoding{prefix = PREFIX_SIMD, opcode = 0xF6}, - .F64X2_PMAX = Encoding{prefix = PREFIX_SIMD, opcode = 0xF7}, - .I32X4_TRUNC_SAT_F32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xF8}, - .I32X4_TRUNC_SAT_F32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xF9}, - .F32X4_CONVERT_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xFA}, - .F32X4_CONVERT_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xFB}, - .I32X4_TRUNC_SAT_F64X2_S_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0xFC}, - .I32X4_TRUNC_SAT_F64X2_U_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0xFD}, - .F64X2_CONVERT_LOW_I32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0xFE}, - .F64X2_CONVERT_LOW_I32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0xFF}, - .I8X16_RELAXED_SWIZZLE = Encoding{prefix = PREFIX_SIMD, opcode = 0x100}, - .I32X4_RELAXED_TRUNC_F32X4_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x101}, - .I32X4_RELAXED_TRUNC_F32X4_U = Encoding{prefix = PREFIX_SIMD, opcode = 0x102}, - .I32X4_RELAXED_TRUNC_F64X2_S_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0x103}, - .I32X4_RELAXED_TRUNC_F64X2_U_ZERO = Encoding{prefix = PREFIX_SIMD, opcode = 0x104}, - .F32X4_RELAXED_MADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x105}, - .F32X4_RELAXED_NMADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x106}, - .F64X2_RELAXED_MADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x107}, - .F64X2_RELAXED_NMADD = Encoding{prefix = PREFIX_SIMD, opcode = 0x108}, - .I8X16_RELAXED_LANESELECT = Encoding{prefix = PREFIX_SIMD, opcode = 0x109}, - .I16X8_RELAXED_LANESELECT = Encoding{prefix = PREFIX_SIMD, opcode = 0x10A}, - .I32X4_RELAXED_LANESELECT = Encoding{prefix = PREFIX_SIMD, opcode = 0x10B}, - .I64X2_RELAXED_LANESELECT = Encoding{prefix = PREFIX_SIMD, opcode = 0x10C}, - .F32X4_RELAXED_MIN = Encoding{prefix = PREFIX_SIMD, opcode = 0x10D}, - .F32X4_RELAXED_MAX = Encoding{prefix = PREFIX_SIMD, opcode = 0x10E}, - .F64X2_RELAXED_MIN = Encoding{prefix = PREFIX_SIMD, opcode = 0x10F}, - .F64X2_RELAXED_MAX = Encoding{prefix = PREFIX_SIMD, opcode = 0x110}, - .I16X8_RELAXED_Q15MULR_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x111}, - .I16X8_RELAXED_DOT_I8X16_I7X16_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x112}, - .I32X4_RELAXED_DOT_I8X16_I7X16_ADD_S = Encoding{prefix = PREFIX_SIMD, opcode = 0x113}, + .V128_LOAD = {prefix = PREFIX_SIMD, opcode = 0x00, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD8X8_S = {prefix = PREFIX_SIMD, opcode = 0x01, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD8X8_U = {prefix = PREFIX_SIMD, opcode = 0x02, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD16X4_S = {prefix = PREFIX_SIMD, opcode = 0x03, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD16X4_U = {prefix = PREFIX_SIMD, opcode = 0x04, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD32X2_S = {prefix = PREFIX_SIMD, opcode = 0x05, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD32X2_U = {prefix = PREFIX_SIMD, opcode = 0x06, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD8_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x07, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD16_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x08, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD32_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x09, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD64_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x0A, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_STORE = {prefix = PREFIX_SIMD, opcode = 0x0B, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_CONST = {prefix = PREFIX_SIMD, opcode = 0x0C, imm = {.LANES16, .NONE}}, + .I8X16_SHUFFLE = {prefix = PREFIX_SIMD, opcode = 0x0D, imm = {.LANES16, .NONE}}, + .I8X16_SWIZZLE = {prefix = PREFIX_SIMD, opcode = 0x0E}, + .I8X16_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x0F}, + .I16X8_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x10}, + .I32X4_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x11}, + .I64X2_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x12}, + .F32X4_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x13}, + .F64X2_SPLAT = {prefix = PREFIX_SIMD, opcode = 0x14}, + .I8X16_EXTRACT_LANE_S = {prefix = PREFIX_SIMD, opcode = 0x15, imm = {.LANE, .NONE}}, + .I8X16_EXTRACT_LANE_U = {prefix = PREFIX_SIMD, opcode = 0x16, imm = {.LANE, .NONE}}, + .I8X16_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x17, imm = {.LANE, .NONE}}, + .I16X8_EXTRACT_LANE_S = {prefix = PREFIX_SIMD, opcode = 0x18, imm = {.LANE, .NONE}}, + .I16X8_EXTRACT_LANE_U = {prefix = PREFIX_SIMD, opcode = 0x19, imm = {.LANE, .NONE}}, + .I16X8_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x1A, imm = {.LANE, .NONE}}, + .I32X4_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x1B, imm = {.LANE, .NONE}}, + .I32X4_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x1C, imm = {.LANE, .NONE}}, + .I64X2_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x1D, imm = {.LANE, .NONE}}, + .I64X2_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x1E, imm = {.LANE, .NONE}}, + .F32X4_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x1F, imm = {.LANE, .NONE}}, + .F32X4_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x20, imm = {.LANE, .NONE}}, + .F64X2_EXTRACT_LANE = {prefix = PREFIX_SIMD, opcode = 0x21, imm = {.LANE, .NONE}}, + .F64X2_REPLACE_LANE = {prefix = PREFIX_SIMD, opcode = 0x22, imm = {.LANE, .NONE}}, + .I8X16_EQ = {prefix = PREFIX_SIMD, opcode = 0x23}, + .I8X16_NE = {prefix = PREFIX_SIMD, opcode = 0x24}, + .I8X16_LT_S = {prefix = PREFIX_SIMD, opcode = 0x25}, + .I8X16_LT_U = {prefix = PREFIX_SIMD, opcode = 0x26}, + .I8X16_GT_S = {prefix = PREFIX_SIMD, opcode = 0x27}, + .I8X16_GT_U = {prefix = PREFIX_SIMD, opcode = 0x28}, + .I8X16_LE_S = {prefix = PREFIX_SIMD, opcode = 0x29}, + .I8X16_LE_U = {prefix = PREFIX_SIMD, opcode = 0x2A}, + .I8X16_GE_S = {prefix = PREFIX_SIMD, opcode = 0x2B}, + .I8X16_GE_U = {prefix = PREFIX_SIMD, opcode = 0x2C}, + .I16X8_EQ = {prefix = PREFIX_SIMD, opcode = 0x2D}, + .I16X8_NE = {prefix = PREFIX_SIMD, opcode = 0x2E}, + .I16X8_LT_S = {prefix = PREFIX_SIMD, opcode = 0x2F}, + .I16X8_LT_U = {prefix = PREFIX_SIMD, opcode = 0x30}, + .I16X8_GT_S = {prefix = PREFIX_SIMD, opcode = 0x31}, + .I16X8_GT_U = {prefix = PREFIX_SIMD, opcode = 0x32}, + .I16X8_LE_S = {prefix = PREFIX_SIMD, opcode = 0x33}, + .I16X8_LE_U = {prefix = PREFIX_SIMD, opcode = 0x34}, + .I16X8_GE_S = {prefix = PREFIX_SIMD, opcode = 0x35}, + .I16X8_GE_U = {prefix = PREFIX_SIMD, opcode = 0x36}, + .I32X4_EQ = {prefix = PREFIX_SIMD, opcode = 0x37}, + .I32X4_NE = {prefix = PREFIX_SIMD, opcode = 0x38}, + .I32X4_LT_S = {prefix = PREFIX_SIMD, opcode = 0x39}, + .I32X4_LT_U = {prefix = PREFIX_SIMD, opcode = 0x3A}, + .I32X4_GT_S = {prefix = PREFIX_SIMD, opcode = 0x3B}, + .I32X4_GT_U = {prefix = PREFIX_SIMD, opcode = 0x3C}, + .I32X4_LE_S = {prefix = PREFIX_SIMD, opcode = 0x3D}, + .I32X4_LE_U = {prefix = PREFIX_SIMD, opcode = 0x3E}, + .I32X4_GE_S = {prefix = PREFIX_SIMD, opcode = 0x3F}, + .I32X4_GE_U = {prefix = PREFIX_SIMD, opcode = 0x40}, + .F32X4_EQ = {prefix = PREFIX_SIMD, opcode = 0x41}, + .F32X4_NE = {prefix = PREFIX_SIMD, opcode = 0x42}, + .F32X4_LT = {prefix = PREFIX_SIMD, opcode = 0x43}, + .F32X4_GT = {prefix = PREFIX_SIMD, opcode = 0x44}, + .F32X4_LE = {prefix = PREFIX_SIMD, opcode = 0x45}, + .F32X4_GE = {prefix = PREFIX_SIMD, opcode = 0x46}, + .F64X2_EQ = {prefix = PREFIX_SIMD, opcode = 0x47}, + .F64X2_NE = {prefix = PREFIX_SIMD, opcode = 0x48}, + .F64X2_LT = {prefix = PREFIX_SIMD, opcode = 0x49}, + .F64X2_GT = {prefix = PREFIX_SIMD, opcode = 0x4A}, + .F64X2_LE = {prefix = PREFIX_SIMD, opcode = 0x4B}, + .F64X2_GE = {prefix = PREFIX_SIMD, opcode = 0x4C}, + .V128_NOT = {prefix = PREFIX_SIMD, opcode = 0x4D}, + .V128_AND = {prefix = PREFIX_SIMD, opcode = 0x4E}, + .V128_ANDNOT = {prefix = PREFIX_SIMD, opcode = 0x4F}, + .V128_OR = {prefix = PREFIX_SIMD, opcode = 0x50}, + .V128_XOR = {prefix = PREFIX_SIMD, opcode = 0x51}, + .V128_BITSELECT = {prefix = PREFIX_SIMD, opcode = 0x52}, + .V128_ANY_TRUE = {prefix = PREFIX_SIMD, opcode = 0x53}, + .V128_LOAD8_LANE = {prefix = PREFIX_SIMD, opcode = 0x54, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_LOAD16_LANE = {prefix = PREFIX_SIMD, opcode = 0x55, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_LOAD32_LANE = {prefix = PREFIX_SIMD, opcode = 0x56, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_LOAD64_LANE = {prefix = PREFIX_SIMD, opcode = 0x57, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_STORE8_LANE = {prefix = PREFIX_SIMD, opcode = 0x58, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_STORE16_LANE = {prefix = PREFIX_SIMD, opcode = 0x59, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_STORE32_LANE = {prefix = PREFIX_SIMD, opcode = 0x5A, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_STORE64_LANE = {prefix = PREFIX_SIMD, opcode = 0x5B, imm = {.MEMARG, .LANE}, flags = MEM}, + .V128_LOAD32_ZERO = {prefix = PREFIX_SIMD, opcode = 0x5C, imm = {.MEMARG, .NONE}, flags = MEM}, + .V128_LOAD64_ZERO = {prefix = PREFIX_SIMD, opcode = 0x5D, imm = {.MEMARG, .NONE}, flags = MEM}, + .F32X4_DEMOTE_F64X2_ZERO = {prefix = PREFIX_SIMD, opcode = 0x5E}, + .F64X2_PROMOTE_LOW_F32X4 = {prefix = PREFIX_SIMD, opcode = 0x5F}, + .I8X16_ABS = {prefix = PREFIX_SIMD, opcode = 0x60}, + .I8X16_NEG = {prefix = PREFIX_SIMD, opcode = 0x61}, + .I8X16_POPCNT = {prefix = PREFIX_SIMD, opcode = 0x62}, + .I8X16_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0x63}, + .I8X16_BITMASK = {prefix = PREFIX_SIMD, opcode = 0x64}, + .I8X16_NARROW_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0x65}, + .I8X16_NARROW_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0x66}, + .F32X4_CEIL = {prefix = PREFIX_SIMD, opcode = 0x67}, + .F32X4_FLOOR = {prefix = PREFIX_SIMD, opcode = 0x68}, + .F32X4_TRUNC = {prefix = PREFIX_SIMD, opcode = 0x69}, + .F32X4_NEAREST = {prefix = PREFIX_SIMD, opcode = 0x6A}, + .I8X16_SHL = {prefix = PREFIX_SIMD, opcode = 0x6B}, + .I8X16_SHR_S = {prefix = PREFIX_SIMD, opcode = 0x6C}, + .I8X16_SHR_U = {prefix = PREFIX_SIMD, opcode = 0x6D}, + .I8X16_ADD = {prefix = PREFIX_SIMD, opcode = 0x6E}, + .I8X16_ADD_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x6F}, + .I8X16_ADD_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x70}, + .I8X16_SUB = {prefix = PREFIX_SIMD, opcode = 0x71}, + .I8X16_SUB_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x72}, + .I8X16_SUB_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x73}, + .F64X2_CEIL = {prefix = PREFIX_SIMD, opcode = 0x74}, + .F64X2_FLOOR = {prefix = PREFIX_SIMD, opcode = 0x75}, + .I8X16_MIN_S = {prefix = PREFIX_SIMD, opcode = 0x76}, + .I8X16_MIN_U = {prefix = PREFIX_SIMD, opcode = 0x77}, + .I8X16_MAX_S = {prefix = PREFIX_SIMD, opcode = 0x78}, + .I8X16_MAX_U = {prefix = PREFIX_SIMD, opcode = 0x79}, + .F64X2_TRUNC = {prefix = PREFIX_SIMD, opcode = 0x7A}, + .I8X16_AVGR_U = {prefix = PREFIX_SIMD, opcode = 0x7B}, + .I16X8_EXTADD_PAIRWISE_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x7C}, + .I16X8_EXTADD_PAIRWISE_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x7D}, + .I32X4_EXTADD_PAIRWISE_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0x7E}, + .I32X4_EXTADD_PAIRWISE_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0x7F}, + .I16X8_ABS = {prefix = PREFIX_SIMD, opcode = 0x80}, + .I16X8_NEG = {prefix = PREFIX_SIMD, opcode = 0x81}, + .I16X8_Q15MULR_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x82}, + .I16X8_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0x83}, + .I16X8_BITMASK = {prefix = PREFIX_SIMD, opcode = 0x84}, + .I16X8_NARROW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0x85}, + .I16X8_NARROW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0x86}, + .I16X8_EXTEND_LOW_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x87}, + .I16X8_EXTEND_HIGH_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x88}, + .I16X8_EXTEND_LOW_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x89}, + .I16X8_EXTEND_HIGH_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x8A}, + .I16X8_SHL = {prefix = PREFIX_SIMD, opcode = 0x8B}, + .I16X8_SHR_S = {prefix = PREFIX_SIMD, opcode = 0x8C}, + .I16X8_SHR_U = {prefix = PREFIX_SIMD, opcode = 0x8D}, + .I16X8_ADD = {prefix = PREFIX_SIMD, opcode = 0x8E}, + .I16X8_ADD_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x8F}, + .I16X8_ADD_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x90}, + .I16X8_SUB = {prefix = PREFIX_SIMD, opcode = 0x91}, + .I16X8_SUB_SAT_S = {prefix = PREFIX_SIMD, opcode = 0x92}, + .I16X8_SUB_SAT_U = {prefix = PREFIX_SIMD, opcode = 0x93}, + .F64X2_NEAREST = {prefix = PREFIX_SIMD, opcode = 0x94}, + .I16X8_MUL = {prefix = PREFIX_SIMD, opcode = 0x95}, + .I16X8_MIN_S = {prefix = PREFIX_SIMD, opcode = 0x96}, + .I16X8_MIN_U = {prefix = PREFIX_SIMD, opcode = 0x97}, + .I16X8_MAX_S = {prefix = PREFIX_SIMD, opcode = 0x98}, + .I16X8_MAX_U = {prefix = PREFIX_SIMD, opcode = 0x99}, + .I16X8_AVGR_U = {prefix = PREFIX_SIMD, opcode = 0x9B}, + .I16X8_EXTMUL_LOW_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x9C}, + .I16X8_EXTMUL_HIGH_I8X16_S = {prefix = PREFIX_SIMD, opcode = 0x9D}, + .I16X8_EXTMUL_LOW_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x9E}, + .I16X8_EXTMUL_HIGH_I8X16_U = {prefix = PREFIX_SIMD, opcode = 0x9F}, + .I32X4_ABS = {prefix = PREFIX_SIMD, opcode = 0xA0}, + .I32X4_NEG = {prefix = PREFIX_SIMD, opcode = 0xA1}, + .I32X4_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0xA3}, + .I32X4_BITMASK = {prefix = PREFIX_SIMD, opcode = 0xA4}, + .I32X4_EXTEND_LOW_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xA7}, + .I32X4_EXTEND_HIGH_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xA8}, + .I32X4_EXTEND_LOW_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xA9}, + .I32X4_EXTEND_HIGH_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xAA}, + .I32X4_SHL = {prefix = PREFIX_SIMD, opcode = 0xAB}, + .I32X4_SHR_S = {prefix = PREFIX_SIMD, opcode = 0xAC}, + .I32X4_SHR_U = {prefix = PREFIX_SIMD, opcode = 0xAD}, + .I32X4_ADD = {prefix = PREFIX_SIMD, opcode = 0xAE}, + .I32X4_SUB = {prefix = PREFIX_SIMD, opcode = 0xB1}, + .I32X4_MUL = {prefix = PREFIX_SIMD, opcode = 0xB5}, + .I32X4_MIN_S = {prefix = PREFIX_SIMD, opcode = 0xB6}, + .I32X4_MIN_U = {prefix = PREFIX_SIMD, opcode = 0xB7}, + .I32X4_MAX_S = {prefix = PREFIX_SIMD, opcode = 0xB8}, + .I32X4_MAX_U = {prefix = PREFIX_SIMD, opcode = 0xB9}, + .I32X4_DOT_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xBA}, + .I32X4_EXTMUL_LOW_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xBC}, + .I32X4_EXTMUL_HIGH_I16X8_S = {prefix = PREFIX_SIMD, opcode = 0xBD}, + .I32X4_EXTMUL_LOW_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xBE}, + .I32X4_EXTMUL_HIGH_I16X8_U = {prefix = PREFIX_SIMD, opcode = 0xBF}, + .I64X2_ABS = {prefix = PREFIX_SIMD, opcode = 0xC0}, + .I64X2_NEG = {prefix = PREFIX_SIMD, opcode = 0xC1}, + .I64X2_ALL_TRUE = {prefix = PREFIX_SIMD, opcode = 0xC3}, + .I64X2_BITMASK = {prefix = PREFIX_SIMD, opcode = 0xC4}, + .I64X2_EXTEND_LOW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xC7}, + .I64X2_EXTEND_HIGH_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xC8}, + .I64X2_EXTEND_LOW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xC9}, + .I64X2_EXTEND_HIGH_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xCA}, + .I64X2_SHL = {prefix = PREFIX_SIMD, opcode = 0xCB}, + .I64X2_SHR_S = {prefix = PREFIX_SIMD, opcode = 0xCC}, + .I64X2_SHR_U = {prefix = PREFIX_SIMD, opcode = 0xCD}, + .I64X2_ADD = {prefix = PREFIX_SIMD, opcode = 0xCE}, + .I64X2_SUB = {prefix = PREFIX_SIMD, opcode = 0xD1}, + .I64X2_MUL = {prefix = PREFIX_SIMD, opcode = 0xD5}, + .I64X2_EQ = {prefix = PREFIX_SIMD, opcode = 0xD6}, + .I64X2_NE = {prefix = PREFIX_SIMD, opcode = 0xD7}, + .I64X2_LT_S = {prefix = PREFIX_SIMD, opcode = 0xD8}, + .I64X2_GT_S = {prefix = PREFIX_SIMD, opcode = 0xD9}, + .I64X2_LE_S = {prefix = PREFIX_SIMD, opcode = 0xDA}, + .I64X2_GE_S = {prefix = PREFIX_SIMD, opcode = 0xDB}, + .I64X2_EXTMUL_LOW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xDC}, + .I64X2_EXTMUL_HIGH_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xDD}, + .I64X2_EXTMUL_LOW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xDE}, + .I64X2_EXTMUL_HIGH_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xDF}, + .F32X4_ABS = {prefix = PREFIX_SIMD, opcode = 0xE0}, + .F32X4_NEG = {prefix = PREFIX_SIMD, opcode = 0xE1}, + .F32X4_SQRT = {prefix = PREFIX_SIMD, opcode = 0xE3}, + .F32X4_ADD = {prefix = PREFIX_SIMD, opcode = 0xE4}, + .F32X4_SUB = {prefix = PREFIX_SIMD, opcode = 0xE5}, + .F32X4_MUL = {prefix = PREFIX_SIMD, opcode = 0xE6}, + .F32X4_DIV = {prefix = PREFIX_SIMD, opcode = 0xE7}, + .F32X4_MIN = {prefix = PREFIX_SIMD, opcode = 0xE8}, + .F32X4_MAX = {prefix = PREFIX_SIMD, opcode = 0xE9}, + .F32X4_PMIN = {prefix = PREFIX_SIMD, opcode = 0xEA}, + .F32X4_PMAX = {prefix = PREFIX_SIMD, opcode = 0xEB}, + .F64X2_ABS = {prefix = PREFIX_SIMD, opcode = 0xEC}, + .F64X2_NEG = {prefix = PREFIX_SIMD, opcode = 0xED}, + .F64X2_SQRT = {prefix = PREFIX_SIMD, opcode = 0xEF}, + .F64X2_ADD = {prefix = PREFIX_SIMD, opcode = 0xF0}, + .F64X2_SUB = {prefix = PREFIX_SIMD, opcode = 0xF1}, + .F64X2_MUL = {prefix = PREFIX_SIMD, opcode = 0xF2}, + .F64X2_DIV = {prefix = PREFIX_SIMD, opcode = 0xF3}, + .F64X2_MIN = {prefix = PREFIX_SIMD, opcode = 0xF4}, + .F64X2_MAX = {prefix = PREFIX_SIMD, opcode = 0xF5}, + .F64X2_PMIN = {prefix = PREFIX_SIMD, opcode = 0xF6}, + .F64X2_PMAX = {prefix = PREFIX_SIMD, opcode = 0xF7}, + .I32X4_TRUNC_SAT_F32X4_S = {prefix = PREFIX_SIMD, opcode = 0xF8}, + .I32X4_TRUNC_SAT_F32X4_U = {prefix = PREFIX_SIMD, opcode = 0xF9}, + .F32X4_CONVERT_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xFA}, + .F32X4_CONVERT_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xFB}, + .I32X4_TRUNC_SAT_F64X2_S_ZERO = {prefix = PREFIX_SIMD, opcode = 0xFC}, + .I32X4_TRUNC_SAT_F64X2_U_ZERO = {prefix = PREFIX_SIMD, opcode = 0xFD}, + .F64X2_CONVERT_LOW_I32X4_S = {prefix = PREFIX_SIMD, opcode = 0xFE}, + .F64X2_CONVERT_LOW_I32X4_U = {prefix = PREFIX_SIMD, opcode = 0xFF}, + .I8X16_RELAXED_SWIZZLE = {prefix = PREFIX_SIMD, opcode = 0x100}, + .I32X4_RELAXED_TRUNC_F32X4_S = {prefix = PREFIX_SIMD, opcode = 0x101}, + .I32X4_RELAXED_TRUNC_F32X4_U = {prefix = PREFIX_SIMD, opcode = 0x102}, + .I32X4_RELAXED_TRUNC_F64X2_S_ZERO = {prefix = PREFIX_SIMD, opcode = 0x103}, + .I32X4_RELAXED_TRUNC_F64X2_U_ZERO = {prefix = PREFIX_SIMD, opcode = 0x104}, + .F32X4_RELAXED_MADD = {prefix = PREFIX_SIMD, opcode = 0x105}, + .F32X4_RELAXED_NMADD = {prefix = PREFIX_SIMD, opcode = 0x106}, + .F64X2_RELAXED_MADD = {prefix = PREFIX_SIMD, opcode = 0x107}, + .F64X2_RELAXED_NMADD = {prefix = PREFIX_SIMD, opcode = 0x108}, + .I8X16_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x109}, + .I16X8_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x10A}, + .I32X4_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x10B}, + .I64X2_RELAXED_LANESELECT = {prefix = PREFIX_SIMD, opcode = 0x10C}, + .F32X4_RELAXED_MIN = {prefix = PREFIX_SIMD, opcode = 0x10D}, + .F32X4_RELAXED_MAX = {prefix = PREFIX_SIMD, opcode = 0x10E}, + .F64X2_RELAXED_MIN = {prefix = PREFIX_SIMD, opcode = 0x10F}, + .F64X2_RELAXED_MAX = {prefix = PREFIX_SIMD, opcode = 0x110}, + .I16X8_RELAXED_Q15MULR_S = {prefix = PREFIX_SIMD, opcode = 0x111}, + .I16X8_RELAXED_DOT_I8X16_I7X16_S = {prefix = PREFIX_SIMD, opcode = 0x112}, + .I32X4_RELAXED_DOT_I8X16_I7X16_ADD_S = {prefix = PREFIX_SIMD, opcode = 0x113}, // ------------------------------------------ 0xFE threads / atomics prefix - .MEMORY_ATOMIC_NOTIFY = Encoding{prefix = PREFIX_ATOM, opcode = 0x00, imm = {.MEMARG, .NONE}, flags = MEM}, - .MEMORY_ATOMIC_WAIT32 = Encoding{prefix = PREFIX_ATOM, opcode = 0x01, imm = {.MEMARG, .NONE}, flags = MEM}, - .MEMORY_ATOMIC_WAIT64 = Encoding{prefix = PREFIX_ATOM, opcode = 0x02, imm = {.MEMARG, .NONE}, flags = MEM}, - .ATOMIC_FENCE = Encoding{prefix = PREFIX_ATOM, opcode = 0x03, imm = {.ZERO_BYTE, .NONE}}, - .I32_ATOMIC_LOAD = Encoding{prefix = PREFIX_ATOM, opcode = 0x10, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_LOAD = Encoding{prefix = PREFIX_ATOM, opcode = 0x11, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_LOAD8_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x12, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_LOAD16_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x13, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_LOAD8_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x14, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_LOAD16_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x15, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_LOAD32_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x16, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_STORE = Encoding{prefix = PREFIX_ATOM, opcode = 0x17, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_STORE = Encoding{prefix = PREFIX_ATOM, opcode = 0x18, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_STORE8 = Encoding{prefix = PREFIX_ATOM, opcode = 0x19, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_STORE16 = Encoding{prefix = PREFIX_ATOM, opcode = 0x1A, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_STORE8 = Encoding{prefix = PREFIX_ATOM, opcode = 0x1B, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_STORE16 = Encoding{prefix = PREFIX_ATOM, opcode = 0x1C, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_STORE32 = Encoding{prefix = PREFIX_ATOM, opcode = 0x1D, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW_ADD = Encoding{prefix = PREFIX_ATOM, opcode = 0x1E, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW_ADD = Encoding{prefix = PREFIX_ATOM, opcode = 0x1F, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW8_ADD_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x20, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW16_ADD_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x21, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW8_ADD_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x22, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW16_ADD_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x23, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW32_ADD_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x24, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW_SUB = Encoding{prefix = PREFIX_ATOM, opcode = 0x25, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW_SUB = Encoding{prefix = PREFIX_ATOM, opcode = 0x26, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW8_SUB_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x27, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW16_SUB_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x28, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW8_SUB_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x29, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW16_SUB_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x2A, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW32_SUB_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x2B, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW_AND = Encoding{prefix = PREFIX_ATOM, opcode = 0x2C, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW_AND = Encoding{prefix = PREFIX_ATOM, opcode = 0x2D, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW8_AND_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x2E, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW16_AND_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x2F, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW8_AND_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x30, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW16_AND_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x31, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW32_AND_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x32, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW_OR = Encoding{prefix = PREFIX_ATOM, opcode = 0x33, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW_OR = Encoding{prefix = PREFIX_ATOM, opcode = 0x34, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW8_OR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x35, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW16_OR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x36, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW8_OR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x37, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW16_OR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x38, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW32_OR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x39, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW_XOR = Encoding{prefix = PREFIX_ATOM, opcode = 0x3A, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW_XOR = Encoding{prefix = PREFIX_ATOM, opcode = 0x3B, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW8_XOR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x3C, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW16_XOR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x3D, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW8_XOR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x3E, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW16_XOR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x3F, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW32_XOR_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x40, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW_XCHG = Encoding{prefix = PREFIX_ATOM, opcode = 0x41, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW_XCHG = Encoding{prefix = PREFIX_ATOM, opcode = 0x42, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW8_XCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x43, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW16_XCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x44, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW8_XCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x45, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW16_XCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x46, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW32_XCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x47, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW_CMPXCHG = Encoding{prefix = PREFIX_ATOM, opcode = 0x48, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW_CMPXCHG = Encoding{prefix = PREFIX_ATOM, opcode = 0x49, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW8_CMPXCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x4A, imm = {.MEMARG, .NONE}, flags = MEM}, - .I32_ATOMIC_RMW16_CMPXCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x4B, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW8_CMPXCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x4C, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW16_CMPXCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x4D, imm = {.MEMARG, .NONE}, flags = MEM}, - .I64_ATOMIC_RMW32_CMPXCHG_U = Encoding{prefix = PREFIX_ATOM, opcode = 0x4E, imm = {.MEMARG, .NONE}, flags = MEM}, + .MEMORY_ATOMIC_NOTIFY = {prefix = PREFIX_ATOM, opcode = 0x00, imm = {.MEMARG, .NONE}, flags = MEM}, + .MEMORY_ATOMIC_WAIT32 = {prefix = PREFIX_ATOM, opcode = 0x01, imm = {.MEMARG, .NONE}, flags = MEM}, + .MEMORY_ATOMIC_WAIT64 = {prefix = PREFIX_ATOM, opcode = 0x02, imm = {.MEMARG, .NONE}, flags = MEM}, + .ATOMIC_FENCE = {prefix = PREFIX_ATOM, opcode = 0x03, imm = {.ZERO_BYTE, .NONE}}, + .I32_ATOMIC_LOAD = {prefix = PREFIX_ATOM, opcode = 0x10, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_LOAD = {prefix = PREFIX_ATOM, opcode = 0x11, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_LOAD8_U = {prefix = PREFIX_ATOM, opcode = 0x12, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_LOAD16_U = {prefix = PREFIX_ATOM, opcode = 0x13, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_LOAD8_U = {prefix = PREFIX_ATOM, opcode = 0x14, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_LOAD16_U = {prefix = PREFIX_ATOM, opcode = 0x15, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_LOAD32_U = {prefix = PREFIX_ATOM, opcode = 0x16, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_STORE = {prefix = PREFIX_ATOM, opcode = 0x17, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_STORE = {prefix = PREFIX_ATOM, opcode = 0x18, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_STORE8 = {prefix = PREFIX_ATOM, opcode = 0x19, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_STORE16 = {prefix = PREFIX_ATOM, opcode = 0x1A, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_STORE8 = {prefix = PREFIX_ATOM, opcode = 0x1B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_STORE16 = {prefix = PREFIX_ATOM, opcode = 0x1C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_STORE32 = {prefix = PREFIX_ATOM, opcode = 0x1D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_ADD = {prefix = PREFIX_ATOM, opcode = 0x1E, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_ADD = {prefix = PREFIX_ATOM, opcode = 0x1F, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x20, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x21, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x22, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x23, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_ADD_U = {prefix = PREFIX_ATOM, opcode = 0x24, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_SUB = {prefix = PREFIX_ATOM, opcode = 0x25, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_SUB = {prefix = PREFIX_ATOM, opcode = 0x26, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x27, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x28, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x29, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x2A, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_SUB_U = {prefix = PREFIX_ATOM, opcode = 0x2B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_AND = {prefix = PREFIX_ATOM, opcode = 0x2C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_AND = {prefix = PREFIX_ATOM, opcode = 0x2D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_AND_U = {prefix = PREFIX_ATOM, opcode = 0x2E, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_AND_U = {prefix = PREFIX_ATOM, opcode = 0x2F, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_AND_U = {prefix = PREFIX_ATOM, opcode = 0x30, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_AND_U = {prefix = PREFIX_ATOM, opcode = 0x31, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_AND_U = {prefix = PREFIX_ATOM, opcode = 0x32, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_OR = {prefix = PREFIX_ATOM, opcode = 0x33, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_OR = {prefix = PREFIX_ATOM, opcode = 0x34, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_OR_U = {prefix = PREFIX_ATOM, opcode = 0x35, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_OR_U = {prefix = PREFIX_ATOM, opcode = 0x36, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_OR_U = {prefix = PREFIX_ATOM, opcode = 0x37, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_OR_U = {prefix = PREFIX_ATOM, opcode = 0x38, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_OR_U = {prefix = PREFIX_ATOM, opcode = 0x39, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_XOR = {prefix = PREFIX_ATOM, opcode = 0x3A, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_XOR = {prefix = PREFIX_ATOM, opcode = 0x3B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3E, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x3F, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_XOR_U = {prefix = PREFIX_ATOM, opcode = 0x40, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_XCHG = {prefix = PREFIX_ATOM, opcode = 0x41, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_XCHG = {prefix = PREFIX_ATOM, opcode = 0x42, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x43, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x44, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x45, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x46, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_XCHG_U = {prefix = PREFIX_ATOM, opcode = 0x47, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW_CMPXCHG = {prefix = PREFIX_ATOM, opcode = 0x48, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW_CMPXCHG = {prefix = PREFIX_ATOM, opcode = 0x49, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW8_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4A, imm = {.MEMARG, .NONE}, flags = MEM}, + .I32_ATOMIC_RMW16_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4B, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW8_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4C, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW16_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4D, imm = {.MEMARG, .NONE}, flags = MEM}, + .I64_ATOMIC_RMW32_CMPXCHG_U = {prefix = PREFIX_ATOM, opcode = 0x4E, imm = {.MEMARG, .NONE}, flags = MEM}, } // Per-mnemonic encode form. Returns a pointer into the rodata table. From 5e53cba0dce80ee8aa52b3b8bbf17f100e345af5 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 16 Jun 2026 14:38:28 +0100 Subject: [PATCH 18/27] More formatting improvements --- core/rexcode/wasm/decoder.odin | 18 +++++++------- core/rexcode/wasm/encoder.odin | 36 ++++++++++++++++++--------- core/rexcode/wasm/encoding_types.odin | 7 ++++-- core/rexcode/wasm/printer.odin | 33 +++++++++++++++++------- 4 files changed, 62 insertions(+), 32 deletions(-) diff --git a/core/rexcode/wasm/decoder.odin b/core/rexcode/wasm/decoder.odin index ee98bf6e6..00ee8cd79 100644 --- a/core/rexcode/wasm/decoder.odin +++ b/core/rexcode/wasm/decoder.odin @@ -157,10 +157,10 @@ decode_one :: proc( field := off raw := read_uleb(data, &off) or_return op := Operand{index = u32(raw), kind = .INDEX, idx_kind = idx_kind_for(m, ki)} - if lid, sym := reloc_label_at(relocs, field); sym { - op.index = lid + if lid, found := reloc_label_at(relocs, field); found { + op.index = lid op.flags.symbolic = true - op.size = 5 + op.size = 5 } inst.ops[slot] = op slot += 1 @@ -168,9 +168,7 @@ decode_one :: proc( case .MEMARG: align := read_uleb(data, &off) or_return offset := read_uleb(data, &off) or_return - inst.ops[slot] = Operand{ - memarg = Memarg{align = u32(align), offset = u32(offset)}, kind = .MEMARG, - } + inst.ops[slot] = Operand{memarg = Memarg{align = u32(align), offset = u32(offset)}, kind = .MEMARG} slot += 1 case .REFTYPE: @@ -178,7 +176,8 @@ decode_one :: proc( next = pc return } - t := data[off]; off += 1 + t := data[off] + off += 1 inst.ops[slot] = Operand{immediate = i64(t), kind = .IMMEDIATE, size = 1} slot += 1 @@ -206,7 +205,8 @@ decode_one :: proc( next = pc return } - l := data[off]; off += 1 + l := data[off] + off += 1 inst.ops[slot] = Operand{immediate = i64(l), kind = .IMMEDIATE, size = 1} slot += 1 @@ -254,5 +254,5 @@ reloc_label_at :: #force_inline proc "contextless" (relocs: []Relocation, offset return r.label_id, true } } - return 0, false + return } diff --git a/core/rexcode/wasm/encoder.odin b/core/rexcode/wasm/encoder.odin index bb3f182c9..fd453f548 100644 --- a/core/rexcode/wasm/encoder.odin +++ b/core/rexcode/wasm/encoder.odin @@ -71,14 +71,14 @@ encode_one :: #force_inline proc( ) -> (size: u32, ok: bool) { if inst.mnemonic == .INVALID { append(errors, Error{inst_idx = u32(inst_idx), code = .INVALID_MNEMONIC}) - return 0, false + return } form := encoding_form(inst.mnemonic) need := encoded_size(inst, form) if pc + need > u32(len(code)) { append(errors, Error{inst_idx = u32(inst_idx), code = .BUFFER_OVERFLOW}) - return 0, false + return } off := pc @@ -156,34 +156,46 @@ encode_one :: #force_inline proc( @(private="file") encoded_size :: proc(inst: ^Instruction, form: ^Encoding) -> u32 { - size: u32 = form.prefix == PREFIX_NONE ? 1 : 1 + uleb_size(u64(form.opcode)) + size: u32 = 1 + if form.prefix != PREFIX_NONE { + size += uleb_size(u64(form.opcode)) + } opi := 0 for k in form.imm { switch k { case .NONE: case .BLOCKTYPE, .I32, .I64: - size += sleb_size(inst.ops[opi].immediate); opi += 1 + size += sleb_size(inst.ops[opi].immediate) + opi += 1 case .F32: - size += 4; opi += 1 + size += 4 + opi += 1 case .F64: - size += 8; opi += 1 + size += 8 + opi += 1 case .IDX: op := &inst.ops[opi] size += op.flags.symbolic ? 5 : uleb_size(u64(op.index)) - opi += 1 + opi += 1 case .MEMARG: ma := inst.ops[opi].memarg - size += uleb_size(u64(ma.align)) + uleb_size(u64(ma.offset)); opi += 1 + size += uleb_size(u64(ma.align)) + uleb_size(u64(ma.offset)) + opi += 1 case .REFTYPE: - size += 1; opi += 1 + size += 1 + opi += 1 case .BR_TABLE: size += uleb_size(u64(len(inst.targets))) - for t in inst.targets { size += uleb_size(u64(t)) } - size += uleb_size(u64(inst.ops[opi].index)); opi += 1 + for t in inst.targets { + size += uleb_size(u64(t)) + } + size += uleb_size(u64(inst.ops[opi].index)) + opi += 1 case .ZERO_BYTE: size += 1 case .LANE: - size += 1; opi += 1 + size += 1 + opi += 1 case .LANES16: size += 16 } diff --git a/core/rexcode/wasm/encoding_types.odin b/core/rexcode/wasm/encoding_types.odin index 71d1605f3..b2dc4358a 100644 --- a/core/rexcode/wasm/encoding_types.odin +++ b/core/rexcode/wasm/encoding_types.odin @@ -118,7 +118,9 @@ write_uleb_padded5 :: #force_inline proc "contextless" (code: []u8, offset: ^u32 uleb_size :: #force_inline proc "contextless" (value: u64) -> u32 { v := value n: u32 = 1 - for v >= 0x80 { v >>= 7; n += 1 } + for /**/; v >= 0x80; n += 1 { + v >>= 7 + } return n } @@ -168,7 +170,8 @@ read_sleb :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (val if shift < 64 && (b & 0x40) != 0 { value |= -(i64(1) << shift) } - return value, true + ok = true + return } write_u32le :: #force_inline proc(code: []u8, offset: ^u32, v: u32) { diff --git a/core/rexcode/wasm/printer.odin b/core/rexcode/wasm/printer.odin index a6e382b2c..8aa9b50ad 100644 --- a/core/rexcode/wasm/printer.odin +++ b/core/rexcode/wasm/printer.odin @@ -356,7 +356,7 @@ write_label :: proc( opts: ^Print_Options, ) { if label_names != nil { - if name, has := label_names^[label_id]; has { + if name, ok := label_names^[label_id]; ok { strings.write_string(sb, name) return } @@ -367,12 +367,20 @@ write_label :: proc( @(private="file") write_decimal_u32 :: proc(sb: ^strings.Builder, v: u32) { - if v == 0 { strings.write_byte(sb, '0'); return } + if v == 0 { + strings.write_byte(sb, '0') + return + } + buf: [10]u8 i := 0 - n := v - for n > 0 { buf[i] = '0' + u8(n % 10); n /= 10; i += 1 } - for j := i - 1; j >= 0; j -= 1 { strings.write_byte(sb, buf[j]) } + for n := v; n > 0; i += 1 { + buf[i] = '0' + u8(n % 10) + n /= 10 + } + for j := i - 1; j >= 0; j -= 1 { + strings.write_byte(sb, buf[j]) + } } @(private="file") @@ -387,10 +395,17 @@ write_signed_decimal :: proc(sb: ^strings.Builder, v: i64) { @(private="file") write_decimal_u64 :: proc(sb: ^strings.Builder, v: u64) { - if v == 0 { strings.write_byte(sb, '0'); return } + if v == 0 { + strings.write_byte(sb, '0') + return + } buf: [20]u8 i := 0 - n := v - for n > 0 { buf[i] = '0' + u8(n % 10); n /= 10; i += 1 } - for j := i - 1; j >= 0; j -= 1 { strings.write_byte(sb, buf[j]) } + for n := v; n > 0; i += 1 { + buf[i] = '0' + u8(n % 10) + n /= 10 + } + for j := i - 1; j >= 0; j -= 1 { + strings.write_byte(sb, buf[j]) + } } From 3a5439f60e5b577ce3be325627ec7f4d04cef35e Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 16 Jun 2026 15:26:01 +0100 Subject: [PATCH 19/27] Compiler: Improve error propagation when all of the overloads have the same return values --- src/check_expr.cpp | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/check_expr.cpp b/src/check_expr.cpp index a9c9f1fb0..0eca029d3 100644 --- a/src/check_expr.cpp +++ b/src/check_expr.cpp @@ -7811,6 +7811,30 @@ gb_internal CallArgumentData check_call_arguments_proc_group(CheckerContext *c, } data.result_type = t_invalid; + if (procs.count > 0) { + Type *first_type = base_type(procs[0]->type); + GB_ASSERT(first_type->kind == Type_Proc); + Type *first_results = first_type->Proc.results; + bool all_the_same = true; + for (isize i = 1; i < procs.count; i++) { + Type *type = base_type(procs[i]->type); + if (type->kind != Type_Proc) { + all_the_same = false; + break; + } + Type *results = type->Proc.results; + if (!are_types_identical(first_results, results)) { + all_the_same = false; + break; + } + } + if (all_the_same) { + GB_ASSERT_MSG(is_type_tuple(first_results), "%s", type_to_string(first_results)); + data.result_type = first_results; + } + } + + } else if (valids.count > 1) { ERROR_BLOCK(); From 0d9ad7259b7df18ad64efda37b8c810348e37212 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Tue, 16 Jun 2026 16:39:03 +0100 Subject: [PATCH 20/27] Make `decode_one` public --- core/rexcode/wasm/decoder.odin | 4 ---- 1 file changed, 4 deletions(-) diff --git a/core/rexcode/wasm/decoder.odin b/core/rexcode/wasm/decoder.odin index 00ee8cd79..ea13ba5c3 100644 --- a/core/rexcode/wasm/decoder.odin +++ b/core/rexcode/wasm/decoder.odin @@ -67,11 +67,7 @@ decode :: proc( return } -// ============================================================================= -// Internal -// ============================================================================= -@(private="file") decode_one :: proc( data: []u8, relocs: []Relocation, From 098936108cb587e936ff215106829d88f102af5a Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 17 Jun 2026 11:58:41 +0100 Subject: [PATCH 21/27] Add `core:rexcode/wasm/module` --- core/rexcode/wasm/decoder.odin | 24 +- core/rexcode/wasm/encoder.odin | 9 +- core/rexcode/wasm/encoding_types.odin | 12 +- core/rexcode/wasm/module/module.odin | 151 ++++++++++ core/rexcode/wasm/module/parse.odin | 402 ++++++++++++++++++++++++++ core/rexcode/wasm/module/print.odin | 241 +++++++++++++++ core/rexcode/wasm/module/relocs.odin | 93 ++++++ core/rexcode/wasm/printer.odin | 94 +++--- 8 files changed, 944 insertions(+), 82 deletions(-) create mode 100644 core/rexcode/wasm/module/module.odin create mode 100644 core/rexcode/wasm/module/parse.odin create mode 100644 core/rexcode/wasm/module/print.odin create mode 100644 core/rexcode/wasm/module/relocs.odin diff --git a/core/rexcode/wasm/decoder.odin b/core/rexcode/wasm/decoder.odin index ea13ba5c3..6d1aa2fd1 100644 --- a/core/rexcode/wasm/decoder.odin +++ b/core/rexcode/wasm/decoder.odin @@ -19,8 +19,7 @@ import "base:runtime" // its immediates in declaration order, reconstructing Operands. // // WASM control flow is structured (branches carry relative label depths, not -// byte offsets), so there is no PC-relative label inference -- `label_defs` -// is part of the universal signature but left untouched. Object-file index +// byte offsets), so there is no PC-relative label inference. Object-file index // relocations *are* re-attached: when an input relocation lands on a decoded // index field, that operand is marked `symbolic` and carries the label id. // @@ -39,7 +38,6 @@ decode :: proc( relocs: []Relocation, instructions: ^[dynamic]Instruction, inst_info: ^[dynamic]Instruction_Info, - label_defs: ^[dynamic]Label_Definition, errors: ^[dynamic]Error, targets_allocator := context.allocator, ) -> (byte_count: u32, ok: bool) { @@ -157,6 +155,8 @@ decode_one :: proc( op.index = lid op.flags.symbolic = true op.size = 5 + } else if m == .CALL { + op.flags.symbolic = true } inst.ops[slot] = op slot += 1 @@ -229,15 +229,15 @@ decode_one :: proc( @(private="file") idx_kind_for :: #force_inline proc "contextless" (m: Mnemonic, which: int) -> Index_Kind { #partial switch m { - case .BR, .BR_IF: return .LABEL - case .CALL, .REF_FUNC: return .FUNC - case .CALL_INDIRECT: return which == 0 ? .TYPE : .TABLE - case .LOCAL_GET, .LOCAL_SET, .LOCAL_TEE: return .LOCAL - case .GLOBAL_GET, .GLOBAL_SET: return .GLOBAL - case .MEMORY_INIT, .DATA_DROP: return .DATA - case .TABLE_INIT: return which == 0 ? .ELEM : .TABLE - case .ELEM_DROP: return .ELEM - case .TABLE_COPY: return .TABLE + case .BR, .BR_IF: return .LABEL + case .CALL, .REF_FUNC: return .FUNC + case .CALL_INDIRECT: return which == 0 ? .TYPE : .TABLE + case .LOCAL_GET, .LOCAL_SET, .LOCAL_TEE: return .LOCAL + case .GLOBAL_GET, .GLOBAL_SET: return .GLOBAL + case .MEMORY_INIT, .DATA_DROP: return .DATA + case .TABLE_INIT: return which == 0 ? .ELEM : .TABLE + case .ELEM_DROP: return .ELEM + case .TABLE_COPY: return .TABLE case .TABLE_GROW, .TABLE_SIZE, .TABLE_FILL: return .TABLE } return .NONE diff --git a/core/rexcode/wasm/encoder.odin b/core/rexcode/wasm/encoder.odin index fd453f548..df9d63a1b 100644 --- a/core/rexcode/wasm/encoder.odin +++ b/core/rexcode/wasm/encoder.odin @@ -45,9 +45,8 @@ encode :: proc( ) -> (byte_count: u32, ok: bool) { errors_start := u32(len(errors)) - for i in 0..>= 7 - if v != 0 { b |= 0x80 } + if v != 0 { + b |= 0x80 + } code[offset^] = b offset^ += 1 if v == 0 { @@ -94,7 +96,9 @@ write_sleb :: #force_inline proc "contextless" (code: []u8, offset: ^u32, value: b := u8(v & 0x7F) v >>= 7 // arithmetic shift on signed value sign-extends done := (v == 0 && (b & 0x40) == 0) || (v == -1 && (b & 0x40) != 0) - if !done { b |= 0x80 } + if !done { + b |= 0x80 + } code[offset^] = b offset^ += 1 if done { @@ -109,7 +113,9 @@ write_uleb_padded5 :: #force_inline proc "contextless" (code: []u8, offset: ^u32 for i := 0; i < 5 && offset^ < u32(len(code)); i += 1 { b := u8(v & 0x7F) v >>= 7 - if i != 4 { b |= 0x80 } + if i != 4 { + b |= 0x80 + } code[offset^] = b offset^ += 1 } diff --git a/core/rexcode/wasm/module/module.odin b/core/rexcode/wasm/module/module.odin new file mode 100644 index 000000000..cd371721b --- /dev/null +++ b/core/rexcode/wasm/module/module.odin @@ -0,0 +1,151 @@ +package rexcode_wasm_module + +import "base:runtime" +import "core:rexcode/wasm" + +WASM_MAGIC :: u32(0x6d736100) // "\0asm" as a little-endian u32 +WASM_VERSION :: u32(1) + +Section_Id :: enum u8 { // Binary section ids (WebAssembly core spec §5.5.2). + CUSTOM = 0, + TYPE = 1, + IMPORT = 2, + FUNCTION = 3, + TABLE = 4, + MEMORY = 5, + GLOBAL = 6, + EXPORT = 7, + START = 8, + ELEMENT = 9, + CODE = 10, + DATA = 11, + DATA_COUNT = 12, +} + +Section :: struct { + id: Section_Id, + offset: u32, // file offset of the section *contents* + size: u32, // contents length in bytes + count: u32, // element count + name: string, // custom-section name (borrowed) +} + +External_Kind :: enum u8 { + FUNC = 0, + TABLE = 1, + MEMORY = 2, + GLOBAL = 3, +} + +@(rodata) +external_kind_string := [External_Kind]string{ + .FUNC = "func", + .TABLE = "table", + .MEMORY = "memory", + .GLOBAL = "global", +} + +Func_Type :: struct { + params: []wasm.Value_Type, + results: []wasm.Value_Type, +} + +Import :: struct { + kind: External_Kind, + module_name: string, // borrowed + field_name: string, // borrowed + index: u32, // typeidx for FUNC, 0 for other kinds +} + +Export :: struct { + kind: External_Kind, + name: string, // borrowed + index: u32, +} + +// A compressed run of declared locals (e.g. `3 x i32`) +Local_Group :: struct { + count: u32, + type: wasm.Value_Type, +} + +// A function in the module's function index space. +// Imported functions occupy the low indices, followed by the module-defined functions. +Function :: struct { + func_index: u32, + type_index: u32, + type: Func_Type, // resolved signature ({} if the type id was out of range) + imported: bool, + name: string, // export / name-section / import field (borrowed) + import_module: string, // borrowed, "" for defined functions + import_field: string, // borrowed, "" for defined functions + + // defined functions only: + locals: []Local_Group, + body_offset: u32, // file offset of the instruction stream + body_size: u32, // instruction-stream length in bytes +} + +Module :: struct { + version: u32, + sections: []Section, + types: []Func_Type, + imports: []Import, + functions: []Function, // whole function index space (imports + defined) + exports: []Export, + start: i64, // -1 if absent, else the start funcidx + + data: []u8, // borrowed reference to the whole file (body decode reads from it) + + allocator: runtime.Allocator, +} + +// ----------------------------------------------------------------------------- +// Small display helpers +// ----------------------------------------------------------------------------- + + +@(require_results) +section_name :: proc(id: Section_Id) -> string { + switch id { + case .CUSTOM: return "custom" + case .TYPE: return "type" + case .IMPORT: return "import" + case .FUNCTION: return "function" + case .TABLE: return "table" + case .MEMORY: return "memory" + case .GLOBAL: return "global" + case .EXPORT: return "export" + case .START: return "start" + case .ELEMENT: return "element" + case .CODE: return "code" + case .DATA: return "data" + case .DATA_COUNT: return "data.count" + } + return "unknown" +} + +@(require_results) +valtype_name :: proc(t: wasm.Value_Type) -> string { + switch t { + case .I32: return "i32" + case .I64: return "i64" + case .F32: return "f32" + case .F64: return "f64" + case .V128: return "v128" + case .FUNCREF: return "funcref" + case .EXTERNREF: return "externref" + } + return "?" +} + +@(require_results) +external_kind_name :: proc(k: External_Kind) -> string { + switch k { + case .FUNC: return "func" + case .TABLE: return "table" + case .MEMORY: return "memory" + case .GLOBAL: return "global" + } + return "?" +} diff --git a/core/rexcode/wasm/module/parse.odin b/core/rexcode/wasm/module/parse.odin new file mode 100644 index 000000000..44dfc3f89 --- /dev/null +++ b/core/rexcode/wasm/module/parse.odin @@ -0,0 +1,402 @@ +package rexcode_wasm_module + +import "base:runtime" +import "core:rexcode/wasm" + +Parse_Error :: enum { + NONE = 0, + TRUNCATED, + BAD_MAGIC, + BAD_TYPE_FORM, // a functype did not start with 0x60 + BAD_SECTION, // section contents extend past the section size + BAD_ULEB, // ULEB number didn't stop after 10 bytes +} + +Reader_Error :: union #shared_nil { + Parse_Error, + runtime.Allocator_Error, +} + +Reader :: struct { + data: []u8, + off: u32, +} + +@(require_results) +reader :: proc(data: []u8, off: u32) -> Reader { + return Reader{data = data, off = off} +} + +@(require_results) +rd_byte :: proc(r: ^Reader) -> (u8, Parse_Error) { + if r.off >= u32(len(r.data)) { + return 0, .TRUNCATED + } + b := r.data[r.off] + r.off += 1 + return b, .NONE +} + +@(require_results) +rd_u32le_block :: proc(r: ^Reader) -> (u32, Parse_Error) { + if r.off + 4 > u32(len(r.data)) { + return 0, .TRUNCATED + } + v := u32(r.data[r.off]) | + u32(r.data[r.off+1])<<8 | + u32(r.data[r.off+2])<<16 | + u32(r.data[r.off+3])<<24 + r.off += 4 + return v, .NONE +} + +@(require_results) +rd_uleb :: proc(r: ^Reader) -> (u64, Parse_Error) { + shift: uint = 0 + value: u64 = 0 + for _ in 0..<10 { + if r.off >= u32(len(r.data)) { + return 0, .TRUNCATED + } + b := r.data[r.off] + r.off += 1 + value |= u64(b & 0x7F) << shift + if b & 0x80 == 0 { + return value, .NONE + } + shift += 7 + } + return 0, .BAD_ULEB +} + +// Signed-LEB128 reader. +@(require_results) +rd_sleb :: proc(r: ^Reader) -> (i64, Parse_Error) { + shift: uint = 0 + value: i64 = 0 + b: u8 = 0 + for _ in 0..<10 { + if r.off >= u32(len(r.data)) { + return 0, .TRUNCATED + } + b = r.data[r.off] + r.off += 1 + value |= i64(b & 0x7F) << shift + shift += 7 + if b & 0x80 == 0 { + break + } + } + if shift < 64 && (b & 0x40) != 0 { + value |= -(i64(1) << shift) + } + return value, .NONE +} + + +@(require_results) +rd_u32 :: proc(r: ^Reader) -> (u32, Parse_Error) { + v, err := rd_uleb(r) + return u32(v), err +} + +@(require_results) +rd_name :: proc(r: ^Reader) -> (val: string, err: Parse_Error) { + n := rd_u32(r) or_return + if r.off + n > u32(len(r.data)) { + err = .TRUNCATED + return + } + val = string(r.data[r.off:][:n]) + r.off += n + return +} + +@(require_results) +rd_valtype_vec :: proc(r: ^Reader, allocator: runtime.Allocator) -> (out: []wasm.Value_Type, err: Reader_Error) { + n := rd_u32(r) or_return + + // now actually parse it + out = make([]wasm.Value_Type, int(n), allocator) or_return + for &v in out { + v = wasm.Value_Type(rd_byte(r) or_return) + } + return +} + +@(require_results) +rd_limits :: proc(r: ^Reader) -> (min: u64, max: Maybe(u64), err: Parse_Error) { + flags := rd_byte(r) or_return + min = rd_uleb(r) or_return + if flags & 0x01 != 0 { + max = rd_uleb(r) or_return + } + return +} + + +@(require_results) +parse :: proc(data: []u8, allocator := context.allocator) -> (m: Module, err: Reader_Error) { + context.allocator = allocator + + m.data = data + m.start = -1 + m.allocator = allocator + + r := reader(data, 0) + if (rd_u32le_block(&r) or_else 0) != WASM_MAGIC { + return m, .BAD_MAGIC + } + m.version = rd_u32le_block(&r) or_return + + secs: [dynamic]Section + for r.off < u32(len(data)) { + id := Section_Id(rd_byte(&r) or_return) + size := rd_u32(&r) or_return + content := r.off + if content + size > u32(len(data)) { + return m, .BAD_SECTION + } + + sec := Section{id = id, offset = content, size = size} + switch id { + case .CUSTOM: + sub := reader(data, content) + sec.name = rd_name(&sub) or_return + case .START: + // funcidx, no vector count + case .TYPE, .IMPORT, .FUNCTION, .TABLE, .MEMORY, .GLOBAL, + .EXPORT, .ELEMENT, .CODE, .DATA, .DATA_COUNT: + sub := reader(data, content) + sec.count = rd_u32(&sub) or_return + } + append(&secs, sec) or_return + r.off = content + size + } + m.sections = secs[:] + + + func_typeidx: []u32 + codes: []Code_Body + + for &sec in m.sections { + s := reader(data, sec.offset) + #partial switch sec.id { + case .TYPE: m.types = parse_types (&s, allocator) or_return + case .IMPORT: m.imports = parse_imports (&s, allocator) or_return + case .FUNCTION: func_typeidx = parse_function_section(&s, allocator) or_return + case .EXPORT: m.exports = parse_exports (&s, allocator) or_return + case .CODE: codes = parse_code (&s, allocator) or_return + case .START: m.start = i64(rd_u32(&s) or_return) + } + } + + build_functions(&m, func_typeidx, codes, allocator) or_return + apply_name_section(&m) + return +} + +@(require_results) +parse_types :: proc(r: ^Reader, allocator: runtime.Allocator) -> (out: []Func_Type, err: Reader_Error) { + n := rd_u32(r) or_return + out = make([]Func_Type, int(n), allocator) or_return + for &func in out { + form := rd_byte(r) or_return + if form != 0x60 { + return out, .BAD_TYPE_FORM + } + func.params = rd_valtype_vec(r, allocator) or_return + func.results = rd_valtype_vec(r, allocator) or_return + } + return +} + +@(require_results) +parse_imports :: proc(r: ^Reader, allocator: runtime.Allocator) -> (out: []Import, err: Reader_Error) { + n := rd_u32(r) or_return + out = make([]Import, int(n), allocator) or_return + for &imp in out { + imp.module_name = rd_name(r) or_return + imp.field_name = rd_name(r) or_return + imp.kind = External_Kind(rd_byte(r) or_return) + switch imp.kind { + case .FUNC: + imp.index = rd_u32(r) or_return + case .TABLE: + _ = rd_byte(r) or_return // reftype + _, _ = rd_limits(r) or_return + case .MEMORY: + _, _ = rd_limits(r) or_return + case .GLOBAL: + _ = rd_byte(r) or_return // valtype + _ = rd_byte(r) or_return // mutability + } + } + return +} + +@(require_results) +parse_function_section :: proc(r: ^Reader, allocator: runtime.Allocator) -> (out: []u32, err: Reader_Error) { + n := rd_u32(r) or_return + out = make([]u32, int(n), allocator) or_return + for &idx in out { + idx = rd_u32(r) or_return + } + return +} + +@(require_results) +parse_exports :: proc(r: ^Reader, allocator: runtime.Allocator) -> (out: []Export, err: Reader_Error) { + n := rd_u32(r) or_return + out = make([]Export, int(n), allocator) or_return + for &e in out { + e.name = rd_name(r) or_return + e.kind = External_Kind(rd_byte(r) or_return) + e.index = rd_u32(r) or_return + } + return +} + +Code_Body :: struct { + locals: []Local_Group, + body_offset: u32, + body_size: u32, +} + +@(require_results) +parse_code :: proc(r: ^Reader, allocator: runtime.Allocator) -> (out: []Code_Body, err: Reader_Error) { + n := rd_u32(r) or_return + out = make([]Code_Body, int(n), allocator) or_return + for &code_body in out { + total := rd_u32(r) or_return + body_start := r.off + body_end := body_start + total + + nl := rd_u32(r) or_return + locals := make([]Local_Group, int(nl), allocator) or_return + for &local in locals { + cnt := rd_u32(r) or_return + t := wasm.Value_Type(rd_byte(r) or_return) + local = Local_Group{count = cnt, type = t} + } + code_body = Code_Body{ + locals = locals, + body_offset = r.off, + body_size = body_end > r.off ? body_end - r.off : 0, + } + r.off = body_end // jump past the expression to the next entry + } + return +} + +@(require_results) +build_functions :: proc(m: ^Module, func_typeidx: []u32, codes: []Code_Body, allocator: runtime.Allocator) -> runtime.Allocator_Error { + num_imports := 0 + for imp in m.imports { + if imp.kind == .FUNC { + num_imports += 1 + } + } + total := num_imports + len(func_typeidx) + if total == 0 { + return nil + } + + funcs := make([]Function, total, allocator) or_return + + idx := 0 + for imp in m.imports { + (imp.kind == .FUNC) or_continue + f := Function{ + func_index = u32(idx), + type_index = imp.index, + imported = true, + name = imp.field_name, + import_module = imp.module_name, + import_field = imp.field_name, + } + if int(imp.index) < len(m.types) { + f.type = m.types[imp.index] + } + funcs[idx] = f + idx += 1 + } + + for tidx, i in func_typeidx { + fi := num_imports + i + f := Function{ + func_index = u32(fi), + type_index = tidx, + imported = false, + } + if int(tidx) < len(m.types) { + f.type = m.types[tidx] + } + if i < len(codes) { + c := &codes[i] + f.locals = c.locals + f.body_offset = c.body_offset + f.body_size = c.body_size + } + funcs[fi] = f + } + + for e in m.exports { + if e.kind == .FUNC && int(e.index) < total && funcs[e.index].name == "" { + funcs[e.index].name = e.name + } + } + + m.functions = funcs + return nil +} + +// Override function names with debug names from the "name" custom section's function-names subsection (id 1), if it exists. +apply_name_section :: proc(m: ^Module) { + for sec in m.sections { + if sec.id != .CUSTOM || sec.name != "name" { + continue + } + + r := reader(m.data, sec.offset) + _ = rd_name(&r) or_break // re-read the section name to position at the subsections + end := sec.offset + sec.size + + for r.off < end { + sub_id := rd_byte(&r) or_break + sub_size := rd_u32(&r) or_break + payload_end := r.off + sub_size + if sub_id == 1 { + count := rd_u32(&r) or_break + for _ in 0.. 0 { + strings.write_string(sb, "\n.import\n") + for imp, i in m.imports { + fmt.sbprintf(sb, " [%d] %s %q %q idx:%d\n", i, external_kind_string[imp.kind], imp.module_name, imp.field_name, imp.index) + } + } + + if len(m.exports) > 0 { + strings.write_string(sb, "\n.export\n") + for e, i in m.exports { + fmt.sbprintf(sb, " [%d] %s %q idx:%d\n", i, external_kind_string[e.kind], e.name, e.index) + } + } + + if len(m.types) > 0 { + strings.write_string(sb, "\n.") + strings.write_string(sb, section_name(.TYPE)) + strings.write_string(sb, "\n") + for t, i in m.types { + strings.write_string(sb, " [") + write_u64(sb, u64(i)) + strings.write_string(sb, "] ") + write_func_type(sb, t) + strings.write_byte(sb, '\n') + } + } + + + func_relocs: []wasm.Relocation + for rg in relocs_group { + if rg.target_section == .FUNCTION { + func_relocs = rg.relocs + break + } + } + + + strings.write_string(sb, "\nfunctions:\n") + for f in m.functions { + strings.write_string(sb, " [") + write_u64(sb, u64(f.func_index)) + strings.write_string(sb, "] ") + if f.name != "" { + strings.write_byte(sb, '$') + strings.write_quoted_string(sb, f.name) + strings.write_byte(sb, ' ') + } + write_func_type(sb, f.type) + + if f.imported { + strings.write_string(sb, " @ import ") + strings.write_quoted_string(sb, f.import_module) + strings.write_string(sb, " ") + strings.write_quoted_string(sb, f.import_field) + strings.write_string(sb, "\n") + continue + } + + strings.write_byte(sb, '\n') + write_locals(sb, f.locals) + write_body(sb, m, f, func_relocs, &label_names) + } +} + +// Disassemble and print one function body. Returns the empty string for +// imported functions (which have no body). +aprint_function :: proc(m: Module, f: Function, relocs: []wasm.Relocation, label_names: ^map[u32]string, allocator := context.allocator) -> string { + if f.imported || f.body_size == 0 { + return "" + } + body := m.data[f.body_offset:][:f.body_size] + + insts: [dynamic]wasm.Instruction + info: [dynamic]wasm.Instruction_Info + errs: [dynamic]wasm.Error + defer delete(insts) + defer delete(info) + defer delete(errs) + + wasm.decode(body, relocs, &insts, &info, &errs) + return wasm.aprint(insts[:], info[:], allocator=allocator, label_names=label_names) +} + +write_body :: proc(sb: ^strings.Builder, m: Module, f: Function, relocs: []wasm.Relocation, label_names: ^map[u32]string) { + if f.body_size == 0 { return } + text := aprint_function(m, f, relocs, label_names, context.temp_allocator) + for line in strings.split_lines_iterator(&text) { + if line == "" { + continue + } + strings.write_string(sb, " ") + strings.write_string(sb, line) + strings.write_byte(sb, '\n') + } +} + +write_locals :: proc(sb: ^strings.Builder, locals: []Local_Group) { + if len(locals) == 0 { return } + strings.write_string(sb, " locals:") + for g in locals { + strings.write_byte(sb, ' ') + if g.count > 1 { + write_u64(sb, u64(g.count)) + strings.write_string(sb, "x") + } + strings.write_string(sb, valtype_name(g.type)) + } + strings.write_byte(sb, '\n') +} + +write_func_type :: proc(sb: ^strings.Builder, t: Func_Type) { + strings.write_byte(sb, '(') + for p, i in t.params { + if i > 0 { strings.write_string(sb, ", ") } + strings.write_string(sb, valtype_name(p)) + } + strings.write_string(sb, ") -> ") + strings.write_byte(sb, '(') + for rt, i in t.results { + if i > 0 { strings.write_string(sb, ", ") } + strings.write_string(sb, valtype_name(rt)) + } + strings.write_byte(sb, ')') +} + +write_u64 :: proc(sb: ^strings.Builder, v: u64) { + if v == 0 { strings.write_byte(sb, '0'); return } + buf: [20]u8 + i := 0 + n := v + for n > 0 { buf[i] = '0' + u8(n % 10); n /= 10; i += 1 } + for j := i - 1; j >= 0; j -= 1 { strings.write_byte(sb, buf[j]) } +} + +write_padded :: proc(sb: ^strings.Builder, s: string, width: int) { + strings.write_string(sb, s) + for _ in len(s).. (reloc_groups: []Reloc_Group, err: Reader_Error) { + groups: [dynamic]Reloc_Group + groups.allocator = m.allocator + for sec in m.sections { + if !(sec.id == .CUSTOM && strings.has_prefix(sec.name, "reloc.")) { + continue + } + + r := reader(m.data[sec.offset:][:sec.size], 0) + _ = rd_name(&r) or_return // step past the custom-section name + target := Section_Id(rd_u32(&r) or_return) + count := rd_u32(&r) or_return + + out := make([]wasm.Relocation, int(count), m.allocator) + w := 0 + for _ in 0.. (wasm.Relocation_Type, bool) { + switch code { + case 0: return .FUNCTION_INDEX_LEB, true // R_WASM_FUNCTION_INDEX_LEB + case 1: return .TABLE_INDEX_SLEB, true // R_WASM_TABLE_INDEX_SLEB + case 2: return .TABLE_INDEX_I32, true // R_WASM_TABLE_INDEX_I32 + case 3: return .MEMORY_ADDR_LEB, true // R_WASM_MEMORY_ADDR_LEB + case 4: return .MEMORY_ADDR_SLEB, true // R_WASM_MEMORY_ADDR_SLEB + case 5: return .MEMORY_ADDR_I32, true // R_WASM_MEMORY_ADDR_I32 + case 6: return .TYPE_INDEX_LEB, true // R_WASM_TYPE_INDEX_LEB + case 7: return .GLOBAL_INDEX_LEB, true // R_WASM_GLOBAL_INDEX_LEB + case 20: return .TABLE_NUMBER_LEB, true // R_WASM_TABLE_NUMBER_LEB + } + return .NONE, false +} + +// MEMORY_ADDR_* (3,4,5) and the *_OFFSET_I32 (8,9) forms carry a trailing +// signed-LEB addend; the index-type relocations do not. +@(require_results) +reloc_has_addend :: proc(code: u8) -> bool { + switch code { + case 3, 4, 5, 8, 9: return true + } + return false +} + +@(require_results) +reloc_field_size :: proc(t: wasm.Relocation_Type) -> u8 { + #partial switch t { + case .TABLE_INDEX_I32, .MEMORY_ADDR_I32: + return 4 // 4-byte LE field + } + return 5 // 5-byte padded (S)LEB field +} diff --git a/core/rexcode/wasm/printer.odin b/core/rexcode/wasm/printer.odin index 8aa9b50ad..e449318c5 100644 --- a/core/rexcode/wasm/printer.odin +++ b/core/rexcode/wasm/printer.odin @@ -55,8 +55,6 @@ sbprint :: proc( sb: ^strings.Builder, instructions: []Instruction, inst_info: []Instruction_Info, - label_defs: []Label_Definition, - tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, ) { @@ -98,7 +96,7 @@ sbprint :: proc( write_decimal_u32(sb, u32(bb)) } case: - for slot in 0.. string { sb := strings.builder_make(allocator) - sbprint(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + sbprint(&sb, instructions, inst_info, options, label_names) return strings.to_string(sb) } aprintln :: proc( - instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, - tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, + instructions: []Instruction, inst_info: []Instruction_Info, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, allocator := context.allocator, ) -> string { sb := strings.builder_make(allocator) - sbprintln(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + sbprintln(&sb, instructions, inst_info, options, label_names) return strings.to_string(sb) } tprint :: proc( - instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, - tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, + instructions: []Instruction, inst_info: []Instruction_Info, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, ) -> string { sb := strings.builder_make(context.temp_allocator) - sbprint(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + sbprint(&sb, instructions, inst_info, options, label_names) return strings.to_string(sb) } tprintln :: proc( - instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, - tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, + instructions: []Instruction, inst_info: []Instruction_Info, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, ) -> string { sb := strings.builder_make(context.temp_allocator) - sbprintln(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + sbprintln(&sb, instructions, inst_info, options, label_names) return strings.to_string(sb) } bprint :: proc( buf: []u8, - instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, - tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, + instructions: []Instruction, inst_info: []Instruction_Info, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, ) -> string { sb := strings.builder_from_bytes(buf) - sbprint(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + sbprint(&sb, instructions, inst_info, options, label_names) return strings.to_string(sb) } bprintln :: proc( buf: []u8, - instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, - tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, + instructions: []Instruction, inst_info: []Instruction_Info, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, ) -> string { sb := strings.builder_from_bytes(buf) - sbprintln(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + sbprintln(&sb, instructions, inst_info, options, label_names) return strings.to_string(sb) } fprint :: proc( fd: ^os.File, - instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, - tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, + instructions: []Instruction, inst_info: []Instruction_Info, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, ) { sb := strings.builder_make(context.temp_allocator) - sbprint(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + sbprint(&sb, instructions, inst_info, options, label_names) os.write_string(fd, strings.to_string(sb)) } fprintln :: proc( fd: ^os.File, - instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, - tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, + instructions: []Instruction, inst_info: []Instruction_Info, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, ) { sb := strings.builder_make(context.temp_allocator) - sbprintln(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + sbprintln(&sb, instructions, inst_info, options, label_names) os.write_string(fd, strings.to_string(sb)) } wprint :: proc( w: io.Writer, - instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, - tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, + instructions: []Instruction, inst_info: []Instruction_Info, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, ) { sb := strings.builder_make(context.temp_allocator) - sbprint(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + sbprint(&sb, instructions, inst_info, options, label_names) io.write_string(w, strings.to_string(sb)) } wprintln :: proc( w: io.Writer, - instructions: []Instruction, inst_info: []Instruction_Info, label_defs: []Label_Definition, - tokens: ^[dynamic]Token = nil, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, + instructions: []Instruction, inst_info: []Instruction_Info, options: ^Print_Options = nil, label_names: ^map[u32]string = nil, ) { sb := strings.builder_make(context.temp_allocator) - sbprintln(&sb, instructions, inst_info, label_defs, tokens, options, label_names) + sbprintln(&sb, instructions, inst_info, options, label_names) io.write_string(w, strings.to_string(sb)) } @@ -247,7 +229,6 @@ wprintln :: proc( // Internal writers // ============================================================================= -@(private="file") write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { name := MNEMONIC_NAMES[m] if name == "" { strings.write_string(sb, ""); return } @@ -265,7 +246,6 @@ write_mnemonic :: proc(sb: ^strings.Builder, m: Mnemonic, uppercase: bool) { } } -@(private="file") write_operand :: proc( sb: ^strings.Builder, op: ^Operand, @@ -293,19 +273,18 @@ write_operand :: proc( } case .MEMARG: - // WAT prints non-trivial memargs as `offset=N align=N` (omitting either - // when it is the natural default is a refinement; we print both). - strings.write_string(sb, "offset=") - write_decimal_u32(sb, op.memarg.offset) - strings.write_string(sb, " align=") + // WAT prints non-trivial memargs as `align=N offset=N` + // omitting either when it is the natural default is a refinement. + strings.write_string(sb, "align=") write_decimal_u32(sb, op.memarg.align) + strings.write_string(sb, " offset=") + write_decimal_u32(sb, op.memarg.offset) case .BLOCK_TYPE: write_block_type(sb, op.immediate) } } -@(private="file") write_block_type :: proc(sb: ^strings.Builder, v: i64) { switch Block_Type(v) { case .EMPTY: // no result annotation @@ -324,7 +303,6 @@ write_block_type :: proc(sb: ^strings.Builder, v: i64) { } } -@(private="file") write_heap_type :: proc(sb: ^strings.Builder, b: u8) { #partial switch Value_Type(b) { case .FUNCREF: strings.write_string(sb, "func") @@ -334,7 +312,6 @@ write_heap_type :: proc(sb: ^strings.Builder, b: u8) { } } -@(private="file") write_float :: proc(sb: ^strings.Builder, op: ^Operand) { buf: [40]u8 if op.size == 4 { @@ -348,7 +325,6 @@ write_float :: proc(sb: ^strings.Builder, op: ^Operand) { } } -@(private="file") write_label :: proc( sb: ^strings.Builder, label_id: u32, @@ -357,15 +333,15 @@ write_label :: proc( ) { if label_names != nil { if name, ok := label_names^[label_id]; ok { - strings.write_string(sb, name) + strings.write_string(sb, "$") + strings.write_quoted_string(sb, name) return } } - strings.write_string(sb, opts.label_prefix) + strings.write_string(sb, "$") write_decimal_u32(sb, label_id) } -@(private="file") write_decimal_u32 :: proc(sb: ^strings.Builder, v: u32) { if v == 0 { strings.write_byte(sb, '0') @@ -383,7 +359,6 @@ write_decimal_u32 :: proc(sb: ^strings.Builder, v: u32) { } } -@(private="file") write_signed_decimal :: proc(sb: ^strings.Builder, v: i64) { if v < 0 { strings.write_byte(sb, '-') @@ -393,7 +368,6 @@ write_signed_decimal :: proc(sb: ^strings.Builder, v: i64) { } } -@(private="file") write_decimal_u64 :: proc(sb: ^strings.Builder, v: u64) { if v == 0 { strings.write_byte(sb, '0') From bd89538ca25c91cdef0be3594dbf24035663613c Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 17 Jun 2026 12:03:31 +0100 Subject: [PATCH 22/27] Inline procedures which are only used once --- core/rexcode/wasm/module/print.odin | 122 +++++++++++++--------------- 1 file changed, 57 insertions(+), 65 deletions(-) diff --git a/core/rexcode/wasm/module/print.odin b/core/rexcode/wasm/module/print.odin index 8351cda90..17a0d0dbe 100644 --- a/core/rexcode/wasm/module/print.odin +++ b/core/rexcode/wasm/module/print.odin @@ -14,8 +14,24 @@ print_module :: proc(m: Module) { } sbprint_module :: proc(sb: ^strings.Builder, m: Module) { + write_func_type :: proc(sb: ^strings.Builder, t: Func_Type) { + strings.write_byte(sb, '(') + for p, i in t.params { + if i > 0 { strings.write_string(sb, ", ") } + strings.write_string(sb, valtype_name(p)) + } + strings.write_string(sb, ") -> ") + strings.write_byte(sb, '(') + for rt, i in t.results { + if i > 0 { strings.write_string(sb, ", ") } + strings.write_string(sb, valtype_name(rt)) + } + strings.write_byte(sb, ')') + } + + strings.write_string(sb, "WebAssembly Module, Version: ") - write_u64(sb, u64(m.version)) + strings.write_u64(sb, u64(m.version)) strings.write_byte(sb, '\n') label_names: map[u32]string @@ -31,6 +47,13 @@ sbprint_module :: proc(sb: ^strings.Builder, m: Module) { // sections for sec in m.sections { + write_padded :: proc(sb: ^strings.Builder, s: string, width: int) { + strings.write_string(sb, s) + for _ in len(s).. 1 { + strings.write_u64(sb, u64(g.count)) + strings.write_string(sb, "x") + } + strings.write_string(sb, valtype_name(g.type)) + } + strings.write_byte(sb, '\n') + } + + if f.body_size != 0 { + tmp_sb: strings.Builder + defer strings.builder_destroy(&tmp_sb) + text := sbprint_function(&tmp_sb, m, f, func_relocs, &label_names) + for line in strings.split_lines_iterator(&text) { + if line == "" { + continue + } + strings.write_string(sb, " ") + strings.write_string(sb, line) + strings.write_byte(sb, '\n') + } + } } } // Disassemble and print one function body. Returns the empty string for // imported functions (which have no body). -aprint_function :: proc(m: Module, f: Function, relocs: []wasm.Relocation, label_names: ^map[u32]string, allocator := context.allocator) -> string { +sbprint_function :: proc(sb: ^strings.Builder, m: Module, f: Function, relocs: []wasm.Relocation, label_names: ^map[u32]string) -> string { if f.imported || f.body_size == 0 { return "" } @@ -181,61 +228,6 @@ aprint_function :: proc(m: Module, f: Function, relocs: []wasm.Relocation, label defer delete(errs) wasm.decode(body, relocs, &insts, &info, &errs) - return wasm.aprint(insts[:], info[:], allocator=allocator, label_names=label_names) -} - -write_body :: proc(sb: ^strings.Builder, m: Module, f: Function, relocs: []wasm.Relocation, label_names: ^map[u32]string) { - if f.body_size == 0 { return } - text := aprint_function(m, f, relocs, label_names, context.temp_allocator) - for line in strings.split_lines_iterator(&text) { - if line == "" { - continue - } - strings.write_string(sb, " ") - strings.write_string(sb, line) - strings.write_byte(sb, '\n') - } -} - -write_locals :: proc(sb: ^strings.Builder, locals: []Local_Group) { - if len(locals) == 0 { return } - strings.write_string(sb, " locals:") - for g in locals { - strings.write_byte(sb, ' ') - if g.count > 1 { - write_u64(sb, u64(g.count)) - strings.write_string(sb, "x") - } - strings.write_string(sb, valtype_name(g.type)) - } - strings.write_byte(sb, '\n') -} - -write_func_type :: proc(sb: ^strings.Builder, t: Func_Type) { - strings.write_byte(sb, '(') - for p, i in t.params { - if i > 0 { strings.write_string(sb, ", ") } - strings.write_string(sb, valtype_name(p)) - } - strings.write_string(sb, ") -> ") - strings.write_byte(sb, '(') - for rt, i in t.results { - if i > 0 { strings.write_string(sb, ", ") } - strings.write_string(sb, valtype_name(rt)) - } - strings.write_byte(sb, ')') -} - -write_u64 :: proc(sb: ^strings.Builder, v: u64) { - if v == 0 { strings.write_byte(sb, '0'); return } - buf: [20]u8 - i := 0 - n := v - for n > 0 { buf[i] = '0' + u8(n % 10); n /= 10; i += 1 } - for j := i - 1; j >= 0; j -= 1 { strings.write_byte(sb, buf[j]) } -} - -write_padded :: proc(sb: ^strings.Builder, s: string, width: int) { - strings.write_string(sb, s) - for _ in len(s).. Date: Wed, 17 Jun 2026 12:14:06 +0100 Subject: [PATCH 23/27] Minor reorganization --- core/rexcode/wasm/module/module.odin | 1 + core/rexcode/wasm/module/print.odin | 5 ++--- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/core/rexcode/wasm/module/module.odin b/core/rexcode/wasm/module/module.odin index cd371721b..a12ab48d9 100644 --- a/core/rexcode/wasm/module/module.odin +++ b/core/rexcode/wasm/module/module.odin @@ -76,6 +76,7 @@ Function :: struct { type_index: u32, type: Func_Type, // resolved signature ({} if the type id was out of range) imported: bool, + exported: bool, name: string, // export / name-section / import field (borrowed) import_module: string, // borrowed, "" for defined functions import_field: string, // borrowed, "" for defined functions diff --git a/core/rexcode/wasm/module/print.odin b/core/rexcode/wasm/module/print.odin index 17a0d0dbe..0d9ee5055 100644 --- a/core/rexcode/wasm/module/print.odin +++ b/core/rexcode/wasm/module/print.odin @@ -42,8 +42,7 @@ sbprint_module :: proc(sb: ^strings.Builder, m: Module) { } } - relocs_group, _ := parse_relocations(m, m.allocator) - defer delete(relocs_group, m.allocator) + relocs_group, _ := parse_relocations(m, context.temp_allocator) // sections for sec in m.sections { @@ -173,7 +172,7 @@ sbprint_module :: proc(sb: ^strings.Builder, m: Module) { write_func_type(sb, f.type) if f.imported { - strings.write_string(sb, " @ import ") + strings.write_string(sb, "\n import ") strings.write_quoted_string(sb, f.import_module) strings.write_string(sb, " ") strings.write_quoted_string(sb, f.import_field) From b5810fea69033491e1c6a0e182f914cac0d7c594 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 17 Jun 2026 12:17:04 +0100 Subject: [PATCH 24/27] Remove dead parameters --- core/rexcode/wasm/encoder.odin | 2 -- 1 file changed, 2 deletions(-) diff --git a/core/rexcode/wasm/encoder.odin b/core/rexcode/wasm/encoder.odin index df9d63a1b..d87f1a792 100644 --- a/core/rexcode/wasm/encoder.odin +++ b/core/rexcode/wasm/encoder.odin @@ -40,8 +40,6 @@ encode :: proc( code: []u8, relocs: ^[dynamic]Relocation, errors: ^[dynamic]Error, - resolve: bool = true, - base_address: u64 = 0, ) -> (byte_count: u32, ok: bool) { errors_start := u32(len(errors)) From 5670aa7604501471d01931c6b59146fd32e09751 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 17 Jun 2026 12:24:25 +0100 Subject: [PATCH 25/27] Minor changes --- core/rexcode/wasm/decoder.odin | 40 ++++++++++++++------------- core/rexcode/wasm/encoder.odin | 6 ++-- core/rexcode/wasm/encoding_types.odin | 12 +++++--- 3 files changed, 32 insertions(+), 26 deletions(-) diff --git a/core/rexcode/wasm/decoder.odin b/core/rexcode/wasm/decoder.odin index 6d1aa2fd1..c58516d6e 100644 --- a/core/rexcode/wasm/decoder.odin +++ b/core/rexcode/wasm/decoder.odin @@ -78,7 +78,6 @@ decode_one :: proc( return } - // --- opcode (and optional misc sub-opcode) ------------------------------ b0 := data[off] off += 1 @@ -111,7 +110,6 @@ decode_one :: proc( inst.mnemonic = m inst.flags = {} - // --- immediates --------------------------------------------------------- slot := 0 for k, ki in form.imm { switch k { @@ -120,37 +118,39 @@ decode_one :: proc( case .BLOCKTYPE: v := read_sleb(data, &off) or_return - inst.ops[slot] = Operand{immediate = v, kind = .BLOCK_TYPE} + inst.ops[slot] = Operand{kind = .BLOCK_TYPE, immediate = v} slot += 1 case .I32: v := read_sleb(data, &off) or_return - inst.ops[slot] = Operand{immediate = v, kind = .IMMEDIATE, size = 4} + inst.ops[slot] = Operand{kind = .IMMEDIATE, immediate = v, size = 4} slot += 1 case .I64: v := read_sleb(data, &off) or_return - inst.ops[slot] = Operand{immediate = v, kind = .IMMEDIATE, size = 8} + inst.ops[slot] = Operand{kind = .IMMEDIATE, immediate = v, size = 8} slot += 1 case .F32: - bits := read_u32le(data, &off) or_return + bits := read_u32_block(data, &off) or_return inst.ops[slot] = Operand{ - immediate = i64(bits), kind = .IMMEDIATE, size = 4, flags = {is_float = true}, + kind = .IMMEDIATE, + immediate = i64(bits), size = 4, flags = {is_float = true}, } slot += 1 case .F64: - bits := read_u64le(data, &off) or_return + bits := read_u64_block(data, &off) or_return inst.ops[slot] = Operand{ - immediate = i64(bits), kind = .IMMEDIATE, size = 8, flags = {is_float = true}, + kind = .IMMEDIATE, + immediate = i64(bits), size = 8, flags = {is_float = true}, } slot += 1 case .IDX: field := off raw := read_uleb(data, &off) or_return - op := Operand{index = u32(raw), kind = .INDEX, idx_kind = idx_kind_for(m, ki)} + op := Operand{kind = .INDEX, index = u32(raw), idx_kind = idx_kind_for(m, ki)} if lid, found := reloc_label_at(relocs, field); found { op.index = lid op.flags.symbolic = true @@ -162,9 +162,11 @@ decode_one :: proc( slot += 1 case .MEMARG: + // TODO(bill): Is this fully correct? + // See: https://webassembly.github.io/spec/core/binary/instructions.html#memory-instructions align := read_uleb(data, &off) or_return offset := read_uleb(data, &off) or_return - inst.ops[slot] = Operand{memarg = Memarg{align = u32(align), offset = u32(offset)}, kind = .MEMARG} + inst.ops[slot] = Operand{kind = .MEMARG, memarg = Memarg{align = u32(align), offset = u32(offset)}} slot += 1 case .REFTYPE: @@ -174,7 +176,7 @@ decode_one :: proc( } t := data[off] off += 1 - inst.ops[slot] = Operand{immediate = i64(t), kind = .IMMEDIATE, size = 1} + inst.ops[slot] = Operand{kind = .IMMEDIATE, immediate = i64(t), size = 1} slot += 1 case .BR_TABLE: @@ -186,7 +188,7 @@ decode_one :: proc( } def := read_uleb(data, &off) or_return inst.targets = targets - inst.ops[slot] = Operand{index = u32(def), kind = .INDEX, idx_kind = .LABEL} + inst.ops[slot] = Operand{kind = .INDEX, index = u32(def), idx_kind = .LABEL} slot += 1 case .ZERO_BYTE: @@ -194,7 +196,7 @@ decode_one :: proc( next = pc return } - off += 1 // reserved 0x00, consumes no operand + off += 1 // reserved 0x00, consumes no operand case .LANE: if off >= u32(len(data)) { @@ -203,7 +205,7 @@ decode_one :: proc( } l := data[off] off += 1 - inst.ops[slot] = Operand{immediate = i64(l), kind = .IMMEDIATE, size = 1} + inst.ops[slot] = Operand{kind = .IMMEDIATE, immediate = i64(l), size = 1} slot += 1 case .LANES16: @@ -211,8 +213,8 @@ decode_one :: proc( next = pc return } - copy(inst.bytes[:], data[off:off + 16]) - off += 16 // value lives in inst.bytes, no operand + copy(inst.bytes[:], data[off:][:16]) + off += 16 // value lives in inst.bytes, no operand } } @@ -231,11 +233,11 @@ idx_kind_for :: #force_inline proc "contextless" (m: Mnemonic, which: int) -> In #partial switch m { case .BR, .BR_IF: return .LABEL case .CALL, .REF_FUNC: return .FUNC - case .CALL_INDIRECT: return which == 0 ? .TYPE : .TABLE + case .CALL_INDIRECT: return .TYPE if which == 0 else .TABLE case .LOCAL_GET, .LOCAL_SET, .LOCAL_TEE: return .LOCAL case .GLOBAL_GET, .GLOBAL_SET: return .GLOBAL case .MEMORY_INIT, .DATA_DROP: return .DATA - case .TABLE_INIT: return which == 0 ? .ELEM : .TABLE + case .TABLE_INIT: return .ELEM if which == 0 else .TABLE case .ELEM_DROP: return .ELEM case .TABLE_COPY: return .TABLE case .TABLE_GROW, .TABLE_SIZE, .TABLE_FILL: return .TABLE diff --git a/core/rexcode/wasm/encoder.odin b/core/rexcode/wasm/encoder.odin index d87f1a792..6c0ef0c81 100644 --- a/core/rexcode/wasm/encoder.odin +++ b/core/rexcode/wasm/encoder.odin @@ -54,7 +54,7 @@ encode :: proc( } -encode_one :: #force_inline proc( +encode_one :: proc( inst: ^Instruction, pc: u32, inst_idx: u16, @@ -96,10 +96,10 @@ encode_one :: #force_inline proc( write_sleb(code, &off, inst.ops[opi].immediate) opi += 1 case .F32: - write_u32le(code, &off, u32(inst.ops[opi].immediate)) + write_u32_block(code, &off, u32(inst.ops[opi].immediate)) opi += 1 case .F64: - write_u64le(code, &off, u64(inst.ops[opi].immediate)) + write_u64_block(code, &off, u64(inst.ops[opi].immediate)) opi += 1 case .IDX: op := &inst.ops[opi] diff --git a/core/rexcode/wasm/encoding_types.odin b/core/rexcode/wasm/encoding_types.odin index 76d35fec0..9a3a5fc8f 100644 --- a/core/rexcode/wasm/encoding_types.odin +++ b/core/rexcode/wasm/encoding_types.odin @@ -146,6 +146,7 @@ sleb_size :: #force_inline proc "contextless" (value: i64) -> u32 { // Read unsigned LEB128 starting at `*offset`; advances it. `ok` is false on // truncation. Reads at most `max` bytes (10 covers u64). +@(require_results) read_uleb :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (value: u64, ok: bool) { shift: uint = 0 for i := 0; i < 10 && offset^ < u32(len(data)); i += 1 { @@ -161,6 +162,7 @@ read_uleb :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (val } // Read signed LEB128 starting at `*offset`; advances it. +@(require_results) read_sleb :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (value: i64, ok: bool) { shift: uint = 0 b: u8 = 0 @@ -180,7 +182,7 @@ read_sleb :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (val return } -write_u32le :: #force_inline proc(code: []u8, offset: ^u32, v: u32) { +write_u32_block :: #force_inline proc(code: []u8, offset: ^u32, v: u32) { assert(offset^+ 4 <= u32(len(code))) code[offset^+0] = u8(v) code[offset^+1] = u8(v >> 8) @@ -189,7 +191,7 @@ write_u32le :: #force_inline proc(code: []u8, offset: ^u32, v: u32) { offset^ += 4 } -write_u64le :: #force_inline proc(code: []u8, offset: ^u32, v: u64) { +write_u64_block :: #force_inline proc(code: []u8, offset: ^u32, v: u64) { assert(offset^+ 8 <= u32(len(code))) for i in u32(0)..<8 { code[offset^+i] = u8(v >> (8 * i)) @@ -197,7 +199,8 @@ write_u64le :: #force_inline proc(code: []u8, offset: ^u32, v: u64) { offset^ += 8 } -read_u32le :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (u32, bool) { +@(require_results) +read_u32_block :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (u32, bool) { if offset^ + 4 > u32(len(data)) { return 0, false } @@ -209,7 +212,8 @@ read_u32le :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (u3 return v, true } -read_u64le :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (u64, bool) { +@(require_results) +read_u64_block :: #force_inline proc "contextless" (data: []u8, offset: ^u32) -> (u64, bool) { if offset^ + 8 > u32(len(data)) { return 0, false } From 53fe1938688233a0a48fdaf86d5a17dfbf1fac38 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 17 Jun 2026 12:39:45 +0100 Subject: [PATCH 26/27] Use log2 for the alignment, remove unneeded code --- core/rexcode/wasm/decoder.odin | 2 ++ core/rexcode/wasm/encoder.odin | 7 +++- core/rexcode/wasm/printer.odin | 64 ++++++---------------------------- 3 files changed, 19 insertions(+), 54 deletions(-) diff --git a/core/rexcode/wasm/decoder.odin b/core/rexcode/wasm/decoder.odin index c58516d6e..30a4abebb 100644 --- a/core/rexcode/wasm/decoder.odin +++ b/core/rexcode/wasm/decoder.odin @@ -166,6 +166,8 @@ decode_one :: proc( // See: https://webassembly.github.io/spec/core/binary/instructions.html#memory-instructions align := read_uleb(data, &off) or_return offset := read_uleb(data, &off) or_return + // NOTE(bill) this appears to be stored as log2 even though the docs say otherwise + align = 1< 0; i += 1 { - buf[i] = '0' + u8(n % 10) - n /= 10 - } - for j := i - 1; j >= 0; j -= 1 { - strings.write_byte(sb, buf[j]) - } -} - -write_signed_decimal :: proc(sb: ^strings.Builder, v: i64) { - if v < 0 { - strings.write_byte(sb, '-') - write_decimal_u64(sb, u64(-(v + 1)) + 1) - } else { - write_decimal_u64(sb, u64(v)) - } -} - -write_decimal_u64 :: proc(sb: ^strings.Builder, v: u64) { - if v == 0 { - strings.write_byte(sb, '0') - return - } - buf: [20]u8 - i := 0 - for n := v; n > 0; i += 1 { - buf[i] = '0' + u8(n % 10) - n /= 10 - } - for j := i - 1; j >= 0; j -= 1 { - strings.write_byte(sb, buf[j]) - } -} + strings.write_u64(sb, u64(label_id)) +} \ No newline at end of file From b6fdabc874ca6cd7bb90378a539f34cc7547f5be Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 17 Jun 2026 13:42:26 +0100 Subject: [PATCH 27/27] Parse `custom` sections `target_features` and `name` --- core/rexcode/wasm/module/module.odin | 53 +++++++++++++++ core/rexcode/wasm/module/parse.odin | 96 ++++++++++++++++++++++++++++ core/rexcode/wasm/module/print.odin | 44 +++++++++++-- 3 files changed, 188 insertions(+), 5 deletions(-) diff --git a/core/rexcode/wasm/module/module.odin b/core/rexcode/wasm/module/module.odin index a12ab48d9..a9706ee74 100644 --- a/core/rexcode/wasm/module/module.odin +++ b/core/rexcode/wasm/module/module.odin @@ -90,6 +90,7 @@ Function :: struct { Module :: struct { version: u32, sections: []Section, + customs: []Custom_Section, types: []Func_Type, imports: []Import, functions: []Function, // whole function index space (imports + defined) @@ -101,6 +102,58 @@ Module :: struct { allocator: runtime.Allocator, } + + +// ----------------------------------------------------------------------------- +// Custom Section Layout +// ----------------------------------------------------------------------------- + +Custom_Section :: struct { + section: Section, + variant: union { + Custom_Section_Name, + Custom_Section_Target_Features, + }, +} + +Custom_Section_Name_Function :: struct { + id: u32, + name: string, // borrowed +} + +Custom_Section_Name_Local :: struct { + idx: u32, + name: string, // borrowed +} + +Custom_Section_Name_Function_Locals :: struct { + func_idx: u32, + locals: []Custom_Section_Name_Local, +} + +Custom_Section_Name :: struct { + module_name: string, + functions: []Custom_Section_Name_Function, + locals: []Custom_Section_Name_Function_Locals, +} + +Custom_Section_Target_Feature_Prefix :: enum u8 { + Used = '+', + Disallowed = '-', + Required = '=', +} + +Custom_Section_Target_Feature :: struct { + prefix: Custom_Section_Target_Feature_Prefix, + feature: string, // borrowed +} + + +Custom_Section_Target_Features :: struct { + features: []Custom_Section_Target_Feature, +} + + // ----------------------------------------------------------------------------- // Small display helpers // ----------------------------------------------------------------------------- diff --git a/core/rexcode/wasm/module/parse.odin b/core/rexcode/wasm/module/parse.odin index 44dfc3f89..b4cd4ae99 100644 --- a/core/rexcode/wasm/module/parse.odin +++ b/core/rexcode/wasm/module/parse.odin @@ -191,6 +191,9 @@ parse :: proc(data: []u8, allocator := context.allocator) -> (m: Module, err: Re } } + parse_custom_sections(&m, allocator) or_return + + build_functions(&m, func_typeidx, codes, allocator) or_return apply_name_section(&m) return @@ -289,6 +292,86 @@ parse_code :: proc(r: ^Reader, allocator: runtime.Allocator) -> (out: []Code_Bod return } +@(require_results) +parse_custom_sections :: proc(m: ^Module, allocator: runtime.Allocator) -> Reader_Error { + custom_count := 0 + for &sec in m.sections { + if sec.id == .CUSTOM { + custom_count += 1 + } + } + m.customs = make([]Custom_Section, custom_count, allocator) or_return + custom_index := 0 + for &sec in m.sections { + if sec.id != .CUSTOM { + continue + } + + custom := &m.customs[custom_index] + custom_index += 1 + + custom.section = sec + + section_data := m.data[sec.offset:][:sec.size] + r := reader(section_data, 0) + sec_name := rd_name(&r) or_continue + assert(sec_name == sec.name) + + custom_block: switch sec.name { + case "name": + cname: Custom_Section_Name + defer custom.variant = cname + + for r.off < u32(len(r.data)) { + id := rd_byte(&r) or_return + size := rd_u32(&r) or_return + end_off := r.off+size + defer r.off = end_off + + switch id { + case 0: // module + cname.module_name = rd_name(&r) or_return + case 1: // functions + count := rd_u32(&r) or_return + cname.functions = make([]Custom_Section_Name_Function, count, allocator) or_return + for &func in cname.functions { + func.id = rd_u32(&r) or_return + func.name = rd_name(&r) or_return + } + case 2: // locals + count := rd_u32(&r) or_return + + cname.locals = make([]Custom_Section_Name_Function_Locals, count, allocator) or_return + + for &local_func in cname.locals { + local_func.func_idx = rd_u32(&r) or_return + local_count := rd_u32(&r) or_return + local_func.locals = make([]Custom_Section_Name_Local, local_count, allocator) or_return + for &local in local_func.locals { + local.idx = rd_u32(&r) or_return + local.name = rd_name(&r) or_return + } + } + } + } + + case "target_features": + target_features: Custom_Section_Target_Features + defer custom.variant = target_features + + count := rd_u32(&r) or_return + target_features.features = make([]Custom_Section_Target_Feature, count, allocator) or_return + + for &feature in target_features.features { + feature.prefix = Custom_Section_Target_Feature_Prefix(rd_byte(&r) or_return) + feature.feature = rd_name(&r) or_return + } + } + } + + return nil +} + @(require_results) build_functions :: proc(m: ^Module, func_typeidx: []u32, codes: []Code_Body, allocator: runtime.Allocator) -> runtime.Allocator_Error { num_imports := 0 @@ -393,6 +476,19 @@ module_destroy :: proc(m: ^Module) { delete(f.locals, m.allocator) } } + for c in m.customs { + switch v in c.variant { + case Custom_Section_Name: + for function_locals in v.locals { + delete(function_locals.locals, m.allocator) + } + delete(v.functions, m.allocator) + delete(v.locals, m.allocator) + case Custom_Section_Target_Features: + delete(v.features) + } + } + delete(m.customs, m.allocator) delete(m.sections, m.allocator) delete(m.types, m.allocator) delete(m.imports, m.allocator) diff --git a/core/rexcode/wasm/module/print.odin b/core/rexcode/wasm/module/print.odin index 0d9ee5055..59d7b5da8 100644 --- a/core/rexcode/wasm/module/print.odin +++ b/core/rexcode/wasm/module/print.odin @@ -5,12 +5,12 @@ import "core:os" import "core:fmt" import wasm "../" -print_module :: proc(m: Module) { +print_module :: proc(m: Module, file: ^os.File) { sb := strings.builder_make(context.allocator) defer strings.builder_destroy(&sb) sbprint_module(&sb, m) s := strings.to_string(sb) - os.write_string(os.stdout, s) + os.write_string(file, s) } sbprint_module :: proc(sb: ^strings.Builder, m: Module) { @@ -69,11 +69,45 @@ sbprint_module :: proc(sb: ^strings.Builder, m: Module) { } strings.write_byte(sb, '\n') - data := m.data[sec.offset:][:sec.size] + section_data := m.data[sec.offset:][:sec.size] section_printing: #partial switch sec.id { + case .CUSTOM: + for c in m.customs { + if c.section != sec { + continue + } + switch v in c.variant { + case Custom_Section_Name: + if v.module_name != "" { + fmt.sbprintf(sb, " module: %q\n", v.module_name) + } + if len(v.functions) > 0 { + fmt.sbprintf(sb, " functions:\n") + for f in v.functions { + fmt.sbprintf(sb, " [%d] %q\n", f.id, f.name) + } + } + if len(v.locals) > 0 { + fmt.sbprintf(sb, " locals:\n") + for fl in v.locals { + fmt.sbprintf(sb, " [%d] function\n", fl.func_idx) + for local in fl.locals { + fmt.sbprintf(sb, " [%d] %q\n", local.idx, local.name) + } + } + } + case Custom_Section_Target_Features: + for f in v.features { + fmt.sbprintf(sb, " \"%c%s\"\n", u8(f.prefix), f.feature) + } + } + break + } + strings.write_byte(sb, '\n') + case .DATA: - r := reader(data, 0) + r := reader(section_data, 0) count := rd_u32(&r) or_break section_printing assert(count == sec.count) for i in 0..