From bda4c2cd959763ef7606c2883d95c7cd556c5377 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 19 Aug 2026 16:44:19 +0100 Subject: [PATCH 1/3] Merge `ENCODING_TABLE` and `CLOBBER_TABLE` into a single `INSTRUCTION_TABLE` --- .../isa/x86/tablegen/clobber_table.odin | 5041 --------------- .../isa/x86/tablegen/encoding_table.odin | 5416 ++++++++--------- core/rexcode/isa/x86/tablegen/gen.odin | 18 +- 3 files changed, 2673 insertions(+), 7802 deletions(-) delete mode 100644 core/rexcode/isa/x86/tablegen/clobber_table.odin diff --git a/core/rexcode/isa/x86/tablegen/clobber_table.odin b/core/rexcode/isa/x86/tablegen/clobber_table.odin deleted file mode 100644 index a3348447a..000000000 --- a/core/rexcode/isa/x86/tablegen/clobber_table.odin +++ /dev/null @@ -1,5041 +0,0 @@ -// clobber_table.odin -- PER-FORM side-effect table for rexcode_x86_tablegen -// -// Type: [Mnemonic][]x86.Clobber (parallel to [Mnemonic][]Encoding) -// -// HOW EACH FORM IS SPECIALISED FROM THE UNION: -// 1. Implicit-operand normalisation. An operand that is an implicit register -// (AL/AX/EAX/RAX_IMPL -> RAX, CL_IMPL -> RCX, XMM0_IMPL -> XMM0, -// ST0_IMPL -> FPU_ST) or an implicit constant (ONE_IMPL) is removed from the -// OP0.3 slot set and, if that slot was written/read, folded into -// implicit_wr/implicit_rd. Registers that are implicit but NOT tied to an -// operand (RSP for the stack, RSI/RDI/RCX for strings, RDX for MULX, ...) -// are inherent and kept on every form. -// 2. Slot trimming. OP slots that are .NONE in a given form are dropped from -// written/read. -// 3. Per-form memory. writes_mem/reads_mem keep the union's DIRECTION but are -// asserted on a form only when that form actually carries a memory-capable -// operand, OR the instruction addresses memory implicitly (stack, string, -// XLAT table, MASKMOVDQU/[rDI] store, VMCS). Consequently register-only -// forms of otherwise-memory instructions (e.g. MOV r,imm; FADD ST(0),ST(i); -// FST ST(i); MOVLHPS; PEXTRW r32,xmm) no longer carry the blanket memory -// flag the union used. Shadow-stack accesses are not implicit: the -// shadow-stack instructions that touch memory (WRSS/WRUSS/RSTORSSP/CLRSSBSY) -// all do so through an explicit m64 operand and are covered by the -// memory-capable-operand branch above. -// 4. Family splits that the union could only approximate: -// IMUL -- 1-operand form writes RDX:RAX implicitly (r/m8 -> AX only); -// 2-operand form is OP0 *= OP1; 3-operand form is OP0 = OP1 * imm -// (OP0 not read); neither multi-operand form touches RAX/RDX. -// MUL/DIV/IDIV -- the r/m8 form uses the A-register only and does not -// touch (R)DX. -// SHL/SHR/SAR/ROL/ROR/RCL/RCR/SHLD/SHRD -- only the CL form reads RCX; -// the 1/imm8 forms do not. -// Flags and side_effects are uniform across a mnemonic's forms and are carried -// through unchanged, EXCEPT where a single mnemonic aliases two distinct -// instructions: MOVSD and CMPSD each name both a string operation and an SSE -// scalar-double operation, so their string form and their SSE form carry -// different flags and side_effects. -// -// INVARIANT preserved: a form is a freely-eliminable no-op iff every clobber set -// is empty AND side_effects == {} (only .NOP and the .INVALID sentinel qualify). - -package rexcode_x86_tablegen - -import "core:rexcode/isa/x86" - -@(rodata) -CLOBBER_TABLE := [Mnemonic][]x86.Clobber{ - .INVALID = {}, - - - // 8.1 Data Transfer Encodings - .MOV = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .MOVABS = { - {written={0}, read={1}}, - {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}, - {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}, - }, - .MOVZX = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .MOVSX = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .MOVSXD = { - {written={0}, read={1}, reads_mem=true}, - }, - .XCHG = { // asserts LOCK when a mem operand is used - {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}, - {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, - {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, - {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, - {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}, - }, - .PUSH = { - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}, - }, - .POP = { - {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}, - {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}, - }, - .LEA = { // no memory access: computes effective address only - {written={0}}, - {written={0}}, - {written={0}}, - }, - - // 8.2 Arithmetic Encodings - .ADD = { - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - }, - .ADC = { - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - }, - .SUB = { - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - }, - .SBB = { - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - }, - .MUL = { // RAX/RDX widths follow operand size (r/m8 -> AX only) - {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, - }, - .IMUL = { // union of forms: 1-op writes RDX:RAX (implicit); 2/3-op writes OP0, no implicit - {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-op r/m8: AX <- AL*r/m8 - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 1-operand form: RDX:RAX <- RAX * r/m - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 2-operand form: OP0 *= OP1 - {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}, // 3-operand form: OP0 = OP1 * imm (OP0 not read) - }, - .DIV = { // RDX:RAX = quotient/remainder; r/m8 uses AX only - {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .IDIV = { // RDX:RAX = quotient/remainder; r/m8 uses AX only - {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, // r/m8 form: A-register only, no (R)DX - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .INC = { // CF deliberately NOT affected - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - }, - .DEC = { // CF deliberately NOT affected - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}, - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - }, - .NEG = { - {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - }, - .CMP = { // no operand written; flags only - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - - // 8.3 Logical Encodings - .AND = { - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - }, - .OR = { - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - }, - .XOR = { - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - }, - .NOT = { - {written={0}, read={0}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, writes_mem=true, reads_mem=true}, - }, - .TEST = { // no operand written; flags only - {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}, - {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}, - }, - - // 8.4 Shift/Rotate Encodings - .SHL = { // OF defined only for 1-bit count; count==0 leaves flags unchanged - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - }, - .SHR = { // OF defined only for 1-bit count; count==0 leaves flags unchanged - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - }, - .SAR = { // OF defined only for 1-bit count; count==0 leaves flags unchanged - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}, - }, - .ROL = { // only CF/OF affected; count==0 leaves flags unchanged - {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - }, - .ROR = { // only CF/OF affected; count==0 leaves flags unchanged - {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}, - }, - .RCL = { - {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - }, - .RCR = { - {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}, - }, - .SHLD = { - {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - }, - .SHRD = { - {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}, - }, - - // 8.5 Bit Operation Encodings - .BT = { // ZF unaffected - {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - }, - .BTS = { // ZF unaffected - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - }, - .BTR = { // ZF unaffected - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - }, - .BTC = { // ZF unaffected - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}, - }, - .BSF = { // destination undefined when source == 0 - {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - }, - .BSR = { // destination undefined when source == 0 - {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}, - }, - .POPCNT = { // ZF per source; CF/OF/SF/AF/PF cleared - {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .LZCNT = { - {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - }, - .TZCNT = { - {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - }, - - // 8.6 Control Flow Encodings - .JMP = { // indirect forms read reg/mem; writes RIP - {read={0}, side_effects={.CONTROL}}, - {read={0}, side_effects={.CONTROL}}, - {read={0}, reads_mem=true, side_effects={.CONTROL}}, - {read={0}, reads_mem=true, side_effects={.CONTROL}}, - {read={0}, reads_mem=true, side_effects={.CONTROL}}, - {read={0}, reads_mem=true, side_effects={.CONTROL}}, - }, - .JA = { // reads flags; writes RIP on taken branch - {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, - {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, - }, - .JAE = { // reads flags; writes RIP on taken branch - {flags_rd={.CF}, side_effects={.CONTROL}}, - {flags_rd={.CF}, side_effects={.CONTROL}}, - }, - .JB = { // reads flags; writes RIP on taken branch - {flags_rd={.CF}, side_effects={.CONTROL}}, - {flags_rd={.CF}, side_effects={.CONTROL}}, - }, - .JBE = { // reads flags; writes RIP on taken branch - {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, - {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, - }, - .JC = { // reads flags; writes RIP on taken branch - {flags_rd={.CF}, side_effects={.CONTROL}}, - {flags_rd={.CF}, side_effects={.CONTROL}}, - }, - .JE = { // reads flags; writes RIP on taken branch - {flags_rd={.ZF}, side_effects={.CONTROL}}, - {flags_rd={.ZF}, side_effects={.CONTROL}}, - }, - .JZ = { // reads flags; writes RIP on taken branch - {flags_rd={.ZF}, side_effects={.CONTROL}}, - {flags_rd={.ZF}, side_effects={.CONTROL}}, - }, - .JG = { // reads flags; writes RIP on taken branch - {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, - {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, - }, - .JGE = { // reads flags; writes RIP on taken branch - {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, - {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, - }, - .JL = { // reads flags; writes RIP on taken branch - {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, - {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, - }, - .JLE = { // reads flags; writes RIP on taken branch - {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, - {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, - }, - .JNA = { // reads flags; writes RIP on taken branch - {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, - {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, - }, - .JNAE = { // reads flags; writes RIP on taken branch - {flags_rd={.CF}, side_effects={.CONTROL}}, - {flags_rd={.CF}, side_effects={.CONTROL}}, - }, - .JNB = { // reads flags; writes RIP on taken branch - {flags_rd={.CF}, side_effects={.CONTROL}}, - {flags_rd={.CF}, side_effects={.CONTROL}}, - }, - .JNBE = { // reads flags; writes RIP on taken branch - {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, - {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}, - }, - .JNC = { // reads flags; writes RIP on taken branch - {flags_rd={.CF}, side_effects={.CONTROL}}, - {flags_rd={.CF}, side_effects={.CONTROL}}, - }, - .JNE = { // reads flags; writes RIP on taken branch - {flags_rd={.ZF}, side_effects={.CONTROL}}, - {flags_rd={.ZF}, side_effects={.CONTROL}}, - }, - .JNZ = { // reads flags; writes RIP on taken branch - {flags_rd={.ZF}, side_effects={.CONTROL}}, - {flags_rd={.ZF}, side_effects={.CONTROL}}, - }, - .JNG = { // reads flags; writes RIP on taken branch - {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, - {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, - }, - .JNGE = { // reads flags; writes RIP on taken branch - {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, - {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, - }, - .JNL = { // reads flags; writes RIP on taken branch - {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, - {flags_rd={.SF, .OF}, side_effects={.CONTROL}}, - }, - .JNLE = { // reads flags; writes RIP on taken branch - {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, - {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}, - }, - .JNO = { // reads flags; writes RIP on taken branch - {flags_rd={.OF}, side_effects={.CONTROL}}, - {flags_rd={.OF}, side_effects={.CONTROL}}, - }, - .JNP = { // reads flags; writes RIP on taken branch - {flags_rd={.PF}, side_effects={.CONTROL}}, - {flags_rd={.PF}, side_effects={.CONTROL}}, - }, - .JNS = { // reads flags; writes RIP on taken branch - {flags_rd={.SF}, side_effects={.CONTROL}}, - {flags_rd={.SF}, side_effects={.CONTROL}}, - }, - .JO = { // reads flags; writes RIP on taken branch - {flags_rd={.OF}, side_effects={.CONTROL}}, - {flags_rd={.OF}, side_effects={.CONTROL}}, - }, - .JP = { // reads flags; writes RIP on taken branch - {flags_rd={.PF}, side_effects={.CONTROL}}, - {flags_rd={.PF}, side_effects={.CONTROL}}, - }, - .JPE = { // reads flags; writes RIP on taken branch - {flags_rd={.PF}, side_effects={.CONTROL}}, - {flags_rd={.PF}, side_effects={.CONTROL}}, - }, - .JPO = { // reads flags; writes RIP on taken branch - {flags_rd={.PF}, side_effects={.CONTROL}}, - {flags_rd={.PF}, side_effects={.CONTROL}}, - }, - .JS = { // reads flags; writes RIP on taken branch - {flags_rd={.SF}, side_effects={.CONTROL}}, - {flags_rd={.SF}, side_effects={.CONTROL}}, - }, - .JCXZ = { // reads CX - {implicit_rd={.RCX}, side_effects={.CONTROL}}, - }, - .JECXZ = { // reads ECX - {implicit_rd={.RCX}, side_effects={.CONTROL}}, - }, - .JRCXZ = { // reads RCX - {implicit_rd={.RCX}, side_effects={.CONTROL}}, - }, - .LOOP = { - {implicit_wr={.RCX}, implicit_rd={.RCX}, side_effects={.CONTROL}}, - }, - .LOOPE = { - {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, - }, - .LOOPNE = { - {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}, - }, - .CALL = { // pushes return address - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}, - }, - .RET = { // pops return address (+imm16 form adjusts RSP) - {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, - {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}, - }, - .IRET = { // pops RIP/CS/RFLAGS (privileged bits conditionally) - {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, - }, - .IRETD = { // pops RIP/CS/RFLAGS (privileged bits conditionally) - {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, - }, - .IRETQ = { // pops RIP/CS/RFLAGS (privileged bits conditionally) - {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}, - }, - .INT = { // pushes RFLAGS/CS/RIP; clears TF/IF via gate - {read={0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, - }, - .INT3 = { // pushes RFLAGS/CS/RIP; clears TF/IF via gate - {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, - }, - .INTO = { // #OF only if OF=1 - {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}, - }, - .SYSCALL = { // RCX<-RIP, R11<-RFLAGS; RFLAGS masked by IA32_FMASK - {implicit_wr={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.INTERRUPT, .CONTROL}}, - }, - .SYSRET = { // RIP<-RCX, RFLAGS<-R11 - {implicit_rd={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, - }, - .SYSENTER = { // privileged; RSP/RIP from MSRs - {implicit_wr={.RSP}, flags_wr={.IF}, side_effects={.INTERRUPT, .CONTROL}}, - }, - .SYSEXIT = { // privileged; RSP<-RDX/RCX, RIP<-RCX/RDX - {implicit_wr={.RSP}, implicit_rd={.RCX, .RDX}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}, - }, - - // 8.7 Conditional Set/Move Encodings - .SETA = { - {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, - }, - .SETAE = { - {written={0}, flags_rd={.CF}, writes_mem=true}, - }, - .SETB = { - {written={0}, flags_rd={.CF}, writes_mem=true}, - }, - .SETBE = { - {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, - }, - .SETC = { - {written={0}, flags_rd={.CF}, writes_mem=true}, - }, - .SETE = { - {written={0}, flags_rd={.ZF}, writes_mem=true}, - }, - .SETG = { - {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - }, - .SETGE = { - {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, - }, - .SETL = { - {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, - }, - .SETLE = { - {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - }, - .SETNA = { - {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, - }, - .SETNAE = { - {written={0}, flags_rd={.CF}, writes_mem=true}, - }, - .SETNB = { - {written={0}, flags_rd={.CF}, writes_mem=true}, - }, - .SETNBE = { - {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}, - }, - .SETNC = { - {written={0}, flags_rd={.CF}, writes_mem=true}, - }, - .SETNE = { - {written={0}, flags_rd={.ZF}, writes_mem=true}, - }, - .SETNG = { - {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - }, - .SETNGE = { - {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, - }, - .SETNL = { - {written={0}, flags_rd={.SF, .OF}, writes_mem=true}, - }, - .SETNLE = { - {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}, - }, - .SETNO = { - {written={0}, flags_rd={.OF}, writes_mem=true}, - }, - .SETNP = { - {written={0}, flags_rd={.PF}, writes_mem=true}, - }, - .SETNS = { - {written={0}, flags_rd={.SF}, writes_mem=true}, - }, - .SETNZ = { - {written={0}, flags_rd={.ZF}, writes_mem=true}, - }, - .SETO = { - {written={0}, flags_rd={.OF}, writes_mem=true}, - }, - .SETP = { - {written={0}, flags_rd={.PF}, writes_mem=true}, - }, - .SETPE = { - {written={0}, flags_rd={.PF}, writes_mem=true}, - }, - .SETPO = { - {written={0}, flags_rd={.PF}, writes_mem=true}, - }, - .SETS = { - {written={0}, flags_rd={.SF}, writes_mem=true}, - }, - .SETZ = { - {written={0}, flags_rd={.ZF}, writes_mem=true}, - }, - .CMOVA = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - }, - .CMOVAE = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - }, - .CMOVB = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - }, - .CMOVBE = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - }, - .CMOVC = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - }, - .CMOVE = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - }, - .CMOVG = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - }, - .CMOVGE = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - }, - .CMOVL = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - }, - .CMOVLE = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - }, - .CMOVNA = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - }, - .CMOVNAE = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - }, - .CMOVNB = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - }, - .CMOVNBE = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}, - }, - .CMOVNC = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}, - }, - .CMOVNE = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - }, - .CMOVNG = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - }, - .CMOVNGE = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - }, - .CMOVNL = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}, - }, - .CMOVNLE = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}, - }, - .CMOVNO = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, - }, - .CMOVNP = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - }, - .CMOVNS = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, - }, - .CMOVNZ = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - }, - .CMOVO = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}, - }, - .CMOVP = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - }, - .CMOVPE = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - }, - .CMOVPO = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}, - }, - .CMOVS = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}, - }, - .CMOVZ = { // conditional write of OP0 - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}, - }, - - // 8.8 String Operation Encodings - .MOVS = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - }, - .MOVSB = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - }, - .MOVSW = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - }, - .MOVSD = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - // SSE variants - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVSQ = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - }, - .CMPS = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - }, - .CMPSB = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - }, - .CMPSW = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - }, - .CMPSD = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CMPSQ = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - }, - .SCAS = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - }, - .SCASB = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - }, - .SCASW = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - }, - .SCASD = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - }, - .SCASQ = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}, - }, - .LODS = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, - }, - .LODSB = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, - }, - .LODSW = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, - }, - .LODSD = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, - }, - .LODSQ = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}, - }, - .STOS = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - }, - .STOSB = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - }, - .STOSW = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - }, - .STOSD = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - }, - .STOSQ = { // REP/REPZ/REPNZ forms read+write RCX - {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}, - }, - - // 8.9 Flag Operation Encodings - .CLC = { - {flags_wr={.CF}}, - }, - .STC = { - {flags_wr={.CF}}, - }, - .CMC = { - {flags_wr={.CF}, flags_rd={.CF}}, - }, - .CLD = { - {flags_wr={.DF}}, - }, - .STD = { - {flags_wr={.DF}}, - }, - .CLI = { - {flags_wr={.IF}}, - }, - .STI = { - {flags_wr={.IF}}, - }, - .LAHF = { // AH <- flags - {implicit_wr={.RAX}, flags_rd={.CF, .PF, .AF, .ZF, .SF}}, - }, - .SAHF = { // flags <- AH - {implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF}}, - }, - .PUSHF = { - {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, - }, - .PUSHFD = { - {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, - }, - .PUSHFQ = { - {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}, - }, - .POPF = { - {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, - }, - .POPFD = { - {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, - }, - .POPFQ = { - {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}, - }, - - // 8.10 Miscellaneous Encodings - .NOP = { // no register/flag/memory clobber - {}, - {}, - {}, - {}, - }, - .HLT = { // no register/flag/memory clobber - {side_effects={.HALT, .PRIVILEGED}}, - }, - .WAIT = { // waits on pending x87 exception - {implicit_rd={.FPU_SW}}, - }, - .LOCK = { // no register/flag/memory clobber - {side_effects={.FENCE}}, - }, - .UD0 = { // no register/flag/memory clobber - {side_effects={.TRAP}}, - }, - .UD1 = { // no register/flag/memory clobber - {side_effects={.TRAP}}, - }, - .UD2 = { // no register/flag/memory clobber - {side_effects={.TRAP}}, - }, - .CPUID = { - {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING}}, - }, - .RDTSC = { - {implicit_wr={.RAX, .RDX}}, - }, - .RDTSCP = { - {implicit_wr={.RAX, .RCX, .RDX}}, - }, - .RDPMC = { - {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, - }, - .XGETBV = { - {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, - }, - .XSETBV = { // privileged; writes XCR[ECX] - {implicit_rd={.RAX, .RCX, .RDX}}, - }, - .CBW = { - {implicit_wr={.RAX}, implicit_rd={.RAX}}, - }, - .CWDE = { - {implicit_wr={.RAX}, implicit_rd={.RAX}}, - }, - .CDQE = { - {implicit_wr={.RAX}, implicit_rd={.RAX}}, - }, - .CWD = { - {implicit_wr={.RDX}, implicit_rd={.RAX}}, - }, - .CDQ = { - {implicit_wr={.RDX}, implicit_rd={.RAX}}, - }, - .CQO = { - {implicit_wr={.RDX}, implicit_rd={.RAX}}, - }, - - // 8.11 BMI/ADX Encodings - .ANDN = { - {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - }, - .BEXTR = { - {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, - {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}, - }, - .BLSI = { - {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - }, - .BLSMSK = { - {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - }, - .BLSR = { - {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - }, - .BZHI = { - {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}, - }, - .PDEP = { // no flags affected - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .PEXT = { // no flags affected - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .RORX = { // no flags affected - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .SARX = { // no flags affected (unlike SAR/SHL/SHR) - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .SHLX = { // no flags affected (unlike SAR/SHL/SHR) - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .SHRX = { // no flags affected (unlike SAR/SHL/SHR) - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .MULX = { // no flags affected; implicit multiplicand in rDX - {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}, - {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}, - }, - .ADCX = { // only CF (chains with ADCX) - {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}, - }, - .ADOX = { // only OF (chains with ADOX) - {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, - {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}, - }, - - // 8.12 SSE Encodings - .MOVAPS = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVUPS = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVAPD = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVUPD = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVSS = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVDQA = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVDQU = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVQ = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .MOVD = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVLPS = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVHPS = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVLPD = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVHPD = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVLHPS = { - {written={0}, read={1}}, - }, - .MOVHLPS = { - {written={0}, read={1}}, - }, - .MOVMSKPS = { // destination is a GPR - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .MOVMSKPD = { // destination is a GPR - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .MOVNTPS = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVNTPD = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVNTDQ = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .MOVNTDQA = { - {written={0}, read={1}, reads_mem=true}, - }, - .ADDPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .ADDPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .ADDSS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .ADDSD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .SUBPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .SUBPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .SUBSS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .SUBSD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MULPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MULPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MULSS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MULSD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .DIVPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .DIVPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .DIVSS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .DIVSD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .SQRTPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .SQRTPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .SQRTSS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .SQRTSD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .RCPPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .RCPSS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .RSQRTPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .RSQRTSS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MAXPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MAXPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MAXSS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MAXSD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MINPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MINPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MINSS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MINSD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .ANDPS = { - {written={0}, read={1}, reads_mem=true}, - }, - .ANDPD = { - {written={0}, read={1}, reads_mem=true}, - }, - .ANDNPS = { - {written={0}, read={1}, reads_mem=true}, - }, - .ANDNPD = { - {written={0}, read={1}, reads_mem=true}, - }, - .ORPS = { - {written={0}, read={1}, reads_mem=true}, - }, - .ORPD = { - {written={0}, read={1}, reads_mem=true}, - }, - .XORPS = { - {written={0}, read={1}, reads_mem=true}, - }, - .XORPD = { - {written={0}, read={1}, reads_mem=true}, - }, - .CMPPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CMPPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CMPSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .COMISS = { // OF/SF/AF cleared - {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, - }, - .COMISD = { // OF/SF/AF cleared - {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, - }, - .UCOMISS = { // OF/SF/AF cleared - {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, - }, - .UCOMISD = { // OF/SF/AF cleared - {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, - }, - .SHUFPS = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .SHUFPD = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .UNPCKLPS = { - {written={0}, read={1}, reads_mem=true}, - }, - .UNPCKHPS = { - {written={0}, read={1}, reads_mem=true}, - }, - .UNPCKLPD = { - {written={0}, read={1}, reads_mem=true}, - }, - .UNPCKHPD = { - {written={0}, read={1}, reads_mem=true}, - }, - .CVTPS2PD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTPD2PS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTSS2SD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTSD2SS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTPS2DQ = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTPD2DQ = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTDQ2PS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTDQ2PD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTSS2SI = { // destination is a GPR - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTSD2SI = { // destination is a GPR - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTSI2SS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTSI2SD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTTPS2DQ = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTTPD2DQ = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTTSS2SI = { // destination is a GPR - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .CVTTSD2SI = { // destination is a GPR - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .PADDB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PADDW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PADDD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PADDQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSUBB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSUBW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSUBD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSUBQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PADDSB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PADDSW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PADDUSB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PADDUSW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSUBSB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSUBSW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSUBUSB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSUBUSW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMULLW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMULHW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMULHUW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMULUDQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMADDWD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PAND = { - {written={0}, read={1}, reads_mem=true}, - }, - .PANDN = { - {written={0}, read={1}, reads_mem=true}, - }, - .POR = { - {written={0}, read={1}, reads_mem=true}, - }, - .PXOR = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSLLW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}}, - }, - .PSLLD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}}, - }, - .PSLLQ = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}}, - }, - .PSRLW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}}, - }, - .PSRLD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}}, - }, - .PSRLQ = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}}, - }, - .PSRAW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}}, - }, - .PSRAD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}}, - }, - .PCMPEQB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PCMPEQW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PCMPEQD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PCMPGTB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PCMPGTW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PCMPGTD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PACKSSWB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PACKSSDW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PACKUSWB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PUNPCKLBW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PUNPCKLWD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PUNPCKLDQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PUNPCKLQDQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PUNPCKHBW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PUNPCKHWD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PUNPCKHDQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PUNPCKHQDQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSHUFD = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .PSHUFHW = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .PSHUFLW = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .PSHUFW = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .PEXTRW = { // destination may be memory - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .PINSRW = { - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .PMOVMSKB = { // destination is a GPR - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .PAVGB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PAVGW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMAXUB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMAXSW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMINUB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMINSW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSADBW = { - {written={0}, read={1}, reads_mem=true}, - }, - .MASKMOVDQU = { // byte-masked store to DS:[rDI] - {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, - }, - .LFENCE = { // ordering/hint; no clobber - {side_effects={.FENCE, .SERIALIZING}}, - }, - .SFENCE = { // ordering/hint; no clobber - {side_effects={.FENCE}}, - }, - .MFENCE = { // ordering/hint; no clobber - {side_effects={.FENCE}}, - }, - .PAUSE = { // ordering/hint; no clobber - {side_effects={.HINT}}, - }, - .CLFLUSH = { // flushes cache line for the addressed byte - {read={0}, reads_mem=true, side_effects={.CACHE}}, - }, - .ADDSUBPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .ADDSUBPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .HADDPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .HADDPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .HSUBPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .HSUBPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .MOVDDUP = { - {written={0}, read={1}, reads_mem=true}, - }, - .MOVSLDUP = { - {written={0}, read={1}, reads_mem=true}, - }, - .MOVSHDUP = { - {written={0}, read={1}, reads_mem=true}, - }, - .LDDQU = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSHUFB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PHADDW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PHADDD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PHADDSW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PHSUBW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PHSUBD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PHSUBSW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMADDUBSW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMULHRSW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSIGNB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSIGNW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PSIGND = { - {written={0}, read={1}, reads_mem=true}, - }, - .PABSB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PABSW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PABSD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PALIGNR = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .BLENDPS = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .BLENDPD = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .BLENDVPS = { - {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, - }, - .BLENDVPD = { - {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, - }, - .PBLENDW = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .PBLENDVB = { - {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, - }, - .DPPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .DPPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .EXTRACTPS = { // destination may be memory - {written={0}, read={1}, writes_mem=true}, - }, - .INSERTPS = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .MPSADBW = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .PACKUSDW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PEXTRB = { // destination may be memory - {written={0}, read={1}, writes_mem=true}, - }, - .PEXTRD = { // destination may be memory - {written={0}, read={1}, writes_mem=true}, - }, - .PEXTRQ = { // destination may be memory - {written={0}, read={1}, writes_mem=true}, - }, - .PHMINPOSUW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PINSRB = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .PINSRD = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .PINSRQ = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .PMAXSB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMAXSD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMAXUW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMAXUD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMINSB = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMINSD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMINUW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMINUD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVSXBW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVSXBD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVSXBQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVSXWD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVSXWQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVSXDQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVZXBW = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVZXBD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVZXBQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVZXWD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVZXWQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMOVZXDQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMULDQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PMULLD = { - {written={0}, read={1}, reads_mem=true}, - }, - .PTEST = { // ZF from AND, CF from ANDN; others cleared - {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - }, - .ROUNDPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .ROUNDPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .ROUNDSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .ROUNDSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .PCMPEQQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .CRC32 = { // accumulates CRC into OP0; no flags - {written={0}, read={0, 1}, reads_mem=true}, - {written={0}, read={0, 1}, reads_mem=true}, - {written={0}, read={0, 1}, reads_mem=true}, - {written={0}, read={0, 1}, reads_mem=true}, - {written={0}, read={0, 1}, reads_mem=true}, - }, - .PCMPESTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .PCMPESTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .PCMPISTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared - {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .PCMPISTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared - {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .PCMPGTQ = { - {written={0}, read={1}, reads_mem=true}, - }, - .PCLMULQDQ = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .AESDEC = { - {written={0}, read={1}, reads_mem=true}, - }, - .AESDECLAST = { - {written={0}, read={1}, reads_mem=true}, - }, - .AESENC = { - {written={0}, read={1}, reads_mem=true}, - }, - .AESENCLAST = { - {written={0}, read={1}, reads_mem=true}, - }, - .AESIMC = { - {written={0}, read={1}, reads_mem=true}, - }, - .AESKEYGENASSIST = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .SHA1MSG1 = { - {written={0}, read={1}, reads_mem=true}, - }, - .SHA1MSG2 = { - {written={0}, read={1}, reads_mem=true}, - }, - .SHA1NEXTE = { - {written={0}, read={1}, reads_mem=true}, - }, - .SHA1RNDS4 = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .SHA256MSG1 = { - {written={0}, read={1}, reads_mem=true}, - }, - .SHA256MSG2 = { - {written={0}, read={1}, reads_mem=true}, - }, - .SHA256RNDS2 = { - {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}, - }, - - // 8.13 AVX/AVX2 Encodings - .VADDPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VADDPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VADDSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VADDSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSUBPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSUBPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSUBSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSUBSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMULPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMULPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMULSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMULSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VDIVPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VDIVPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VDIVSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VDIVSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSQRTPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSQRTPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSQRTSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSQRTSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRCPPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRCPSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRSQRTPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRSQRTSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMAXPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMAXPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMAXSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMAXSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMINPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMINPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMINSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VMINSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VANDPS = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VANDPD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VANDNPS = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VANDNPD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VORPS = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VORPD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VXORPS = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VXORPD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VCMPPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCMPPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCMPSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCMPSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCOMISS = { // OF/SF/AF cleared - {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, - }, - .VCOMISD = { // OF/SF/AF cleared - {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, - }, - .VUCOMISS = { // OF/SF/AF cleared - {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, - }, - .VUCOMISD = { // OF/SF/AF cleared - {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}, - }, - .VSHUFPS = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VSHUFPD = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VUNPCKLPS = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VUNPCKHPS = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VUNPCKLPD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VUNPCKHPD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VBLENDPS = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VBLENDPD = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VBLENDVPS = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VBLENDVPD = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VDPPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VDPPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VROUNDPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VROUNDPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VROUNDSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VROUNDSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VEXTRACTPS = { // destination may be memory - {written={0}, read={1}, writes_mem=true}, - }, - .VINSERTPS = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VMOVAPS = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVUPS = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVAPD = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVUPD = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVSS = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}}, - }, - .VMOVSD = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}}, - }, - .VMOVDQA = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVDQU = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVQ = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VMOVD = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVLPS = { - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVHPS = { - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVLPD = { - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVHPD = { - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVLHPS = { - {written={0}, read={1, 2}}, - }, - .VMOVHLPS = { - {written={0}, read={1, 2}}, - }, - .VMOVMSKPS = { // destination is a GPR - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VMOVMSKPD = { // destination is a GPR - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VMOVNTPS = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVNTPD = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVNTDQ = { - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .VMOVNTDQA = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VADDSUBPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VADDSUBPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VHADDPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VHADDPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VHSUBPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VHSUBPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VLDDQU = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VMOVDDUP = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VMOVSLDUP = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VMOVSHDUP = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPCMPESTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .VPCMPESTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared ; reads EAX/EDX lengths - {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .VPCMPISTRI = { // ECX<-index; CF/ZF/SF/OF set, AF/PF cleared - {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .VPCMPISTRM = { // XMM0<-mask; CF/ZF/SF/OF set, AF/PF cleared - {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .VPBROADCASTB = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPBROADCASTW = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPBROADCASTD = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPBROADCASTQ = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VCVTPS2PD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTPD2PS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTSS2SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTSD2SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTPS2DQ = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTPD2DQ = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTDQ2PS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTDQ2PD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTSS2SI = { // destination is a GPR - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTSD2SI = { // destination is a GPR - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTSI2SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTSI2SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTTPS2DQ = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTTPD2DQ = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTTSS2SI = { // destination is a GPR - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTTSD2SI = { // destination is a GPR - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VPADDB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPADDW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPADDD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPADDQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSUBB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSUBW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSUBD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSUBQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMULLW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMULHW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMULHUW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMULUDQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMADDWD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPAND = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPANDN = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPOR = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPXOR = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSLLW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - }, - .VPSLLD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - }, - .VPSLLQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - }, - .VPSRLW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - }, - .VPSRLD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - }, - .VPSRLQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - }, - .VPSRAW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - }, - .VPSRAD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}}, - }, - .VPCMPEQB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPEQW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPEQD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPEQQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPGTB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPGTW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPGTD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPGTQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPACKSSWB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPACKSSDW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPACKUSWB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPACKUSDW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPUNPCKLBW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPUNPCKLWD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPUNPCKLDQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPUNPCKLQDQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPUNPCKHBW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPUNPCKHWD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPUNPCKHDQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPUNPCKHQDQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSHUFD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSHUFHW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSHUFLW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPEXTRB = { // destination may be memory - {written={0}, read={1}, writes_mem=true}, - }, - .VPEXTRW = { // destination may be memory - {written={0}, read={1}}, - {written={0}, read={1}, writes_mem=true}, - }, - .VPEXTRD = { // destination may be memory - {written={0}, read={1}, writes_mem=true}, - }, - .VPEXTRQ = { // destination may be memory - {written={0}, read={1}, writes_mem=true}, - }, - .VPINSRB = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPINSRW = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPINSRD = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPINSRQ = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPMOVMSKB = { // destination is a GPR - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VPTEST = { // ZF from AND, CF from ANDN; others cleared - {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - }, - .VPSHUFB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPHADDW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPHADDD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPHADDSW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPHSUBW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPHSUBD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPHSUBSW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMADDUBSW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMULHRSW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSIGNB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSIGNW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSIGND = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPABSB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPABSW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPABSD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPALIGNR = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPBLENDW = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPBLENDVB = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VMPSADBW = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPHMINPOSUW = { - {written={0}, read={1}, reads_mem=true}, - }, - .VPMAXSB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMAXSD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMAXUW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMAXUD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMINSB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMINSD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMINUW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMINUD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMOVSXBW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVSXBD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVSXBQ = { - {written={0}, read={1}}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVSXWD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVSXWQ = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVSXDQ = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVZXBW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVZXBD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVZXBQ = { - {written={0}, read={1}}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVZXWD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVZXWQ = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVZXDQ = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMULDQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMULLD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VMASKMOVDQU = { // byte-masked store to DS:[rDI] - {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}, - }, - .VPCLMULQDQ = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VAESDEC = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VAESDECLAST = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VAESENC = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VAESENCLAST = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VAESIMC = { - {written={0}, read={1}, reads_mem=true}, - }, - .VAESKEYGENASSIST = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VBROADCASTSS = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VBROADCASTSD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}}, - }, - .VBROADCASTF128 = { - {written={0}, read={1}, reads_mem=true}, - }, - .VEXTRACTF128 = { - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - }, - .VINSERTF128 = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPERM2F128 = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VMASKMOVPS = { - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - }, - .VMASKMOVPD = { - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - }, - .VTESTPS = { // ZF from AND, CF from ANDN; others cleared - {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - }, - .VTESTPD = { // ZF from AND, CF from ANDN; others cleared - {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}, - }, - .VZEROALL = { // zeroes the entire vector register file (YMM/ZMM) - {implicit_wr={.VECTOR}}, - }, - .VZEROUPPER = { // zeroes bits [MAXVL-1:128] of every vector register - {implicit_wr={.VECTOR}}, - }, - .VBROADCASTI128 = { - {written={0}, read={1}, reads_mem=true}, - }, - .VEXTRACTI128 = { - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - }, - .VINSERTI128 = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPERM2I128 = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPERMD = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMPS = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMQ = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMPD = { - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPBLENDD = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPSLLVD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSLLVQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSRLVD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSRLVQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSRAVD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMASKMOVD = { - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - }, - .VPMASKMOVQ = { - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}, - }, - .VGATHERDPS = { // mask operand (OP2) is zeroed as elements are gathered - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - }, - .VGATHERDPD = { // mask operand (OP2) is zeroed as elements are gathered - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - }, - .VGATHERQPS = { // mask operand (OP2) is zeroed as elements are gathered - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - }, - .VGATHERQPD = { // mask operand (OP2) is zeroed as elements are gathered - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - }, - .VPGATHERDD = { // mask operand (OP2) is zeroed as elements are gathered - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - }, - .VPGATHERDQ = { // mask operand (OP2) is zeroed as elements are gathered - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - }, - .VPGATHERQD = { // mask operand (OP2) is zeroed as elements are gathered - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - }, - .VPGATHERQQ = { // mask operand (OP2) is zeroed as elements are gathered - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - {written={0, 2}, read={0, 1, 2}, reads_mem=true}, - }, - - // 8.14 FMA Encodings - .VFMADD132PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADD213PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADD231PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADD132PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADD213PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADD231PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADD132SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADD213SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADD231SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADD132SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADD213SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADD231SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB132PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB213PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB231PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB132PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB213PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB231PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB132SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB213SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB231SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB132SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB213SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUB231SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD132PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD213PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD231PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD132PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD213PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD231PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD132SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD213SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD231SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD132SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD213SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMADD231SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB132PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB213PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB231PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB132PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB213PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB231PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB132SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB213SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB231SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB132SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB213SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFNMSUB231SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADDSUB132PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADDSUB213PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADDSUB231PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADDSUB132PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADDSUB213PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMADDSUB231PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUBADD132PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUBADD213PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUBADD231PS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUBADD132PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUBADD213PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFMSUBADD231PD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTPH2PS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VCVTPS2PH = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}, - }, - - // 8.15 AVX-512 Encodings - .VMOVDQA32 = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VMOVDQA64 = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VMOVDQU8 = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VMOVDQU16 = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VMOVDQU32 = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VMOVDQU64 = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPBLENDMB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPBLENDMW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPBLENDMD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPBLENDMQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VBLENDMPS = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VBLENDMPD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPB = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPUB = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPW = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPUW = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPD = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPUD = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPQ = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCMPUQ = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPTESTMB = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPTESTMW = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPTESTMD = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPTESTMQ = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPTESTNMB = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPTESTNMW = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPTESTNMD = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPTESTNMQ = { // result written to an opmask register (k1), not EFLAGS - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPCOMPRESSD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPCOMPRESSQ = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VCOMPRESSPS = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VCOMPRESSPD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPEXPANDD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPEXPANDQ = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VEXPANDPS = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VEXPANDPD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPCONFLICTD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPCONFLICTQ = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPLZCNTD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPLZCNTQ = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPERMI2B = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMI2W = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMI2D = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMI2Q = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMI2PS = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMI2PD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMT2B = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMT2W = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMT2D = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMT2Q = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMT2PS = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMT2PD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPERMW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMOVB2M = { // sign bits -> opmask register - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VPMOVW2M = { // sign bits -> opmask register - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VPMOVD2M = { // sign bits -> opmask register - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VPMOVQ2M = { // sign bits -> opmask register - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VPMOVM2B = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VPMOVM2W = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VPMOVM2D = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VPMOVM2Q = { - {written={0}, read={1}}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .VPMOVQB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVSQB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVUSQB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVQW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVSQW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVUSQW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVQD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVSQD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVUSQD = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVDB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVSDB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVUSDB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVDW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVSDW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVUSDW = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVWB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVSWB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPMOVUSWB = { - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VPROLD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPROLQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPROLVD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPROLVQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPRORD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPRORQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPRORVD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPRORVQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSCATTERDD = { // opmask k1 is consumed and cleared per element - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - }, - .VPSCATTERDQ = { // opmask k1 is consumed and cleared per element - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - }, - .VPSCATTERQD = { // opmask k1 is consumed and cleared per element - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - }, - .VPSCATTERQQ = { // opmask k1 is consumed and cleared per element - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - }, - .VSCATTERDPS = { // opmask k1 is consumed and cleared per element - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - }, - .VSCATTERDPD = { // opmask k1 is consumed and cleared per element - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - }, - .VSCATTERQPS = { // opmask k1 is consumed and cleared per element - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - }, - .VSCATTERQPD = { // opmask k1 is consumed and cleared per element - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - }, - .VPSRAVQ = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSRAVW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSLLVW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPSRLVW = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VRANGEPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRANGEPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRANGESS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRANGESD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VREDUCEPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VREDUCEPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VREDUCESS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VREDUCESD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRNDSCALEPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRNDSCALEPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRNDSCALESS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRNDSCALESD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRSQRT14PS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRSQRT14PD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRSQRT14SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRSQRT14SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRCP14PS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRCP14PD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRCP14SS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VRCP14SD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSCALEFPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSCALEFPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSCALEFSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VSCALEFSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VGETEXPPS = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VGETEXPPD = { // may set MXCSR exception/status bits - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VGETEXPSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VGETEXPSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VGETMANTPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VGETMANTPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VGETMANTSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VGETMANTSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFIXUPIMMPS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFIXUPIMMPD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFIXUPIMMSS = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFIXUPIMMSD = { // may set MXCSR exception/status bits - {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}, - }, - .VFPCLASSPS = { // class predicate written to an opmask register - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VFPCLASSPD = { // class predicate written to an opmask register - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - {written={0}, read={1}, reads_mem=true}, - }, - .VFPCLASSSS = { // class predicate written to an opmask register - {written={0}, read={1}, reads_mem=true}, - }, - .VFPCLASSSD = { // class predicate written to an opmask register - {written={0}, read={1}, reads_mem=true}, - }, - .VALIGNQ = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VALIGND = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VDBPSADBW = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPTERNLOGD = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPTERNLOGQ = { - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - {written={0}, read={1, 2, 3}, reads_mem=true}, - }, - .VPDPWSSD = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .VPMULTISHIFTQB = { - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - {written={0}, read={1, 2}, reads_mem=true}, - }, - .KADDW = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KADDB = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KADDQ = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KADDD = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KANDW = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KANDB = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KANDQ = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KANDD = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KANDNW = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KANDNB = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KANDNQ = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KANDND = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KMOVW = { // opmask <-> GPR/mem/opmask - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .KMOVB = { // opmask <-> GPR/mem/opmask - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .KMOVQ = { // opmask <-> GPR/mem/opmask - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .KMOVD = { // opmask <-> GPR/mem/opmask - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}}, - {written={0}, read={1}}, - }, - .KNOTW = { // opmask register operation - {written={0}, read={1}}, - }, - .KNOTB = { // opmask register operation - {written={0}, read={1}}, - }, - .KNOTQ = { // opmask register operation - {written={0}, read={1}}, - }, - .KNOTD = { // opmask register operation - {written={0}, read={1}}, - }, - .KORW = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KORB = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KORQ = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KORD = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KORTESTW = { // sets ZF/CF from mask test - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - }, - .KORTESTB = { // sets ZF/CF from mask test - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - }, - .KORTESTQ = { // sets ZF/CF from mask test - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - }, - .KORTESTD = { // sets ZF/CF from mask test - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - }, - .KSHIFTLW = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KSHIFTLB = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KSHIFTLQ = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KSHIFTLD = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KSHIFTRW = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KSHIFTRB = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KSHIFTRQ = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KSHIFTRD = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KTESTW = { // sets ZF/CF from mask test - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - }, - .KTESTB = { // sets ZF/CF from mask test - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - }, - .KTESTQ = { // sets ZF/CF from mask test - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - }, - .KTESTD = { // sets ZF/CF from mask test - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - }, - .KUNPCKBW = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KUNPCKWD = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KUNPCKDQ = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KXNORW = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KXNORB = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KXNORQ = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KXNORD = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KXORW = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KXORB = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KXORQ = { // opmask register operation - {written={0}, read={1, 2}}, - }, - .KXORD = { // opmask register operation - {written={0}, read={1, 2}}, - }, - - // 8.16 x87 FPU Encodings - .FADD = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FADDP = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FIADD = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - }, - .FSUB = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FSUBP = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FISUB = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - }, - .FSUBR = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FSUBRP = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FISUBR = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - }, - .FMUL = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FMULP = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FIMUL = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - }, - .FDIV = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FDIVP = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FIDIV = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - }, - .FDIVR = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FDIVRP = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FIDIVR = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - }, - .FSQRT = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FABS = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FCHS = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FPREM = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FPREM1 = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FRNDINT = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FSCALE = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FXTRACT = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FXAM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FLD = { // push onto x87 stack - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}}, - }, - .FILD = { // push onto x87 stack - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - }, - .FBLD = { // push onto x87 stack - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - }, - .FST = { // store (FSTP/FISTP/FBSTP pop the stack) - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}}, - }, - .FSTP = { // store (FSTP/FISTP/FBSTP pop the stack) - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}}, - }, - .FIST = { // store (FSTP/FISTP/FBSTP pop the stack) - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FISTP = { // store (FSTP/FISTP/FBSTP pop the stack) - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FISTTP = { // store (FSTP/FISTP/FBSTP pop the stack) - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FBSTP = { // store (FSTP/FISTP/FBSTP pop the stack) - {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FXCH = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FCMOVB = { // conditional x87 move; reads EFLAGS - {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, - }, - .FCMOVE = { // conditional x87 move; reads EFLAGS - {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, - }, - .FCMOVBE = { // conditional x87 move; reads EFLAGS - {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, - }, - .FCMOVU = { // conditional x87 move; reads EFLAGS - {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, - }, - .FCMOVNB = { // conditional x87 move; reads EFLAGS - {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}, - }, - .FCMOVNE = { // conditional x87 move; reads EFLAGS - {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}, - }, - .FCMOVNBE = { // conditional x87 move; reads EFLAGS - {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}, - }, - .FCMOVNU = { // conditional x87 move; reads EFLAGS - {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}, - }, - .FCOM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // m32 - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // m64 - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // ST(i) - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // no operand (ST(1)) - }, - .FCOMP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // m32 - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, // m64 - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // ST(i) - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, // no operand (ST(1)) - }, - .FCOMPP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FICOM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - }, - .FICOMP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}, - }, - .FCOMI = { // compares ST(0):ST(i) into EFLAGS - {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, - }, - .FCOMIP = { // compares ST(0):ST(i) into EFLAGS - {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, - }, - .FUCOMI = { // compares ST(0):ST(i) into EFLAGS - {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, - }, - .FUCOMIP = { // compares ST(0):ST(i) into EFLAGS - {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}, - }, - .FUCOM = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FUCOMP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FUCOMPP = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FTST = { // sets x87 condition codes C0-C3 (status word), not EFLAGS - {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FLDZ = { // push onto x87 stack - {implicit_wr={.FPU_ST, .FPU_SW}}, - }, - .FLD1 = { // push onto x87 stack - {implicit_wr={.FPU_ST, .FPU_SW}}, - }, - .FLDPI = { // push onto x87 stack - {implicit_wr={.FPU_ST, .FPU_SW}}, - }, - .FLDL2T = { // push onto x87 stack - {implicit_wr={.FPU_ST, .FPU_SW}}, - }, - .FLDL2E = { // push onto x87 stack - {implicit_wr={.FPU_ST, .FPU_SW}}, - }, - .FLDLG2 = { // push onto x87 stack - {implicit_wr={.FPU_ST, .FPU_SW}}, - }, - .FLDLN2 = { // push onto x87 stack - {implicit_wr={.FPU_ST, .FPU_SW}}, - }, - .FSIN = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FCOS = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FSINCOS = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FPTAN = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FPATAN = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .F2XM1 = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FYL2X = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FYL2XP1 = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FINIT = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FNINIT = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FINCSTP = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FDECSTP = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FFREE = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FFREEP = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FNOP = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FWAIT = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FCLEX = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FNCLEX = { // x87 arithmetic: updates ST(0) and status word C1 - {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}, - }, - .FSTCW = { // stores x87 (and SSE) state to memory - {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FNSTCW = { // stores x87 (and SSE) state to memory - {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FLDCW = { // loads x87 (and SSE) state from memory - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - }, - .FSTENV = { // stores x87 (and SSE) state to memory - {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FNSTENV = { // stores x87 (and SSE) state to memory - {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FLDENV = { // loads x87 (and SSE) state from memory - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - }, - .FSAVE = { // stores x87 (and SSE) state to memory - {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FNSAVE = { // stores x87 (and SSE) state to memory - {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FRSTOR = { // loads x87 (and SSE) state from memory - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - }, - .FSTSW = { // AX form writes AX; m2byte form writes memory - {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, - {implicit_wr={.RAX, .FPU_SW}}, - }, - .FNSTSW = { // AX form writes AX; m2byte form writes memory - {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}, - {implicit_wr={.RAX, .FPU_SW}}, - }, - .FXSAVE = { // stores x87 (and SSE) state to memory - {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FXSAVE64 = { // stores x87 (and SSE) state to memory - {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}, - }, - .FXRSTOR = { // loads x87 (and SSE) state from memory - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - }, - .FXRSTOR64 = { // loads x87 (and SSE) state from memory - {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}, - }, - - // 8.17 System Instruction Encodings - .LGDT = { // privileged load - {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - }, - .SGDT = { // stores descriptor/register to r/m (privileged for some) - {written={0}, writes_mem=true}, - {written={0}, writes_mem=true}, - }, - .LIDT = { // privileged load - {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - }, - .SIDT = { // stores descriptor/register to r/m (privileged for some) - {written={0}, writes_mem=true}, - {written={0}, writes_mem=true}, - }, - .LLDT = { // privileged load - {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - }, - .SLDT = { // stores descriptor/register to r/m (privileged for some) - {written={0}, writes_mem=true}, - {written={0}}, - {written={0}}, - }, - .LTR = { // privileged load - {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - }, - .STR = { // stores descriptor/register to r/m (privileged for some) - {written={0}, writes_mem=true}, - {written={0}}, - {written={0}}, - }, - .LMSW = { // privileged load - {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - }, - .SMSW = { // stores descriptor/register to r/m (privileged for some) - {written={0}, writes_mem=true}, - {written={0}}, - {written={0}}, - }, - .CLTS = { // privileged; no GPR/EFLAGS clobber modeled - {side_effects={.PRIVILEGED}}, - }, - .ARPL = { // legacy; adjusts RPL, sets ZF - {written={0}, read={1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, - }, - .LAR = { // ZF=1 on success; OP0 undefined on failure - {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, - }, - .LSL = { // ZF=1 on success; OP0 undefined on failure - {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, - {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}, - }, - .VERR = { // ZF=1 if segment is readable/writable - {read={0}, flags_wr={.ZF}, reads_mem=true}, - }, - .VERW = { // ZF=1 if segment is readable/writable - {read={0}, flags_wr={.ZF}, reads_mem=true}, - }, - .INVD = { // privileged; no GPR/EFLAGS clobber modeled - {side_effects={.SERIALIZING, .PRIVILEGED}}, - }, - .WBINVD = { // privileged; no GPR/EFLAGS clobber modeled - {side_effects={.SERIALIZING, .PRIVILEGED}}, - }, - .INVLPG = { // privileged; no GPR/EFLAGS clobber modeled - {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}, - }, - .INVPCID = { // VMX/INVx status reported in ZF/CF - {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .RSM = { // privileged; no GPR/EFLAGS clobber modeled - {side_effects={.SERIALIZING, .PRIVILEGED}}, - }, - .RDMSR = { // privileged; EDX:EAX <- MSR[ECX] - {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED}}, - }, - .WRMSR = { // privileged; MSR[ECX] <- EDX:EAX - {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.SERIALIZING, .PRIVILEGED}}, - }, - .VMCALL = { // privileged; no GPR/EFLAGS clobber modeled - {side_effects={.PRIVILEGED}}, - }, - .VMLAUNCH = { // VMX/INVx status reported in ZF/CF - {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .VMRESUME = { // VMX/INVx status reported in ZF/CF - {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .VMXOFF = { // privileged; no GPR/EFLAGS clobber modeled - {side_effects={.PRIVILEGED}}, - }, - .VMXON = { // VMX/INVx status reported in ZF/CF - {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .VMCLEAR = { // VMX/INVx status reported in ZF/CF - {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .VMPTRLD = { // VMX/INVx status reported in ZF/CF - {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .VMPTRST = { // VMX/INVx status reported in ZF/CF - {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .VMREAD = { // VMX status in ZF/CF - {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .VMWRITE = { // VMX status in ZF/CF - {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .VMFUNC = { // privileged; no GPR/EFLAGS clobber modeled - {side_effects={.PRIVILEGED}}, - }, - .INVEPT = { // VMX/INVx status reported in ZF/CF - {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .INVVPID = { // VMX/INVx status reported in ZF/CF - {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - - // 8.18 Security and Memory Protection Encodings - .ENCLS = { // SGX enclave leaf; behaviour selected by EAX - {side_effects={.PRIVILEGED}}, - }, - .ENCLU = { // SGX enclave leaf; behaviour selected by EAX - {side_effects={.PRIVILEGED}}, - }, - .ENCLV = { // SGX enclave leaf; behaviour selected by EAX - {side_effects={.PRIVILEGED}}, - }, - .RDPKRU = { // EAX <- PKRU (EDX cleared); reads ECX - {implicit_wr={.RAX}, implicit_rd={.RCX}}, - }, - .WRPKRU = { // PKRU <- EAX; ECX/EDX must be 0 - {implicit_rd={.RAX, .RCX, .RDX}}, - }, - .INCSSPD = { // advances SSP - {read={0}, side_effects={.CET}}, - }, - .INCSSPQ = { // advances SSP - {read={0}, side_effects={.CET}}, - }, - .RDSSPD = { // reads shadow-stack pointer into OP0 - {written={0}, side_effects={.CET}}, - }, - .RDSSPQ = { // reads shadow-stack pointer into OP0 - {written={0}, side_effects={.CET}}, - }, - .SAVEPREVSSP = { // CET shadow-stack management - {side_effects={.CET}}, - }, - .RSTORSSP = { // CET shadow-stack management - {read={0}, reads_mem=true, writes_mem=true, side_effects={.CET}}, // reads restore token, writes previous-ssp token - }, - .WRSSD = { // writes to shadow stack - {read={0, 1}, writes_mem=true, side_effects={.CET}}, - }, - .WRSSQ = { // writes to shadow stack - {read={0, 1}, writes_mem=true, side_effects={.CET}}, - }, - .WRUSSD = { // writes to shadow stack - {read={0, 1}, writes_mem=true, side_effects={.CET}}, - }, - .WRUSSQ = { // writes to shadow stack - {read={0, 1}, writes_mem=true, side_effects={.CET}}, - }, - .SETSSBSY = { // CET shadow-stack management - {side_effects={.CET}}, - }, - .CLRSSBSY = { // CET shadow-stack management - {read={0}, reads_mem=true, writes_mem=true, side_effects={.CET}}, // reads token, clears busy bit - }, - .ENDBR64 = { // CET landing pad; NOP-like - {side_effects={.HINT, .CET}}, - }, - .ENDBR32 = { // CET landing pad; NOP-like - {side_effects={.HINT, .CET}}, - }, - - // 8.19 XSAVE/XRSTOR State Management Encodings - .XSAVE = { // saves state components selected by EDX:EAX - {implicit_rd={.RAX, .RDX}, writes_mem=true}, - }, - .XSAVE64 = { // saves state components selected by EDX:EAX - {implicit_rd={.RAX, .RDX}, writes_mem=true}, - }, - .XRSTOR = { // restores state components selected by EDX:EAX - {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}, - }, - .XRSTOR64 = { // restores state components selected by EDX:EAX - {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}, - }, - .XSAVEOPT = { // saves state components selected by EDX:EAX - {implicit_rd={.RAX, .RDX}, writes_mem=true}, - }, - .XSAVEOPT64 = { // saves state components selected by EDX:EAX - {implicit_rd={.RAX, .RDX}, writes_mem=true}, - }, - .XSAVEC = { // saves state components selected by EDX:EAX - {implicit_rd={.RAX, .RDX}, writes_mem=true}, - }, - .XSAVEC64 = { // saves state components selected by EDX:EAX - {implicit_rd={.RAX, .RDX}, writes_mem=true}, - }, - .XSAVES = { // saves state components selected by EDX:EAX - {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, - }, - .XSAVES64 = { // saves state components selected by EDX:EAX - {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}, - }, - .XRSTORS = { // restores state components selected by EDX:EAX - {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .XRSTORS64 = { // restores state components selected by EDX:EAX - {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - - // 8.20 Cache and Prefetch Encodings - .PREFETCHT0 = { // cache hint/maintenance; no register or flag clobber - {read={0}, reads_mem=true, side_effects={.HINT}}, - }, - .PREFETCHT1 = { // cache hint/maintenance; no register or flag clobber - {read={0}, reads_mem=true, side_effects={.HINT}}, - }, - .PREFETCHT2 = { // cache hint/maintenance; no register or flag clobber - {read={0}, reads_mem=true, side_effects={.HINT}}, - }, - .PREFETCHNTA = { // cache hint/maintenance; no register or flag clobber - {read={0}, reads_mem=true, side_effects={.HINT}}, - }, - .PREFETCHW = { // cache hint/maintenance; no register or flag clobber - {read={0}, reads_mem=true, side_effects={.HINT}}, - }, - .CLFLUSHOPT = { // cache hint/maintenance; no register or flag clobber - {read={0}, reads_mem=true, side_effects={.CACHE}}, - }, - .CLWB = { // cache hint/maintenance; no register or flag clobber - {read={0}, reads_mem=true, side_effects={.CACHE}}, - }, - .CLDEMOTE = { // cache hint/maintenance; no register or flag clobber - {read={0}, reads_mem=true, side_effects={.HINT}}, - }, - - // 8.21 Atomic and Byte Swap Encodings - .BSWAP = { - {written={0}, read={0}}, - {written={0}, read={0}}, - }, - .CMPXCHG = { // ZF set on match; on mismatch RAX <- dest - {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - }, - .CMPXCHG8B = { // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, - }, - .CMPXCHG16B = { // EDX:EAX (RDX:RAX) compared; ECX:EBX (RCX:RBX) is the new value - {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}, - }, - .XADD = { - {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}, - }, - - // 8.22 Miscellaneous Encodings - .BOUND = { // #BR if out of bounds - {read={0, 1}, reads_mem=true, side_effects={.TRAP}}, - {read={0, 1}, reads_mem=true, side_effects={.TRAP}}, - }, - .ENTER = { // builds stack frame - {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}, - }, - .LEAVE = { - {implicit_wr={.RSP, .RBP}, implicit_rd={.RBP}, reads_mem=true}, - }, - .XLAT = { // AL <- [rBX + AL] - {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, - }, - .XLATB = { // AL <- [rBX + AL] - {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}, - }, - .MOVBE = { // byte-swapping load/store - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - {written={0}, read={1}, writes_mem=true, reads_mem=true}, - }, - .RDRAND = { // CF=1 if value valid; OF/SF/ZF/AF/PF cleared - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - }, - .RDSEED = { // CF=1 if value valid; OF/SF/ZF/AF/PF cleared - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}, - }, - // 8.23 Additional System / GPR Encodings - .SWAPGS = { // privileged; swaps GS.base with IA32_KERNEL_GS_BASE - {side_effects={.PRIVILEGED}}, - }, - .MONITOR = { // arms address monitor for [rAX]; ECX=extensions, EDX=hints - {implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true}, - }, - .MWAIT = { // EAX=hints, ECX=extensions; enters optimized wait - {implicit_rd={.RAX, .RCX}, side_effects={.HALT}}, - }, - .CLAC = { // clears EFLAGS.AC (not modeled in Clobber_Flags); CPL0 - {side_effects={.PRIVILEGED}}, - }, - .STAC = { // sets EFLAGS.AC (not modeled in Clobber_Flags); CPL0 - {side_effects={.PRIVILEGED}}, - }, - .RDFSBASE = { - {written={0}}, - {written={0}}, - }, - .RDGSBASE = { - {written={0}}, - {written={0}}, - }, - .WRFSBASE = { - {read={0}}, - {read={0}}, - }, - .WRGSBASE = { - {read={0}}, - {read={0}}, - }, - .PTWRITE = { // writes source to a PT trace packet; no flags - {read={0}, reads_mem=true}, - {read={0}, reads_mem=true}, - }, - .RDPID = { // dest <- IA32_TSC_AUX - {written={0}}, - }, - .WBNOINVD = { // privileged; writes back caches without invalidation - {side_effects={.SERIALIZING, .PRIVILEGED}}, - }, - .SERIALIZE = { // serializes execution; no register/flag clobber - {side_effects={.SERIALIZING}}, - }, - .PREFETCH = { // cache hint; no register or flag clobber - {read={0}, reads_mem=true, side_effects={.HINT}}, - }, - - // 8.24 WAITPKG Encodings - .TPAUSE = { // reads control r32 + EDX:EAX deadline; CF <- result - {read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}}, - }, - .UMONITOR = { // arms address monitor for [reg] - {read={0}, reads_mem=true}, - }, - .UMWAIT = { // reads control r32 + EDX:EAX deadline; CF <- result - {read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}}, - }, - - // 8.25 Direct Store / Enqueue Store Encodings - .MOVDIRI = { // direct store of source register to memory - {read={0, 1}, writes_mem=true}, - {read={0, 1}, writes_mem=true}, - }, - .MOVDIR64B = { // 64-byte direct store: reads m512, writes [reg] - {read={0}, implicit_rd={.RAX}, reads_mem=true, writes_mem=true}, - }, - .ENQCMD = { // enqueue store: reads m512, writes to device [reg]; ZF <- status - {read={0}, reads_mem=true, writes_mem=true, flags_wr={.ZF}}, - }, - .ENQCMDS = { // supervisor enqueue store; ZF <- status - {read={0}, reads_mem=true, writes_mem=true, flags_wr={.ZF}}, - }, - - // 8.26 Remote Atomic Operation (RAO-INT) Encodings - .AADD = { // atomic [mem] += reg; no flags, no result loaded - {read={0, 1}, writes_mem=true, reads_mem=true}, - {read={0, 1}, writes_mem=true, reads_mem=true}, - }, - .AAND = { // atomic [mem] &= reg - {read={0, 1}, writes_mem=true, reads_mem=true}, - {read={0, 1}, writes_mem=true, reads_mem=true}, - }, - .AOR = { // atomic [mem] |= reg - {read={0, 1}, writes_mem=true, reads_mem=true}, - {read={0, 1}, writes_mem=true, reads_mem=true}, - }, - .AXOR = { // atomic [mem] ^= reg - {read={0, 1}, writes_mem=true, reads_mem=true}, - {read={0, 1}, writes_mem=true, reads_mem=true}, - }, - - // 8.27 Restricted Transactional Memory (RTM) Encodings - .XEND = { // commits transaction; may transfer control on abort - {side_effects={.CONTROL}}, - }, - .XTEST = { // ZF <- (not in transactional region) - {flags_wr={.ZF}}, - }, - - // 8.28 AMD SVM Encodings - .VMRUN = { // privileged; runs guest from VMCB at [rAX] - {implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .VMMCALL = { // guest-to-hypervisor call - {side_effects={.PRIVILEGED}}, - }, - .VMLOAD = { // privileged; loads guest state from VMCB at [rAX] - {implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .VMSAVE = { // privileged; saves guest state to VMCB at [rAX] - {implicit_rd={.RAX}, writes_mem=true, side_effects={.PRIVILEGED}}, - }, - .STGI = { // privileged; sets global interrupt flag - {side_effects={.PRIVILEGED}}, - }, - .CLGI = { // privileged; clears global interrupt flag - {side_effects={.PRIVILEGED}}, - }, - .SKINIT = { // privileged; secure init from SLB at EAX - {implicit_rd={.RAX}, side_effects={.PRIVILEGED}}, - }, - .INVLPGA = { // privileged; invalidates TLB entry [rAX] for ASID ECX - {implicit_rd={.RAX, .RCX}, side_effects={.PRIVILEGED}}, - }, - .INVLPGB = { // privileged; rAX=va, ECX=count, EDX=flags - {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.PRIVILEGED}}, - }, - .TLBSYNC = { // privileged; synchronizes broadcast TLB invalidations - {side_effects={.PRIVILEGED}}, - }, - - // 8.29 AMD SEV-SNP Encodings - .PVALIDATE = { // rAX=addr, ECX=size, EDX=validate; EAX<-rc, flags set - {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}, - }, - .RMPADJUST = { // privileged; rAX=addr, RCX=attrs, RDX=level; EAX<-rc - {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}, - }, - .RMPUPDATE = { // privileged; rAX=addr, RCX=ptr to RMP state; EAX<-rc - {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, writes_mem=true, side_effects={.PRIVILEGED}}, - }, - .PSMASH = { // privileged; rAX=addr; EAX<-rc; splits 2M RMP entry - {implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, side_effects={.PRIVILEGED}}, - }, - - // 8.30 AMD Miscellaneous Encodings - .CLZERO = { // zeroes the cache line at [rAX] - {implicit_rd={.RAX}, writes_mem=true, side_effects={.CACHE}}, - }, - .MONITORX = { // arms address monitor for [rAX] with timer (EBX) - {implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true}, - }, - .MWAITX = { // EAX=hints, ECX=extensions, EBX=timer; enters wait - {implicit_rd={.RAX, .RCX, .RBX}, side_effects={.HALT}}, - }, - .RDPRU = { // ECX selects register; EDX:EAX <- value - {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}, - }, - .MCOMMIT = { // commits pending stores; CF <- error status - {flags_wr={.CF}, side_effects={.FENCE}}, - }, -} diff --git a/core/rexcode/isa/x86/tablegen/encoding_table.odin b/core/rexcode/isa/x86/tablegen/encoding_table.odin index bbdca40af..12c1e65b2 100644 --- a/core/rexcode/isa/x86/tablegen/encoding_table.odin +++ b/core/rexcode/isa/x86/tablegen/encoding_table.odin @@ -1,5104 +1,5016 @@ -// rexcode · Brendan Punsky (dotbmp@github), original author +// Code generated by instruction_table_gen.odin. DO NOT EDIT BY HAND. +// Single source of truth: one Form (Encoding + Clobber) per instruction shape. package rexcode_x86_tablegen +import "core:rexcode/isa/x86" + +// Form couples one encoding shape with its architectural effects. +// `using encoding` keeps existing field access (form.opcode, form.ops, +// form.flags, ...) working unchanged when code moves from []Encoding to []Form. +Form :: struct { + using encoding: Encoding, + clobber: Clobber, +} + // ============================================================================= -// x86 ENCODING_TABLE +// x86 INSTRUCTION_TABLE // ============================================================================= // -// Indexed by Mnemonic. Each entry is a slice of Encoding forms, one per -// operand-shape variant. Encoding shape: {mnemonic, ops[4], enc[4], opcode, -// ext, flags}. The matcher walks the slice and picks the first form whose -// Operand_Type list satisfies the user's Instruction operands. +// Type: [Mnemonic][]Form, indexed by Mnemonic. Each entry is a slice of Form, +// one per operand-shape variant. A Form couples an encoding with its +// architectural effects in a single record: +// +// Form :: struct { using encoding: Encoding, clobber: x86.Clobber } +// +// encoding: {mnemonic, ops[4], enc[4], opcode, ext, flags} // the bytes. +// clobber: {written, read, implicit_wr/rd, flags_wr/undef/rd, +// writes_mem, reads_mem, side_effects} // the effects. +// +// This is the single source of truth. Encoding and clobber used to live in two +// separate [Mnemonic][]T tables that had to be kept index-for-index aligned by +// hand; pairing them in one Form makes that alignment structural, so a form's +// bytes and its effects can no longer drift apart. +// +// MATCHING. The matcher walks a mnemonic's slice and selects the first Form +// whose Operand_Type list (encoding.ops) satisfies the user's Instruction +// operands. Only the encoding half is consulted during the scan; the clobber +// half is read after a Form is chosen. (Keep this in mind if the scan is hot: +// clobber data widens the stride but is never touched while matching.) +// +// HOW EACH FORM'S CLOBBER IS SPECIALISED. A mnemonic's effects begin as one +// per-mnemonic "union" and are narrowed to each individual form: +// +// 1. Implicit-operand normalisation. An operand that is an implicit register +// (AL/AX/EAX/RAX_IMPL -> RAX, CL_IMPL -> RCX, XMM0_IMPL -> XMM0, +// ST0_IMPL -> FPU_ST) or an implicit constant (ONE_IMPL) is removed from +// the OP0..3 slot set and, if that slot was written/read, folded into +// implicit_wr/implicit_rd. Registers that are implicit but NOT tied to an +// operand (RSP for the stack, RSI/RDI/RCX for strings, RDX for MULX, ...) +// are inherent and kept on every form. +// 2. Slot trimming. OP slots that are .NONE in a given form are dropped from +// written/read. +// 3. Per-form memory. writes_mem/reads_mem keep the union's DIRECTION but are +// asserted on a form only when that form actually carries a memory-capable +// operand, OR the instruction addresses memory implicitly (stack, string, +// XLAT table, MASKMOVDQU/[rDI] store, VMCS). Consequently register-only +// forms of otherwise-memory instructions (e.g. MOV r,imm; FADD ST(0),ST(i); +// FST ST(i); MOVLHPS; PEXTRW r32,xmm) do not carry the blanket memory flag +// the union used. Shadow-stack accesses are not implicit: the shadow-stack +// instructions that touch memory (WRSS/WRUSS/RSTORSSP/CLRSSBSY) all do so +// through an explicit m64 operand and are covered by the memory-capable- +// operand branch above. +// 4. Family splits that a single per-mnemonic union could only approximate: +// IMUL: 1-operand form writes RDX:RAX implicitly (r/m8 -> AX only); +// 2-operand form is OP0 *= OP1; 3-operand form is OP0 = OP1 * imm +// (OP0 not read); neither multi-operand form touches RAX/RDX. +// MUL/DIV/IDIV: the r/m8 form uses the A-register only and does not +// touch (R)DX. +// SHL/SHR/SAR/ROL/ROR/RCL/RCR/SHLD/SHRD: only the CL form reads RCX; +// the 1/imm8 forms do not. +// +// FLAGS AND SIDE EFFECTS are uniform across a mnemonic's forms and carry through +// unchanged, EXCEPT where one mnemonic aliases two distinct instructions: MOVSD +// and CMPSD each name both a string operation and an SSE scalar-double +// operation, so their string form and their SSE form carry different flags and +// side_effects. +// +// INVARIANT. A Form is a freely-eliminable no-op iff every clobber set is empty +// AND side_effects == {} (only .NOP and the .INVALID sentinel qualify). Note +// this is a property of clobber alone; the encoding half never makes a Form +// eliminable. @(rodata) -ENCODING_TABLE := [Mnemonic][]Encoding{ +INSTRUCTION_TABLE := [Mnemonic][]Form{ .INVALID = {}, - - // ------------------------------------------------------------------------- - // SECTION: 8.1 Data Transfer Encodings - // ------------------------------------------------------------------------- .MOV = { - {.MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x88, 0, {}}, - {.MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {}}, - {.MOV, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {}}, - {.MOV, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {force_rex_w=true}}, - {.MOV, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8A, 0, {}}, - {.MOV, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {}}, - {.MOV, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {}}, - {.MOV, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {force_rex_w=true}}, - {.MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, 0xB0, 0, {}}, - {.MOV, {.R16, .IMM16, .NONE, .NONE}, {.OP_R, .IW, .NONE, .NONE}, 0xB8, 0, {}}, - {.MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, 0xB8, 0, {}}, - {.MOV, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, 0xB8, 0, {force_rex_w=true}}, - {.MOV, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC6, 0, {modrm_reg_ext=true}}, - {.MOV, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true}}, - {.MOV, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true}}, - {.MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true, force_rex_w=true}}, - {.MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {}}, - {.MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, - {.MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, - {.MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true}}, - {.MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {}}, - {.MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, - {.MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, - {.MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true}}, - {.MOV, {.RM16, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {}}, - {.MOV, {.RM64, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {force_rex_w=true}}, - {.MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {}}, - {.MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {force_rex_w=true}}, - {.MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F}}, - {.MOV, {.CR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F}}, - {.MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F}}, - {.MOV, {.DR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F}}, + {{.MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x88, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x89, 0, {force_rex_w=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8A, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8B, 0, {force_rex_w=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.R8, .IMM8, .NONE, .NONE}, {.OP_R, .IB, .NONE, .NONE}, 0xB0, 0, {}}, {written={0}, read={1}}}, + {{.MOV, {.R16, .IMM16, .NONE, .NONE}, {.OP_R, .IW, .NONE, .NONE}, 0xB8, 0, {}}, {written={0}, read={1}}}, + {{.MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, 0xB8, 0, {}}, {written={0}, read={1}}}, + {{.MOV, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, 0xB8, 0, {force_rex_w=true}}, {written={0}, read={1}}}, + {{.MOV, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC6, 0, {modrm_reg_ext=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {modrm_reg_ext=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xC7, 0, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {}}, {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true}}, {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {}}, {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true}}, {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.RM16, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.RM64, .SREG, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8C, 0, {force_rex_w=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8E, 0, {force_rex_w=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F}}, {written={0}, read={1}}}, + {{.MOV, {.CR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F}}, {written={0}, read={1}}}, + {{.MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F}}, {written={0}, read={1}}}, + {{.MOV, {.DR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F}}, {written={0}, read={1}}}, }, - .MOVABS = { // 64-bit immediate MOV (alias for MOV with 64-bit imm) - {.MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, 0xB8, 0, {force_rex_w=true}}, - {.MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {}}, - {.MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, - {.MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, - {.MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true}}, - {.MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {}}, - {.MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, - {.MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, - {.MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true}}, + .MOVABS = { + {{.MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, 0xB8, 0, {force_rex_w=true}}, {written={0}, read={1}}}, + {{.MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA0, 0, {}}, {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {}}, {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, 0xA1, 0, {force_rex_w=true}}, {read={1}, implicit_wr={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA2, 0, {}}, {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {}}, {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}}, + {{.MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, 0xA3, 0, {force_rex_w=true}}, {written={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}}, }, .MOVZX = { - {.MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F}}, - {.MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F}}, - {.MOVZX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F, force_rex_w=true}}, - {.MOVZX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB7, 0, {esc=._0F}}, - {.MOVZX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB7, 0, {esc=._0F, force_rex_w=true}}, + {{.MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOVZX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB6, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOVZX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB7, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOVZX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB7, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, reads_mem=true}}, }, .MOVSX = { - {.MOVSX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F}}, - {.MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F}}, - {.MOVSX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F, force_rex_w=true}}, - {.MOVSX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBF, 0, {esc=._0F}}, - {.MOVSX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBF, 0, {esc=._0F, force_rex_w=true}}, + {{.MOVSX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOVSX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBE, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOVSX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBF, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, + {{.MOVSX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBF, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, reads_mem=true}}, }, .MOVSXD = { - {.MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x63, 0, {force_rex_w=true}}, + {{.MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x63, 0, {force_rex_w=true}}, {written={0}, read={1}, reads_mem=true}}, }, .XCHG = { - {.XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {}}, - {.XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {}}, - {.XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {force_rex_w=true}}, - {.XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x86, 0, {lock_ok=true}}, - {.XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true}}, - {.XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true}}, - {.XCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true, force_rex_w=true}}, + {{.XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {}}, {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}}, + {{.XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {}}, {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}}, + {{.XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0x90, 0, {force_rex_w=true}}, {written={1}, read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}}}, + {{.XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x86, 0, {lock_ok=true}}, {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}}, + {{.XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true}}, {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}}, + {{.XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {lock_ok=true}}, {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}}, + {{.XCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x87, 0, {force_rex_w=true, lock_ok=true}}, {written={0, 1}, read={0, 1}, writes_mem=true, reads_mem=true}}, }, .PUSH = { - {.PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x50, 0, {}}, - {.PUSH, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x50, 0, {default_64=true}}, - {.PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 6, {modrm_reg_ext=true}}, - {.PUSH, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 6, {modrm_reg_ext=true, default_64=true}}, - {.PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x6A, 0, {}}, - {.PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, 0x68, 0, {}}, - {.PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x68, 0, {}}, - {.PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA0, 0, {esc=._0F}}, - {.PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA8, 0, {esc=._0F}}, + {{.PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x50, 0, {}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}}, + {{.PUSH, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x50, 0, {default_64=true}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}}, + {{.PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 6, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}}, + {{.PUSH, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 6, {default_64=true, modrm_reg_ext=true}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}}, + {{.PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x6A, 0, {}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}}, + {{.PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, 0x68, 0, {}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}}, + {{.PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x68, 0, {}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}}, + {{.PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA0, 0, {esc=._0F}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}}, + {{.PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA8, 0, {esc=._0F}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true}}, }, .POP = { - {.POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x58, 0, {}}, - {.POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x58, 0, {default_64=true}}, - {.POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x8F, 0, {modrm_reg_ext=true}}, - {.POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x8F, 0, {modrm_reg_ext=true, default_64=true}}, - {.POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA1, 0, {esc=._0F}}, - {.POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA9, 0, {esc=._0F}}, + {{.POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x58, 0, {}}, {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}}, + {{.POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x58, 0, {default_64=true}}, {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}}, + {{.POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x8F, 0, {modrm_reg_ext=true}}, {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}}, + {{.POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x8F, 0, {default_64=true, modrm_reg_ext=true}}, {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true}}, + {{.POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA1, 0, {esc=._0F}}, {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}}, + {{.POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xA9, 0, {esc=._0F}}, {written={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true}}, }, .LEA = { - {.LEA, {.R16, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {}}, - {.LEA, {.R32, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {}}, - {.LEA, {.R64, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {force_rex_w=true}}, + {{.LEA, {.R16, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {}}, {written={0}}}, + {{.LEA, {.R32, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {}}, {written={0}}}, + {{.LEA, {.R64, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x8D, 0, {force_rex_w=true}}, {written={0}}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.2 Arithmetic Encodings - // ------------------------------------------------------------------------- .ADD = { - {.ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x00, 0, {lock_ok=true}}, - {.ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {lock_ok=true}}, - {.ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {lock_ok=true}}, - {.ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {lock_ok=true, force_rex_w=true}}, - {.ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {}}, - {.ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {}}, - {.ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {}}, - {.ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {force_rex_w=true}}, - {.ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x04, 0, {}}, - {.ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x05, 0, {}}, - {.ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {}}, - {.ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {force_rex_w=true}}, - {.ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 0, {modrm_reg_ext=true, lock_ok=true}}, - {.ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 0, {modrm_reg_ext=true, lock_ok=true}}, - {.ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 0, {modrm_reg_ext=true, lock_ok=true}}, - {.ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 0, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, - {.ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {modrm_reg_ext=true, lock_ok=true}}, - {.ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {modrm_reg_ext=true, lock_ok=true}}, - {.ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x00, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x01, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x04, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x05, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x05, 0, {force_rex_w=true}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 0, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 0, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 0, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 0, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 0, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, }, .ADC = { - {.ADC, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {lock_ok=true}}, - {.ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {lock_ok=true}}, - {.ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {lock_ok=true}}, - {.ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {lock_ok=true, force_rex_w=true}}, - {.ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {}}, - {.ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {}}, - {.ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {}}, - {.ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {force_rex_w=true}}, - {.ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x14, 0, {}}, - {.ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x15, 0, {}}, - {.ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {}}, - {.ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {force_rex_w=true}}, - {.ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 2, {modrm_reg_ext=true, lock_ok=true}}, - {.ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 2, {modrm_reg_ext=true, lock_ok=true}}, - {.ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 2, {modrm_reg_ext=true, lock_ok=true}}, - {.ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 2, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, - {.ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {modrm_reg_ext=true, lock_ok=true}}, - {.ADC, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {modrm_reg_ext=true, lock_ok=true}}, - {.ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.ADC, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x14, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, + {{.ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x15, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, + {{.ADC, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, + {{.ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x15, 0, {force_rex_w=true}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, + {{.ADC, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 2, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 2, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 2, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 2, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 2, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, }, .SUB = { - {.SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x28, 0, {lock_ok=true}}, - {.SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {lock_ok=true}}, - {.SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {lock_ok=true}}, - {.SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {lock_ok=true, force_rex_w=true}}, - {.SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {}}, - {.SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {}}, - {.SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {}}, - {.SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {force_rex_w=true}}, - {.SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x2C, 0, {}}, - {.SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x2D, 0, {}}, - {.SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {}}, - {.SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {force_rex_w=true}}, - {.SUB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 5, {modrm_reg_ext=true, lock_ok=true}}, - {.SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 5, {modrm_reg_ext=true, lock_ok=true}}, - {.SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 5, {modrm_reg_ext=true, lock_ok=true}}, - {.SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 5, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, - {.SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {modrm_reg_ext=true, lock_ok=true}}, - {.SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {modrm_reg_ext=true, lock_ok=true}}, - {.SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x28, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x2C, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x2D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x2D, 0, {force_rex_w=true}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.SUB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 5, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 5, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 5, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 5, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 5, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, }, .SBB = { - {.SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x18, 0, {lock_ok=true}}, - {.SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {lock_ok=true}}, - {.SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {lock_ok=true}}, - {.SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {lock_ok=true, force_rex_w=true}}, - {.SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1A, 0, {}}, - {.SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {}}, - {.SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {}}, - {.SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {force_rex_w=true}}, - {.SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x1C, 0, {}}, - {.SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x1D, 0, {}}, - {.SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {}}, - {.SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {force_rex_w=true}}, - {.SBB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 3, {modrm_reg_ext=true, lock_ok=true}}, - {.SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 3, {modrm_reg_ext=true, lock_ok=true}}, - {.SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 3, {modrm_reg_ext=true, lock_ok=true}}, - {.SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 3, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, - {.SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {modrm_reg_ext=true, lock_ok=true}}, - {.SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {modrm_reg_ext=true, lock_ok=true}}, - {.SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x18, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x19, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1A, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1B, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x1C, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, + {{.SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x1D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, + {{.SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, + {{.SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x1D, 0, {force_rex_w=true}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}}}, + {{.SBB, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 3, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 3, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 3, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 3, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 3, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, }, .MUL = { - {.MUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 4, {modrm_reg_ext=true}}, - {.MUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {modrm_reg_ext=true}}, - {.MUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {modrm_reg_ext=true}}, - {.MUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {modrm_reg_ext=true, force_rex_w=true}}, + {{.MUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 4, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.MUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.MUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.MUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 4, {force_rex_w=true, modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, }, .IMUL = { - {.IMUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 5, {modrm_reg_ext=true}}, - {.IMUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {modrm_reg_ext=true}}, - {.IMUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {modrm_reg_ext=true}}, - {.IMUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {modrm_reg_ext=true, force_rex_w=true}}, - {.IMUL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F}}, - {.IMUL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F}}, - {.IMUL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F, force_rex_w=true}}, - {.IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {}}, - {.IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {}}, - {.IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {force_rex_w=true}}, - {.IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, 0x69, 0, {}}, - {.IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, 0x69, 0, {}}, - {.IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, 0x69, 0, {force_rex_w=true}}, + {{.IMUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 5, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 5, {force_rex_w=true, modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xAF, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {}}, {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {}}, {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, 0x6B, 0, {force_rex_w=true}}, {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, 0x69, 0, {}}, {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, 0x69, 0, {}}, {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, + {{.IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, 0x69, 0, {force_rex_w=true}}, {written={0}, read={1, 2}, flags_wr={.CF, .OF}, flags_undef={.PF, .AF, .ZF, .SF}, reads_mem=true}}, }, .DIV = { - {.DIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 6, {modrm_reg_ext=true}}, - {.DIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {modrm_reg_ext=true}}, - {.DIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {modrm_reg_ext=true}}, - {.DIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {modrm_reg_ext=true, force_rex_w=true}}, + {{.DIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 6, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.DIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.DIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.DIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 6, {force_rex_w=true, modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, .IDIV = { - {.IDIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 7, {modrm_reg_ext=true}}, - {.IDIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {modrm_reg_ext=true}}, - {.IDIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {modrm_reg_ext=true}}, - {.IDIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {modrm_reg_ext=true, force_rex_w=true}}, + {{.IDIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 7, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.IDIV, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.IDIV, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.IDIV, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 7, {force_rex_w=true, modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RDX}, flags_undef={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, .INC = { - // i386 short forms (0x40+rd / 0x48+rd) -- 1 byte vs 2 bytes for FF /0. - // These collide with REX in long mode so the matcher filters them - // out when mode != _32 via mode_32_only. Listed first so the encoder - // prefers them in i386. - {.INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x40, 0, {mode_32_only=true}}, - {.INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x40, 0, {mode_32_only=true}}, - - {.INC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFE, 0, {modrm_reg_ext=true, lock_ok=true}}, - {.INC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {modrm_reg_ext=true, lock_ok=true}}, - {.INC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {modrm_reg_ext=true, lock_ok=true}}, - {.INC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x40, 0, {mode_32_only=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}}, + {{.INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x40, 0, {mode_32_only=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}}, + {{.INC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFE, 0, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.INC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.INC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.INC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 0, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, }, .DEC = { - // i386 short forms -- see comment on .INC. - {.DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x48, 0, {mode_32_only=true}}, - {.DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x48, 0, {mode_32_only=true}}, - - {.DEC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFE, 1, {modrm_reg_ext=true, lock_ok=true}}, - {.DEC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {modrm_reg_ext=true, lock_ok=true}}, - {.DEC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {modrm_reg_ext=true, lock_ok=true}}, - {.DEC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x48, 0, {mode_32_only=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}}, + {{.DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0x48, 0, {mode_32_only=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}}}, + {{.DEC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFE, 1, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.DEC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.DEC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.DEC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 1, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, }, .NEG = { - {.NEG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 3, {modrm_reg_ext=true, lock_ok=true}}, - {.NEG, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {modrm_reg_ext=true, lock_ok=true}}, - {.NEG, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {modrm_reg_ext=true, lock_ok=true}}, - {.NEG, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.NEG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 3, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.NEG, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.NEG, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.NEG, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 3, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, }, .CMP = { - {.CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x38, 0, {}}, - {.CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {}}, - {.CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {}}, - {.CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {force_rex_w=true}}, - {.CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3A, 0, {}}, - {.CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {}}, - {.CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {}}, - {.CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {force_rex_w=true}}, - {.CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x3C, 0, {}}, - {.CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x3D, 0, {}}, - {.CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {}}, - {.CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {force_rex_w=true}}, - {.CMP, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 7, {modrm_reg_ext=true}}, - {.CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true}}, - {.CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true}}, - {.CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true, force_rex_w=true}}, - {.CMP, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {modrm_reg_ext=true}}, - {.CMP, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {modrm_reg_ext=true}}, - {.CMP, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {modrm_reg_ext=true, force_rex_w=true}}, + {{.CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x38, 0, {}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x39, 0, {force_rex_w=true}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3A, 0, {}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {force_rex_w=true}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x3C, 0, {}}, {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x3D, 0, {}}, {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {}}, {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x3D, 0, {force_rex_w=true}}, {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.CMP, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 7, {modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 7, {modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 7, {force_rex_w=true, modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.CMP, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 7, {force_rex_w=true, modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.3 Logical Encodings - // ------------------------------------------------------------------------- .AND = { - {.AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {lock_ok=true}}, - {.AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {lock_ok=true}}, - {.AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {lock_ok=true}}, - {.AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {lock_ok=true, force_rex_w=true}}, - {.AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {}}, - {.AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {}}, - {.AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {}}, - {.AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {force_rex_w=true}}, - {.AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x24, 0, {}}, - {.AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x25, 0, {}}, - {.AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {}}, - {.AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {force_rex_w=true}}, - {.AND, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 4, {modrm_reg_ext=true, lock_ok=true}}, - {.AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 4, {modrm_reg_ext=true, lock_ok=true}}, - {.AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 4, {modrm_reg_ext=true, lock_ok=true}}, - {.AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 4, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, - {.AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {modrm_reg_ext=true, lock_ok=true}}, - {.AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {modrm_reg_ext=true, lock_ok=true}}, - {.AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x24, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x25, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x25, 0, {force_rex_w=true}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.AND, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 4, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 4, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 4, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 4, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 4, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, }, .OR = { - {.OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x08, 0, {lock_ok=true}}, - {.OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {lock_ok=true}}, - {.OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {lock_ok=true}}, - {.OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {lock_ok=true, force_rex_w=true}}, - {.OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0A, 0, {}}, - {.OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {}}, - {.OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {}}, - {.OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {force_rex_w=true}}, - {.OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x0C, 0, {}}, - {.OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x0D, 0, {}}, - {.OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {}}, - {.OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {force_rex_w=true}}, - {.OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 1, {modrm_reg_ext=true, lock_ok=true}}, - {.OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 1, {modrm_reg_ext=true, lock_ok=true}}, - {.OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 1, {modrm_reg_ext=true, lock_ok=true}}, - {.OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 1, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, - {.OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {modrm_reg_ext=true, lock_ok=true}}, - {.OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {modrm_reg_ext=true, lock_ok=true}}, - {.OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x08, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x09, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0A, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x0C, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x0D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.OR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x0D, 0, {force_rex_w=true}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 1, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 1, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 1, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 1, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 1, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, }, .XOR = { - {.XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {lock_ok=true}}, - {.XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {lock_ok=true}}, - {.XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {lock_ok=true}}, - {.XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {lock_ok=true, force_rex_w=true}}, - {.XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {}}, - {.XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {}}, - {.XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {}}, - {.XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {force_rex_w=true}}, - {.XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x34, 0, {}}, - {.XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x35, 0, {}}, - {.XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {}}, - {.XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {force_rex_w=true}}, - {.XOR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 6, {modrm_reg_ext=true, lock_ok=true}}, - {.XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 6, {modrm_reg_ext=true, lock_ok=true}}, - {.XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 6, {modrm_reg_ext=true, lock_ok=true}}, - {.XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 6, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, - {.XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {modrm_reg_ext=true, lock_ok=true}}, - {.XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {modrm_reg_ext=true, lock_ok=true}}, - {.XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0x34, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0x35, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0x35, 0, {force_rex_w=true}}, {read={1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.XOR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x80, 6, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0x81, 6, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 6, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0x81, 6, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x83, 6, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, }, .NOT = { - {.NOT, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 2, {modrm_reg_ext=true, lock_ok=true}}, - {.NOT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {modrm_reg_ext=true, lock_ok=true}}, - {.NOT, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {modrm_reg_ext=true, lock_ok=true}}, - {.NOT, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.NOT, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF6, 2, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, writes_mem=true, reads_mem=true}}, + {{.NOT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, writes_mem=true, reads_mem=true}}, + {{.NOT, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, writes_mem=true, reads_mem=true}}, + {{.NOT, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xF7, 2, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0}, writes_mem=true, reads_mem=true}}, }, .TEST = { - {.TEST, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x84, 0, {}}, - {.TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {}}, - {.TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {}}, - {.TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {force_rex_w=true}}, - {.TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0xA8, 0, {}}, - {.TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0xA9, 0, {}}, - {.TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {}}, - {.TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {force_rex_w=true}}, - {.TEST, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xF6, 0, {modrm_reg_ext=true}}, - {.TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true}}, - {.TEST, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true}}, - {.TEST, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true, force_rex_w=true}}, + {{.TEST, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x84, 0, {}}, {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {}}, {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {}}, {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x85, 0, {force_rex_w=true}}, {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, 0xA8, 0, {}}, {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, 0xA9, 0, {}}, {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {}}, {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, 0xA9, 0, {force_rex_w=true}}, {read={1}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}}}, + {{.TEST, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xF6, 0, {modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.TEST, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, + {{.TEST, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, 0xF7, 0, {force_rex_w=true, modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.4 Shift/Rotate Encodings - // ------------------------------------------------------------------------- .SHL = { - {.SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true}}, - {.SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true, force_rex_w=true}}, - {.SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true, force_rex_w=true}}, - {.SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true, force_rex_w=true}}, + {{.SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 4, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 4, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 4, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 4, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, }, .SHR = { - {.SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true}}, - {.SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true, force_rex_w=true}}, - {.SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true, force_rex_w=true}}, - {.SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true, force_rex_w=true}}, + {{.SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 5, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 5, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 5, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 5, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 5, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 5, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, }, .SAR = { - {.SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true}}, - {.SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true, force_rex_w=true}}, - {.SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true, force_rex_w=true}}, - {.SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true, force_rex_w=true}}, + {{.SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 7, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 7, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 7, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 7, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 7, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, + {{.SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 7, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .PF, .ZF, .SF, .OF}, flags_undef={.AF}, writes_mem=true, reads_mem=true}}, }, .ROL = { - {.ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true}}, - {.ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true, force_rex_w=true}}, - {.ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true, force_rex_w=true}}, - {.ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true, force_rex_w=true}}, + {{.ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 0, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 0, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 0, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 0, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 0, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 0, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, }, .ROR = { - {.ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true}}, - {.ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true, force_rex_w=true}}, - {.ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true, force_rex_w=true}}, - {.ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true, force_rex_w=true}}, + {{.ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 1, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 1, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 1, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 1, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 1, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, + {{.ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 1, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, writes_mem=true, reads_mem=true}}, }, .RCL = { - {.RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true}}, - {.RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true, force_rex_w=true}}, - {.RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true, force_rex_w=true}}, - {.RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true, force_rex_w=true}}, + {{.RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 2, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 2, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 2, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 2, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 2, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 2, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, }, .RCR = { - {.RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true}}, - {.RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true, force_rex_w=true}}, - {.RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true, force_rex_w=true}}, - {.RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true, force_rex_w=true}}, + {{.RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD0, 3, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD2, 3, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC0, 3, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD1, 3, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, 0xD3, 3, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0}, implicit_rd={.RCX}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, + {{.RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xC1, 3, {force_rex_w=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF, .OF}, flags_rd={.CF}, writes_mem=true, reads_mem=true}}, }, .SHLD = { - {.SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F}}, - {.SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F}}, - {.SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, force_rex_w=true}}, - {.SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F}}, - {.SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F}}, - {.SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, force_rex_w=true}}, + {{.SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F}}, {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F}}, {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xA4, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F}}, {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F}}, {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xA5, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, }, .SHRD = { - {.SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F}}, - {.SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F}}, - {.SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, force_rex_w=true}}, - {.SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F}}, - {.SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F}}, - {.SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, force_rex_w=true}}, + {{.SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F}}, {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F}}, {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0xAC, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={0, 1, 2}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F}}, {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F}}, {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, + {{.SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, 0xAD, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={0, 1}, implicit_rd={.RCX}, flags_wr={.CF, .PF, .ZF, .SF}, flags_undef={.AF, .OF}, writes_mem=true, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.5 Bit Operation Encodings - // ------------------------------------------------------------------------- .BT = { - {.BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F}}, - {.BT, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F}}, - {.BT, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F, force_rex_w=true}}, - {.BT, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, modrm_reg_ext=true}}, - {.BT, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, modrm_reg_ext=true}}, - {.BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F}}, {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.BT, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F}}, {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.BT, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F, force_rex_w=true}}, {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.BT, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.BT, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, }, .BTS = { - {.BTS, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, lock_ok=true}}, - {.BTS, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, lock_ok=true}}, - {.BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, lock_ok=true, force_rex_w=true}}, - {.BTS, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, modrm_reg_ext=true, lock_ok=true}}, - {.BTS, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, modrm_reg_ext=true, lock_ok=true}}, - {.BTS, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.BTS, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTS, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xAB, 0, {esc=._0F, force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTS, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTS, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTS, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 5, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, }, .BTR = { - {.BTR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, lock_ok=true}}, - {.BTR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, lock_ok=true}}, - {.BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, lock_ok=true, force_rex_w=true}}, - {.BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, modrm_reg_ext=true, lock_ok=true}}, - {.BTR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, modrm_reg_ext=true, lock_ok=true}}, - {.BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.BTR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB3, 0, {esc=._0F, force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 6, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, }, .BTC = { - {.BTC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, lock_ok=true}}, - {.BTC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, lock_ok=true}}, - {.BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, lock_ok=true, force_rex_w=true}}, - {.BTC, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, modrm_reg_ext=true, lock_ok=true}}, - {.BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, modrm_reg_ext=true, lock_ok=true}}, - {.BTC, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.BTC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xBB, 0, {esc=._0F, force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTC, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.BTC, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0xBA, 7, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_undef={.PF, .AF, .SF, .OF}, writes_mem=true, reads_mem=true}}, }, .BSF = { - {.BSF, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F}}, - {.BSF, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F}}, - {.BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, force_rex_w=true}}, + {{.BSF, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F}}, {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.BSF, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F}}, {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}}, }, .BSR = { - {.BSR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F}}, - {.BSR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F}}, - {.BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, force_rex_w=true}}, + {{.BSR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F}}, {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.BSR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F}}, {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_wr={.ZF}, flags_undef={.CF, .PF, .AF, .SF, .OF}, reads_mem=true}}, }, .POPCNT = { - {.POPCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.POPCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.POPCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, + {{.POPCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.POPCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, + {{.POPCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB8, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, .LZCNT = { - {.LZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.LZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, + {{.LZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.LZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBD, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, }, .TZCNT = { - {.TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.TZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, + {{.TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.TZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xBC, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, {written={0}, read={1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.6 Control Flow Encodings - // ------------------------------------------------------------------------- .JMP = { - {.JMP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xEB, 0, {}}, - {.JMP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0xE9, 0, {}}, - {.JMP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 4, {modrm_reg_ext=true, default_64=true}}, - {.JMP, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {modrm_reg_ext=true}}, - {.JMP, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {modrm_reg_ext=true}}, - {.JMP, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {modrm_reg_ext=true, force_rex_w=true}}, + {{.JMP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xEB, 0, {}}, {read={0}, side_effects={.CONTROL}}}, + {{.JMP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0xE9, 0, {}}, {read={0}, side_effects={.CONTROL}}}, + {{.JMP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 4, {default_64=true, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.CONTROL}}}, + {{.JMP, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.CONTROL}}}, + {{.JMP, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.CONTROL}}}, + {{.JMP, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 5, {force_rex_w=true, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.CONTROL}}}, }, .JA = { - {.JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x77, 0, {}}, - {.JA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x87, 0, {esc=._0F}}, + {{.JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x77, 0, {}}, {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}}, + {{.JA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x87, 0, {esc=._0F}}, {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}}, }, .JAE = { - {.JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {}}, - {.JAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F}}, + {{.JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, + {{.JAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, }, .JB = { - {.JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {}}, - {.JB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F}}, + {{.JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, + {{.JB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, }, .JBE = { - {.JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x76, 0, {}}, - {.JBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x86, 0, {esc=._0F}}, + {{.JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x76, 0, {}}, {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}}, + {{.JBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x86, 0, {esc=._0F}}, {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}}, }, - .JC = { // Alias for JB (carry = below) - {.JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {}}, - {.JC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F}}, + .JC = { + {{.JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, + {{.JC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, }, .JE = { - {.JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x74, 0, {}}, - {.JE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x84, 0, {esc=._0F}}, + {{.JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x74, 0, {}}, {flags_rd={.ZF}, side_effects={.CONTROL}}}, + {{.JE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x84, 0, {esc=._0F}}, {flags_rd={.ZF}, side_effects={.CONTROL}}}, }, - .JZ = { // Alias for JE (zero = equal) - {.JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x74, 0, {}}, - {.JZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x84, 0, {esc=._0F}}, + .JZ = { + {{.JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x74, 0, {}}, {flags_rd={.ZF}, side_effects={.CONTROL}}}, + {{.JZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x84, 0, {esc=._0F}}, {flags_rd={.ZF}, side_effects={.CONTROL}}}, }, .JG = { - {.JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7F, 0, {}}, - {.JG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8F, 0, {esc=._0F}}, + {{.JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7F, 0, {}}, {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}}, + {{.JG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8F, 0, {esc=._0F}}, {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}}, }, .JGE = { - {.JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7D, 0, {}}, - {.JGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8D, 0, {esc=._0F}}, + {{.JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7D, 0, {}}, {flags_rd={.SF, .OF}, side_effects={.CONTROL}}}, + {{.JGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8D, 0, {esc=._0F}}, {flags_rd={.SF, .OF}, side_effects={.CONTROL}}}, }, .JL = { - {.JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7C, 0, {}}, - {.JL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8C, 0, {esc=._0F}}, + {{.JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7C, 0, {}}, {flags_rd={.SF, .OF}, side_effects={.CONTROL}}}, + {{.JL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8C, 0, {esc=._0F}}, {flags_rd={.SF, .OF}, side_effects={.CONTROL}}}, }, .JLE = { - {.JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7E, 0, {}}, - {.JLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8E, 0, {esc=._0F}}, + {{.JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7E, 0, {}}, {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}}, + {{.JLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8E, 0, {esc=._0F}}, {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}}, }, - .JNA = { // Alias for JBE (not above = below or equal) - {.JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x76, 0, {}}, - {.JNA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x86, 0, {esc=._0F}}, + .JNA = { + {{.JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x76, 0, {}}, {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}}, + {{.JNA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x86, 0, {esc=._0F}}, {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}}, }, - .JNAE = { // Alias for JB (not above or equal = below) - {.JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {}}, - {.JNAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F}}, + .JNAE = { + {{.JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x72, 0, {}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, + {{.JNAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x82, 0, {esc=._0F}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, }, - .JNB = { // Alias for JAE (not below = above or equal) - {.JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {}}, - {.JNB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F}}, + .JNB = { + {{.JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, + {{.JNB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, }, - .JNBE = { // Alias for JA (not below or equal = above) - {.JNBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x77, 0, {}}, - {.JNBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x87, 0, {esc=._0F}}, + .JNBE = { + {{.JNBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x77, 0, {}}, {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}}, + {{.JNBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x87, 0, {esc=._0F}}, {flags_rd={.CF, .ZF}, side_effects={.CONTROL}}}, }, - .JNC = { // Alias for JAE (no carry = above or equal) - {.JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {}}, - {.JNC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F}}, + .JNC = { + {{.JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x73, 0, {}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, + {{.JNC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x83, 0, {esc=._0F}}, {flags_rd={.CF}, side_effects={.CONTROL}}}, }, .JNE = { - {.JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x75, 0, {}}, - {.JNE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x85, 0, {esc=._0F}}, + {{.JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x75, 0, {}}, {flags_rd={.ZF}, side_effects={.CONTROL}}}, + {{.JNE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x85, 0, {esc=._0F}}, {flags_rd={.ZF}, side_effects={.CONTROL}}}, }, - .JNZ = { // Alias for JNE (not zero = not equal) - {.JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x75, 0, {}}, - {.JNZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x85, 0, {esc=._0F}}, + .JNZ = { + {{.JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x75, 0, {}}, {flags_rd={.ZF}, side_effects={.CONTROL}}}, + {{.JNZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x85, 0, {esc=._0F}}, {flags_rd={.ZF}, side_effects={.CONTROL}}}, }, - .JNG = { // Alias for JLE (not greater = less or equal) - {.JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7E, 0, {}}, - {.JNG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8E, 0, {esc=._0F}}, + .JNG = { + {{.JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7E, 0, {}}, {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}}, + {{.JNG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8E, 0, {esc=._0F}}, {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}}, }, - .JNGE = { // Alias for JL (not greater or equal = less) - {.JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7C, 0, {}}, - {.JNGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8C, 0, {esc=._0F}}, + .JNGE = { + {{.JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7C, 0, {}}, {flags_rd={.SF, .OF}, side_effects={.CONTROL}}}, + {{.JNGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8C, 0, {esc=._0F}}, {flags_rd={.SF, .OF}, side_effects={.CONTROL}}}, }, - .JNL = { // Alias for JGE (not less = greater or equal) - {.JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7D, 0, {}}, - {.JNL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8D, 0, {esc=._0F}}, + .JNL = { + {{.JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7D, 0, {}}, {flags_rd={.SF, .OF}, side_effects={.CONTROL}}}, + {{.JNL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8D, 0, {esc=._0F}}, {flags_rd={.SF, .OF}, side_effects={.CONTROL}}}, }, - .JNLE = { // Alias for JG (not less or equal = greater) - {.JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7F, 0, {}}, - {.JNLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8F, 0, {esc=._0F}}, + .JNLE = { + {{.JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7F, 0, {}}, {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}}, + {{.JNLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8F, 0, {esc=._0F}}, {flags_rd={.ZF, .SF, .OF}, side_effects={.CONTROL}}}, }, .JNO = { - {.JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x71, 0, {}}, - {.JNO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x81, 0, {esc=._0F}}, + {{.JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x71, 0, {}}, {flags_rd={.OF}, side_effects={.CONTROL}}}, + {{.JNO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x81, 0, {esc=._0F}}, {flags_rd={.OF}, side_effects={.CONTROL}}}, }, .JNP = { - {.JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7B, 0, {}}, - {.JNP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8B, 0, {esc=._0F}}, + {{.JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7B, 0, {}}, {flags_rd={.PF}, side_effects={.CONTROL}}}, + {{.JNP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8B, 0, {esc=._0F}}, {flags_rd={.PF}, side_effects={.CONTROL}}}, }, .JNS = { - {.JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x79, 0, {}}, - {.JNS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x89, 0, {esc=._0F}}, + {{.JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x79, 0, {}}, {flags_rd={.SF}, side_effects={.CONTROL}}}, + {{.JNS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x89, 0, {esc=._0F}}, {flags_rd={.SF}, side_effects={.CONTROL}}}, }, .JO = { - {.JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x70, 0, {}}, - {.JO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x80, 0, {esc=._0F}}, + {{.JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x70, 0, {}}, {flags_rd={.OF}, side_effects={.CONTROL}}}, + {{.JO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x80, 0, {esc=._0F}}, {flags_rd={.OF}, side_effects={.CONTROL}}}, }, .JP = { - {.JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7A, 0, {}}, - {.JP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8A, 0, {esc=._0F}}, + {{.JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7A, 0, {}}, {flags_rd={.PF}, side_effects={.CONTROL}}}, + {{.JP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8A, 0, {esc=._0F}}, {flags_rd={.PF}, side_effects={.CONTROL}}}, }, - .JPE = { // Alias for JP (parity even = parity) - {.JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7A, 0, {}}, - {.JPE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8A, 0, {esc=._0F}}, + .JPE = { + {{.JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7A, 0, {}}, {flags_rd={.PF}, side_effects={.CONTROL}}}, + {{.JPE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8A, 0, {esc=._0F}}, {flags_rd={.PF}, side_effects={.CONTROL}}}, }, - .JPO = { // Alias for JNP (parity odd = no parity) - {.JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7B, 0, {}}, - {.JPO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8B, 0, {esc=._0F}}, + .JPO = { + {{.JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x7B, 0, {}}, {flags_rd={.PF}, side_effects={.CONTROL}}}, + {{.JPO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x8B, 0, {esc=._0F}}, {flags_rd={.PF}, side_effects={.CONTROL}}}, }, .JS = { - {.JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x78, 0, {}}, - {.JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x88, 0, {esc=._0F}}, + {{.JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x78, 0, {}}, {flags_rd={.SF}, side_effects={.CONTROL}}}, + {{.JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x88, 0, {esc=._0F}}, {flags_rd={.SF}, side_effects={.CONTROL}}}, }, - .JCXZ = { // Jump if CX is zero (16-bit mode) - needs address size override - {.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {}}, + .JCXZ = { + {{.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, }, - .JECXZ = { // Jump if ECX is zero (32-bit mode) - {.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {}}, + .JECXZ = { + {{.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, }, - .JRCXZ = { // Jump if RCX is zero (64-bit mode) - {.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {force_rex_w=true}}, + .JRCXZ = { + {{.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {force_rex_w=true}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, }, .LOOP = { - {.LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE2, 0, {}}, + {{.LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE2, 0, {}}, {implicit_wr={.RCX}, implicit_rd={.RCX}, side_effects={.CONTROL}}}, }, .LOOPE = { - {.LOOPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE1, 0, {}}, + {{.LOOPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE1, 0, {}}, {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}}, }, .LOOPNE = { - {.LOOPNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE0, 0, {}}, + {{.LOOPNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE0, 0, {}}, {implicit_wr={.RCX}, implicit_rd={.RCX}, flags_rd={.ZF}, side_effects={.CONTROL}}}, }, .CALL = { - {.CALL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0xE8, 0, {}}, - {.CALL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 2, {modrm_reg_ext=true, default_64=true}}, - {.CALL, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {modrm_reg_ext=true}}, - {.CALL, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {modrm_reg_ext=true}}, - {.CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {modrm_reg_ext=true, force_rex_w=true}}, + {{.CALL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0xE8, 0, {}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, side_effects={.CONTROL}}}, + {{.CALL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 2, {default_64=true, modrm_reg_ext=true}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}}, + {{.CALL, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}}, + {{.CALL, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {modrm_reg_ext=true}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}}, + {{.CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xFF, 3, {force_rex_w=true, modrm_reg_ext=true}}, {read={0}, implicit_wr={.RSP}, implicit_rd={.RSP}, writes_mem=true, reads_mem=true, side_effects={.CONTROL}}}, }, .RET = { - {.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xC3, 0, {}}, - {.RET, {.IMM16, .NONE, .NONE, .NONE}, {.IW , .NONE, .NONE, .NONE}, 0xC2, 0, {}}, + {{.RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xC3, 0, {}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}}, + {{.RET, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, 0xC2, 0, {}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, reads_mem=true, side_effects={.CONTROL}}}, }, .IRET = { - {.IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCF, 0, {opsize_16=true}}, + {{.IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCF, 0, {opsize_16=true}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}}, }, .IRETD = { - {.IRETD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCF, 0, {}}, + {{.IRETD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCF, 0, {}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}}, }, .IRETQ = { - {.IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCF, 0, {force_rex_w=true}}, + {{.IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCF, 0, {force_rex_w=true}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true, side_effects={.SERIALIZING, .CONTROL}}}, }, .INT = { - {.INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xCD, 0, {}}, + {{.INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xCD, 0, {}}, {read={0}, implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}}, }, .INT3 = { - {.INT3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCC, 0, {}}, + {{.INT3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCC, 0, {}}, {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}}, }, - .INTO = { // Interrupt on overflow (invalid in 64-bit mode) - {.INTO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCE, 0, {}}, + .INTO = { + {{.INTO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xCE, 0, {}}, {implicit_wr={.RSP}, flags_wr={.IF}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true, side_effects={.INTERRUPT, .CONTROL}}}, }, .SYSCALL = { - {.SYSCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x05, 0, {esc=._0F}}, + {{.SYSCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x05, 0, {esc=._0F}}, {implicit_wr={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.INTERRUPT, .CONTROL}}}, }, .SYSRET = { - {.SYSRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x07, 0, {esc=._0F}}, + {{.SYSRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x07, 0, {esc=._0F}}, {implicit_rd={.RCX, .R11}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}}, }, .SYSENTER = { - {.SYSENTER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x34, 0, {esc=._0F}}, + {{.SYSENTER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x34, 0, {esc=._0F}}, {implicit_wr={.RSP}, flags_wr={.IF}, side_effects={.INTERRUPT, .CONTROL}}}, }, .SYSEXIT = { - {.SYSEXIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x35, 0, {esc=._0F}}, + {{.SYSEXIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x35, 0, {esc=._0F}}, {implicit_wr={.RSP}, implicit_rd={.RCX, .RDX}, side_effects={.SERIALIZING, .INTERRUPT, .PRIVILEGED, .CONTROL}}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.7 Conditional Set/Move Encodings - // ------------------------------------------------------------------------- .SETA = { - {.SETA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x97, 0, {esc=._0F}}, + {{.SETA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x97, 0, {esc=._0F}}, {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}}, }, .SETAE = { - {.SETAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F}}, + {{.SETAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F}}, {written={0}, flags_rd={.CF}, writes_mem=true}}, }, .SETB = { - {.SETB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F}}, + {{.SETB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F}}, {written={0}, flags_rd={.CF}, writes_mem=true}}, }, .SETBE = { - {.SETBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x96, 0, {esc=._0F}}, + {{.SETBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x96, 0, {esc=._0F}}, {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}}, }, - .SETC = { // Alias for SETB (carry = below) - {.SETC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F}}, + .SETC = { + {{.SETC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F}}, {written={0}, flags_rd={.CF}, writes_mem=true}}, }, .SETE = { - {.SETE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x94, 0, {esc=._0F}}, + {{.SETE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x94, 0, {esc=._0F}}, {written={0}, flags_rd={.ZF}, writes_mem=true}}, }, .SETG = { - {.SETG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9F, 0, {esc=._0F}}, + {{.SETG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9F, 0, {esc=._0F}}, {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}}, }, .SETGE = { - {.SETGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9D, 0, {esc=._0F}}, + {{.SETGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9D, 0, {esc=._0F}}, {written={0}, flags_rd={.SF, .OF}, writes_mem=true}}, }, .SETL = { - {.SETL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9C, 0, {esc=._0F}}, + {{.SETL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9C, 0, {esc=._0F}}, {written={0}, flags_rd={.SF, .OF}, writes_mem=true}}, }, .SETLE = { - {.SETLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9E, 0, {esc=._0F}}, + {{.SETLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9E, 0, {esc=._0F}}, {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}}, }, - .SETNA = { // Alias for SETBE - {.SETNA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x96, 0, {esc=._0F}}, + .SETNA = { + {{.SETNA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x96, 0, {esc=._0F}}, {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}}, }, - .SETNAE = { // Alias for SETB - {.SETNAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F}}, + .SETNAE = { + {{.SETNAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x92, 0, {esc=._0F}}, {written={0}, flags_rd={.CF}, writes_mem=true}}, }, - .SETNB = { // Alias for SETAE - {.SETNB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F}}, + .SETNB = { + {{.SETNB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F}}, {written={0}, flags_rd={.CF}, writes_mem=true}}, }, - .SETNBE = { // Alias for SETA - {.SETNBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x97, 0, {esc=._0F}}, + .SETNBE = { + {{.SETNBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x97, 0, {esc=._0F}}, {written={0}, flags_rd={.CF, .ZF}, writes_mem=true}}, }, - .SETNC = { // Alias for SETAE - {.SETNC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F}}, + .SETNC = { + {{.SETNC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x93, 0, {esc=._0F}}, {written={0}, flags_rd={.CF}, writes_mem=true}}, }, .SETNE = { - {.SETNE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x95, 0, {esc=._0F}}, + {{.SETNE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x95, 0, {esc=._0F}}, {written={0}, flags_rd={.ZF}, writes_mem=true}}, }, - .SETNG = { // Alias for SETLE - {.SETNG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9E, 0, {esc=._0F}}, + .SETNG = { + {{.SETNG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9E, 0, {esc=._0F}}, {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}}, }, - .SETNGE = { // Alias for SETL - {.SETNGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9C, 0, {esc=._0F}}, + .SETNGE = { + {{.SETNGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9C, 0, {esc=._0F}}, {written={0}, flags_rd={.SF, .OF}, writes_mem=true}}, }, - .SETNL = { // Alias for SETGE - {.SETNL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9D, 0, {esc=._0F}}, + .SETNL = { + {{.SETNL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9D, 0, {esc=._0F}}, {written={0}, flags_rd={.SF, .OF}, writes_mem=true}}, }, - .SETNLE = { // Alias for SETG - {.SETNLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9F, 0, {esc=._0F}}, + .SETNLE = { + {{.SETNLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9F, 0, {esc=._0F}}, {written={0}, flags_rd={.ZF, .SF, .OF}, writes_mem=true}}, }, .SETNO = { - {.SETNO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x91, 0, {esc=._0F}}, + {{.SETNO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x91, 0, {esc=._0F}}, {written={0}, flags_rd={.OF}, writes_mem=true}}, }, .SETNP = { - {.SETNP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9B, 0, {esc=._0F}}, + {{.SETNP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9B, 0, {esc=._0F}}, {written={0}, flags_rd={.PF}, writes_mem=true}}, }, .SETNS = { - {.SETNS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x99, 0, {esc=._0F}}, + {{.SETNS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x99, 0, {esc=._0F}}, {written={0}, flags_rd={.SF}, writes_mem=true}}, }, - .SETNZ = { // Alias for SETNE - {.SETNZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x95, 0, {esc=._0F}}, + .SETNZ = { + {{.SETNZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x95, 0, {esc=._0F}}, {written={0}, flags_rd={.ZF}, writes_mem=true}}, }, .SETO = { - {.SETO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x90, 0, {esc=._0F}}, + {{.SETO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x90, 0, {esc=._0F}}, {written={0}, flags_rd={.OF}, writes_mem=true}}, }, .SETP = { - {.SETP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9A, 0, {esc=._0F}}, + {{.SETP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9A, 0, {esc=._0F}}, {written={0}, flags_rd={.PF}, writes_mem=true}}, }, - .SETPE = { // Alias for SETP (parity even) - {.SETPE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9A, 0, {esc=._0F}}, + .SETPE = { + {{.SETPE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9A, 0, {esc=._0F}}, {written={0}, flags_rd={.PF}, writes_mem=true}}, }, - .SETPO = { // Alias for SETNP (parity odd) - {.SETPO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9B, 0, {esc=._0F}}, + .SETPO = { + {{.SETPO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x9B, 0, {esc=._0F}}, {written={0}, flags_rd={.PF}, writes_mem=true}}, }, .SETS = { - {.SETS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x98, 0, {esc=._0F}}, + {{.SETS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x98, 0, {esc=._0F}}, {written={0}, flags_rd={.SF}, writes_mem=true}}, }, - .SETZ = { // Alias for SETE - {.SETZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x94, 0, {esc=._0F}}, + .SETZ = { + {{.SETZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x94, 0, {esc=._0F}}, {written={0}, flags_rd={.ZF}, writes_mem=true}}, }, .CMOVA = { - {.CMOVA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, - {.CMOVA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, - {.CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, + {{.CMOVA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, + {{.CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, }, .CMOVAE = { - {.CMOVAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, }, .CMOVB = { - {.CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, }, .CMOVBE = { - {.CMOVBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, - {.CMOVBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, - {.CMOVBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, + {{.CMOVBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, + {{.CMOVBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, }, - .CMOVC = { // Alias for CMOVB (carry = below) - {.CMOVC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true}}, + .CMOVC = { + {{.CMOVC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, }, .CMOVE = { - {.CMOVE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, - {.CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, - {.CMOVE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, + {{.CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, + {{.CMOVE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, }, .CMOVG = { - {.CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, - {.CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, - {.CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, + {{.CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, + {{.CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, }, .CMOVGE = { - {.CMOVGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, - {.CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, - {.CMOVGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, + {{.CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, + {{.CMOVGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, }, .CMOVL = { - {.CMOVL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, - {.CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, - {.CMOVL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, + {{.CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, + {{.CMOVL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, }, .CMOVLE = { - {.CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, - {.CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, - {.CMOVLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, + {{.CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, + {{.CMOVLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, }, - .CMOVNA = { // Alias for CMOVBE - {.CMOVNA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, - {.CMOVNA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, - {.CMOVNA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, force_rex_w=true}}, + .CMOVNA = { + {{.CMOVNA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, + {{.CMOVNA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, + {{.CMOVNA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x46, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, }, - .CMOVNAE = { // Alias for CMOVB - {.CMOVNAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVNAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, - {.CMOVNAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true}}, + .CMOVNAE = { + {{.CMOVNAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVNAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVNAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, }, - .CMOVNB = { // Alias for CMOVAE - {.CMOVNB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVNB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVNB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true}}, + .CMOVNB = { + {{.CMOVNB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVNB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVNB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, }, - .CMOVNBE = { // Alias for CMOVA - {.CMOVNBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, - {.CMOVNBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, - {.CMOVNBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, force_rex_w=true}}, + .CMOVNBE = { + {{.CMOVNBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, + {{.CMOVNBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, + {{.CMOVNBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x47, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.CF, .ZF}, reads_mem=true}}, }, - .CMOVNC = { // Alias for CMOVAE - {.CMOVNC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVNC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, - {.CMOVNC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true}}, + .CMOVNC = { + {{.CMOVNC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVNC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, + {{.CMOVNC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x43, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.CF}, reads_mem=true}}, }, .CMOVNE = { - {.CMOVNE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, - {.CMOVNE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, - {.CMOVNE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVNE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, + {{.CMOVNE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, + {{.CMOVNE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, }, - .CMOVNG = { // Alias for CMOVLE - {.CMOVNG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, - {.CMOVNG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, - {.CMOVNG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, force_rex_w=true}}, + .CMOVNG = { + {{.CMOVNG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, + {{.CMOVNG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, + {{.CMOVNG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, }, - .CMOVNGE = { // Alias for CMOVL - {.CMOVNGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, - {.CMOVNGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, - {.CMOVNGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, force_rex_w=true}}, + .CMOVNGE = { + {{.CMOVNGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, + {{.CMOVNGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, + {{.CMOVNGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, }, - .CMOVNL = { // Alias for CMOVGE - {.CMOVNL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, - {.CMOVNL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, - {.CMOVNL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, force_rex_w=true}}, + .CMOVNL = { + {{.CMOVNL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, + {{.CMOVNL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, + {{.CMOVNL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4D, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.SF, .OF}, reads_mem=true}}, }, - .CMOVNLE = { // Alias for CMOVG - {.CMOVNLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, - {.CMOVNLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, - {.CMOVNLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, force_rex_w=true}}, + .CMOVNLE = { + {{.CMOVNLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, + {{.CMOVNLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, + {{.CMOVNLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4F, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.ZF, .SF, .OF}, reads_mem=true}}, }, .CMOVNO = { - {.CMOVNO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F}}, - {.CMOVNO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F}}, - {.CMOVNO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVNO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}}, + {{.CMOVNO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}}, + {{.CMOVNO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}}, }, .CMOVNP = { - {.CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, - {.CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, - {.CMOVNP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, + {{.CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, + {{.CMOVNP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, }, .CMOVNS = { - {.CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F}}, - {.CMOVNS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F}}, - {.CMOVNS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}}, + {{.CMOVNS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}}, + {{.CMOVNS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x49, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}}, }, - .CMOVNZ = { // Alias for CMOVNE - {.CMOVNZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, - {.CMOVNZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, - {.CMOVNZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, force_rex_w=true}}, + .CMOVNZ = { + {{.CMOVNZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, + {{.CMOVNZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, + {{.CMOVNZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x45, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, }, .CMOVO = { - {.CMOVO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F}}, - {.CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F}}, - {.CMOVO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}}, + {{.CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}}, + {{.CMOVO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.OF}, reads_mem=true}}, }, .CMOVP = { - {.CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, - {.CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, - {.CMOVP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, + {{.CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, + {{.CMOVP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, }, - .CMOVPE = { // Alias for CMOVP (parity even) - {.CMOVPE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, - {.CMOVPE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, - {.CMOVPE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, force_rex_w=true}}, + .CMOVPE = { + {{.CMOVPE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, + {{.CMOVPE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, + {{.CMOVPE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4A, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, }, - .CMOVPO = { // Alias for CMOVNP (parity odd) - {.CMOVPO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, - {.CMOVPO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, - {.CMOVPO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, force_rex_w=true}}, + .CMOVPO = { + {{.CMOVPO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, + {{.CMOVPO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, + {{.CMOVPO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4B, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.PF}, reads_mem=true}}, }, .CMOVS = { - {.CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F}}, - {.CMOVS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F}}, - {.CMOVS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F, force_rex_w=true}}, + {{.CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}}, + {{.CMOVS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}}, + {{.CMOVS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x48, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.SF}, reads_mem=true}}, }, - .CMOVZ = { // Alias for CMOVE - {.CMOVZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, - {.CMOVZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, - {.CMOVZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, force_rex_w=true}}, + .CMOVZ = { + {{.CMOVZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, + {{.CMOVZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, + {{.CMOVZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_rd={.ZF}, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.8 String Operation Encodings - // ------------------------------------------------------------------------- - .MOVS = { // Generic form, needs size suffix - {.MOVS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA4, 0, {rep_ok=true}}, + .MOVS = { + {{.MOVS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA4, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}}, }, .MOVSB = { - {.MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA4, 0, {rep_ok=true}}, + {{.MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA4, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}}, }, .MOVSW = { - {.MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {rep_ok=true, opsize_16=true}}, + {{.MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {opsize_16=true, rep_ok=true}}, {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}}, }, .MOVSD = { - {.MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {rep_ok=true}}, - {.MOVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F2}}, - {.MOVSD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}}, + {{.MOVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVSD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVSQ = { - {.MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {rep_ok=true, force_rex_w=true}}, + {{.MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA5, 0, {force_rex_w=true, rep_ok=true}}, {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}}, }, - .CMPS = { // Generic form - {.CMPS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA6, 0, {rep_ok=true}}, + .CMPS = { + {{.CMPS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA6, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}}, }, .CMPSB = { - {.CMPSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA6, 0, {rep_ok=true}}, + {{.CMPSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA6, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}}, }, .CMPSW = { - {.CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true, opsize_16=true}}, + {{.CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {opsize_16=true, rep_ok=true}}, {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}}, }, .CMPSD = { - {.CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true}}, - {.CMPSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}}, + {{.CMPSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CMPSQ = { - {.CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {rep_ok=true, force_rex_w=true}}, + {{.CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA7, 0, {force_rex_w=true, rep_ok=true}}, {implicit_wr={.RCX, .RSI, .RDI}, implicit_rd={.RCX, .RSI, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}}, }, - .SCAS = { // Generic form - {.SCAS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAE, 0, {rep_ok=true}}, + .SCAS = { + {{.SCAS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAE, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}}, }, .SCASB = { - {.SCASB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAE, 0, {rep_ok=true}}, + {{.SCASB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAE, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}}, }, .SCASW = { - {.SCASW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAF, 0, {rep_ok=true, opsize_16=true}}, + {{.SCASW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAF, 0, {opsize_16=true, rep_ok=true}}, {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}}, }, .SCASD = { - {.SCASD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAF, 0, {rep_ok=true}}, + {{.SCASD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAF, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}}, }, .SCASQ = { - {.SCASQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAF, 0, {rep_ok=true, force_rex_w=true}}, + {{.SCASQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAF, 0, {force_rex_w=true, rep_ok=true}}, {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, flags_rd={.DF}, reads_mem=true}}, }, - .LODS = { // Generic form - {.LODS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAC, 0, {rep_ok=true}}, + .LODS = { + {{.LODS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAC, 0, {rep_ok=true}}, {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}}, }, .LODSB = { - {.LODSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAC, 0, {rep_ok=true}}, + {{.LODSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAC, 0, {rep_ok=true}}, {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}}, }, .LODSW = { - {.LODSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAD, 0, {rep_ok=true, opsize_16=true}}, + {{.LODSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAD, 0, {opsize_16=true, rep_ok=true}}, {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}}, }, .LODSD = { - {.LODSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAD, 0, {rep_ok=true}}, + {{.LODSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAD, 0, {rep_ok=true}}, {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}}, }, .LODSQ = { - {.LODSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAD, 0, {rep_ok=true, force_rex_w=true}}, + {{.LODSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAD, 0, {force_rex_w=true, rep_ok=true}}, {implicit_wr={.RAX, .RSI}, implicit_rd={.RSI}, flags_rd={.DF}, reads_mem=true}}, }, - .STOS = { // Generic form - {.STOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAA, 0, {rep_ok=true}}, + .STOS = { + {{.STOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAA, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}}, }, .STOSB = { - {.STOSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAA, 0, {rep_ok=true}}, + {{.STOSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAA, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}}, }, .STOSW = { - {.STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAB, 0, {rep_ok=true, opsize_16=true}}, + {{.STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAB, 0, {opsize_16=true, rep_ok=true}}, {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}}, }, .STOSD = { - {.STOSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAB, 0, {rep_ok=true}}, + {{.STOSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAB, 0, {rep_ok=true}}, {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}}, }, .STOSQ = { - {.STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAB, 0, {rep_ok=true, force_rex_w=true}}, + {{.STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAB, 0, {force_rex_w=true, rep_ok=true}}, {implicit_wr={.RCX, .RDI}, implicit_rd={.RAX, .RCX, .RDI}, flags_rd={.DF}, writes_mem=true, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.9 Flag Operation Encodings - // ------------------------------------------------------------------------- .CLC = { - {.CLC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF8, 0, {}}, + {{.CLC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF8, 0, {}}, {flags_wr={.CF}}}, }, .STC = { - {.STC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF9, 0, {}}, + {{.STC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF9, 0, {}}, {flags_wr={.CF}}}, }, .CMC = { - {.CMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF5, 0, {}}, + {{.CMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF5, 0, {}}, {flags_wr={.CF}, flags_rd={.CF}}}, }, .CLD = { - {.CLD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC, 0, {}}, + {{.CLD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFC, 0, {}}, {flags_wr={.DF}}}, }, .STD = { - {.STD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFD, 0, {}}, + {{.STD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFD, 0, {}}, {flags_wr={.DF}}}, }, .CLI = { - {.CLI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFA, 0, {}}, + {{.CLI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFA, 0, {}}, {flags_wr={.IF}}}, }, .STI = { - {.STI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFB, 0, {}}, + {{.STI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xFB, 0, {}}, {flags_wr={.IF}}}, }, .LAHF = { - {.LAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9F, 0, {}}, + {{.LAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9F, 0, {}}, {implicit_wr={.RAX}, flags_rd={.CF, .PF, .AF, .ZF, .SF}}}, }, .SAHF = { - {.SAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9E, 0, {}}, + {{.SAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9E, 0, {}}, {implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF}}}, }, .PUSHF = { - {.PUSHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9C, 0, {opsize_16=true}}, + {{.PUSHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9C, 0, {opsize_16=true}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}}, }, .PUSHFD = { - {.PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9C, 0, {}}, + {{.PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9C, 0, {}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}}, }, .PUSHFQ = { - {.PUSHFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9C, 0, {default_64=true}}, + {{.PUSHFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9C, 0, {default_64=true}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_rd={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, writes_mem=true}}, }, .POPF = { - {.POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9D, 0, {opsize_16=true}}, + {{.POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9D, 0, {opsize_16=true}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}}, }, .POPFD = { - {.POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9D, 0, {}}, + {{.POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9D, 0, {}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}}, }, .POPFQ = { - {.POPFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9D, 0, {default_64=true}}, + {{.POPFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9D, 0, {default_64=true}}, {implicit_wr={.RSP}, implicit_rd={.RSP}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF, .DF, .IF}, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.10 Miscellaneous Encodings - // ------------------------------------------------------------------------- .NOP = { - {.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x90, 0, {}}, - {.NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, modrm_reg_ext=true}}, - {.NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, modrm_reg_ext=true}}, - {.NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x90, 0, {}}, {}}, + {{.NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, modrm_reg_ext=true}}, {}}, + {{.NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, modrm_reg_ext=true}}, {}}, + {{.NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1F, 0, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {}}, }, .HLT = { - {.HLT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF4, 0, {}}, + {{.HLT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF4, 0, {}}, {side_effects={.HALT, .PRIVILEGED}}}, }, - .WAIT = { // Also known as FWAIT - {.WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9B, 0, {}}, + .WAIT = { + {{.WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9B, 0, {}}, {implicit_rd={.FPU_SW}}}, }, - .LOCK = { // LOCK prefix - {.LOCK, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0, 0, {}}, + .LOCK = { + {{.LOCK, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF0, 0, {}}, {side_effects={.FENCE}}}, }, .UD0 = { - {.UD0, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFF, 0, {esc=._0F}}, + {{.UD0, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFF, 0, {esc=._0F}}, {side_effects={.TRAP}}}, }, .UD1 = { - {.UD1, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB9, 0, {esc=._0F}}, + {{.UD1, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xB9, 0, {esc=._0F}}, {side_effects={.TRAP}}}, }, .UD2 = { - {.UD2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0B, 0, {esc=._0F}}, + {{.UD2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0B, 0, {esc=._0F}}, {side_effects={.TRAP}}}, }, .CPUID = { - {.CPUID, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA2, 0, {esc=._0F}}, + {{.CPUID, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xA2, 0, {esc=._0F}}, {implicit_wr={.RAX, .RBX, .RCX, .RDX}, implicit_rd={.RAX, .RCX}, side_effects={.SERIALIZING}}}, }, .RDTSC = { - {.RDTSC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x31, 0, {esc=._0F}}, + {{.RDTSC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x31, 0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}}}, }, - .RDTSCP = { // 0F 01 F9 - {.RDTSCP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xF9, {esc=._0F}}, + .RDTSCP = { + {{.RDTSCP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xF9, {esc=._0F}}, {implicit_wr={.RAX, .RCX, .RDX}}}, }, .RDPMC = { - {.RDPMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x33, 0, {esc=._0F}}, + {{.RDPMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x33, 0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}}, }, - .XGETBV = { // 0F 01 D0 - {.XGETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD0, {esc=._0F}}, + .XGETBV = { + {{.XGETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}}, }, - .XSETBV = { // 0F 01 D1 - {.XSETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD1, {esc=._0F}}, + .XSETBV = { + {{.XSETBV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD1, {esc=._0F}}, {implicit_rd={.RAX, .RCX, .RDX}}}, }, .CBW = { - {.CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x98, 0, {opsize_16=true}}, + {{.CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x98, 0, {opsize_16=true}}, {implicit_wr={.RAX}, implicit_rd={.RAX}}}, }, .CWDE = { - {.CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x98, 0, {}}, + {{.CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x98, 0, {}}, {implicit_wr={.RAX}, implicit_rd={.RAX}}}, }, .CDQE = { - {.CDQE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x98, 0, {force_rex_w=true}}, + {{.CDQE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x98, 0, {force_rex_w=true}}, {implicit_wr={.RAX}, implicit_rd={.RAX}}}, }, .CWD = { - {.CWD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x99, 0, {opsize_16=true}}, + {{.CWD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x99, 0, {opsize_16=true}}, {implicit_wr={.RDX}, implicit_rd={.RAX}}}, }, .CDQ = { - {.CDQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x99, 0, {}}, + {{.CDQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x99, 0, {}}, {implicit_wr={.RDX}, implicit_rd={.RAX}}}, }, .CQO = { - {.CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x99, 0, {force_rex_w=true}}, + {{.CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x99, 0, {force_rex_w=true}}, {implicit_wr={.RDX}, implicit_rd={.RAX}}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.11 BMI/ADX Encodings - // ------------------------------------------------------------------------- .ANDN = { - {.ANDN, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF2, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.ANDN, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF2, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {{.ANDN, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF2, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}}, + {{.ANDN, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF2, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}}, }, .BEXTR = { - {.BEXTR, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.BEXTR, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {{.BEXTR, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}}, + {{.BEXTR, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .OF}, flags_undef={.PF, .AF, .SF}, reads_mem=true}}, }, .BLSI = { - {.BLSI, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 3, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, - {.BLSI, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 3, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, + {{.BLSI, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 3, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}}, + {{.BLSI, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 3, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}}, }, .BLSMSK = { - {.BLSMSK, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 2, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, - {.BLSMSK, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 2, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, + {{.BLSMSK, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 2, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}}, + {{.BLSMSK, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 2, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}}, }, .BLSR = { - {.BLSR, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 1, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, - {.BLSR, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 1, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, + {{.BLSR, {.R32, .RM32, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 1, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}}, + {{.BLSR, {.R64, .RM64, .NONE, .NONE}, {.VVVV, .MR, .NONE, .NONE}, 0xF3, 1, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}}, }, .BZHI = { - {.BZHI, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF5, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.BZHI, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF5, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {{.BZHI, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF5, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}}, + {{.BZHI, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF5, 0, {esc=._0F38, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, flags_wr={.CF, .ZF, .SF, .OF}, flags_undef={.PF, .AF}, reads_mem=true}}, }, .PDEP = { - {.PDEP, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.PDEP, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {{.PDEP, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.PDEP, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .PEXT = { - {.PEXT, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.PEXT, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {{.PEXT, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.PEXT, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .RORX = { - {.RORX, {.R32, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xF0, 0, {esc=._0F3A, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.RORX, {.R64, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xF0, 0, {esc=._0F3A, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {{.RORX, {.R32, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xF0, 0, {esc=._0F3A, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.RORX, {.R64, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xF0, 0, {esc=._0F3A, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, }, .SARX = { - {.SARX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.SARX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {{.SARX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.SARX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .SHLX = { - {.SHLX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.SHLX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {{.SHLX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.SHLX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .SHRX = { - {.SHRX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.SHRX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {{.SHRX, {.R32, .RM32, .R32, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.SHRX, {.R64, .RM64, .R64, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0xF7, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .MULX = { - {.MULX, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, - {.MULX, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, + {{.MULX, {.R32, .R32, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}}, + {{.MULX, {.R64, .R64, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0, 1}, read={2}, implicit_rd={.RDX}, reads_mem=true}}, }, .ADCX = { - {.ADCX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_66}}, - {.ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_66, force_rex_w=true}}, + {{.ADCX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}}, + {{.ADCX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_66, force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.CF}, flags_rd={.CF}, reads_mem=true}}, }, .ADOX = { - {.ADOX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_F3}}, - {.ADOX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_F3, force_rex_w=true}}, + {{.ADOX, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_F3}}, {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}}, + {{.ADOX, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, prefix=PREFIX_F3, force_rex_w=true}}, {written={0}, read={0, 1}, flags_wr={.OF}, flags_rd={.OF}, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.12 SSE Encodings - // ------------------------------------------------------------------------- .MOVAPS = { - {.MOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F}}, - {.MOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F}}, + {{.MOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVUPS = { - {.MOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F}}, - {.MOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F}}, + {{.MOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVAPD = { - {.MOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=PREFIX_66}}, - {.MOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.MOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVUPD = { - {.MOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_66}}, - {.MOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.MOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVSS = { - {.MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.MOVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVDQA = { - {.MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66}}, - {.MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVDQU = { - {.MOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.MOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.MOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVQ = { - {.MOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.MOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xD6, 0, {esc=._0F, prefix=PREFIX_66}}, - {.MOVQ, {.MM, .MM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F}}, - {.MOVQ, {.MM_M64, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F}}, - {.MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_66, force_rex_w=true}}, - {.MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66, force_rex_w=true}}, + {{.MOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xD6, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVQ, {.MM, .MM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVQ, {.MM_M64, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_66, force_rex_w=true}}, {written={0}, read={1}}}, + {{.MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66, force_rex_w=true}}, {written={0}, read={1}}}, }, .MOVD = { - {.MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66}}, - {.MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_66}}, - {.MOVD, {.MM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F}}, - {.MOVD, {.RM32, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F}}, + {{.MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVD, {.MM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVD, {.RM32, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVLPS = { - {.MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F}}, - {.MOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F}}, + {{.MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVHPS = { - {.MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F}}, - {.MOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F}}, + {{.MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVLPD = { - {.MOVLPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_66}}, - {.MOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.MOVLPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVHPD = { - {.MOVHPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_66}}, - {.MOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.MOVHPD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVLHPS = { - {.MOVLHPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F}}, + {{.MOVLHPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F}}, {written={0}, read={1}}}, }, .MOVHLPS = { - {.MOVHLPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F}}, + {{.MOVHLPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F}}, {written={0}, read={1}}}, }, .MOVMSKPS = { - {.MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F}}, - {.MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, force_rex_w=true}}, + {{.MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F}}, {written={0}, read={1}}}, + {{.MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}}}, }, .MOVMSKPD = { - {.MOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=PREFIX_66}}, - {.MOVMSKPD, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=PREFIX_66, force_rex_w=true}}, + {{.MOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}}}, + {{.MOVMSKPD, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=PREFIX_66, force_rex_w=true}}, {written={0}, read={1}}}, }, .MOVNTPS = { - {.MOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F}}, + {{.MOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVNTPD = { - {.MOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.MOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVNTDQ = { - {.MOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.MOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .MOVNTDQA = { - {.MOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.MOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .ADDPS = { - {.ADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F}}, + {{.ADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .ADDPD = { - {.ADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.ADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .ADDSS = { - {.ADDSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.ADDSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .ADDSD = { - {.ADDSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.ADDSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .SUBPS = { - {.SUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F}}, + {{.SUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .SUBPD = { - {.SUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.SUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .SUBSS = { - {.SUBSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.SUBSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .SUBSD = { - {.SUBSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.SUBSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MULPS = { - {.MULPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F}}, + {{.MULPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MULPD = { - {.MULPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.MULPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MULSS = { - {.MULSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.MULSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MULSD = { - {.MULSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.MULSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .DIVPS = { - {.DIVPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F}}, + {{.DIVPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .DIVPD = { - {.DIVPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.DIVPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .DIVSS = { - {.DIVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.DIVSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .DIVSD = { - {.DIVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.DIVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .SQRTPS = { - {.SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F}}, + {{.SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .SQRTPD = { - {.SQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.SQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .SQRTSS = { - {.SQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.SQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .SQRTSD = { - {.SQRTSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.SQRTSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .RCPPS = { - {.RCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F}}, + {{.RCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .RCPSS = { - {.RCPSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.RCPSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .RSQRTPS = { - {.RSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F}}, + {{.RSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .RSQRTSS = { - {.RSQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.RSQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MAXPS = { - {.MAXPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F}}, + {{.MAXPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MAXPD = { - {.MAXPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.MAXPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MAXSS = { - {.MAXSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.MAXSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MAXSD = { - {.MAXSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.MAXSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MINPS = { - {.MINPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F}}, + {{.MINPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MINPD = { - {.MINPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.MINPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MINSS = { - {.MINSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.MINSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MINSD = { - {.MINSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.MINSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .ANDPS = { - {.ANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x54, 0, {esc=._0F}}, + {{.ANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x54, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, }, .ANDPD = { - {.ANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x54, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.ANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x54, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .ANDNPS = { - {.ANDNPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x55, 0, {esc=._0F}}, + {{.ANDNPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x55, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, }, .ANDNPD = { - {.ANDNPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x55, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.ANDNPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x55, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .ORPS = { - {.ORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x56, 0, {esc=._0F}}, + {{.ORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x56, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, }, .ORPD = { - {.ORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x56, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.ORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x56, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .XORPS = { - {.XORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x57, 0, {esc=._0F}}, + {{.XORPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x57, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, }, .XORPD = { - {.XORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x57, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.XORPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x57, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .CMPPS = { - {.CMPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F}}, + {{.CMPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CMPPD = { - {.CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CMPSS = { - {.CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .COMISS = { - {.COMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F}}, + {{.COMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F}}, {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}}, }, .COMISD = { - {.COMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.COMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, prefix=PREFIX_66}}, {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}}, }, .UCOMISS = { - {.UCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F}}, + {{.UCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F}}, {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}}, }, .UCOMISD = { - {.UCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.UCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, prefix=PREFIX_66}}, {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}}, }, .SHUFPS = { - {.SHUFPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC6, 0, {esc=._0F}}, + {{.SHUFPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC6, 0, {esc=._0F}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .SHUFPD = { - {.SHUFPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC6, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.SHUFPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC6, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .UNPCKLPS = { - {.UNPCKLPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x14, 0, {esc=._0F}}, + {{.UNPCKLPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x14, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, }, .UNPCKHPS = { - {.UNPCKHPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x15, 0, {esc=._0F}}, + {{.UNPCKHPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x15, 0, {esc=._0F}}, {written={0}, read={1}, reads_mem=true}}, }, .UNPCKLPD = { - {.UNPCKLPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x14, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.UNPCKLPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x14, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .UNPCKHPD = { - {.UNPCKHPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x15, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.UNPCKHPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x15, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .CVTPS2PD = { - {.CVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F}}, + {{.CVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTPD2PS = { - {.CVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.CVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTSS2SD = { - {.CVTSS2SD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.CVTSS2SD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTSD2SS = { - {.CVTSD2SS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.CVTSD2SS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTPS2DQ = { - {.CVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.CVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTPD2DQ = { - {.CVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.CVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTDQ2PS = { - {.CVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F}}, + {{.CVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTDQ2PD = { - {.CVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.CVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTSS2SI = { - {.CVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, + {{.CVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTSD2SI = { - {.CVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F2}}, - {.CVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F2, force_rex_w=true}}, + {{.CVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.CVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F2, force_rex_w=true}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTSI2SS = { - {.CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.CVTSI2SS, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, + {{.CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.CVTSI2SS, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTSI2SD = { - {.CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F2}}, - {.CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F2, force_rex_w=true}}, + {{.CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F2, force_rex_w=true}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTTPS2DQ = { - {.CVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.CVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTTPD2DQ = { - {.CVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.CVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTTSS2SI = { - {.CVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F3}}, - {.CVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, + {{.CVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.CVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .CVTTSD2SI = { - {.CVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F2}}, - {.CVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F2, force_rex_w=true}}, + {{.CVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.CVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F2, force_rex_w=true}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .PADDB = { - {.PADDB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFC, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PADDB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFC, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PADDW = { - {.PADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFD, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFD, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PADDD = { - {.PADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFE, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFE, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PADDQ = { - {.PADDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD4, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PADDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD4, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSUBB = { - {.PSUBB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PSUBB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSUBW = { - {.PSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF9, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF9, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSUBD = { - {.PSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFA, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFA, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSUBQ = { - {.PSUBQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFB, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PSUBQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xFB, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PADDSB = { - {.PADDSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEC, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PADDSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEC, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PADDSW = { - {.PADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xED, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xED, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PADDUSB = { - {.PADDUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDC, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PADDUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDC, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PADDUSW = { - {.PADDUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDD, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PADDUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDD, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSUBSB = { - {.PSUBSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE8, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PSUBSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE8, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSUBSW = { - {.PSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE9, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE9, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSUBUSB = { - {.PSUBUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD8, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PSUBUSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD8, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSUBUSW = { - {.PSUBUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD9, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PSUBUSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD9, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMULLW = { - {.PMULLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD5, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PMULLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD5, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMULHW = { - {.PMULHW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE5, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PMULHW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE5, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMULHUW = { - {.PMULHUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE4, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PMULHUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE4, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMULUDQ = { - {.PMULUDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF4, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PMULUDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF4, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMADDWD = { - {.PMADDWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF5, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PMADDWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF5, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PAND = { - {.PAND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PAND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PANDN = { - {.PANDN, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDF, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PANDN, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDF, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .POR = { - {.POR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEB, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.POR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEB, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PXOR = { - {.PXOR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEF, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PXOR, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEF, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSLLW = { - {.PSLLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F, prefix=PREFIX_66}}, - {.PSLLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 6, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, + {{.PSLLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, + {{.PSLLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 6, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {written={0}, read={1}}}, }, .PSLLD = { - {.PSLLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF2, 0, {esc=._0F, prefix=PREFIX_66}}, - {.PSLLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 6, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, + {{.PSLLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF2, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, + {{.PSLLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 6, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {written={0}, read={1}}}, }, .PSLLQ = { - {.PSLLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF3, 0, {esc=._0F, prefix=PREFIX_66}}, - {.PSLLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x73, 6, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, + {{.PSLLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF3, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, + {{.PSLLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x73, 6, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {written={0}, read={1}}}, }, .PSRLW = { - {.PSRLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD1, 0, {esc=._0F, prefix=PREFIX_66}}, - {.PSRLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 2, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, + {{.PSRLW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD1, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, + {{.PSRLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 2, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {written={0}, read={1}}}, }, .PSRLD = { - {.PSRLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD2, 0, {esc=._0F, prefix=PREFIX_66}}, - {.PSRLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 2, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, + {{.PSRLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD2, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, + {{.PSRLD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 2, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {written={0}, read={1}}}, }, .PSRLQ = { - {.PSRLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD3, 0, {esc=._0F, prefix=PREFIX_66}}, - {.PSRLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x73, 2, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, + {{.PSRLQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD3, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, + {{.PSRLQ, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x73, 2, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {written={0}, read={1}}}, }, .PSRAW = { - {.PSRAW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE1, 0, {esc=._0F, prefix=PREFIX_66}}, - {.PSRAW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 4, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, + {{.PSRAW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE1, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, + {{.PSRAW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x71, 4, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {written={0}, read={1}}}, }, .PSRAD = { - {.PSRAD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE2, 0, {esc=._0F, prefix=PREFIX_66}}, - {.PSRAD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 4, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, + {{.PSRAD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE2, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, + {{.PSRAD, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, 0x72, 4, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {written={0}, read={1}}}, }, .PCMPEQB = { - {.PCMPEQB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x74, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PCMPEQB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x74, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PCMPEQW = { - {.PCMPEQW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x75, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PCMPEQW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x75, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PCMPEQD = { - {.PCMPEQD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x76, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PCMPEQD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x76, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PCMPGTB = { - {.PCMPGTB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x64, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PCMPGTB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x64, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PCMPGTW = { - {.PCMPGTW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x65, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PCMPGTW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x65, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PCMPGTD = { - {.PCMPGTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x66, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PCMPGTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x66, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PACKSSWB = { - {.PACKSSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x63, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PACKSSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x63, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PACKSSDW = { - {.PACKSSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6B, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PACKSSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6B, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PACKUSWB = { - {.PACKUSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x67, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PACKUSWB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x67, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PUNPCKLBW = { - {.PUNPCKLBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x60, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PUNPCKLBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x60, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PUNPCKLWD = { - {.PUNPCKLWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x61, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PUNPCKLWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x61, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PUNPCKLDQ = { - {.PUNPCKLDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PUNPCKLDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PUNPCKLQDQ = { - {.PUNPCKLQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6C, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PUNPCKLQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6C, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PUNPCKHBW = { - {.PUNPCKHBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x68, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PUNPCKHBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x68, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PUNPCKHWD = { - {.PUNPCKHWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x69, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PUNPCKHWD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x69, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PUNPCKHDQ = { - {.PUNPCKHDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6A, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PUNPCKHDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6A, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PUNPCKHQDQ = { - {.PUNPCKHQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6D, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PUNPCKHQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6D, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSHUFD = { - {.PSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .PSHUFHW = { - {.PSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.PSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .PSHUFLW = { - {.PSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.PSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .PSHUFW = { - {.PSHUFW, {.MM, .MM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F}}, + {{.PSHUFW, {.MM, .MM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .PEXTRW = { - {.PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=PREFIX_66}}, - {.PEXTRW, {.R64, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=PREFIX_66, force_rex_w=true}}, + {{.PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}}}, + {{.PEXTRW, {.R64, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=PREFIX_66, force_rex_w=true}}, {written={0}, read={1}}}, }, .PINSRW = { - {.PINSRW, {.XMM, .R32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC4, 0, {esc=._0F, prefix=PREFIX_66}}, - {.PINSRW, {.XMM, .M16, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC4, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PINSRW, {.XMM, .R32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC4, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1, 2}}}, + {{.PINSRW, {.XMM, .M16, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC4, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .PMOVMSKB = { - {.PMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=PREFIX_66}}, - {.PMOVMSKB, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=PREFIX_66, force_rex_w=true}}, + {{.PMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}}}, + {{.PMOVMSKB, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=PREFIX_66, force_rex_w=true}}, {written={0}, read={1}}}, }, .PAVGB = { - {.PAVGB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE0, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PAVGB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE0, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PAVGW = { - {.PAVGW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE3, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PAVGW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE3, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMAXUB = { - {.PMAXUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDE, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PMAXUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDE, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMAXSW = { - {.PMAXSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEE, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PMAXSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEE, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMINUB = { - {.PMINUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDA, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PMINUB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDA, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMINSW = { - {.PMINSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEA, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PMINSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xEA, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSADBW = { - {.PSADBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.PSADBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF6, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .MASKMOVDQU = { - {.MASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF7, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.MASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF7, 0, {esc=._0F, prefix=PREFIX_66}}, {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}}, }, .LFENCE = { - {.LFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAE, 0xE8, {esc=._0F}}, + {{.LFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAE, 0xE8, {esc=._0F}}, {side_effects={.FENCE, .SERIALIZING}}}, }, .SFENCE = { - {.SFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAE, 0xF8, {esc=._0F}}, + {{.SFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAE, 0xF8, {esc=._0F}}, {side_effects={.FENCE}}}, }, .MFENCE = { - {.MFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAE, 0xF0, {esc=._0F}}, + {{.MFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAE, 0xF0, {esc=._0F}}, {side_effects={.FENCE}}}, }, .PAUSE = { - {.PAUSE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x90, 0, {prefix=PREFIX_F3}}, + {{.PAUSE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x90, 0, {prefix=PREFIX_F3}}, {side_effects={.HINT}}}, }, .CLFLUSH = { - {.CLFLUSH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 7, {esc=._0F, modrm_reg_ext=true}}, + {{.CLFLUSH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 7, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.CACHE}}}, }, .ADDSUBPS = { - {.ADDSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.ADDSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .ADDSUBPD = { - {.ADDSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.ADDSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .HADDPS = { - {.HADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.HADDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .HADDPD = { - {.HADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.HADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .HSUBPS = { - {.HSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.HSUBPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .HSUBPD = { - {.HSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_66}}, + {{.HSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .MOVDDUP = { - {.MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, reads_mem=true}}, }, .MOVSLDUP = { - {.MOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.MOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, reads_mem=true}}, }, .MOVSHDUP = { - {.MOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_F3}}, + {{.MOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_F3}}, {written={0}, read={1}, reads_mem=true}}, }, .LDDQU = { - {.LDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=PREFIX_F2}}, + {{.LDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=PREFIX_F2}}, {written={0}, read={1}, reads_mem=true}}, }, .PSHUFB = { - {.PSHUFB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x00, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PSHUFB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x00, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PHADDW = { - {.PHADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x01, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PHADDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x01, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PHADDD = { - {.PHADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PHADDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PHADDSW = { - {.PHADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PHADDSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PHSUBW = { - {.PHSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x05, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PHSUBW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x05, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PHSUBD = { - {.PHSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x06, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PHSUBD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x06, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PHSUBSW = { - {.PHSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x07, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PHSUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x07, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMADDUBSW = { - {.PMADDUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x04, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMADDUBSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x04, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMULHRSW = { - {.PMULHRSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMULHRSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0B, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSIGNB = { - {.PSIGNB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x08, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PSIGNB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x08, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSIGNW = { - {.PSIGNW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x09, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PSIGNW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x09, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PSIGND = { - {.PSIGND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0A, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PSIGND, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0A, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PABSB = { - {.PABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PABSW = { - {.PABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PABSD = { - {.PABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PALIGNR = { - {.PALIGNR, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0F, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.PALIGNR, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0F, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .BLENDPS = { - {.BLENDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0C, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.BLENDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0C, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .BLENDPD = { - {.BLENDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0D, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.BLENDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0D, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .BLENDVPS = { - {.BLENDVPS, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.BLENDVPS, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}}, }, .BLENDVPD = { - {.BLENDVPD, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.BLENDVPD, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}}, }, .PBLENDW = { - {.PBLENDW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0E, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.PBLENDW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0E, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .PBLENDVB = { - {.PBLENDVB, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PBLENDVB, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}}, }, .DPPS = { - {.DPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x40, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.DPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x40, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .DPPD = { - {.DPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x41, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.DPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x41, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .EXTRACTPS = { - {.EXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x17, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.EXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x17, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true}}, }, .INSERTPS = { - {.INSERTPS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x21, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.INSERTPS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x21, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .MPSADBW = { - {.MPSADBW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.MPSADBW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .PACKUSDW = { - {.PACKUSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PACKUSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2B, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PEXTRB = { - {.PEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x14, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.PEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x14, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true}}, }, .PEXTRD = { - {.PEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.PEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1}, writes_mem=true}}, }, .PEXTRQ = { - {.PEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=PREFIX_66, force_rex_w=true}}, + {{.PEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=PREFIX_66, force_rex_w=true}}, {written={0}, read={1}, writes_mem=true}}, }, .PHMINPOSUW = { - {.PHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PINSRB = { - {.PINSRB, {.XMM, .RM8, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x20, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.PINSRB, {.XMM, .RM8, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x20, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .PINSRD = { - {.PINSRD, {.XMM, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x22, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.PINSRD, {.XMM, .RM32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x22, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .PINSRQ = { - {.PINSRQ, {.XMM, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x22, 0, {esc=._0F3A, prefix=PREFIX_66, force_rex_w=true}}, + {{.PINSRQ, {.XMM, .RM64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x22, 0, {esc=._0F3A, prefix=PREFIX_66, force_rex_w=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .PMAXSB = { - {.PMAXSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3C, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMAXSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3C, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMAXSD = { - {.PMAXSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3D, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMAXSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3D, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMAXUW = { - {.PMAXUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3E, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMAXUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3E, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMAXUD = { - {.PMAXUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3F, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMAXUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3F, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMINSB = { - {.PMINSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMINSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMINSD = { - {.PMINSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMINSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMINUW = { - {.PMINUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3A, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMINUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3A, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMINUD = { - {.PMINUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMINUD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x3B, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVSXBW = { - {.PMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVSXBD = { - {.PMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVSXBQ = { - {.PMOVSXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVSXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVSXWD = { - {.PMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVSXWQ = { - {.PMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVSXDQ = { - {.PMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVZXBW = { - {.PMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVZXBD = { - {.PMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVZXBQ = { - {.PMOVZXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVZXBQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVZXWD = { - {.PMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVZXWQ = { - {.PMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMOVZXDQ = { - {.PMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMULDQ = { - {.PMULDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMULDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PMULLD = { - {.PMULLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PMULLD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x40, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PTEST = { - {.PTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=PREFIX_66}}, {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, }, .ROUNDPS = { - {.ROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.ROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .ROUNDPD = { - {.ROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.ROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .ROUNDSS = { - {.ROUNDSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0A, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.ROUNDSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0A, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .ROUNDSD = { - {.ROUNDSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0B, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.ROUNDSD, {.XMM, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x0B, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .PCMPEQQ = { - {.PCMPEQQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PCMPEQQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .CRC32 = { - {.CRC32, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, prefix=PREFIX_F2}}, - {.CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=PREFIX_F2}}, - {.CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=PREFIX_F2}}, - {.CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, prefix=PREFIX_F2, force_rex_w=true}}, - {.CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=PREFIX_F2, force_rex_w=true}}, + {{.CRC32, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, prefix=PREFIX_F2}}, {written={0}, read={0, 1}, reads_mem=true}}, + {{.CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=PREFIX_F2}}, {written={0}, read={0, 1}, reads_mem=true}}, + {{.CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=PREFIX_F2}}, {written={0}, read={0, 1}, reads_mem=true}}, + {{.CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, prefix=PREFIX_F2, force_rex_w=true}}, {written={0}, read={0, 1}, reads_mem=true}}, + {{.CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, prefix=PREFIX_F2, force_rex_w=true}}, {written={0}, read={0, 1}, reads_mem=true}}, }, .PCMPESTRI = { - {.PCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x61, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.PCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x61, 0, {esc=._0F3A, prefix=PREFIX_66}}, {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, .PCMPESTRM = { - {.PCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x60, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.PCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x60, 0, {esc=._0F3A, prefix=PREFIX_66}}, {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, .PCMPISTRI = { - {.PCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x63, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.PCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x63, 0, {esc=._0F3A, prefix=PREFIX_66}}, {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, .PCMPISTRM = { - {.PCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x62, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.PCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x62, 0, {esc=._0F3A, prefix=PREFIX_66}}, {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, .PCMPGTQ = { - {.PCMPGTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x37, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.PCMPGTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x37, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .PCLMULQDQ = { - {.PCLMULQDQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x44, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.PCLMULQDQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x44, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .AESDEC = { - {.AESDEC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDE, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.AESDEC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDE, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .AESDECLAST = { - {.AESDECLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDF, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.AESDECLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDF, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .AESENC = { - {.AESENC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDC, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.AESENC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDC, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .AESENCLAST = { - {.AESENCLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDD, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.AESENCLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDD, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .AESIMC = { - {.AESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.AESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F38, prefix=PREFIX_66}}, {written={0}, read={1}, reads_mem=true}}, }, .AESKEYGENASSIST = { - {.AESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xDF, 0, {esc=._0F3A, prefix=PREFIX_66}}, + {{.AESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xDF, 0, {esc=._0F3A, prefix=PREFIX_66}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .SHA1MSG1 = { - {.SHA1MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC9, 0, {esc=._0F38}}, + {{.SHA1MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC9, 0, {esc=._0F38}}, {written={0}, read={1}, reads_mem=true}}, }, .SHA1MSG2 = { - {.SHA1MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCA, 0, {esc=._0F38}}, + {{.SHA1MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCA, 0, {esc=._0F38}}, {written={0}, read={1}, reads_mem=true}}, }, .SHA1NEXTE = { - {.SHA1NEXTE, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC8, 0, {esc=._0F38}}, + {{.SHA1NEXTE, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC8, 0, {esc=._0F38}}, {written={0}, read={1}, reads_mem=true}}, }, .SHA1RNDS4 = { - {.SHA1RNDS4, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xCC, 0, {esc=._0F3A}}, + {{.SHA1RNDS4, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xCC, 0, {esc=._0F3A}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .SHA256MSG1 = { - {.SHA256MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCC, 0, {esc=._0F38}}, + {{.SHA256MSG1, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCC, 0, {esc=._0F38}}, {written={0}, read={1}, reads_mem=true}}, }, .SHA256MSG2 = { - {.SHA256MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCD, 0, {esc=._0F38}}, + {{.SHA256MSG2, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xCD, 0, {esc=._0F38}}, {written={0}, read={1}, reads_mem=true}}, }, .SHA256RNDS2 = { - {.SHA256RNDS2, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0xCB, 0, {esc=._0F38}}, + {{.SHA256RNDS2, {.XMM, .XMM_M128, .XMM0_IMPL, .NONE}, {.REG, .MR, .IMPL, .NONE}, 0xCB, 0, {esc=._0F38}}, {written={0}, read={1}, implicit_rd={.XMM0}, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.13 AVX/AVX2 Encodings - // ------------------------------------------------------------------------- .VADDPS = { - {.VADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VADDPD = { - {.VADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VADDSS = { - {.VADDSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VADDSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VADDSD = { - {.VADDSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, + {{.VADDSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x58, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VSUBPS = { - {.VSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VSUBPD = { - {.VSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VSUBSS = { - {.VSUBSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VSUBSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VSUBSD = { - {.VSUBSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, + {{.VSUBSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMULPS = { - {.VMULPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMULPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VMULPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VMULPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMULPD = { - {.VMULPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMULPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMULPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VMULPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMULSS = { - {.VMULSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VMULSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMULSD = { - {.VMULSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, + {{.VMULSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x59, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VDIVPS = { - {.VDIVPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VDIVPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VDIVPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VDIVPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VDIVPD = { - {.VDIVPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VDIVPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VDIVPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VDIVPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VDIVSS = { - {.VDIVSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VDIVSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VDIVSD = { - {.VDIVSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, + {{.VDIVSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5E, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VSQRTPS = { - {.VSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VSQRTPD = { - {.VSQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VSQRTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VSQRTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VSQRTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VSQRTSS = { - {.VSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VSQRTSD = { - {.VSQRTSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, + {{.VSQRTSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x51, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRCPPS = { - {.VRCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VRCPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VRCPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRCPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x53, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRCPSS = { - {.VRCPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x53, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VRCPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x53, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRSQRTPS = { - {.VRSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VRSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VRSQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRSQRTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x52, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRSQRTSS = { - {.VRSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x52, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VRSQRTSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x52, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMAXPS = { - {.VMAXPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMAXPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VMAXPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VMAXPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMAXPD = { - {.VMAXPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMAXPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMAXPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VMAXPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMAXSS = { - {.VMAXSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VMAXSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMAXSD = { - {.VMAXSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, + {{.VMAXSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMINPS = { - {.VMINPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMINPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VMINPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VMINPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMINPD = { - {.VMINPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMINPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMINPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VMINPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMINSS = { - {.VMINSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VMINSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VMINSD = { - {.VMINSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, + {{.VMINSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VANDPS = { - {.VANDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VANDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VANDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VANDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VANDPD = { - {.VANDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VANDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VANDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VANDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x54, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VANDNPS = { - {.VANDNPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VANDNPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VANDNPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VANDNPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VANDNPD = { - {.VANDNPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VANDNPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VANDNPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VANDNPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x55, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VORPS = { - {.VORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VORPD = { - {.VORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x56, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VXORPS = { - {.VXORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VXORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VXORPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VXORPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VXORPD = { - {.VXORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VXORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VXORPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VXORPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x57, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VCMPPS = { - {.VCMPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VCMPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VCMPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCMPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCMPPD = { - {.VCMPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VCMPPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VCMPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCMPPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCMPSS = { - {.VCMPSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VCMPSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCMPSD = { - {.VCMPSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, + {{.VCMPSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC2, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCOMISS = { - {.VCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, vex_type=.VEX, vex_l=.LIG}}, + {{.VCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, vex_type=.VEX}}, {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}}, }, .VCOMISD = { - {.VCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG}}, + {{.VCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX}}, {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}}, }, .VUCOMISS = { - {.VUCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, vex_type=.VEX, vex_l=.LIG}}, + {{.VUCOMISS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, vex_type=.VEX}}, {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}}, }, .VUCOMISD = { - {.VUCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG}}, + {{.VUCOMISD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX}}, {read={0, 1}, implicit_wr={.MXCSR}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}, reads_mem=true}}, }, .VSHUFPS = { - {.VSHUFPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VSHUFPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VSHUFPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VSHUFPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VSHUFPD = { - {.VSHUFPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VSHUFPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VSHUFPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VSHUFPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC6, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VUNPCKLPS = { - {.VUNPCKLPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VUNPCKLPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VUNPCKLPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VUNPCKLPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VUNPCKHPS = { - {.VUNPCKHPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VUNPCKHPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VUNPCKHPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VUNPCKHPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VUNPCKLPD = { - {.VUNPCKLPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VUNPCKLPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VUNPCKLPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VUNPCKLPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VUNPCKHPD = { - {.VUNPCKHPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VUNPCKHPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VUNPCKHPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VUNPCKHPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VBLENDPS = { - {.VBLENDPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0C, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VBLENDPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0C, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VBLENDPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0C, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VBLENDPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0C, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VBLENDPD = { - {.VBLENDPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0D, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VBLENDPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0D, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VBLENDPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0D, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VBLENDPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0D, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VBLENDVPS = { - {.VBLENDVPS, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4A, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VBLENDVPS, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4A, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VBLENDVPS, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4A, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VBLENDVPS, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4A, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VBLENDVPD = { - {.VBLENDVPD, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4B, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VBLENDVPD, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4B, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VBLENDVPD, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4B, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VBLENDVPD, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4B, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VDPPS = { - {.VDPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x40, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VDPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x40, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VDPPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x40, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VDPPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x40, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VDPPD = { - {.VDPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x41, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VDPPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x41, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VROUNDPS = { - {.VROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VROUNDPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VROUNDPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VROUNDPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VROUNDPD = { - {.VROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VROUNDPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VROUNDPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VROUNDPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VROUNDSS = { - {.VROUNDSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0A, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG}}, + {{.VROUNDSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0A, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VROUNDSD = { - {.VROUNDSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0B, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG}}, + {{.VROUNDSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0B, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VEXTRACTPS = { - {.VEXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x17, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VEXTRACTPS, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x17, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true}}, }, .VINSERTPS = { - {.VINSERTPS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x21, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VINSERTPS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x21, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VMOVAPS = { - {.VMOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVAPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {.VMOVAPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVAPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVAPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVAPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVAPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVUPS = { - {.VMOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVUPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, - {.VMOVUPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVUPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVUPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVAPD = { - {.VMOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVAPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VMOVAPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVAPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVAPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVAPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVAPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x29, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVUPD = { - {.VMOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVUPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VMOVUPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVUPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVUPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVUPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVUPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVSS = { - {.VMOVSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, - {.VMOVSS, {.M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, - {.VMOVSS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VMOVSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVSS, {.M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVSS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}}}, }, .VMOVSD = { - {.VMOVSD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, - {.VMOVSD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, - {.VMOVSD, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, + {{.VMOVSD, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVSD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVSD, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1, 2}}}, }, .VMOVDQA = { - {.VMOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVDQA, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VMOVDQA, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVDQA, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVDQA, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVDQU = { - {.VMOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, - {.VMOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, - {.VMOVDQU, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, - {.VMOVDQU, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVDQU, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVDQU, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVDQU, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVDQU, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVQ = { - {.VMOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, - {.VMOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xD6, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VMOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.VMOVQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVQ, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xD6, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VMOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}}}, }, .VMOVD = { - {.VMOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VMOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7E, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVLPS = { - {.VMOVLPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, + {{.VMOVLPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VMOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVHPS = { - {.VMOVHPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, + {{.VMOVHPS, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VMOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVLPD = { - {.VMOVLPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VMOVLPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VMOVLPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVHPD = { - {.VMOVHPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VMOVHPD, {.XMM, .XMM, .M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VMOVHPD, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x17, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVLHPS = { - {.VMOVLHPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, + {{.VMOVLHPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}}}, }, .VMOVHLPS = { - {.VMOVHLPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, + {{.VMOVHLPS, {.XMM, .XMM, .XMM, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}}}, }, .VMOVMSKPS = { - {.VMOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVMSKPS, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VMOVMSKPS, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}}}, }, .VMOVMSKPD = { - {.VMOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVMSKPD, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVMSKPD, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VMOVMSKPD, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x50, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}}}, }, .VMOVNTPS = { - {.VMOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VMOVNTPS, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVNTPS, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVNTPS, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVNTPD = { - {.VMOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVNTPD, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVNTPD, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVNTPD, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x2B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVNTDQ = { - {.VMOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVNTDQ, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVNTDQ, {.M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.VMOVNTDQ, {.M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xE7, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .VMOVNTDQA = { - {.VMOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMOVNTDQA, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVNTDQA, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVNTDQA, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VADDSUBPS = { - {.VADDSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, - {.VADDSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + {{.VADDSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VADDSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VADDSUBPD = { - {.VADDSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VADDSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VADDSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VADDSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD0, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, - .VHADDPS = { // <-- the instruction you named - {.VHADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, - {.VHADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + .VHADDPS = { + {{.VHADDPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VHADDPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VHADDPD = { - {.VHADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VHADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VHADDPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VHADDPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VHSUBPS = { - {.VHSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, - {.VHSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + {{.VHSUBPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VHSUBPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VHSUBPD = { - {.VHSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VHSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VHSUBPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VHSUBPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, - .VLDDQU = { // 2-operand (load only) - {.VLDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, - {.VLDDQU, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + .VLDDQU = { + {{.VLDDQU, {.XMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VLDDQU, {.YMM, .M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VMOVDDUP = { - {.VMOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, - {.VMOVDDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VMOVSLDUP = { - {.VMOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, - {.VMOVSLDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVSLDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x12, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VMOVSHDUP = { - {.VMOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, - {.VMOVSHDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, + {{.VMOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVSHDUP, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x16, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, - // VEX.128.66.0F3A. — ESTR* also have a W1 (RAX/RDX) variant; W0 shown to match the SSE entries. .VPCMPESTRI = { - {.VPCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x61, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.VPCMPESTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x61, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {implicit_wr={.RCX}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, .VPCMPESTRM = { - {.VPCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x60, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.VPCMPESTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x60, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {implicit_wr={.XMM0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, .VPCMPISTRI = { - {.VPCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x63, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VPCMPISTRI, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x63, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {implicit_wr={.RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, .VPCMPISTRM = { - {.VPCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x62, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VPCMPISTRM, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x62, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {implicit_wr={.XMM0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, - // VEX.128/256.66.0F38.W0 element broadcasts (AVX2). reg-source + memory-source forms, mirroring .VBROADCASTSS .VPBROADCASTB = { - {.VPBROADCASTB, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPBROADCASTB, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, - {.VPBROADCASTB, {.XMM, .M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPBROADCASTB, {.YMM, .M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPBROADCASTB, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPBROADCASTB, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPBROADCASTB, {.XMM, .M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPBROADCASTB, {.YMM, .M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x78, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPBROADCASTW = { - {.VPBROADCASTW, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPBROADCASTW, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, - {.VPBROADCASTW, {.XMM, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPBROADCASTW, {.YMM, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPBROADCASTW, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPBROADCASTW, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPBROADCASTW, {.XMM, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPBROADCASTW, {.YMM, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPBROADCASTD = { - {.VPBROADCASTD, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPBROADCASTD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, - {.VPBROADCASTD, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPBROADCASTD, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPBROADCASTD, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPBROADCASTD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPBROADCASTD, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPBROADCASTD, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x58, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPBROADCASTQ = { - {.VPBROADCASTQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPBROADCASTQ, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, - {.VPBROADCASTQ, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPBROADCASTQ, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPBROADCASTQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPBROADCASTQ, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPBROADCASTQ, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPBROADCASTQ, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x59, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VCVTPS2PD = { - {.VCVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPS2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VCVTPS2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTPS2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTPD2PS = { - {.VCVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPD2PS, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VCVTPD2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTPD2PS, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTSS2SD = { - {.VCVTSS2SD, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, + {{.VCVTSS2SD, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTSD2SS = { - {.VCVTSD2SS, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, + {{.VCVTSD2SS, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x5A, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTPS2DQ = { - {.VCVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VCVTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTPD2DQ = { - {.VCVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + {{.VCVTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTDQ2PS = { - {.VCVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, - {.VCVTDQ2PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VCVTDQ2PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTDQ2PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTDQ2PD = { - {.VCVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, - {.VCVTDQ2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, + {{.VCVTDQ2PD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTDQ2PD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTSS2SI = { - {.VCVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, - {.VCVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VCVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTSD2SI = { - {.VCVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, - {.VCVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VCVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2D, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTSI2SS = { - {.VCVTSI2SS, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, - {.VCVTSI2SS, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VCVTSI2SS, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTSI2SS, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTSI2SD = { - {.VCVTSI2SD, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, - {.VCVTSI2SD, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VCVTSI2SD, {.XMM, .XMM, .RM32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTSI2SD, {.XMM, .XMM, .RM64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2A, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTTPS2DQ = { - {.VCVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, - {.VCVTTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, + {{.VCVTTPS2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTTPS2DQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5B, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTTPD2DQ = { - {.VCVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VCVTTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VCVTTPD2DQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTTPD2DQ, {.XMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xE6, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTTSS2SI = { - {.VCVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG}}, - {.VCVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VCVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTTSD2SI = { - {.VCVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG}}, - {.VCVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VCVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x2C, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VPADDB = { - {.VPADDB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFC, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPADDB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFC, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPADDB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFC, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPADDB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFC, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPADDW = { - {.VPADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFD, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFD, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFD, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFD, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPADDD = { - {.VPADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFE, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFE, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFE, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFE, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPADDQ = { - {.VPADDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPADDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPADDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPADDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSUBB = { - {.VPSUBB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF8, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSUBB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF8, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSUBB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF8, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSUBB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF8, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSUBW = { - {.VPSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF9, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF9, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF9, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF9, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSUBD = { - {.VPSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFA, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFA, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFA, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFA, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSUBQ = { - {.VPSUBQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSUBQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSUBQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSUBQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xFB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMULLW = { - {.VPMULLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMULLW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMULLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMULLW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xD5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMULHW = { - {.VPMULHW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMULHW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMULHW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMULHW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMULHUW = { - {.VPMULHUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMULHUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMULHUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMULHUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xE4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMULUDQ = { - {.VPMULUDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMULUDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMULUDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMULUDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMADDWD = { - {.VPMADDWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMADDWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMADDWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMADDWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xF5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPAND = { - {.VPAND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPAND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPAND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPAND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPANDN = { - {.VPANDN, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPANDN, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPANDN, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPANDN, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPOR = { - {.VPOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEB, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPXOR = { - {.VPXOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEF, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPXOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEF, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPXOR, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEF, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPXOR, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xEF, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSLLW = { - {.VPSLLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSLLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 6, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSLLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VPSLLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 6, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSLLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSLLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 6, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, + {{.VPSLLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSLLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 6, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, }, .VPSLLD = { - {.VPSLLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSLLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 6, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSLLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VPSLLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 6, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSLLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSLLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 6, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, + {{.VPSLLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSLLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 6, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, }, .VPSLLQ = { - {.VPSLLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF3, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSLLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 6, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSLLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF3, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VPSLLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 6, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSLLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF3, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSLLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 6, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, + {{.VPSLLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xF3, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSLLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 6, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, }, .VPSRLW = { - {.VPSRLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSRLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 2, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSRLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VPSRLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 2, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSRLW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRLW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 2, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, + {{.VPSRLW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRLW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 2, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, }, .VPSRLD = { - {.VPSRLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSRLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 2, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSRLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VPSRLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 2, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSRLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRLD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 2, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, + {{.VPSRLD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRLD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 2, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, }, .VPSRLQ = { - {.VPSRLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD3, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSRLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 2, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSRLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD3, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VPSRLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 2, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSRLQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD3, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRLQ, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 2, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, + {{.VPSRLQ, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xD3, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRLQ, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x73, 2, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, }, .VPSRAW = { - {.VPSRAW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSRAW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 4, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSRAW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VPSRAW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 4, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSRAW, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRAW, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 4, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, + {{.VPSRAW, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE1, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRAW, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x71, 4, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, }, .VPSRAD = { - {.VPSRAD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSRAD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 4, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSRAD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VPSRAD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 4, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSRAD, {.XMM, .XMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRAD, {.XMM, .XMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 4, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, + {{.VPSRAD, {.YMM, .YMM, .XMM_M128, .NONE}, {.VVVV, .REG, .MR, .NONE}, 0xE2, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRAD, {.YMM, .YMM, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 4, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, modrm_reg_ext=true}}, {written={0}, read={1, 2}}}, }, .VPCMPEQB = { - {.VPCMPEQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x74, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPEQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x74, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPCMPEQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x74, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPEQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x74, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPEQW = { - {.VPCMPEQW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPEQW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPCMPEQW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPEQW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPEQD = { - {.VPCMPEQD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPEQD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPCMPEQD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPEQD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPEQQ = { - {.VPCMPEQQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPEQQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPCMPEQQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPEQQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPGTB = { - {.VPCMPGTB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPGTB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPCMPGTB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPGTB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPGTW = { - {.VPCMPGTW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPGTW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPCMPGTW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPGTW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPGTD = { - {.VPCMPGTD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPGTD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPCMPGTD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPGTD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPGTQ = { - {.VPCMPGTQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x37, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPCMPGTQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x37, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPCMPGTQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x37, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPGTQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x37, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPACKSSWB = { - {.VPACKSSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x63, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPACKSSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x63, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPACKSSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x63, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPACKSSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x63, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPACKSSDW = { - {.VPACKSSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPACKSSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPACKSSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPACKSSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPACKUSWB = { - {.VPACKUSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x67, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPACKUSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x67, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPACKUSWB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x67, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPACKUSWB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x67, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPACKUSDW = { - {.VPACKUSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPACKUSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPACKUSDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPACKUSDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPUNPCKLBW = { - {.VPUNPCKLBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x60, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKLBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x60, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPUNPCKLBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x60, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPUNPCKLBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x60, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPUNPCKLWD = { - {.VPUNPCKLWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x61, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKLWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x61, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPUNPCKLWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x61, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPUNPCKLWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x61, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPUNPCKLDQ = { - {.VPUNPCKLDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x62, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKLDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x62, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPUNPCKLDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x62, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPUNPCKLDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x62, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPUNPCKLQDQ = { - {.VPUNPCKLQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKLQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPUNPCKLQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPUNPCKLQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6C, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPUNPCKHBW = { - {.VPUNPCKHBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x68, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKHBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x68, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPUNPCKHBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x68, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPUNPCKHBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x68, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPUNPCKHWD = { - {.VPUNPCKHWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x69, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKHWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x69, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPUNPCKHWD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x69, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPUNPCKHWD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x69, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPUNPCKHDQ = { - {.VPUNPCKHDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKHDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPUNPCKHDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPUNPCKHDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPUNPCKHQDQ = { - {.VPUNPCKHQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPUNPCKHQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPUNPCKHQDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPUNPCKHQDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x6D, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSHUFD = { - {.VPSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSHUFD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSHUFD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSHUFHW = { - {.VPSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, - {.VPSHUFHW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, + {{.VPSHUFHW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSHUFHW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSHUFLW = { - {.VPSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, - {.VPSHUFLW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, + {{.VPSHUFLW, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSHUFLW, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x70, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPEXTRB = { - {.VPEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x14, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VPEXTRB, {.RM8, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x14, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true}}, }, .VPEXTRW = { - {.VPEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPEXTRW, {.RM16, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x15, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VPEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xC5, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPEXTRW, {.RM16, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x15, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true}}, }, .VPEXTRD = { - {.VPEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VPEXTRD, {.RM32, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true}}, }, .VPEXTRQ = { - {.VPEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.VPEXTRQ, {.RM64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x16, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true}}, }, .VPINSRB = { - {.VPINSRB, {.XMM, .XMM, .RM8, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x20, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VPINSRB, {.XMM, .XMM, .RM8, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x20, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPINSRW = { - {.VPINSRW, {.XMM, .XMM, .RM16, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VPINSRW, {.XMM, .XMM, .RM16, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0xC4, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPINSRD = { - {.VPINSRD, {.XMM, .XMM, .RM32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x22, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VPINSRD, {.XMM, .XMM, .RM32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x22, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPINSRQ = { - {.VPINSRQ, {.XMM, .XMM, .RM64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x22, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.VPINSRQ, {.XMM, .XMM, .RM64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x22, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPMOVMSKB = { - {.VPMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVMSKB, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVMSKB, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPMOVMSKB, {.R32, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xD7, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}}}, }, .VPTEST = { - {.VPTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPTEST, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPTEST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.VPTEST, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x17, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, }, .VPSHUFB = { - {.VPSHUFB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x00, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSHUFB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x00, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSHUFB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x00, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSHUFB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x00, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPHADDW = { - {.VPHADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x01, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPHADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x01, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPHADDW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x01, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPHADDW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x01, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPHADDD = { - {.VPHADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x02, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPHADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x02, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPHADDD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x02, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPHADDD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x02, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPHADDSW = { - {.VPHADDSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x03, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPHADDSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x03, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPHADDSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x03, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPHADDSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x03, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPHSUBW = { - {.VPHSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x05, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPHSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x05, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPHSUBW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x05, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPHSUBW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x05, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPHSUBD = { - {.VPHSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x06, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPHSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x06, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPHSUBD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x06, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPHSUBD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x06, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPHSUBSW = { - {.VPHSUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x07, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPHSUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x07, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPHSUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x07, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPHSUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x07, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMADDUBSW = { - {.VPMADDUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x04, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMADDUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x04, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMADDUBSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x04, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMADDUBSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x04, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMULHRSW = { - {.VPMULHRSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMULHRSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMULHRSW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMULHRSW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSIGNB = { - {.VPSIGNB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x08, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSIGNB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x08, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSIGNB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x08, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSIGNB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x08, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSIGNW = { - {.VPSIGNW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x09, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSIGNW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x09, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSIGNW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x09, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSIGNW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x09, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSIGND = { - {.VPSIGND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPSIGND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPSIGND, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSIGND, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x0A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPABSB = { - {.VPABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPABSB, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPABSB, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPABSB, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPABSW = { - {.VPABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPABSW, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPABSW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPABSW, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPABSD = { - {.VPABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPABSD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPABSD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPABSD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPALIGNR = { - {.VPALIGNR, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPALIGNR, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPALIGNR, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VPALIGNR, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPBLENDW = { - {.VPBLENDW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPBLENDW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPBLENDW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VPBLENDW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPBLENDVB = { - {.VPBLENDVB, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4C, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPBLENDVB, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4C, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPBLENDVB, {.XMM, .XMM, .XMM_M128, .XMM}, {.REG, .VVVV, .MR, .IS4}, 0x4C, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VPBLENDVB, {.YMM, .YMM, .YMM_M256, .YMM}, {.REG, .VVVV, .MR, .IS4}, 0x4C, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VMPSADBW = { - {.VMPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VMPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPHMINPOSUW = { - {.VPHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VPHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x41, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMAXSB = { - {.VPMAXSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMAXSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMAXSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMAXSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMAXSD = { - {.VPMAXSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMAXSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMAXSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMAXSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMAXUW = { - {.VPMAXUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMAXUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMAXUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMAXUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMAXUD = { - {.VPMAXUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMAXUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMAXUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMAXUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMINSB = { - {.VPMINSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMINSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMINSB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMINSB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMINSD = { - {.VPMINSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMINSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMINSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMINSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMINUW = { - {.VPMINUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMINUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMINUW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMINUW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMINUD = { - {.VPMINUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMINUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMINUD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMINUD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x3B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMOVSXBW = { - {.VPMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVSXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVSXBD = { - {.VPMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVSXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVSXBQ = { - {.VPMOVSXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVSXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPMOVSXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVSXWD = { - {.VPMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVSXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVSXWQ = { - {.VPMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVSXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVSXDQ = { - {.VPMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVSXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVSXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVZXBW = { - {.VPMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVZXBW, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVZXBW, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVZXBD = { - {.VPMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVZXBD, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVZXBD, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVZXBQ = { - {.VPMOVZXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVZXBQ, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPMOVZXBQ, {.YMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVZXWD = { - {.VPMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVZXWD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVZXWD, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVZXWQ = { - {.VPMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVZXWQ, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVZXWQ, {.YMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVZXDQ = { - {.VPMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMOVZXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMOVZXDQ, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVZXDQ, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMULDQ = { - {.VPMULDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMULDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMULDQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMULDQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMULLD = { - {.VPMULLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x40, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPMULLD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x40, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPMULLD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x40, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMULLD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x40, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VMASKMOVDQU = { - {.VMASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF7, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VMASKMOVDQU, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF7, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {read={0, 1}, implicit_rd={.RDI}, flags_rd={.DF}, writes_mem=true}}, }, .VPCLMULQDQ = { - {.VPCLMULQDQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x44, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VPCLMULQDQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x44, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPCLMULQDQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x44, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VPCLMULQDQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x44, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VAESDEC = { - {.VAESDEC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VAESDEC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VAESDECLAST = { - {.VAESDECLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VAESDECLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDF, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VAESENC = { - {.VAESENC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VAESENC, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VAESENCLAST = { - {.VAESENCLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDD, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VAESENCLAST, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xDD, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VAESIMC = { - {.VAESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VAESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xDB, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, }, .VAESKEYGENASSIST = { - {.VAESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xDF, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, + {{.VAESKEYGENASSIST, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0xDF, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VBROADCASTSS = { - {.VBROADCASTSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VBROADCASTSS, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VBROADCASTSS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VBROADCASTSS, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VBROADCASTSS, {.XMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VBROADCASTSS, {.YMM, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VBROADCASTSS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VBROADCASTSS, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x18, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}}}, }, .VBROADCASTSD = { - {.VBROADCASTSD, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x19, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VBROADCASTSD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x19, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VBROADCASTSD, {.YMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x19, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VBROADCASTSD, {.YMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x19, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}}}, }, .VBROADCASTF128 = { - {.VBROADCASTF128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VBROADCASTF128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x1A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VEXTRACTF128 = { - {.VEXTRACTF128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x19, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VEXTRACTF128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x19, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, }, .VINSERTF128 = { - {.VINSERTF128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x18, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VINSERTF128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x18, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPERM2F128 = { - {.VPERM2F128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x06, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPERM2F128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x06, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VMASKMOVPS = { - {.VMASKMOVPS, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMASKMOVPS, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VMASKMOVPS, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMASKMOVPS, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMASKMOVPS, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VMASKMOVPS, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VMASKMOVPS, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VMASKMOVPS, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, }, .VMASKMOVPD = { - {.VMASKMOVPD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMASKMOVPD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VMASKMOVPD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VMASKMOVPD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VMASKMOVPD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VMASKMOVPD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VMASKMOVPD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VMASKMOVPD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x2F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, }, .VTESTPS = { - {.VTESTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VTESTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VTESTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.VTESTPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, }, .VTESTPD = { - {.VTESTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VTESTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VTESTPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, + {{.VTESTPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x0F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {read={0, 1}, flags_wr={.CF, .ZF}, flags_undef={.PF, .AF, .SF, .OF}, reads_mem=true}}, }, .VZEROALL = { - {.VZEROALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x77, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, + {{.VZEROALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x77, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1}}, {implicit_wr={.VECTOR}}}, }, .VZEROUPPER = { - {.VZEROUPPER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x77, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, + {{.VZEROUPPER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x77, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0}}, {implicit_wr={.VECTOR}}}, }, .VBROADCASTI128 = { - {.VBROADCASTI128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VBROADCASTI128, {.YMM, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x5A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, }, .VEXTRACTI128 = { - {.VEXTRACTI128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x39, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VEXTRACTI128, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x39, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, }, .VINSERTI128 = { - {.VINSERTI128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x38, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VINSERTI128, {.YMM, .YMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x38, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPERM2I128 = { - {.VPERM2I128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x46, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, + {{.VPERM2I128, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x46, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPERMD = { - {.VPERMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x36, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPERMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x36, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMPS = { - {.VPERMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPERMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x16, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMQ = { - {.VPERMQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x00, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VPERMQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x00, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMPD = { - {.VPERMPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x01, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VPERMPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x01, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPBLENDD = { - {.VPBLENDD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x02, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPBLENDD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x02, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPBLENDD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x02, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VPBLENDD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x02, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPSLLVD = { - {.VPSLLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPSLLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPSLLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSLLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSLLVQ = { - {.VPSLLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VPSLLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VPSLLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSLLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSRLVD = { - {.VPSRLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPSRLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPSRLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSRLVQ = { - {.VPSRLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VPSRLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VPSRLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSRAVD = { - {.VPSRAVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPSRAVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPSRAVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRAVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMASKMOVD = { - {.VPMASKMOVD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPMASKMOVD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, - {.VPMASKMOVD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPMASKMOVD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPMASKMOVD, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VPMASKMOVD, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VPMASKMOVD, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VPMASKMOVD, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, }, .VPMASKMOVQ = { - {.VPMASKMOVQ, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VPMASKMOVQ, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, - {.VPMASKMOVQ, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VPMASKMOVQ, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VPMASKMOVQ, {.XMM, .XMM, .M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VPMASKMOVQ, {.YMM, .YMM, .M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VPMASKMOVQ, {.M128, .XMM, .XMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, + {{.VPMASKMOVQ, {.M256, .YMM, .YMM, .NONE}, {.MR, .VVVV, .REG, .NONE}, 0x8E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, writes_mem=true, reads_mem=true}}, }, .VGATHERDPS = { - {.VGATHERDPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VGATHERDPS, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VGATHERDPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, + {{.VGATHERDPS, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, }, .VGATHERDPD = { - {.VGATHERDPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VGATHERDPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VGATHERDPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, + {{.VGATHERDPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x92, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, }, .VGATHERQPS = { - {.VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, + {{.VGATHERQPS, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, }, .VGATHERQPD = { - {.VGATHERQPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VGATHERQPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VGATHERQPD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, + {{.VGATHERQPD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x93, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, }, .VPGATHERDD = { - {.VPGATHERDD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPGATHERDD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPGATHERDD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, + {{.VPGATHERDD, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, }, .VPGATHERDQ = { - {.VPGATHERDQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VPGATHERDQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VPGATHERDQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, + {{.VPGATHERDQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x90, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, }, .VPGATHERQD = { - {.VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, + {{.VPGATHERQD, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, }, .VPGATHERQQ = { - {.VPGATHERQQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VPGATHERQQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VPGATHERQQ, {.XMM, .M, .XMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, + {{.VPGATHERQQ, {.YMM, .M, .YMM, .NONE}, {.REG, .MR, .VVVV, .NONE}, 0x91, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0, 2}, read={0, 1, 2}, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.14 FMA Encodings - // ------------------------------------------------------------------------- .VFMADD132PS = { - {.VFMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADD213PS = { - {.VFMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADD231PS = { - {.VFMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADD132PD = { - {.VFMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x98, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADD213PD = { - {.VFMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADD231PD = { - {.VFMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB8, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADD132SS = { - {.VFMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x99, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x99, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADD213SS = { - {.VFMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA9, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA9, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADD231SS = { - {.VFMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB9, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB9, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADD132SD = { - {.VFMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x99, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x99, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADD213SD = { - {.VFMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA9, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA9, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADD231SD = { - {.VFMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB9, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB9, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB132PS = { - {.VFMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB213PS = { - {.VFMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB231PS = { - {.VFMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB132PD = { - {.VFMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB213PD = { - {.VFMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB231PD = { - {.VFMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBA, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB132SS = { - {.VFMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB213SS = { - {.VFMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAB, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAB, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB231SS = { - {.VFMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBB, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBB, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB132SD = { - {.VFMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB213SD = { - {.VFMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAB, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAB, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUB231SD = { - {.VFMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBB, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBB, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD132PS = { - {.VFNMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFNMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFNMADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD213PS = { - {.VFNMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFNMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFNMADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD231PS = { - {.VFNMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFNMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFNMADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD132PD = { - {.VFNMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFNMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFNMADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD213PD = { - {.VFNMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFNMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFNMADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD231PD = { - {.VFNMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFNMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFNMADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBC, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD132SS = { - {.VFNMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFNMADD132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD213SS = { - {.VFNMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAD, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFNMADD213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAD, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD231SS = { - {.VFNMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBD, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFNMADD231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBD, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD132SD = { - {.VFNMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFNMADD132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD213SD = { - {.VFNMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAD, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFNMADD213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAD, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMADD231SD = { - {.VFNMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBD, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFNMADD231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBD, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB132PS = { - {.VFNMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFNMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFNMSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB213PS = { - {.VFNMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFNMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFNMSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB231PS = { - {.VFNMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFNMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFNMSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB132PD = { - {.VFNMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFNMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFNMSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB213PD = { - {.VFNMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFNMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFNMSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB231PD = { - {.VFNMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFNMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFNMSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFNMSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBE, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB132SS = { - {.VFNMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFNMSUB132SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB213SS = { - {.VFNMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAF, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFNMSUB213SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAF, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB231SS = { - {.VFNMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBF, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFNMSUB231SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBF, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB132SD = { - {.VFNMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFNMSUB132SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x9F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB213SD = { - {.VFNMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAF, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFNMSUB213SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xAF, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFNMSUB231SD = { - {.VFNMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBF, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFNMSUB231SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xBF, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADDSUB132PS = { - {.VFMADDSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMADDSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMADDSUB132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADDSUB132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADDSUB213PS = { - {.VFMADDSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMADDSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMADDSUB213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADDSUB213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADDSUB231PS = { - {.VFMADDSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMADDSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMADDSUB231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADDSUB231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADDSUB132PD = { - {.VFMADDSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMADDSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMADDSUB132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADDSUB132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x96, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADDSUB213PD = { - {.VFMADDSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMADDSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMADDSUB213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADDSUB213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMADDSUB231PD = { - {.VFMADDSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMADDSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMADDSUB231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMADDSUB231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB6, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUBADD132PS = { - {.VFMSUBADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMSUBADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMSUBADD132PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUBADD132PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUBADD213PS = { - {.VFMSUBADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMSUBADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMSUBADD213PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUBADD213PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUBADD231PS = { - {.VFMSUBADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.VFMSUBADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.VFMSUBADD231PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUBADD231PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUBADD132PD = { - {.VFMSUBADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMSUBADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMSUBADD132PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUBADD132PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x97, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUBADD213PD = { - {.VFMSUBADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMSUBADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMSUBADD213PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUBADD213PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xA7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFMSUBADD231PD = { - {.VFMSUBADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.VFMSUBADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.VFMSUBADD231PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFMSUBADD231PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0xB7, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, - // F16C instructions .VCVTPH2PS = { - {.VCVTPH2PS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPH2PS, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VCVTPH2PS, {.ZMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2}}, + {{.VCVTPH2PS, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTPH2PS, {.YMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VCVTPH2PS, {.ZMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VCVTPS2PH = { - {.VCVTPS2PH, {.XMM_M64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, - {.VCVTPS2PH, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, - {.VCVTPS2PH, {.YMM_M256, .ZMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2}}, + {{.VCVTPS2PH, {.XMM_M64, .XMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}}, + {{.VCVTPS2PH, {.XMM_M128, .YMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}}, + {{.VCVTPS2PH, {.YMM_M256, .ZMM, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, 0x1D, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, writes_mem=true, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.15 AVX-512 Encodings - // ------------------------------------------------------------------------- .VMOVDQA32 = { - {.VMOVDQA32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VMOVDQA32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VMOVDQA32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VMOVDQA32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VMOVDQA32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, - {.VMOVDQA32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VMOVDQA32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQA32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQA32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQA32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQA32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQA32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VMOVDQA64 = { - {.VMOVDQA64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VMOVDQA64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VMOVDQA64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VMOVDQA64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VMOVDQA64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, - {.VMOVDQA64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VMOVDQA64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQA64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQA64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQA64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQA64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQA64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VMOVDQU8 = { - {.VMOVDQU8, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VMOVDQU8, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VMOVDQU8, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VMOVDQU8, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VMOVDQU8, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, - {.VMOVDQU8, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VMOVDQU8, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU8, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU8, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU8, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU8, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU8, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VMOVDQU16 = { - {.VMOVDQU16, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VMOVDQU16, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VMOVDQU16, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VMOVDQU16, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VMOVDQU16, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, - {.VMOVDQU16, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VMOVDQU16, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU16, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU16, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU16, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU16, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU16, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VMOVDQU32 = { - {.VMOVDQU32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VMOVDQU32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VMOVDQU32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VMOVDQU32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VMOVDQU32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, - {.VMOVDQU32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VMOVDQU32, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU32, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU32, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU32, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU32, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU32, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VMOVDQU64 = { - {.VMOVDQU64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VMOVDQU64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VMOVDQU64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VMOVDQU64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VMOVDQU64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, - {.VMOVDQU64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VMOVDQU64, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU64, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU64, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU64, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU64, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x6F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, + {{.VMOVDQU64, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x7F, 0, {esc=._0F, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, - // AVX-512 blend instructions .VPBLENDMB = { - {.VPBLENDMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPBLENDMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPBLENDMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPBLENDMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPBLENDMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPBLENDMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPBLENDMW = { - {.VPBLENDMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPBLENDMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPBLENDMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPBLENDMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPBLENDMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPBLENDMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x66, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPBLENDMD = { - {.VPBLENDMD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPBLENDMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPBLENDMD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPBLENDMD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPBLENDMD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPBLENDMD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPBLENDMQ = { - {.VPBLENDMQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPBLENDMQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPBLENDMQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPBLENDMQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPBLENDMQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPBLENDMQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x64, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VBLENDMPS = { - {.VBLENDMPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VBLENDMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VBLENDMPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VBLENDMPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VBLENDMPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VBLENDMPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VBLENDMPD = { - {.VBLENDMPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VBLENDMPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VBLENDMPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VBLENDMPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VBLENDMPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VBLENDMPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x65, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, - // AVX-512 comparison instructions (output to mask register) .VPCMPB = { - {.VPCMPB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPCMPB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPCMPB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPCMPB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPUB = { - {.VPCMPUB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPCMPUB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPCMPUB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPCMPUB, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPUB, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPUB, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPW = { - {.VPCMPW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPCMPW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPCMPW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPCMPW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPUW = { - {.VPCMPUW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPCMPUW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPCMPUW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPCMPUW, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPUW, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPUW, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x3E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPD = { - {.VPCMPD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPCMPD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPCMPD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPCMPD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPUD = { - {.VPCMPUD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPCMPUD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPCMPUD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPCMPUD, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPUD, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPUD, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPQ = { - {.VPCMPQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPCMPQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPCMPQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPCMPQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1F, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPCMPUQ = { - {.VPCMPUQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPCMPUQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPCMPUQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPCMPUQ, {.K, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPUQ, {.K, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPCMPUQ, {.K, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x1E, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, - // AVX-512 test instructions (output to mask register) .VPTESTMB = { - {.VPTESTMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPTESTMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPTESTMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPTESTMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPTESTMW = { - {.VPTESTMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPTESTMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPTESTMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPTESTMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPTESTMD = { - {.VPTESTMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPTESTMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPTESTMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPTESTMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPTESTMQ = { - {.VPTESTMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPTESTMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPTESTMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPTESTMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPTESTNMB = { - {.VPTESTNMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPTESTNMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPTESTNMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPTESTNMB, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTNMB, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTNMB, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPTESTNMW = { - {.VPTESTNMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPTESTNMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPTESTNMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPTESTNMW, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTNMW, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTNMW, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x26, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPTESTNMD = { - {.VPTESTNMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPTESTNMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPTESTNMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPTESTNMD, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTNMD, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTNMD, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPTESTNMQ = { - {.VPTESTNMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPTESTNMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPTESTNMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPTESTNMQ, {.K, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTNMQ, {.K, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPTESTNMQ, {.K, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x27, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, - // AVX-512 compress/expand instructions .VPCOMPRESSD = { - {.VPCOMPRESSD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPCOMPRESSD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPCOMPRESSD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPCOMPRESSD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPCOMPRESSD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPCOMPRESSD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPCOMPRESSQ = { - {.VPCOMPRESSQ, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPCOMPRESSQ, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPCOMPRESSQ, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPCOMPRESSQ, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPCOMPRESSQ, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPCOMPRESSQ, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8B, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VCOMPRESSPS = { - {.VCOMPRESSPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VCOMPRESSPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VCOMPRESSPS, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VCOMPRESSPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VCOMPRESSPS, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VCOMPRESSPS, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VCOMPRESSPD = { - {.VCOMPRESSPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VCOMPRESSPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VCOMPRESSPD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VCOMPRESSPD, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VCOMPRESSPD, {.YMM_M256, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VCOMPRESSPD, {.ZMM_M512, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x8A, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPEXPANDD = { - {.VPEXPANDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPEXPANDD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPEXPANDD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPEXPANDD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPEXPANDD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPEXPANDD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPEXPANDQ = { - {.VPEXPANDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPEXPANDQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPEXPANDQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPEXPANDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPEXPANDQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPEXPANDQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x89, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VEXPANDPS = { - {.VEXPANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VEXPANDPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VEXPANDPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VEXPANDPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VEXPANDPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VEXPANDPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VEXPANDPD = { - {.VEXPANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VEXPANDPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VEXPANDPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VEXPANDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VEXPANDPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VEXPANDPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x88, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, - // AVX-512 conflict detection .VPCONFLICTD = { - {.VPCONFLICTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPCONFLICTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPCONFLICTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPCONFLICTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPCONFLICTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPCONFLICTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPCONFLICTQ = { - {.VPCONFLICTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPCONFLICTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPCONFLICTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPCONFLICTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPCONFLICTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPCONFLICTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xC4, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPLZCNTD = { - {.VPLZCNTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPLZCNTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPLZCNTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPLZCNTD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPLZCNTD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPLZCNTD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPLZCNTQ = { - {.VPLZCNTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPLZCNTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPLZCNTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPLZCNTQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPLZCNTQ, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPLZCNTQ, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, - // AVX-512 permute instructions .VPERMI2B = { - {.VPERMI2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPERMI2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPERMI2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPERMI2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMI2W = { - {.VPERMI2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPERMI2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPERMI2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPERMI2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x75, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMI2D = { - {.VPERMI2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPERMI2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPERMI2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPERMI2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMI2Q = { - {.VPERMI2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPERMI2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPERMI2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPERMI2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x76, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMI2PS = { - {.VPERMI2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPERMI2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPERMI2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPERMI2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMI2PD = { - {.VPERMI2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPERMI2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPERMI2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPERMI2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMI2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x77, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMT2B = { - {.VPERMT2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPERMT2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPERMT2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPERMT2B, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2B, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2B, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMT2W = { - {.VPERMT2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPERMT2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPERMT2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPERMT2W, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2W, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2W, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMT2D = { - {.VPERMT2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPERMT2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPERMT2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPERMT2D, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2D, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2D, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMT2Q = { - {.VPERMT2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPERMT2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPERMT2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPERMT2Q, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2Q, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2Q, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMT2PS = { - {.VPERMT2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPERMT2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPERMT2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPERMT2PS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2PS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2PS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMT2PD = { - {.VPERMT2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPERMT2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPERMT2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPERMT2PD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2PD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMT2PD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x7F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMB = { - {.VPERMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPERMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPERMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPERMB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPERMW = { - {.VPERMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPERMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPERMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPERMW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPERMW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x8D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, - // AVX-512 mask-to-vector and vector-to-mask conversions .VPMOVB2M = { - {.VPMOVB2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVB2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVB2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVB2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPMOVB2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPMOVB2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}}}, }, .VPMOVW2M = { - {.VPMOVW2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPMOVW2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPMOVW2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPMOVW2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPMOVW2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPMOVW2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x29, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}}}, }, .VPMOVD2M = { - {.VPMOVD2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVD2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVD2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVD2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPMOVD2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPMOVD2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}}}, }, .VPMOVQ2M = { - {.VPMOVQ2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPMOVQ2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPMOVQ2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPMOVQ2M, {.K, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPMOVQ2M, {.K, .YMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPMOVQ2M, {.K, .ZMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x39, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}}}, }, .VPMOVM2B = { - {.VPMOVM2B, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVM2B, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVM2B, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVM2B, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPMOVM2B, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPMOVM2B, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}}}, }, .VPMOVM2W = { - {.VPMOVM2W, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPMOVM2W, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPMOVM2W, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPMOVM2W, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPMOVM2W, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPMOVM2W, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x28, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}}}, }, .VPMOVM2D = { - {.VPMOVM2D, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVM2D, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVM2D, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVM2D, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPMOVM2D, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPMOVM2D, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}}}, }, .VPMOVM2Q = { - {.VPMOVM2Q, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPMOVM2Q, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPMOVM2Q, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPMOVM2Q, {.XMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}}}, + {{.VPMOVM2Q, {.YMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}}}, + {{.VPMOVM2Q, {.ZMM, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x38, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}}}, }, - // AVX-512 down-conversion instructions .VPMOVQB = { - {.VPMOVQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x32, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVSQB = { - {.VPMOVSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x22, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVUSQB = { - {.VPMOVUSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVUSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVUSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVUSQB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSQB, {.XMM_M32, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSQB, {.XMM_M64, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVQW = { - {.VPMOVQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x34, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVSQW = { - {.VPMOVSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x24, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVUSQW = { - {.VPMOVUSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVUSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVUSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVUSQW, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSQW, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSQW, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVQD = { - {.VPMOVQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x35, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVSQD = { - {.VPMOVSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x25, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVUSQD = { - {.VPMOVUSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVUSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVUSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVUSQD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSQD, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSQD, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVDB = { - {.VPMOVDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x31, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVSDB = { - {.VPMOVSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x21, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVUSDB = { - {.VPMOVUSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVUSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVUSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVUSDB, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSDB, {.XMM_M64, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSDB, {.XMM_M128, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVDW = { - {.VPMOVDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x33, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVSDW = { - {.VPMOVSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x23, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVUSDW = { - {.VPMOVUSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVUSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVUSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVUSDW, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSDW, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSDW, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x13, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVWB = { - {.VPMOVWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x30, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVSWB = { - {.VPMOVSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x20, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VPMOVUSWB = { - {.VPMOVUSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPMOVUSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPMOVUSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPMOVUSWB, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSWB, {.XMM_M128, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VPMOVUSWB, {.YMM_M256, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_F3, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, - // AVX-512 rotate instructions .VPROLD = { - {.VPROLD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPROLD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPROLD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPROLD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPROLD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1, modrm_reg_ext=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPROLD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2, modrm_reg_ext=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPROLQ = { - {.VPROLQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPROLQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPROLQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {modrm_reg_ext=true, esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPROLQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0, modrm_reg_ext=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPROLQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1, modrm_reg_ext=true}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPROLQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 1, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2, modrm_reg_ext=true}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPROLVD = { - {.VPROLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPROLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPROLVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPROLVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPROLVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPROLVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPROLVQ = { - {.VPROLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPROLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPROLVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPROLVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPROLVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPROLVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x15, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPRORD = { - {.VPRORD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPRORD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPRORD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPRORD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPRORD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPRORD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPRORQ = { - {.VPRORQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPRORQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPRORQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPRORQ, {.XMM, .XMM_M128, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPRORQ, {.YMM, .YMM_M256, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPRORQ, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.VVVV, .MR, .IB, .NONE}, 0x72, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPRORVD = { - {.VPRORVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPRORVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPRORVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPRORVD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPRORVD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPRORVD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPRORVQ = { - {.VPRORVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPRORVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPRORVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPRORVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPRORVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPRORVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x14, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, - // AVX-512 scatter instructions (u. M for VSIB addressing) .VPSCATTERDD = { - {.VPSCATTERDD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPSCATTERDD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPSCATTERDD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPSCATTERDD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {read={0, 1}, writes_mem=true}}, + {{.VPSCATTERDD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {read={0, 1}, writes_mem=true}}, + {{.VPSCATTERDD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {read={0, 1}, writes_mem=true}}, }, .VPSCATTERDQ = { - {.VPSCATTERDQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPSCATTERDQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPSCATTERDQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPSCATTERDQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {read={0, 1}, writes_mem=true}}, + {{.VPSCATTERDQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {read={0, 1}, writes_mem=true}}, + {{.VPSCATTERDQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA0, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {read={0, 1}, writes_mem=true}}, }, .VPSCATTERQD = { - {.VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPSCATTERQD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {read={0, 1}, writes_mem=true}}, + {{.VPSCATTERQD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {read={0, 1}, writes_mem=true}}, + {{.VPSCATTERQD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {read={0, 1}, writes_mem=true}}, }, .VPSCATTERQQ = { - {.VPSCATTERQQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPSCATTERQQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPSCATTERQQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPSCATTERQQ, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {read={0, 1}, writes_mem=true}}, + {{.VPSCATTERQQ, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {read={0, 1}, writes_mem=true}}, + {{.VPSCATTERQQ, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA1, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {read={0, 1}, writes_mem=true}}, }, .VSCATTERDPS = { - {.VSCATTERDPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VSCATTERDPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VSCATTERDPS, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VSCATTERDPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {read={0, 1}, writes_mem=true}}, + {{.VSCATTERDPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {read={0, 1}, writes_mem=true}}, + {{.VSCATTERDPS, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {read={0, 1}, writes_mem=true}}, }, .VSCATTERDPD = { - {.VSCATTERDPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VSCATTERDPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VSCATTERDPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VSCATTERDPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {read={0, 1}, writes_mem=true}}, + {{.VSCATTERDPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {read={0, 1}, writes_mem=true}}, + {{.VSCATTERDPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA2, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {read={0, 1}, writes_mem=true}}, }, .VSCATTERQPS = { - {.VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VSCATTERQPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {read={0, 1}, writes_mem=true}}, + {{.VSCATTERQPS, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {read={0, 1}, writes_mem=true}}, + {{.VSCATTERQPS, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {read={0, 1}, writes_mem=true}}, }, .VSCATTERQPD = { - {.VSCATTERQPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VSCATTERQPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VSCATTERQPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VSCATTERQPD, {.M, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {read={0, 1}, writes_mem=true}}, + {{.VSCATTERQPD, {.M, .YMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {read={0, 1}, writes_mem=true}}, + {{.VSCATTERQPD, {.M, .ZMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xA3, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {read={0, 1}, writes_mem=true}}, }, - // AVX-512 variable shift instructions .VPSRAVQ = { - {.VPSRAVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPSRAVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPSRAVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPSRAVQ, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRAVQ, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRAVQ, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSRAVW = { - {.VPSRAVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPSRAVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPSRAVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPSRAVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRAVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRAVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x11, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSLLVW = { - {.VPSLLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPSLLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPSLLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPSLLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSLLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSLLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x12, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPSRLVW = { - {.VPSRLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPSRLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPSRLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPSRLVW, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRLVW, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPSRLVW, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x10, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, - // AVX-512 range instructions .VRANGEPS = { - {.VRANGEPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VRANGEPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VRANGEPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VRANGEPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRANGEPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRANGEPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRANGEPD = { - {.VRANGEPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VRANGEPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VRANGEPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VRANGEPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRANGEPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRANGEPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x50, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRANGESS = { - {.VRANGESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x51, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W0}}, + {{.VRANGESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x51, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRANGESD = { - {.VRANGESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x51, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W1}}, + {{.VRANGESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x51, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, - // AVX-512 reduce instructions .VREDUCEPS = { - {.VREDUCEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VREDUCEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VREDUCEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VREDUCEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VREDUCEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VREDUCEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VREDUCEPD = { - {.VREDUCEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VREDUCEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VREDUCEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VREDUCEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VREDUCEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VREDUCEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x56, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VREDUCESS = { - {.VREDUCESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x57, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W0}}, + {{.VREDUCESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x57, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VREDUCESD = { - {.VREDUCESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x57, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W1}}, + {{.VREDUCESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x57, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, - // AVX-512 rndscale instructions .VRNDSCALEPS = { - {.VRNDSCALEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VRNDSCALEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VRNDSCALEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VRNDSCALEPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRNDSCALEPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRNDSCALEPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x08, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRNDSCALEPD = { - {.VRNDSCALEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VRNDSCALEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VRNDSCALEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VRNDSCALEPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRNDSCALEPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRNDSCALEPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x09, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRNDSCALESS = { - {.VRNDSCALESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0A, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W0}}, + {{.VRNDSCALESS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0A, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRNDSCALESD = { - {.VRNDSCALESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0B, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W1}}, + {{.VRNDSCALESD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x0B, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, - // AVX-512 reciprocal instructions .VRSQRT14PS = { - {.VRSQRT14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VRSQRT14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VRSQRT14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VRSQRT14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRSQRT14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRSQRT14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRSQRT14PD = { - {.VRSQRT14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VRSQRT14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VRSQRT14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VRSQRT14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRSQRT14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRSQRT14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4E, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRSQRT14SS = { - {.VRSQRT14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W0}}, + {{.VRSQRT14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRSQRT14SD = { - {.VRSQRT14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W1}}, + {{.VRSQRT14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4F, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRCP14PS = { - {.VRCP14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VRCP14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VRCP14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VRCP14PS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRCP14PS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRCP14PS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRCP14PD = { - {.VRCP14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VRCP14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VRCP14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VRCP14PD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRCP14PD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VRCP14PD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x4C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRCP14SS = { - {.VRCP14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W0}}, + {{.VRCP14SS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VRCP14SD = { - {.VRCP14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W1}}, + {{.VRCP14SD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, - // AVX-512 scale instructions .VSCALEFPS = { - {.VSCALEFPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VSCALEFPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VSCALEFPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VSCALEFPS, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VSCALEFPS, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VSCALEFPS, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VSCALEFPD = { - {.VSCALEFPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VSCALEFPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VSCALEFPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VSCALEFPD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VSCALEFPD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VSCALEFPD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2C, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VSCALEFSS = { - {.VSCALEFSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W0}}, + {{.VSCALEFSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VSCALEFSD = { - {.VSCALEFSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W1}}, + {{.VSCALEFSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x2D, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, - // AVX-512 get exponent/mantissa instructions .VGETEXPPS = { - {.VGETEXPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VGETEXPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VGETEXPPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VGETEXPPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VGETEXPPS, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VGETEXPPS, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VGETEXPPD = { - {.VGETEXPPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VGETEXPPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VGETEXPPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VGETEXPPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VGETEXPPD, {.YMM, .YMM_M256, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VGETEXPPD, {.ZMM, .ZMM_M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x42, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VGETEXPSS = { - {.VGETEXPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x43, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W0}}, + {{.VGETEXPSS, {.XMM, .XMM, .XMM_M32, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x43, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VGETEXPSD = { - {.VGETEXPSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x43, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W1}}, + {{.VGETEXPSD, {.XMM, .XMM, .XMM_M64, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x43, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VGETMANTPS = { - {.VGETMANTPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VGETMANTPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VGETMANTPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VGETMANTPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VGETMANTPS, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VGETMANTPS, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VGETMANTPD = { - {.VGETMANTPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VGETMANTPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VGETMANTPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VGETMANTPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VGETMANTPD, {.YMM, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VGETMANTPD, {.ZMM, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x26, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VGETMANTSS = { - {.VGETMANTSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x27, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W0}}, + {{.VGETMANTSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x27, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VGETMANTSD = { - {.VGETMANTSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x27, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W1}}, + {{.VGETMANTSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x27, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, - // AVX-512 fixup instructions .VFIXUPIMMPS = { - {.VFIXUPIMMPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VFIXUPIMMPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VFIXUPIMMPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VFIXUPIMMPS, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFIXUPIMMPS, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFIXUPIMMPS, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFIXUPIMMPD = { - {.VFIXUPIMMPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VFIXUPIMMPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VFIXUPIMMPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VFIXUPIMMPD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFIXUPIMMPD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, + {{.VFIXUPIMMPD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x54, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFIXUPIMMSS = { - {.VFIXUPIMMSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x55, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFIXUPIMMSS, {.XMM, .XMM, .XMM_M32, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x55, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, .VFIXUPIMMSD = { - {.VFIXUPIMMSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x55, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFIXUPIMMSD, {.XMM, .XMM, .XMM_M64, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x55, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1}}, {written={0}, read={1, 2, 3}, implicit_wr={.MXCSR}, reads_mem=true}}, }, - // AVX-512 fpclass instructions .VFPCLASSPS = { - {.VFPCLASSPS, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VFPCLASSPS, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VFPCLASSPS, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VFPCLASSPS, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VFPCLASSPS, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VFPCLASSPS, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VFPCLASSPD = { - {.VFPCLASSPD, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VFPCLASSPD, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VFPCLASSPD, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VFPCLASSPD, {.K, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, reads_mem=true}}, + {{.VFPCLASSPD, {.K, .YMM_M256, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1}, reads_mem=true}}, + {{.VFPCLASSPD, {.K, .ZMM_M512, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x66, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1}, reads_mem=true}}, }, .VFPCLASSSS = { - {.VFPCLASSSS, {.K, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x67, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W0}}, + {{.VFPCLASSSS, {.K, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x67, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0}}, {written={0}, read={1}, reads_mem=true}}, }, .VFPCLASSSD = { - {.VFPCLASSSD, {.K, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x67, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.LIG, vex_w=.W1}}, + {{.VFPCLASSSD, {.K, .XMM_M64, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x67, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1}}, {written={0}, read={1}, reads_mem=true}}, }, - // AVX-512 align and misc instructions .VALIGNQ = { - {.VALIGNQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VALIGNQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VALIGNQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VALIGNQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VALIGNQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VALIGNQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VALIGND = { - {.VALIGND, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VALIGND, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VALIGND, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VALIGND, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VALIGND, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VALIGND, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x03, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VDBPSADBW = { - {.VDBPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VDBPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VDBPSADBW, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VDBPSADBW, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VDBPSADBW, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VDBPSADBW, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x42, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPTERNLOGD = { - {.VPTERNLOGD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPTERNLOGD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPTERNLOGD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPTERNLOGD, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VPTERNLOGD, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VPTERNLOGD, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPTERNLOGQ = { - {.VPTERNLOGQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPTERNLOGQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPTERNLOGQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPTERNLOGQ, {.XMM, .XMM, .XMM_M128, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VPTERNLOGQ, {.YMM, .YMM, .YMM_M256, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, + {{.VPTERNLOGQ, {.ZMM, .ZMM, .ZMM_M512, .IMM8}, {.REG, .VVVV, .MR, .IB}, 0x25, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2, 3}, reads_mem=true}}, }, .VPDPWSSD = { - {.VPDPWSSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x52, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W0}}, - {.VPDPWSSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x52, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W0}}, - {.VPDPWSSD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x52, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W0}}, + {{.VPDPWSSD, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x52, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPDPWSSD, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x52, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPDPWSSD, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x52, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W0, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, .VPMULTISHIFTQB = { - {.VPMULTISHIFTQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L0, vex_w=.W1}}, - {.VPMULTISHIFTQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L1, vex_w=.W1}}, - {.VPMULTISHIFTQB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_l=.L2, vex_w=.W1}}, + {{.VPMULTISHIFTQB, {.XMM, .XMM, .XMM_M128, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMULTISHIFTQB, {.YMM, .YMM, .YMM_M256, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}, reads_mem=true}}, + {{.VPMULTISHIFTQB, {.ZMM, .ZMM, .ZMM_M512, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x83, 0, {esc=._0F38, prefix=PREFIX_66, vex_type=.EVEX, vex_w=.W1, vex_l=.L2}}, {written={0}, read={1, 2}, reads_mem=true}}, }, - // Mask register add instructions .KADDW = { - {.KADDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KADDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KADDB = { - {.KADDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KADDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KADDQ = { - {.KADDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KADDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KADDD = { - {.KADDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KADDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4A, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, - // Mask register AND instructions .KANDW = { - {.KANDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KANDW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KANDB = { - {.KANDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KANDB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KANDQ = { - {.KANDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KANDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KANDD = { - {.KANDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KANDD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x41, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, - // Mask register AND NOT instructions .KANDNW = { - {.KANDNW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KANDNW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KANDNB = { - {.KANDNB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KANDNB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KANDNQ = { - {.KANDNQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KANDNQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KANDND = { - {.KANDND, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KANDND, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x42, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, - // Mask register move instructions .KMOVW = { - {.KMOVW, {.K, .K_M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.KMOVW, {.M16, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.KMOVW, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.KMOVW, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KMOVW, {.K, .K_M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.KMOVW, {.M16, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.KMOVW, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, + {{.KMOVW, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, }, .KMOVB = { - {.KMOVB, {.K, .K_M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.KMOVB, {.M8, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.KMOVB, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.KMOVB, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KMOVB, {.K, .K_M8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.KMOVB, {.M8, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.KMOVB, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, + {{.KMOVB, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, }, .KMOVQ = { - {.KMOVQ, {.K, .K_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.KMOVQ, {.M64, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.KMOVQ, {.K, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.KMOVQ, {.R64, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.KMOVQ, {.K, .K_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.KMOVQ, {.M64, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.KMOVQ, {.K, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}}}, + {{.KMOVQ, {.R64, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}}}, }, .KMOVD = { - {.KMOVD, {.K, .K_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.KMOVD, {.M32, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, - {.KMOVD, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, - {.KMOVD, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KMOVD, {.K, .K_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x90, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.KMOVD, {.M32, .K, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x91, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.KMOVD, {.K, .R32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x92, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, + {{.KMOVD, {.R32, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x93, 0, {esc=._0F, prefix=PREFIX_F2, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, }, - // Mask register NOT instructions .KNOTW = { - {.KNOTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KNOTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, }, .KNOTB = { - {.KNOTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KNOTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1}}}, }, .KNOTQ = { - {.KNOTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.KNOTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}}}, }, .KNOTD = { - {.KNOTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.KNOTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x44, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1}}}, }, - // Mask register OR instructions .KORW = { - {.KORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KORB = { - {.KORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KORQ = { - {.KORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KORD = { - {.KORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x45, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, - // Mask register OR test instructions .KORTESTW = { - {.KORTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KORTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, }, .KORTESTB = { - {.KORTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KORTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, }, .KORTESTQ = { - {.KORTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.KORTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, }, .KORTESTD = { - {.KORTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.KORTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x98, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, }, - // Mask register shift left instructions .KSHIFTLW = { - {.KSHIFTLW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x32, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.KSHIFTLW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x32, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}}}, }, .KSHIFTLB = { - {.KSHIFTLB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x32, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KSHIFTLB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x32, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}}}, }, .KSHIFTLQ = { - {.KSHIFTLQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x33, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.KSHIFTLQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x33, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}}}, }, .KSHIFTLD = { - {.KSHIFTLD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x33, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KSHIFTLD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x33, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}}}, }, - // Mask register shift right instructions .KSHIFTRW = { - {.KSHIFTRW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x30, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.KSHIFTRW, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x30, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}}}, }, .KSHIFTRB = { - {.KSHIFTRB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x30, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KSHIFTRB, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x30, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}}}, }, .KSHIFTRQ = { - {.KSHIFTRQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x31, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.KSHIFTRQ, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x31, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {written={0}, read={1, 2}}}, }, .KSHIFTRD = { - {.KSHIFTRD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x31, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KSHIFTRD, {.K, .K, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, 0x31, 0, {esc=._0F3A, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {written={0}, read={1, 2}}}, }, - // Mask register test instructions .KTESTW = { - {.KTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KTESTW, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, }, .KTESTB = { - {.KTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W0}}, + {{.KTESTB, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L0}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, }, .KTESTQ = { - {.KTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.KTESTQ, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, }, .KTESTD = { - {.KTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L0, vex_w=.W1}}, + {{.KTESTD, {.K, .K, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x99, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L0}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, }, - // Mask register unpack instructions .KUNPCKBW = { - {.KUNPCKBW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KUNPCKBW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KUNPCKWD = { - {.KUNPCKWD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KUNPCKWD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KUNPCKDQ = { - {.KUNPCKDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KUNPCKDQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x4B, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, - // Mask register XNOR instructions .KXNORW = { - {.KXNORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KXNORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KXNORB = { - {.KXNORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KXNORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KXNORQ = { - {.KXNORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KXNORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KXNORD = { - {.KXNORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KXNORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x46, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, - // Mask register XOR instructions .KXORW = { - {.KXORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KXORW, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KXORB = { - {.KXORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W0}}, + {{.KXORB, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W0, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KXORQ = { - {.KXORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KXORQ, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, .KXORD = { - {.KXORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_l=.L1, vex_w=.W1}}, + {{.KXORD, {.K, .K, .K, .NONE}, {.REG, .VVVV, .MR, .NONE}, 0x47, 0, {esc=._0F, prefix=PREFIX_66, vex_type=.VEX, vex_w=.W1, vex_l=.L1}}, {written={0}, read={1, 2}}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.16 x87 FPU Encodings - // ------------------------------------------------------------------------- .FADD = { - {.FADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 0, {}}, - {.FADD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 0, {}}, - {.FADD, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xC0, {}}, - {.FADD, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xC0, {}}, + {{.FADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 0 , {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FADD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 0 , {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FADD, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xC0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FADD, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xC0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FADDP = { - {.FADDP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xC0, {}}, - {.FADDP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xC1, {}}, + {{.FADDP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xC0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FADDP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xC1, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FIADD = { - {.FIADD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 0, {}}, - {.FIADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 0, {}}, + {{.FIADD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FIADD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, }, .FSUB = { - {.FSUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 4, {modrm_reg_ext=true}}, - {.FSUB, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 4, {modrm_reg_ext=true}}, - {.FSUB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xE0, {}}, - {.FSUB, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xE8, {}}, + {{.FSUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 4 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FSUB, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 4 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FSUB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xE0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FSUB, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xE8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FSUBP = { - {.FSUBP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xE8, {}}, - {.FSUBP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xE9, {}}, + {{.FSUBP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xE8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FSUBP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xE9, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FISUB = { - {.FISUB, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 4, {modrm_reg_ext=true}}, - {.FISUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 4, {modrm_reg_ext=true}}, + {{.FISUB, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 4, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FISUB, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 4, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, }, .FSUBR = { - {.FSUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 5, {modrm_reg_ext=true}}, - {.FSUBR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 5, {modrm_reg_ext=true}}, - {.FSUBR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xE8, {}}, - {.FSUBR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xE0, {}}, + {{.FSUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 5 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FSUBR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 5 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FSUBR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xE8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FSUBR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xE0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FSUBRP = { - {.FSUBRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xE0, {}}, - {.FSUBRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xE1, {}}, + {{.FSUBRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xE0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FSUBRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xE1, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FISUBR = { - {.FISUBR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 5, {modrm_reg_ext=true}}, - {.FISUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 5, {modrm_reg_ext=true}}, + {{.FISUBR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 5, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FISUBR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 5, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, }, .FMUL = { - {.FMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 1, {modrm_reg_ext=true}}, - {.FMUL, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 1, {modrm_reg_ext=true}}, - {.FMUL, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xC8, {}}, - {.FMUL, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xC8, {}}, + {{.FMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 1 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FMUL, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 1 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FMUL, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xC8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FMUL, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xC8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FMULP = { - {.FMULP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xC8, {}}, - {.FMULP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xC9, {}}, + {{.FMULP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xC8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FMULP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xC9, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FIMUL = { - {.FIMUL, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 1, {modrm_reg_ext=true}}, - {.FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 1, {modrm_reg_ext=true}}, + {{.FIMUL, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 1, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 1, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, }, .FDIV = { - {.FDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 6, {modrm_reg_ext=true}}, - {.FDIV, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 6, {modrm_reg_ext=true}}, - {.FDIV, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xF0, {}}, - {.FDIV, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xF8, {}}, + {{.FDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 6 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FDIV, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 6 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FDIV, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xF0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FDIV, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xF8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FDIVP = { - {.FDIVP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xF8, {}}, - {.FDIVP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xF9, {}}, + {{.FDIVP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xF8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FDIVP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xF9, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FIDIV = { - {.FIDIV, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 6, {modrm_reg_ext=true}}, - {.FIDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 6, {modrm_reg_ext=true}}, + {{.FIDIV, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 6, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FIDIV, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 6, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, }, .FDIVR = { - {.FDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 7, {modrm_reg_ext=true}}, - {.FDIVR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 7, {modrm_reg_ext=true}}, - {.FDIVR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xF8, {}}, - {.FDIVR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xF0, {}}, + {{.FDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 7 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FDIVR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 7 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FDIVR, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xD8, 0xF8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FDIVR, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDC, 0xF0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FDIVRP = { - {.FDIVRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xF0, {}}, - {.FDIVRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xF1, {}}, + {{.FDIVRP, {.STI, .ST0_IMPL, .NONE, .NONE}, {.OP_R, .IMPL, .NONE, .NONE}, 0xDE, 0xF0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FDIVRP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xF1, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FIDIVR = { - {.FIDIVR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 7, {modrm_reg_ext=true}}, - {.FIDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 7, {modrm_reg_ext=true}}, + {{.FIDIVR, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 7, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FIDIVR, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 7, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, }, .FSQRT = { - {.FSQRT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFA, {}}, + {{.FSQRT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFA, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FABS = { - {.FABS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE1, {}}, + {{.FABS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE1, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FCHS = { - {.FCHS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE0, {}}, + {{.FCHS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FPREM = { - {.FPREM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF8, {}}, + {{.FPREM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FPREM1 = { - {.FPREM1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF5, {}}, + {{.FPREM1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF5, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FRNDINT = { - {.FRNDINT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFC, {}}, + {{.FRNDINT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFC, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FSCALE = { - {.FSCALE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFD, {}}, + {{.FSCALE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFD, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FXTRACT = { - {.FXTRACT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF4, {}}, + {{.FXTRACT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF4, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FXAM = { - {.FXAM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE5, {}}, + {{.FXAM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE5, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FLD = { - {.FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 0, {}}, - {.FLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 0, {}}, - {.FLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 5, {modrm_reg_ext=true}}, - {.FLD, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD9, 0xC0, {}}, + {{.FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 0 , {}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, + {{.FLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 0 , {}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, + {{.FLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 5 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, + {{.FLD, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD9, 0xC0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}}}, }, .FILD = { - {.FILD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 0, {}}, - {.FILD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 0, {}}, - {.FILD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 5, {modrm_reg_ext=true}}, + {{.FILD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, + {{.FILD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, + {{.FILD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 5, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, }, .FBLD = { - {.FBLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 4, {modrm_reg_ext=true}}, + {{.FBLD, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 4, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, }, .FST = { - {.FST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 2, {modrm_reg_ext=true}}, - {.FST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 2, {modrm_reg_ext=true}}, - {.FST, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 0xD0, {}}, + {{.FST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 2 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, + {{.FST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 2 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, + {{.FST, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 0xD0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}}}, }, .FSTP = { - {.FSTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 3, {modrm_reg_ext=true}}, - {.FSTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 3, {modrm_reg_ext=true}}, - {.FSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 7, {modrm_reg_ext=true}}, - {.FSTP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 0xD8, {}}, + {{.FSTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 3 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, + {{.FSTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 3 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, + {{.FSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 7 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, + {{.FSTP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 0xD8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}}}, }, .FIST = { - {.FIST, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 2, {modrm_reg_ext=true}}, - {.FIST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 2, {modrm_reg_ext=true}}, + {{.FIST, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 2, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, + {{.FIST, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 2, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FISTP = { - {.FISTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 3, {modrm_reg_ext=true}}, - {.FISTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 3, {modrm_reg_ext=true}}, - {.FISTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 7, {modrm_reg_ext=true}}, + {{.FISTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 3, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, + {{.FISTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 3, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, + {{.FISTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 7, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FISTTP = { - {.FISTTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 1, {modrm_reg_ext=true}}, - {.FISTTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 1, {modrm_reg_ext=true}}, - {.FISTTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 1, {modrm_reg_ext=true}}, + {{.FISTTP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 1, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, + {{.FISTTP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDB, 1, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, + {{.FISTTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 1, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FBSTP = { - {.FBSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 6, {modrm_reg_ext=true}}, + {{.FBSTP, {.M80, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDF, 6, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FXCH = { - {.FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD9, 0xC8, {}}, - {.FXCH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xC9, {}}, + {{.FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD9, 0xC8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FXCH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xC9, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FCMOVB = { - {.FCMOVB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 0xC0, {}}, + {{.FCMOVB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 0xC0, {}}, {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}}, }, .FCMOVE = { - {.FCMOVE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 0xC8, {}}, + {{.FCMOVE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 0xC8, {}}, {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}}, }, .FCMOVBE = { - {.FCMOVBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 0xD0, {}}, + {{.FCMOVBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 0xD0, {}}, {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}}, }, .FCMOVU = { - {.FCMOVU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 0xD8, {}}, + {{.FCMOVU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDA, 0xD8, {}}, {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}}, }, .FCMOVNB = { - {.FCMOVNB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xC0, {}}, + {{.FCMOVNB, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xC0, {}}, {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF}}}, }, .FCMOVNE = { - {.FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xC8, {}}, + {{.FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xC8, {}}, {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.ZF}}}, }, .FCMOVNBE = { - {.FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xD0, {}}, + {{.FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xD0, {}}, {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.CF, .ZF}}}, }, .FCMOVNU = { - {.FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xD8, {}}, + {{.FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xD8, {}}, {implicit_wr={.FPU_ST}, implicit_rd={.FPU_ST}, flags_rd={.PF}}}, }, .FCOM = { - {.FCOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 2, {modrm_reg_ext=true}}, - {.FCOM, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 2, {modrm_reg_ext=true}}, - {.FCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD8, 0xD0, {}}, - {.FCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD8, 0xD1, {}}, + {{.FCOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 2 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FCOM, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 2 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD8, 0xD0, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD8, 0xD1, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FCOMP = { - {.FCOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 3, {modrm_reg_ext=true}}, - {.FCOMP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 3, {modrm_reg_ext=true}}, - {.FCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD8, 0xD8, {}}, - {.FCOMP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD8, 0xD9, {}}, + {{.FCOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD8, 3 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FCOMP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDC, 3 , {modrm_reg_ext=true}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xD8, 0xD8, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FCOMP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD8, 0xD9, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FCOMPP = { - {.FCOMPP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xD9, {}}, + {{.FCOMPP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDE, 0xD9, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FICOM = { - {.FICOM, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 2, {modrm_reg_ext=true}}, - {.FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 2, {modrm_reg_ext=true}}, + {{.FICOM, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 2, {modrm_reg_ext=true}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 2, {modrm_reg_ext=true}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, }, .FICOMP = { - {.FICOMP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 3, {modrm_reg_ext=true}}, - {.FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 3, {modrm_reg_ext=true}}, + {{.FICOMP, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDE, 3, {modrm_reg_ext=true}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, + {{.FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDA, 3, {modrm_reg_ext=true}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}, reads_mem=true}}, }, .FCOMI = { - {.FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xF0, {}}, + {{.FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xF0, {}}, {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}}, }, .FCOMIP = { - {.FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 0xF0, {}}, + {{.FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 0xF0, {}}, {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}}, }, .FUCOMI = { - {.FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xE8, {}}, + {{.FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDB, 0xE8, {}}, {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}}, }, .FUCOMIP = { - {.FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 0xE8, {}}, + {{.FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, 0xDF, 0xE8, {}}, {implicit_rd={.FPU_ST}, flags_wr={.CF, .PF, .ZF}, flags_undef={.AF, .SF, .OF}}}, }, .FUCOM = { - {.FUCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 0xE0, {}}, - {.FUCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDD, 0xE1, {}}, + {{.FUCOM, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 0xE0, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FUCOM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDD, 0xE1, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FUCOMP = { - {.FUCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 0xE8, {}}, - {.FUCOMP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDD, 0xE9, {}}, + {{.FUCOMP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 0xE8, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, + {{.FUCOMP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDD, 0xE9, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FUCOMPP = { - {.FUCOMPP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDA, 0xE9, {}}, + {{.FUCOMPP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDA, 0xE9, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FTST = { - {.FTST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE4, {}}, + {{.FTST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE4, {}}, {implicit_wr={.FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FLDZ = { - {.FLDZ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xEE, {}}, + {{.FLDZ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xEE, {}}, {implicit_wr={.FPU_ST, .FPU_SW}}}, }, .FLD1 = { - {.FLD1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE8, {}}, + {{.FLD1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE8, {}}, {implicit_wr={.FPU_ST, .FPU_SW}}}, }, .FLDPI = { - {.FLDPI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xEB, {}}, + {{.FLDPI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xEB, {}}, {implicit_wr={.FPU_ST, .FPU_SW}}}, }, .FLDL2T = { - {.FLDL2T, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE9, {}}, + {{.FLDL2T, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xE9, {}}, {implicit_wr={.FPU_ST, .FPU_SW}}}, }, .FLDL2E = { - {.FLDL2E, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xEA, {}}, + {{.FLDL2E, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xEA, {}}, {implicit_wr={.FPU_ST, .FPU_SW}}}, }, .FLDLG2 = { - {.FLDLG2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xEC, {}}, + {{.FLDLG2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xEC, {}}, {implicit_wr={.FPU_ST, .FPU_SW}}}, }, .FLDLN2 = { - {.FLDLN2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xED, {}}, + {{.FLDLN2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xED, {}}, {implicit_wr={.FPU_ST, .FPU_SW}}}, }, .FSIN = { - {.FSIN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFE, {}}, + {{.FSIN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFE, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FCOS = { - {.FCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFF, {}}, + {{.FCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFF, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FSINCOS = { - {.FSINCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFB, {}}, + {{.FSINCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xFB, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FPTAN = { - {.FPTAN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF2, {}}, + {{.FPTAN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF2, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FPATAN = { - {.FPATAN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF3, {}}, + {{.FPATAN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF3, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .F2XM1 = { - {.F2XM1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF0, {}}, + {{.F2XM1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FYL2X = { - {.FYL2X, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF1, {}}, + {{.FYL2X, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF1, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FYL2XP1 = { - {.FYL2XP1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF9, {}}, + {{.FYL2XP1, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF9, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FINIT = { - {.FINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDB, 0xE3, {}}, + {{.FINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDB, 0xE3, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FNINIT = { - {.FNINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDB, 0xE3, {}}, + {{.FNINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDB, 0xE3, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FINCSTP = { - {.FINCSTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF7, {}}, + {{.FINCSTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF7, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FDECSTP = { - {.FDECSTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF6, {}}, + {{.FDECSTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xF6, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FFREE = { - {.FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 0xC0, {}}, + {{.FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDD, 0xC0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, - .FFREEP = { // DF C0+i - undocumented, frees ST(i) and pops - {.FFREEP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDF, 0xC0, {}}, + .FFREEP = { + {{.FFREEP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xDF, 0xC0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FNOP = { - {.FNOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xD0, {}}, + {{.FNOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD9, 0xD0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FWAIT = { - {.FWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9B, 0, {}}, + {{.FWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x9B, 0, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FCLEX = { - {.FCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDB, 0xE2, {}}, + {{.FCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDB, 0xE2, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FNCLEX = { - {.FNCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDB, 0xE2, {}}, + {{.FNCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xDB, 0xE2, {}}, {implicit_wr={.FPU_ST, .FPU_SW}, implicit_rd={.FPU_ST}}}, }, .FSTCW = { - {.FSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 7, {modrm_reg_ext=true}}, + {{.FSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 7, {modrm_reg_ext=true}}, {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FNSTCW = { - {.FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 7, {modrm_reg_ext=true}}, + {{.FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 7, {modrm_reg_ext=true}}, {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FLDCW = { - {.FLDCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 5, {modrm_reg_ext=true}}, + {{.FLDCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 5, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, }, .FSTENV = { - {.FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 6, {modrm_reg_ext=true}}, + {{.FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 6, {modrm_reg_ext=true}}, {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FNSTENV = { - {.FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 6, {modrm_reg_ext=true}}, + {{.FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 6, {modrm_reg_ext=true}}, {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FLDENV = { - {.FLDENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 4, {modrm_reg_ext=true}}, + {{.FLDENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xD9, 4, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, }, .FSAVE = { - {.FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 6, {modrm_reg_ext=true}}, + {{.FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 6, {modrm_reg_ext=true}}, {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FNSAVE = { - {.FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 6, {modrm_reg_ext=true}}, + {{.FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 6, {modrm_reg_ext=true}}, {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FRSTOR = { - {.FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 4, {modrm_reg_ext=true}}, + {{.FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 4, {modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, }, .FSTSW = { - {.FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7, {modrm_reg_ext=true}}, - {.FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 0xE0, {}}, + {{.FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7 , {modrm_reg_ext=true}}, {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}}, + {{.FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 0xE0, {}}, {implicit_wr={.RAX, .FPU_SW}}}, }, .FNSTSW = { - {.FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7, {modrm_reg_ext=true}}, - {.FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 0xE0, {}}, + {{.FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xDD, 7 , {modrm_reg_ext=true}}, {implicit_wr={.RAX, .FPU_SW}, writes_mem=true}}, + {{.FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, 0xDF, 0xE0, {}}, {implicit_wr={.RAX, .FPU_SW}}}, }, .FXSAVE = { - {.FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true}}, + {{.FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true}}, {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FXSAVE64 = { - {.FXSAVE64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.FXSAVE64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {implicit_rd={.FPU_ST, .FPU_SW}, writes_mem=true}}, }, .FXRSTOR = { - {.FXRSTOR, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, modrm_reg_ext=true}}, + {{.FXRSTOR, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, }, .FXRSTOR64 = { - {.FXRSTOR64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.FXRSTOR64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {implicit_wr={.FPU_ST, .FPU_SW}, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.17 System Instruction Encodings - // ------------------------------------------------------------------------- .LGDT = { - {.LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 2, {esc=._0F, modrm_reg_ext=true}}, - {.LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 2, {esc=._0F, modrm_reg_ext=true}}, + {{.LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 2, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}}, + {{.LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 2, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}}, }, .SGDT = { - {.SGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 0, {esc=._0F, modrm_reg_ext=true}}, - {.SGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 0, {esc=._0F, modrm_reg_ext=true}}, + {{.SGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 0, {esc=._0F, modrm_reg_ext=true}}, {written={0}, writes_mem=true}}, + {{.SGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 0, {esc=._0F, modrm_reg_ext=true}}, {written={0}, writes_mem=true}}, }, .LIDT = { - {.LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 3, {esc=._0F, modrm_reg_ext=true}}, - {.LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 3, {esc=._0F, modrm_reg_ext=true}}, + {{.LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 3, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}}, + {{.LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 3, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}}, }, .SIDT = { - {.SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 1, {esc=._0F, modrm_reg_ext=true}}, - {.SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 1, {esc=._0F, modrm_reg_ext=true}}, + {{.SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 1, {esc=._0F, modrm_reg_ext=true}}, {written={0}, writes_mem=true}}, + {{.SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 1, {esc=._0F, modrm_reg_ext=true}}, {written={0}, writes_mem=true}}, }, .LLDT = { - {.LLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 2, {esc=._0F, modrm_reg_ext=true}}, + {{.LLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 2, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}}, }, .SLDT = { - {.SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, modrm_reg_ext=true}}, - {.SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, modrm_reg_ext=true}}, - {.SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, modrm_reg_ext=true}}, {written={0}, writes_mem=true}}, + {{.SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, modrm_reg_ext=true}}, {written={0}}}, + {{.SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 0, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {written={0}}}, }, .LTR = { - {.LTR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 3, {esc=._0F, modrm_reg_ext=true}}, + {{.LTR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 3, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}}, }, .STR = { - {.STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, modrm_reg_ext=true}}, - {.STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, modrm_reg_ext=true}}, - {.STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, modrm_reg_ext=true}}, {written={0}, writes_mem=true}}, + {{.STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, modrm_reg_ext=true}}, {written={0}}}, + {{.STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 1, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {written={0}}}, }, .LMSW = { - {.LMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 6, {esc=._0F, modrm_reg_ext=true}}, + {{.LMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 6, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}}, }, .SMSW = { - {.SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, modrm_reg_ext=true}}, - {.SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, modrm_reg_ext=true}}, - {.SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.SMSW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, modrm_reg_ext=true}}, {written={0}, writes_mem=true}}, + {{.SMSW, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, modrm_reg_ext=true}}, {written={0}}}, + {{.SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {written={0}}}, }, - .CLTS = { // 0F 06 - {.CLTS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x06, 0, {esc=._0F}}, + .CLTS = { + {{.CLTS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x06, 0, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - .ARPL = { // Invalid in 64-bit mode - {.ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x63, 0, {}}, + .ARPL = { + {{.ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x63, 0, {}}, {written={0}, read={1}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}}, }, .LAR = { - {.LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F}}, - {.LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F}}, - {.LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F, force_rex_w=true}}, + {{.LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F}}, {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}}, + {{.LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F}}, {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}}, + {{.LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x02, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}}, }, .LSL = { - {.LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F}}, - {.LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F}}, - {.LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F, force_rex_w=true}}, + {{.LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F}}, {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}}, + {{.LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F}}, {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}}, + {{.LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x03, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={1}, flags_wr={.ZF}, reads_mem=true}}, }, .VERR = { - {.VERR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 4, {esc=._0F, modrm_reg_ext=true}}, + {{.VERR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 4, {esc=._0F, modrm_reg_ext=true}}, {read={0}, flags_wr={.ZF}, reads_mem=true}}, }, .VERW = { - {.VERW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 5, {esc=._0F, modrm_reg_ext=true}}, + {{.VERW, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x00, 5, {esc=._0F, modrm_reg_ext=true}}, {read={0}, flags_wr={.ZF}, reads_mem=true}}, }, - .INVD = { // 0F 08 - {.INVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x08, 0, {esc=._0F}}, + .INVD = { + {{.INVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x08, 0, {esc=._0F}}, {side_effects={.SERIALIZING, .PRIVILEGED}}}, }, - .WBINVD = { // 0F 09 - {.WBINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x09, 0, {esc=._0F}}, + .WBINVD = { + {{.WBINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x09, 0, {esc=._0F}}, {side_effects={.SERIALIZING, .PRIVILEGED}}}, }, .INVLPG = { - {.INVLPG, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 7, {esc=._0F, modrm_reg_ext=true}}, + {{.INVLPG, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 7, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.SERIALIZING, .PRIVILEGED}}}, }, .INVPCID = { - {.INVPCID, {.R32, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x82, 0, {esc=._0F38, prefix=PREFIX_66}}, - {.INVPCID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x82, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.INVPCID, {.R32, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x82, 0, {esc=._0F38, prefix=PREFIX_66}}, {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, + {{.INVPCID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x82, 0, {esc=._0F38, prefix=PREFIX_66}}, {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, - .RSM = { // 0F AA - {.RSM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAA, 0, {esc=._0F}}, + .RSM = { + {{.RSM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xAA, 0, {esc=._0F}}, {side_effects={.SERIALIZING, .PRIVILEGED}}}, }, - .RDMSR = { // 0F 32 - {.RDMSR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x32, 0, {esc=._0F}}, + .RDMSR = { + {{.RDMSR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x32, 0, {esc=._0F}}, {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}, side_effects={.PRIVILEGED}}}, }, - .WRMSR = { // 0F 30 - {.WRMSR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x30, 0, {esc=._0F}}, + .WRMSR = { + {{.WRMSR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x30, 0, {esc=._0F}}, {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.SERIALIZING, .PRIVILEGED}}}, }, - .VMCALL = { // 0F 01 C1 - {.VMCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC1, {esc=._0F}}, + .VMCALL = { + {{.VMCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC1, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - .VMLAUNCH = { // 0F 01 C2 - {.VMLAUNCH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC2, {esc=._0F}}, + .VMLAUNCH = { + {{.VMLAUNCH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC2, {esc=._0F}}, {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, - .VMRESUME = { // 0F 01 C3 - {.VMRESUME, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC3, {esc=._0F}}, + .VMRESUME = { + {{.VMRESUME, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC3, {esc=._0F}}, {flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, - .VMXOFF = { // 0F 01 C4 - {.VMXOFF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC4, {esc=._0F}}, + .VMXOFF = { + {{.VMXOFF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC4, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, .VMXON = { - {.VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + {{.VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, .VMCLEAR = { - {.VMCLEAR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_66}}, + {{.VMCLEAR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, .VMPTRLD = { - {.VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, + {{.VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, .VMPTRST = { - {.VMPTRST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, + {{.VMPTRST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, .VMREAD = { - {.VMREAD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x78, 0, {esc=._0F}}, + {{.VMREAD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0x78, 0, {esc=._0F}}, {written={0}, read={1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}}, }, .VMWRITE = { - {.VMWRITE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F}}, + {{.VMWRITE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x79, 0, {esc=._0F}}, {read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, - .VMFUNC = { // 0F 01 D4 - {.VMFUNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD4, {esc=._0F}}, + .VMFUNC = { + {{.VMFUNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD4, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, .INVEPT = { - {.INVEPT, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x80, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.INVEPT, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x80, 0, {esc=._0F38, prefix=PREFIX_66}}, {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, .INVVPID = { - {.INVVPID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x81, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.INVVPID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x81, 0, {esc=._0F38, prefix=PREFIX_66}}, {read={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, - // ----------------------------------------------------------------------------- - // SECTION: 8.18 Security and Memory Protection Encodings - // ----------------------------------------------------------------------------- - .ENCLS = { // 0F 01 CF - {.ENCLS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xCF, {esc=._0F}}, + .ENCLS = { + {{.ENCLS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xCF, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - .ENCLU = { // 0F 01 D7 - {.ENCLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD7, {esc=._0F}}, + .ENCLU = { + {{.ENCLU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD7, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - .ENCLV = { // 0F 01 C0 - {.ENCLV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC0, {esc=._0F}}, + .ENCLV = { + {{.ENCLV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC0, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - .RDPKRU = { // 0F 01 EE - {.RDPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xEE, {esc=._0F}}, + .RDPKRU = { + {{.RDPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xEE, {esc=._0F}}, {implicit_wr={.RAX}, implicit_rd={.RCX}}}, }, - .WRPKRU = { // 0F 01 EF - {.WRPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xEF, {esc=._0F}}, + .WRPKRU = { + {{.WRPKRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xEF, {esc=._0F}}, {implicit_rd={.RAX, .RCX, .RDX}}}, }, - .INCSSPD = { // F3 0F AE /5 - {.INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + .INCSSPD = { + {{.INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {read={0}, side_effects={.CET}}}, }, - .INCSSPQ = { // F3 REX.W 0F AE /5 - {.INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + .INCSSPQ = { + {{.INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true, modrm_reg_ext=true}}, {read={0}, side_effects={.CET}}}, }, - .RDSSPD = { // F3 0F 1E /1 - {.RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1E, 1, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + .RDSSPD = { + {{.RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1E, 1, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {written={0}, side_effects={.CET}}}, }, - .RDSSPQ = { // F3 REX.W 0F 1E /1 - {.RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1E, 1, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + .RDSSPQ = { + {{.RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1E, 1, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true, modrm_reg_ext=true}}, {written={0}, side_effects={.CET}}}, }, - .SAVEPREVSSP = { // F3 0F 01 EA - {.SAVEPREVSSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xEA, {esc=._0F, prefix=PREFIX_F3}}, + .SAVEPREVSSP = { + {{.SAVEPREVSSP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xEA, {esc=._0F, prefix=PREFIX_F3}}, {side_effects={.CET}}}, }, - .RSTORSSP = { // F3 0F 01 /5 - {.RSTORSSP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 5, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + .RSTORSSP = { + {{.RSTORSSP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x01, 5, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {read={0}, writes_mem=true, reads_mem=true, side_effects={.CET}}}, }, .WRSSD = { - {.WRSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF6, 0, {esc=._0F38}}, + {{.WRSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF6, 0, {esc=._0F38}}, {read={0, 1}, writes_mem=true, side_effects={.CET}}}, }, .WRSSQ = { - {.WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, force_rex_w=true}}, + {{.WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF6, 0, {esc=._0F38, force_rex_w=true}}, {read={0, 1}, writes_mem=true, side_effects={.CET}}}, }, .WRUSSD = { - {.WRUSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_66}}, + {{.WRUSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_66}}, {read={0, 1}, writes_mem=true, side_effects={.CET}}}, }, .WRUSSQ = { - {.WRUSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_66, force_rex_w=true}}, + {{.WRUSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF5, 0, {esc=._0F38, prefix=PREFIX_66, force_rex_w=true}}, {read={0, 1}, writes_mem=true, side_effects={.CET}}}, }, - .SETSSBSY = { // F3 0F 01 E8 - {.SETSSBSY, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xE8, {esc=._0F, prefix=PREFIX_F3}}, + .SETSSBSY = { + {{.SETSSBSY, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xE8, {esc=._0F, prefix=PREFIX_F3}}, {side_effects={.CET}}}, }, - .CLRSSBSY = { // F3 0F AE /6 - {.CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + .CLRSSBSY = { + {{.CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {read={0}, writes_mem=true, reads_mem=true, side_effects={.CET}}}, }, - .ENDBR64 = { // F3 0F 1E FA - {.ENDBR64, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1E, 0xFA, {esc=._0F, prefix=PREFIX_F3}}, + .ENDBR64 = { + {{.ENDBR64, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1E, 0xFA, {esc=._0F, prefix=PREFIX_F3}}, {side_effects={.HINT, .CET}}}, }, - .ENDBR32 = { // F3 0F 1E FB - {.ENDBR32, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1E, 0xFB, {esc=._0F, prefix=PREFIX_F3}}, + .ENDBR32 = { + {{.ENDBR32, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x1E, 0xFB, {esc=._0F, prefix=PREFIX_F3}}, {side_effects={.HINT, .CET}}}, }, - // ----------------------------------------------------------------------------- - // SECTION: 8.19 XSAVE/XRSTOR State Management Encodings - // ----------------------------------------------------------------------------- .XSAVE = { - {.XSAVE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, modrm_reg_ext=true}}, + {{.XSAVE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, modrm_reg_ext=true}}, {implicit_rd={.RAX, .RDX}, writes_mem=true}}, }, .XSAVE64 = { - {.XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {implicit_rd={.RAX, .RDX}, writes_mem=true}}, }, .XRSTOR = { - {.XRSTOR, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, modrm_reg_ext=true}}, + {{.XRSTOR, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, modrm_reg_ext=true}}, {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}}, }, .XRSTOR64 = { - {.XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 5, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true}}, }, .XSAVEOPT = { - {.XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true}}, + {{.XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true}}, {implicit_rd={.RAX, .RDX}, writes_mem=true}}, }, .XSAVEOPT64 = { - {.XSAVEOPT64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.XSAVEOPT64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {implicit_rd={.RAX, .RDX}, writes_mem=true}}, }, .XSAVEC = { - {.XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 4, {esc=._0F, modrm_reg_ext=true}}, + {{.XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 4, {esc=._0F, modrm_reg_ext=true}}, {implicit_rd={.RAX, .RDX}, writes_mem=true}}, }, .XSAVEC64 = { - {.XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 4, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 4, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {implicit_rd={.RAX, .RDX}, writes_mem=true}}, }, .XSAVES = { - {.XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 5, {esc=._0F, modrm_reg_ext=true}}, + {{.XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 5, {esc=._0F, modrm_reg_ext=true}}, {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}}, }, .XSAVES64 = { - {.XSAVES64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 5, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.XSAVES64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 5, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {implicit_rd={.RAX, .RDX}, writes_mem=true, side_effects={.PRIVILEGED}}}, }, .XRSTORS = { - {.XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 3, {esc=._0F, modrm_reg_ext=true}}, + {{.XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 3, {esc=._0F, modrm_reg_ext=true}}, {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, .XRSTORS64 = { - {.XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 3, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 3, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {implicit_wr={.MXCSR, .FPU_ST, .FPU_SW}, implicit_rd={.RAX, .RDX}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, - // ----------------------------------------------------------------------------- - // SECTION: 8.20 Cache and Prefetch Encodings - // ----------------------------------------------------------------------------- .PREFETCHT0 = { - {.PREFETCHT0, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 1, {esc=._0F, modrm_reg_ext=true}}, + {{.PREFETCHT0, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 1, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.HINT}}}, }, .PREFETCHT1 = { - {.PREFETCHT1, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 2, {esc=._0F, modrm_reg_ext=true}}, + {{.PREFETCHT1, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 2, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.HINT}}}, }, .PREFETCHT2 = { - {.PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 3, {esc=._0F, modrm_reg_ext=true}}, + {{.PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 3, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.HINT}}}, }, .PREFETCHNTA = { - {.PREFETCHNTA, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 0, {esc=._0F, modrm_reg_ext=true}}, + {{.PREFETCHNTA, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x18, 0, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.HINT}}}, }, .PREFETCHW = { - {.PREFETCHW, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x0D, 1, {esc=._0F, modrm_reg_ext=true}}, + {{.PREFETCHW, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x0D, 1, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.HINT}}}, }, .CLFLUSHOPT = { - {.CLFLUSHOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 7, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_66}}, + {{.CLFLUSHOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 7, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.CACHE}}}, }, .CLWB = { - {.CLWB, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_66}}, + {{.CLWB, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.CACHE}}}, }, .CLDEMOTE = { - {.CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1C, 0, {esc=._0F, modrm_reg_ext=true}}, + {{.CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x1C, 0, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.HINT}}}, }, - // ----------------------------------------------------------------------------- - // SECTION: 8.21 Atomic and Byte Swap Encodings - // ----------------------------------------------------------------------------- .BSWAP = { - {.BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xC8, 0, {esc=._0F}}, - {.BSWAP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xC8, 0, {esc=._0F, force_rex_w=true}}, + {{.BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xC8, 0, {esc=._0F}}, {written={0}, read={0}}}, + {{.BSWAP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, 0xC8, 0, {esc=._0F, force_rex_w=true}}, {written={0}, read={0}}}, }, .CMPXCHG = { - {.CMPXCHG, {.RM8 , .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB0, 0, {esc=._0F, lock_ok=true}}, - {.CMPXCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, lock_ok=true}}, - {.CMPXCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, lock_ok=true}}, - {.CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, lock_ok=true, force_rex_w=true}}, + {{.CMPXCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB0, 0, {esc=._0F, lock_ok=true}}, {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.CMPXCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, lock_ok=true}}, {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.CMPXCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, lock_ok=true}}, {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xB1, 0, {esc=._0F, force_rex_w=true, lock_ok=true}}, {written={0}, read={0, 1}, implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, }, .CMPXCHG8B = { - {.CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 1, {esc=._0F, modrm_reg_ext=true, lock_ok=true}}, + {{.CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 1, {esc=._0F, lock_ok=true, modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}}, }, .CMPXCHG16B = { - {.CMPXCHG16B, {.M128, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 1, {esc=._0F, modrm_reg_ext=true, lock_ok=true, force_rex_w=true}}, + {{.CMPXCHG16B, {.M128, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 1, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true}}, {read={0}, implicit_wr={.RAX, .RDX}, implicit_rd={.RAX, .RBX, .RCX, .RDX}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}}, }, .XADD = { - {.XADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC0, 0, {esc=._0F, lock_ok=true}}, - {.XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, lock_ok=true}}, - {.XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, lock_ok=true}}, - {.XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, lock_ok=true, force_rex_w=true}}, + {{.XADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC0, 0, {esc=._0F, lock_ok=true}}, {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, lock_ok=true}}, {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, lock_ok=true}}, {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, + {{.XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xC1, 0, {esc=._0F, force_rex_w=true, lock_ok=true}}, {written={0, 1}, read={0, 1}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true}}, }, - // ----------------------------------------------------------------------------- - // SECTION: 8.22 Miscellaneous Encodings - // ----------------------------------------------------------------------------- - .BOUND = { // Invalid in 64-bit mode - {.BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {mode_32_only=true}}, - {.BOUND, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {mode_32_only=true}}, + .BOUND = { + {{.BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {mode_32_only=true}}, {read={0, 1}, reads_mem=true, side_effects={.TRAP}}}, + {{.BOUND, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0x62, 0, {mode_32_only=true}}, {read={0, 1}, reads_mem=true, side_effects={.TRAP}}}, }, .ENTER = { - {.ENTER, {.IMM16, .IMM8, .NONE, .NONE}, {.IW, .IB, .NONE, .NONE}, 0xC8, 0, {}}, + {{.ENTER, {.IMM16, .IMM8, .NONE, .NONE}, {.IW, .IB, .NONE, .NONE}, 0xC8, 0, {}}, {implicit_wr={.RSP, .RBP}, implicit_rd={.RSP, .RBP}, writes_mem=true}}, }, .LEAVE = { - {.LEAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xC9, 0, {}}, + {{.LEAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xC9, 0, {}}, {implicit_wr={.RSP, .RBP}, implicit_rd={.RBP}, reads_mem=true}}, }, .XLAT = { - {.XLAT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD7, 0, {}}, + {{.XLAT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD7, 0, {}}, {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}}, }, .XLATB = { - {.XLATB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD7, 0, {}}, + {{.XLATB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xD7, 0, {}}, {implicit_wr={.RAX}, implicit_rd={.RAX, .RBX}, reads_mem=true}}, }, .MOVBE = { - {.MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38}}, - {.MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38}}, - {.MOVBE, {.R64, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, force_rex_w=true}}, - {.MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38}}, - {.MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38}}, - {.MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, force_rex_w=true}}, + {{.MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVBE, {.R64, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF0, 0, {esc=._0F38, force_rex_w=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, + {{.MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF1, 0, {esc=._0F38, force_rex_w=true}}, {written={0}, read={1}, writes_mem=true, reads_mem=true}}, }, .RDRAND = { - {.RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, - {.RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, - {.RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 6, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, }, .RDSEED = { - {.RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, - {.RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, - {.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, force_rex_w=true}}, + {{.RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, + {{.RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, force_rex_w=true, modrm_reg_ext=true}}, {written={0}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}}}, }, - // ------------------------------------------------------------------------- - // SECTION: 8.23 Additional System / GPR Encodings - // ------------------------------------------------------------------------- - .SWAPGS = { // 0F 01 F8 - {.SWAPGS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xF8, {esc=._0F}}, + .SWAPGS = { + {{.SWAPGS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xF8, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - .MONITOR = { // 0F 01 C8 - {.MONITOR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC8, {esc=._0F}}, + .MONITOR = { + {{.MONITOR, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC8, {esc=._0F}}, {implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true}}, }, - .MWAIT = { // 0F 01 C9 - {.MWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC9, {esc=._0F}}, + .MWAIT = { + {{.MWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xC9, {esc=._0F}}, {implicit_rd={.RAX, .RCX}, side_effects={.HALT}}}, }, - .CLAC = { // 0F 01 CA - {.CLAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xCA, {esc=._0F}}, + .CLAC = { + {{.CLAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xCA, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - .STAC = { // 0F 01 CB - {.STAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xCB, {esc=._0F}}, + .STAC = { + {{.STAC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xCB, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - .RDFSBASE = { // F3 0F AE /0 - {.RDFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, - {.RDFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + .RDFSBASE = { + {{.RDFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {written={0}}}, + {{.RDFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 0, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true, modrm_reg_ext=true}}, {written={0}}}, }, - .RDGSBASE = { // F3 0F AE /1 - {.RDGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, - {.RDGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + .RDGSBASE = { + {{.RDGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {written={0}}}, + {{.RDGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 1, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true, modrm_reg_ext=true}}, {written={0}}}, }, - .WRFSBASE = { // F3 0F AE /2 - {.WRFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, - {.WRFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + .WRFSBASE = { + {{.WRFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {read={0}}}, + {{.WRFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 2, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true, modrm_reg_ext=true}}, {read={0}}}, }, - .WRGSBASE = { // F3 0F AE /3 - {.WRGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, - {.WRGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + .WRGSBASE = { + {{.WRGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {read={0}}}, + {{.WRGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 3, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true, modrm_reg_ext=true}}, {read={0}}}, }, - .PTWRITE = { // F3 0F AE /4 - {.PTWRITE, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, - {.PTWRITE, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3, force_rex_w=true}}, + .PTWRITE = { + {{.PTWRITE, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {read={0}, reads_mem=true}}, + {{.PTWRITE, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 4, {esc=._0F, prefix=PREFIX_F3, force_rex_w=true, modrm_reg_ext=true}}, {read={0}, reads_mem=true}}, }, - .RDPID = { // F3 0F C7 /7 (r64 in 64-bit mode, no REX.W) - {.RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + .RDPID = { + {{.RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xC7, 7, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {written={0}}}, }, - .WBNOINVD = { // F3 0F 09 - {.WBNOINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x09, 0, {esc=._0F, prefix=PREFIX_F3}}, + .WBNOINVD = { + {{.WBNOINVD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x09, 0, {esc=._0F, prefix=PREFIX_F3}}, {side_effects={.SERIALIZING, .PRIVILEGED}}}, }, - .SERIALIZE = { // NP 0F 01 E8 - {.SERIALIZE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xE8, {esc=._0F}}, + .SERIALIZE = { + {{.SERIALIZE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xE8, {esc=._0F}}, {side_effects={.SERIALIZING}}}, }, - .PREFETCH = { // 0F 0D /0 - {.PREFETCH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x0D, 0, {esc=._0F, modrm_reg_ext=true}}, + .PREFETCH = { + {{.PREFETCH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0x0D, 0, {esc=._0F, modrm_reg_ext=true}}, {read={0}, reads_mem=true, side_effects={.HINT}}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.24 WAITPKG Encodings - // ------------------------------------------------------------------------- - .TPAUSE = { // 66 0F AE /6 - {.TPAUSE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_66}}, + .TPAUSE = { + {{.TPAUSE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=PREFIX_66, modrm_reg_ext=true}}, {read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}}}, }, - .UMONITOR = { // F3 0F AE /6 - {.UMONITOR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F3}}, + .UMONITOR = { + {{.UMONITOR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=PREFIX_F3, modrm_reg_ext=true}}, {read={0}, reads_mem=true}}, }, - .UMWAIT = { // F2 0F AE /6 - {.UMWAIT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, modrm_reg_ext=true, prefix=PREFIX_F2}}, + .UMWAIT = { + {{.UMWAIT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, 0xAE, 6, {esc=._0F, prefix=PREFIX_F2, modrm_reg_ext=true}}, {read={0}, implicit_rd={.RAX, .RDX}, flags_wr={.CF}, side_effects={.HINT}}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.25 Direct Store / Enqueue Store Encodings - // ------------------------------------------------------------------------- - .MOVDIRI = { // NP 0F 38 F9 /r (store r -> m) - {.MOVDIRI, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38}}, - {.MOVDIRI, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38, force_rex_w=true}}, + .MOVDIRI = { + {{.MOVDIRI, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38}}, {read={0, 1}, writes_mem=true}}, + {{.MOVDIRI, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xF9, 0, {esc=._0F38, force_rex_w=true}}, {read={0, 1}, writes_mem=true}}, }, - .MOVDIR64B = { // 66 0F 38 F8 /r (r=dest addr, m512=src) - {.MOVDIR64B, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_66}}, + .MOVDIR64B = { + {{.MOVDIR64B, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_66}}, {read={0}, implicit_rd={.RAX}, writes_mem=true, reads_mem=true}}, }, - .ENQCMD = { // F2 0F 38 F8 /r - {.ENQCMD, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_F2}}, + .ENQCMD = { + {{.ENQCMD, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_F2}}, {read={0}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}}, }, - .ENQCMDS = { // F3 0F 38 F8 /r - {.ENQCMDS, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_F3}}, + .ENQCMDS = { + {{.ENQCMDS, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, 0xF8, 0, {esc=._0F38, prefix=PREFIX_F3}}, {read={0}, flags_wr={.ZF}, writes_mem=true, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.26 Remote Atomic Operation (RAO-INT) Encodings - // ------------------------------------------------------------------------- - .AADD = { // NP 0F 38 FC /r - {.AADD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38}}, - {.AADD, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, force_rex_w=true}}, + .AADD = { + {{.AADD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38}}, {read={0, 1}, writes_mem=true, reads_mem=true}}, + {{.AADD, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, force_rex_w=true}}, {read={0, 1}, writes_mem=true, reads_mem=true}}, }, - .AAND = { // 66 0F 38 FC /r - {.AAND, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_66}}, - {.AAND, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_66, force_rex_w=true}}, + .AAND = { + {{.AAND, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_66}}, {read={0, 1}, writes_mem=true, reads_mem=true}}, + {{.AAND, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_66, force_rex_w=true}}, {read={0, 1}, writes_mem=true, reads_mem=true}}, }, - .AOR = { // F2 0F 38 FC /r - {.AOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F2}}, - {.AOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F2, force_rex_w=true}}, + .AOR = { + {{.AOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F2}}, {read={0, 1}, writes_mem=true, reads_mem=true}}, + {{.AOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F2, force_rex_w=true}}, {read={0, 1}, writes_mem=true, reads_mem=true}}, }, - .AXOR = { // F3 0F 38 FC /r - {.AXOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F3}}, - {.AXOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F3, force_rex_w=true}}, + .AXOR = { + {{.AXOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F3}}, {read={0, 1}, writes_mem=true, reads_mem=true}}, + {{.AXOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, 0xFC, 0, {esc=._0F38, prefix=PREFIX_F3, force_rex_w=true}}, {read={0, 1}, writes_mem=true, reads_mem=true}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.27 Restricted Transactional Memory (RTM) Encodings - // ------------------------------------------------------------------------- - .XEND = { // NP 0F 01 D5 - {.XEND, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD5, {esc=._0F}}, + .XEND = { + {{.XEND, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD5, {esc=._0F}}, {side_effects={.CONTROL}}}, }, - .XTEST = { // NP 0F 01 D6 - {.XTEST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD6, {esc=._0F}}, + .XTEST = { + {{.XTEST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD6, {esc=._0F}}, {flags_wr={.ZF}}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.28 AMD SVM Encodings - // ------------------------------------------------------------------------- - .VMRUN = { // 0F 01 D8 - {.VMRUN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD8, {esc=._0F}}, + .VMRUN = { + {{.VMRUN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD8, {esc=._0F}}, {implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, - .VMMCALL = { // 0F 01 D9 - {.VMMCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD9, {esc=._0F}}, + .VMMCALL = { + {{.VMMCALL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xD9, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - .VMLOAD = { // 0F 01 DA - {.VMLOAD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDA, {esc=._0F}}, + .VMLOAD = { + {{.VMLOAD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDA, {esc=._0F}}, {implicit_rd={.RAX}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, - .VMSAVE = { // 0F 01 DB - {.VMSAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDB, {esc=._0F}}, + .VMSAVE = { + {{.VMSAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDB, {esc=._0F}}, {implicit_rd={.RAX}, writes_mem=true, side_effects={.PRIVILEGED}}}, }, - .STGI = { // 0F 01 DC - {.STGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDC, {esc=._0F}}, + .STGI = { + {{.STGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDC, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - .CLGI = { // 0F 01 DD - {.CLGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDD, {esc=._0F}}, + .CLGI = { + {{.CLGI, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDD, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - .SKINIT = { // 0F 01 DE - {.SKINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDE, {esc=._0F}}, + .SKINIT = { + {{.SKINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDE, {esc=._0F}}, {implicit_rd={.RAX}, side_effects={.PRIVILEGED}}}, }, - .INVLPGA = { // 0F 01 DF - {.INVLPGA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDF, {esc=._0F}}, + .INVLPGA = { + {{.INVLPGA, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xDF, {esc=._0F}}, {implicit_rd={.RAX, .RCX}, side_effects={.PRIVILEGED}}}, }, - .INVLPGB = { // NP 0F 01 FE - {.INVLPGB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F}}, + .INVLPGB = { + {{.INVLPGB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F}}, {implicit_rd={.RAX, .RCX, .RDX}, side_effects={.PRIVILEGED}}}, }, - .TLBSYNC = { // NP 0F 01 FF - {.TLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F}}, + .TLBSYNC = { + {{.TLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F}}, {side_effects={.PRIVILEGED}}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.29 AMD SEV-SNP Encodings - // ------------------------------------------------------------------------- - .PVALIDATE = { // F2 0F 01 FF - {.PVALIDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F, prefix=PREFIX_F2}}, + .PVALIDATE = { + {{.PVALIDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F, prefix=PREFIX_F2}}, {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true}}, }, - .RMPADJUST = { // F3 0F 01 FE - {.RMPADJUST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F, prefix=PREFIX_F3}}, + .RMPADJUST = { + {{.RMPADJUST, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F, prefix=PREFIX_F3}}, {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX, .RDX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, reads_mem=true, side_effects={.PRIVILEGED}}}, }, - .RMPUPDATE = { // F2 0F 01 FE - {.RMPUPDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F, prefix=PREFIX_F2}}, + .RMPUPDATE = { + {{.RMPUPDATE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFE, {esc=._0F, prefix=PREFIX_F2}}, {implicit_wr={.RAX}, implicit_rd={.RAX, .RCX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, reads_mem=true, side_effects={.PRIVILEGED}}}, }, - .PSMASH = { // F3 0F 01 FF - {.PSMASH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F, prefix=PREFIX_F3}}, + .PSMASH = { + {{.PSMASH, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFF, {esc=._0F, prefix=PREFIX_F3}}, {implicit_wr={.RAX}, implicit_rd={.RAX}, flags_wr={.CF, .PF, .AF, .ZF, .SF, .OF}, writes_mem=true, side_effects={.PRIVILEGED}}}, }, - - // ------------------------------------------------------------------------- - // SECTION: 8.30 AMD Miscellaneous Encodings - // ------------------------------------------------------------------------- - .CLZERO = { // 0F 01 FC - {.CLZERO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFC, {esc=._0F}}, + .CLZERO = { + {{.CLZERO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFC, {esc=._0F}}, {implicit_rd={.RAX}, writes_mem=true, side_effects={.CACHE}}}, }, - .MONITORX = { // NP 0F 01 FA - {.MONITORX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFA, {esc=._0F}}, + .MONITORX = { + {{.MONITORX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFA, {esc=._0F}}, {implicit_rd={.RAX, .RCX, .RDX}, reads_mem=true}}, }, - .MWAITX = { // NP 0F 01 FB - {.MWAITX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFB, {esc=._0F}}, + .MWAITX = { + {{.MWAITX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFB, {esc=._0F}}, {implicit_rd={.RAX, .RBX, .RCX}, side_effects={.HALT}}}, }, - .RDPRU = { // 0F 01 FD - {.RDPRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFD, {esc=._0F}}, + .RDPRU = { + {{.RDPRU, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFD, {esc=._0F}}, {implicit_wr={.RAX, .RDX}, implicit_rd={.RCX}}}, }, - .MCOMMIT = { // F3 0F 01 FA - {.MCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFA, {esc=._0F, prefix=PREFIX_F3}}, + .MCOMMIT = { + {{.MCOMMIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x01, 0xFA, {esc=._0F, prefix=PREFIX_F3}}, {flags_wr={.CF}, side_effects={.FENCE}}}, }, } diff --git a/core/rexcode/isa/x86/tablegen/gen.odin b/core/rexcode/isa/x86/tablegen/gen.odin index 54da4475d..41346c4ff 100644 --- a/core/rexcode/isa/x86/tablegen/gen.odin +++ b/core/rexcode/isa/x86/tablegen/gen.odin @@ -84,7 +84,7 @@ main :: proc() { // ----------------------------------------------------------------------------- total_forms :: proc() -> (n: int) { - for m in Mnemonic { n += len(ENCODING_TABLE[m]) } + for m in Mnemonic { n += len(INSTRUCTION_TABLE[m]) } return } @@ -97,7 +97,7 @@ emit_encode_tables :: proc() { max_name := 0 for m in Mnemonic { - if len(ENCODING_TABLE[m]) > 0 { + if len(INSTRUCTION_TABLE[m]) > 0 { max_name = max(max_name, len(reflect.enum_string(m))) } } @@ -105,21 +105,20 @@ emit_encode_tables :: proc() { strings.write_string(&sb, "@(rodata)\n") fmt.sbprintfln(&sb, "ENCODE_FORMS := [%d]lib.Encoding{{", total_forms()) for m in Mnemonic { - forms := ENCODING_TABLE[m] + forms := &INSTRUCTION_TABLE[m] if len(forms) == 0 { continue } fmt.sbprintfln(&sb, "\t// .%v", m) - for f in forms { write_encoding(&sb, f, max_name) } + for f in forms { write_encoding(&sb, f.encoding, max_name) } } strings.write_string(&sb, "}\n\n") strings.write_string(&sb, "@(rodata)\n") fmt.sbprintfln(&sb, "CLOBBER_FORMS := [%d]lib.Clobber{{", total_forms()) for m in Mnemonic { - forms := CLOBBER_TABLE[m] - assert(len(forms) == len(ENCODING_TABLE[m])) + forms := &INSTRUCTION_TABLE[m] if len(forms) == 0 { continue } fmt.sbprintfln(&sb, "\t// .%v", m) - for f in forms { write_clobber(&sb, f, max_name) } + for f in forms { write_clobber(&sb, f.clobber, max_name) } } strings.write_string(&sb, "}\n\n") @@ -130,7 +129,7 @@ emit_encode_tables :: proc() { strings.write_string(&sb, "ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{\n") start := 0 for m in Mnemonic { - n := len(ENCODING_TABLE[m]) + n := len(INSTRUCTION_TABLE[m]) name := reflect.enum_string(m) fmt.sbprintf(&sb, "\t.%s", name) for _ in 0.. (n_legacy, n_vex, n_evex: int) { legacy, vex, evex: [dynamic]Collected_Entry for m in Mnemonic { - for enc in ENCODING_TABLE[m] { + for &form in INSTRUCTION_TABLE[m] { + enc := &form.encoding e := Collected_Entry{ esc = enc.flags.esc, prefix = enc.flags.prefix, From 22bdf11436859feaeffad35a6c2c4bca8ad81b22 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 19 Aug 2026 16:44:42 +0100 Subject: [PATCH 2/3] Rename to instruction_table.odin --- .../x86/tablegen/{encoding_table.odin => instruction_table.odin} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename core/rexcode/isa/x86/tablegen/{encoding_table.odin => instruction_table.odin} (100%) diff --git a/core/rexcode/isa/x86/tablegen/encoding_table.odin b/core/rexcode/isa/x86/tablegen/instruction_table.odin similarity index 100% rename from core/rexcode/isa/x86/tablegen/encoding_table.odin rename to core/rexcode/isa/x86/tablegen/instruction_table.odin From ea04ce30e4d6227744f1217a3132c0628e97d89f Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 19 Aug 2026 16:45:23 +0100 Subject: [PATCH 3/3] Remove dead comment --- core/rexcode/isa/x86/tablegen/instruction_table.odin | 1 - 1 file changed, 1 deletion(-) diff --git a/core/rexcode/isa/x86/tablegen/instruction_table.odin b/core/rexcode/isa/x86/tablegen/instruction_table.odin index 12c1e65b2..aa9f8e5b9 100644 --- a/core/rexcode/isa/x86/tablegen/instruction_table.odin +++ b/core/rexcode/isa/x86/tablegen/instruction_table.odin @@ -1,4 +1,3 @@ -// Code generated by instruction_table_gen.odin. DO NOT EDIT BY HAND. // Single source of truth: one Form (Encoding + Clobber) per instruction shape. package rexcode_x86_tablegen