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Add more MOV forms; fix liveness check for lanes

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This commit is contained in:
gingerBill
2026-08-31 17:51:24 +01:00
parent 07b5c2ee0f
commit 4f8a91092b
12 changed files with 2044 additions and 1937 deletions
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24
core/rexcode/isa/arm64/tablegen/cpp-compiler/cpp-gen.odin
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@@ -974,18 +974,30 @@ main :: proc() {
// shift == log2(bytes). Derived from the widest register operand in the form
// (the data being loaded/stored). 0 => no such constraint. Generic across ISAs.
u16 form_transfer_bytes(Encoding const &form) const {
// Mnemonic-pinned access sizes (byte/halfword variants).
switch (form.mnemonic) {
case M_LDRB: case M_LDRSB: case M_STRB:
case M_LDARB: case M_STLRB:
case M_LDXRB: case M_STXRB: case M_LDAXRB: case M_STLXRB:
return 1;
case M_LDRH: case M_LDRSH: case M_STRH:
case M_LDARH: case M_STLRH:
case M_LDXRH: case M_STXRH: case M_LDAXRH: case M_STLXRH:
return 2;
case M_LDRSW:
return 4;
}
// Otherwise the access equals the widest register operand (plain
// ldr/str x/w/q, ldp/stp, etc.).
u16 widest = 0;
for (int j = 0; j < gb_count_of(form.ops); j++) {
auto t = form.ops[j];
if (!t) {
break;
}
if (!t) break;
AsmOperandKind k = kind_from_operand_type(t);
if (k == AsmOperand_Register) {
u16 w = operand_type_bit_width(t);
if (w > widest) {
widest = w;
}
if (w > widest) widest = w;
}
}
return cast(u16)(widest / 8);

30
core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin
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@@ -8,7 +8,7 @@ package rexcode_arm64_generated
import lib "../.."
@(rodata)
DECODE_ENTRIES := [2710]lib.Decode_Entry{
DECODE_ENTRIES := [2720]lib.Decode_Entry{
{ .AMX_SET, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} },
{ .AMX_CLR, {.NONE,.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} },
{ .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true, explicit_count=1} },
@@ -1254,6 +1254,10 @@ DECODE_ENTRIES := [2710]lib.Decode_Entry{
{ .DUP, {.V_2S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x0E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} },
{ .DUP, {.V_4S,.W_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x4E040C00, 0xFFFFFC00, .NEON, {explicit_count=2} },
{ .DUP, {.V_2D,.X_REG,.NONE,.NONE,.NONE}, {.VD,.RN,.NONE,.NONE,.NONE}, 0x4E080C00, 0xFFFFFC00, .NEON, {explicit_count=2} },
{ .MOV, {.V_ELEM_B,.W_REG,.NONE,.NONE,.NONE}, {.NEON_IDX5,.RN,.NONE,.NONE,.NONE}, 0x4E011C00, 0xFFFFFC00, .NEON, {explicit_count=2} },
{ .MOV, {.V_ELEM_H,.W_REG,.NONE,.NONE,.NONE}, {.NEON_IDX5,.RN,.NONE,.NONE,.NONE}, 0x4E021C00, 0xFFFFFC00, .NEON, {explicit_count=2} },
{ .MOV, {.V_ELEM_S,.W_REG,.NONE,.NONE,.NONE}, {.NEON_IDX5,.RN,.NONE,.NONE,.NONE}, 0x4E041C00, 0xFFFFFC00, .NEON, {explicit_count=2} },
{ .MOV, {.V_ELEM_D,.X_REG,.NONE,.NONE,.NONE}, {.NEON_IDX5,.RN,.NONE,.NONE,.NONE}, 0x4E081C00, 0xFFFFFC00, .NEON, {is_64=true, explicit_count=2} },
{ .NOT, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {explicit_count=2} },
{ .NOT, {.V_16B,.V_16B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {explicit_count=2} },
{ .REV64, {.V_8B,.V_8B,.NONE,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {explicit_count=2} },
@@ -1389,6 +1393,10 @@ DECODE_ENTRIES := [2710]lib.Decode_Entry{
{ .DUP, {.V_16B,.V_ELEM_B,.VEC_INDEX,.NONE,.NONE}, {.VD,.VN,.NEON_IDX5,.NONE,.NONE}, 0x4E010400, 0xFFE1FC00, .NEON, {explicit_count=3} },
{ .INS, {.V_ELEM_S,.VEC_INDEX,.V_ELEM_S,.VEC_INDEX,.NONE}, {.VD,.NEON_IDX5,.VN,.NEON_IDX4,.NONE}, 0x6E040400, 0xFFE79C00, .NEON, {explicit_count=4} },
{ .INS, {.V_ELEM_B,.VEC_INDEX,.W_REG,.NONE,.NONE}, {.VD,.NEON_IDX5,.RN,.NONE,.NONE}, 0x4E011C00, 0xFFE1FC00, .NEON, {explicit_count=3} },
{ .MOV, {.V_ELEM_B,.V_ELEM_B,.NONE,.NONE,.NONE}, {.NEON_IDX5,.NEON_IDX4,.NONE,.NONE,.NONE}, 0x6E010400, 0xFFFF8400, .NEON, {explicit_count=2} },
{ .MOV, {.V_ELEM_H,.V_ELEM_H,.NONE,.NONE,.NONE}, {.NEON_IDX5,.NEON_IDX4,.NONE,.NONE,.NONE}, 0x6E020400, 0xFFFF8400, .NEON, {explicit_count=2} },
{ .MOV, {.V_ELEM_S,.V_ELEM_S,.NONE,.NONE,.NONE}, {.NEON_IDX5,.NEON_IDX4,.NONE,.NONE,.NONE}, 0x6E040400, 0xFFFF8400, .NEON, {explicit_count=2} },
{ .MOV, {.V_ELEM_D,.V_ELEM_D,.NONE,.NONE,.NONE}, {.NEON_IDX5,.NEON_IDX4,.NONE,.NONE,.NONE}, 0x6E080400, 0xFFFF8400, .NEON, {explicit_count=2} },
{ .ADD, {.V_16B,.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E208400, 0xFFE0FC00, .NEON, {explicit_count=3} },
{ .ADD, {.V_8H,.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4E608400, 0xFFE0FC00, .NEON, {explicit_count=3} },
{ .ADD, {.V_4S,.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.VM,.NONE,.NONE}, 0x4EA08400, 0xFFE0FC00, .NEON, {explicit_count=3} },
@@ -2546,6 +2554,8 @@ DECODE_ENTRIES := [2710]lib.Decode_Entry{
{ .FMOV, {.X_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} },
{ .FMOV, {.D_REG,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} },
{ .FMOV, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {explicit_count=2} },
{ .FMOV, {.X_REG,.V_ELEM_D,.NONE,.NONE,.NONE}, {.RD,.NEON_LANE_D,.NONE,.NONE,.NONE}, 0x9EAE0000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} },
{ .FMOV, {.V_ELEM_D,.X_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x9EAF0000, 0xFFFFFC00, .FP, {is_64=true, explicit_count=2} },
{ .FABS, {.S_REG,.S_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {explicit_count=2} },
{ .FABS, {.D_REG,.D_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1E60C000, 0xFFFFFC00, .FP, {explicit_count=2} },
{ .FABS, {.H_REG,.H_REG,.NONE,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE,.NONE}, 0x1EE0C000, 0xFFFFFC00, .FP16, {explicit_count=2} },
@@ -2728,14 +2738,14 @@ DECODE_INDEX_OP0 := [16]lib.Decode_Index{
0x04 = { 751, 76},
0x05 = { 827, 50},
0x06 = { 877, 56},
0x07 = { 933, 1058},
0x08 = {1991, 16},
0x09 = {2007, 34},
0x0A = {2041, 130},
0x0B = {2171, 21},
0x0C = {2192, 167},
0x0D = {2359, 122},
0x0E = {2481, 49},
0x0F = {2530, 180},
0x07 = { 933, 1066},
0x08 = {1999, 16},
0x09 = {2015, 34},
0x0A = {2049, 130},
0x0B = {2179, 21},
0x0C = {2200, 167},
0x0D = {2367, 122},
0x0E = {2489, 49},
0x0F = {2538, 182},
}

1504
core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin
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File diff suppressed because it is too large Load Diff

72
core/rexcode/isa/arm64/tablegen/instruction_table.odin
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@@ -764,21 +764,23 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{
{{.ERET, {.NONE, .NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE, .NONE}, 0xD69F03E0, 0xFFFFFFFF, .BASE, {branch=true, writes_pc=true}}, {side_effects={.CONTROL, .PRIVILEGED}}},
},
.FMOV = {
{{.FMOV, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}},
{{.FMOV, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}},
{{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, {written={0}}},
{{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, {written={0}}},
{{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, {written={0}}},
{{.FMOV, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}},
{{.FMOV, {.S_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}},
{{.FMOV, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}},
{{.FMOV, {.D_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}},
{{.FMOV, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}},
{{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}},
{{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}},
{{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}},
{{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}},
{{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}},
{{.FMOV, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E204000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}},
{{.FMOV, {.D_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E604000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}},
{{.FMOV, {.S_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1E201000, 0xFFE01FE0, .FP, {}}, {written={0}}},
{{.FMOV, {.D_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1E601000, 0xFFE01FE0, .FP, {}}, {written={0}}},
{{.FMOV, {.H_REG, .IMM_8, .NONE, .NONE, .NONE}, {.RD, .FMOV_SCALAR_IMM, .NONE, .NONE, .NONE}, 0x1EE01000, 0xFFE01FE0, .FP16, {}}, {written={0}}},
{{.FMOV, {.W_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E260000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}},
{{.FMOV, {.S_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E270000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}},
{{.FMOV, {.X_REG, .D_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E660000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}},
{{.FMOV, {.D_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9E670000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}},
{{.FMOV, {.H_REG, .H_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1EE04000, 0xFFFFFC00, .FP16, {}}, {written={0}, read={1}}},
{{.FMOV, {.V_2S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}},
{{.FMOV, {.V_4S, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}},
{{.FMOV, {.V_2D, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x6F00F400, 0xFFF8FC00, .NEON, {}}, {written={0}}},
{{.FMOV, {.V_4H_FP16, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x0F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}},
{{.FMOV, {.V_8H_FP16, .IMM_8, .NONE, .NONE, .NONE}, {.VD, .NEON_IMM8_FMOV, .NONE, .NONE, .NONE}, 0x4F00FC00, 0xFFF8FC00, .FP16, {}}, {written={0}}},
{{.FMOV, {.X_REG, .V_ELEM_D, .NONE, .NONE, .NONE}, {.RD, .NEON_LANE_D, .NONE, .NONE, .NONE}, 0x9EAE0000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}},
{{.FMOV, {.V_ELEM_D, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x9EAF0000, 0xFFFFFC00, .FP, {is_64=true}}, {written={0}, read={1}}},
},
.FABS = {
{{.FABS, {.S_REG, .S_REG, .NONE, .NONE, .NONE}, {.RD, .RN, .NONE, .NONE, .NONE}, 0x1E20C000, 0xFFFFFC00, .FP, {}}, {written={0}, read={1}}},
@@ -3061,22 +3063,30 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{
{{.INS, {.V_ELEM_D, .VEC_INDEX, .X_REG, .NONE, .NONE}, {.VD, .NEON_IDX5, .RN, .NONE, .NONE}, 0x4E081C00, 0xFFEFFC00, .NEON, {}}, {written={0}, read={0, 2}}},
},
.MOV = {
{{.MOV, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}},
{{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}},
{{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}},
{{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}}},
{{.MOV, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}},
{{.MOV, {.P_REG_B, .P_REG, .NONE, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}},
{{.MOV, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}},
{{.MOV, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}},
{{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, {written={0}}},
{{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, {written={0}}},
{{.MOV, {.B_REG, .V_ELEM_B, .NONE, .NONE, .NONE}, {.VD, .NEON_IDX5, .NONE, .NONE, .NONE}, 0x5E010400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.H_REG, .V_ELEM_H, .NONE, .NONE, .NONE}, {.VD, .NEON_IDX5, .NONE, .NONE, .NONE}, 0x5E020400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.S_REG, .V_ELEM_S, .NONE, .NONE, .NONE}, {.VD, .NEON_IDX5, .NONE, .NONE, .NONE}, 0x5E040400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.D_REG, .V_ELEM_D, .NONE, .NONE, .NONE}, {.VD, .NEON_IDX5, .NONE, .NONE, .NONE}, 0x5E080400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.V_8B, .V_8B, .NONE, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE, .NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.V_16B, .V_16B, .NONE, .NONE, .NONE}, {.VD, .VN_VM_DUP, .NONE, .NONE, .NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.Z_REG_B, .P_REG_MERGE, .Z_REG_B, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x0520C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}},
{{.MOV, {.Z_REG_H, .P_REG_MERGE, .Z_REG_H, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x0560C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}},
{{.MOV, {.Z_REG_S, .P_REG_MERGE, .Z_REG_S, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x05A0C000, 0xFFE0E000, .SVE, {}}, {read={0, 1, 2}}},
{{.MOV, {.Z_REG_D, .P_REG_MERGE, .Z_REG_D, .NONE, .NONE}, {.ZD_ZM_DUP, .PG, .VN, .NONE, .NONE}, 0x05E0C000, 0xFFE0E000, .SVE, {is_64=true}}, {read={0, 1, 2}}},
{{.MOV, {.P_REG_B, .P_REG_ZERO, .P_REG, .NONE, .NONE}, {.PD, .PG4, .PN_PM_DUP, .NONE, .NONE}, 0x25004000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1, 2}}},
{{.MOV, {.P_REG_B, .P_REG, .NONE, .NONE, .NONE}, {.PD, .PN_PG_PM_DUP, .NONE, .NONE, .NONE}, 0x25804000, 0xFFE0C210, .SVE, {}}, {written={0}, read={1}}},
{{.MOV, {.W_REG, .W_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {}}, {written={0}, read={1}}},
{{.MOV, {.X_REG, .X_REG, .NONE, .NONE, .NONE}, {.RD, .RM, .NONE, .NONE, .NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true}}, {written={0}, read={1}}},
{{.MOV, {.W_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0x320003E0, 0xFFC003E0, .BASE, {}}, {written={0}}},
{{.MOV, {.X_REG, .BITMASK_IMM, .NONE, .NONE, .NONE}, {.RD, .BITMASK_FIELD, .NONE, .NONE, .NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true}}, {written={0}}},
{{.MOV, {.B_REG, .V_ELEM_B, .NONE, .NONE, .NONE}, {.VD, .NEON_IDX5, .NONE, .NONE, .NONE}, 0x5E010400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.H_REG, .V_ELEM_H, .NONE, .NONE, .NONE}, {.VD, .NEON_IDX5, .NONE, .NONE, .NONE}, 0x5E020400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.S_REG, .V_ELEM_S, .NONE, .NONE, .NONE}, {.VD, .NEON_IDX5, .NONE, .NONE, .NONE}, 0x5E040400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.D_REG, .V_ELEM_D, .NONE, .NONE, .NONE}, {.VD, .NEON_IDX5, .NONE, .NONE, .NONE}, 0x5E080400, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.V_ELEM_B, .W_REG, .NONE, .NONE, .NONE}, {.NEON_IDX5, .RN, .NONE, .NONE, .NONE}, 0x4E011C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.V_ELEM_H, .W_REG, .NONE, .NONE, .NONE}, {.NEON_IDX5, .RN, .NONE, .NONE, .NONE}, 0x4E021C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.V_ELEM_S, .W_REG, .NONE, .NONE, .NONE}, {.NEON_IDX5, .RN, .NONE, .NONE, .NONE}, 0x4E041C00, 0xFFFFFC00, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.V_ELEM_D, .X_REG, .NONE, .NONE, .NONE}, {.NEON_IDX5, .RN, .NONE, .NONE, .NONE}, 0x4E081C00, 0xFFFFFC00, .NEON, {is_64=true}}, {written={0}, read={1}}},
{{.MOV, {.V_ELEM_B, .V_ELEM_B, .NONE, .NONE, .NONE}, {.NEON_IDX5, .NEON_IDX4, .NONE, .NONE, .NONE}, 0x6E010400, 0xFFFF8400, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.V_ELEM_H, .V_ELEM_H, .NONE, .NONE, .NONE}, {.NEON_IDX5, .NEON_IDX4, .NONE, .NONE, .NONE}, 0x6E020400, 0xFFFF8400, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.V_ELEM_S, .V_ELEM_S, .NONE, .NONE, .NONE}, {.NEON_IDX5, .NEON_IDX4, .NONE, .NONE, .NONE}, 0x6E040400, 0xFFFF8400, .NEON, {}}, {written={0}, read={1}}},
{{.MOV, {.V_ELEM_D, .V_ELEM_D, .NONE, .NONE, .NONE}, {.NEON_IDX5, .NEON_IDX4, .NONE, .NONE, .NONE}, 0x6E080400, 0xFFFF8400, .NEON, {}}, {written={0}, read={1}}},
},
.EXT = {
{{.EXT, {.V_8B, .V_8B, .V_8B, .VEC_INDEX, .NONE}, {.VD, .VN, .VM, .NEON_EXT_IDX, .NONE}, 0x2E000000, 0xFFE0C400, .NEON, {}}, {written={0}, read={1, 2}}},

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core/rexcode/isa/arm64/tables/arm64.clobber_forms.bin
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core/rexcode/isa/arm64/tables/arm64.encode_forms.bin
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core/rexcode/isa/arm64/tables/arm64.encode_runs.bin
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core/rexcode/isa/arm64/tables/arm64.entries.bin
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core/rexcode/isa/arm64/tables/arm64.idx_op0.bin
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