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rexcode/arm32: VMOV (ARM core register to scalar) Dd[lane], Rt

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New VMOV_LANE_8/16/32 encodings: Dd at bits 19:16+bit7, lane bits per
element size (.8 = bit21:bit6:bit5 with bit22 size marker; .16 =
bit21:bit6 with bit5 marker; .32 = bit21). Verify round-trips all three
sizes; spot-checked .8 byte-exact incl. max lane; 600 tests green.
This commit is contained in:
Brendan Punsky
2026-06-18 01:34:48 -04:00
committed by Flāvius
parent 5df81b5117
commit 55463b6719
16 changed files with 1066 additions and 1018 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
core/rexcode/arm32/decoder.odin
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@@ -341,6 +341,17 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
return op_dpr_lane(Register(REG_DPR | u16(word & 0x7)), u8(lane))
case .NEON_VM_SCALAR32:
return op_dpr_lane(Register(REG_DPR | u16(word & 0xF)), u8((word >> 5) & 1))
case .VMOV_LANE_8, .VMOV_LANE_16, .VMOV_LANE_32:
n := ((word >> 7) & 1) << 4 | ((word >> 16) & 0xF)
lane: u32 = 0
if enc == .VMOV_LANE_8 {
lane = ((word >> 21) & 1) << 2 | ((word >> 6) & 1) << 1 | ((word >> 5) & 1)
} else if enc == .VMOV_LANE_16 {
lane = ((word >> 21) & 1) << 1 | ((word >> 6) & 1)
} else {
lane = (word >> 21) & 1
}
return op_dpr_lane(Register(REG_DPR | u16(n)), u8(lane))
case .VD_Q:
n := (((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)) >> 1
return op_reg(Register(REG_QPR | u16(n)))

12
core/rexcode/arm32/encoder.odin
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@@ -424,6 +424,18 @@ pack_operand_inline :: #force_inline proc(
case .NEON_VM_SCALAR32:
// Dm in D0..D15 at bits 3:0; lane = bit5.
return (u32(reg_hw(op.reg)) & 0xF) | (u32(op.lane) & 1) << 5
case .VMOV_LANE_8, .VMOV_LANE_16, .VMOV_LANE_32:
n := u32(reg_hw(op.reg)) & 0x1F // Dd
v := (n & 0xF) << 16 | ((n >> 4) & 1) << 7
l := u32(op.lane)
if enc == .VMOV_LANE_8 {
v |= ((l >> 2) & 1) << 21 | ((l >> 1) & 1) << 6 | (l & 1) << 5
} else if enc == .VMOV_LANE_16 {
v |= ((l >> 1) & 1) << 21 | (l & 1) << 6
} else {
v |= (l & 1) << 21
}
return v
case .VFP_IMM8:
// Run the VFP 8-bit float encoder; the user supplies the wire-format
// 32-bit float bit pattern (for F32). The encoder finds the abcdefgh.

7
core/rexcode/arm32/encoding_types.odin
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@@ -305,6 +305,13 @@ Operand_Encoding :: enum u8 {
// .32: Dm in D0..D15 at bits 3:0, lane = bit5
NEON_VM_SCALAR16,
NEON_VM_SCALAR32,
// VMOV (core register to scalar) destination Dd[lane]: Dd at bits 19:16 +
// bit 7; the lane bits depend on element size:
// .8 lane[2:0] = bit22 : bit21 : bit5 .16 lane[1:0] = bit21 : bit6
// .32 lane[0] = bit21
VMOV_LANE_8,
VMOV_LANE_16,
VMOV_LANE_32,
VFP_IMM8, // VFP immediate (VMOV.F32/F64 #imm)
NEON_IMM8_ABCDEFGH, // bits 18-16 (abc) + bits 3-0 (defgh)
NEON_CMODE, // bits 11-8 (cmode for VMOV/VMVN immediate)

4
core/rexcode/arm32/mnemonic_builders.odin
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@@ -958,6 +958,8 @@ emit_vdup_d_r :: #force_inline proc(instructions: ^[dynamic]I
emit_vdup_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vdup_d_dlane(dst, src, lane)) }
inst_vswp_d_d :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .VSWP, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), {}, {}}} }
emit_vswp_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_vswp_d_d(dst, src)) }
inst_vmov_lane_dlane_r :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Register) -> Instruction { return Instruction{mnemonic = .VMOV_LANE, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_reg(src), {}, {}}} }
emit_vmov_lane_dlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_lane_dlane_r(dst, lane, src)) }
inst_vld1_dlist_mem :: #force_inline proc "contextless" (regs: u16, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg_list(regs), op_mem(src), {}, {}}} }
inst_vld1_dlane_mem :: #force_inline proc "contextless" (dst: Register, lane: u8, src: Memory) -> Instruction { return Instruction{mnemonic = .VLD1, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_dpr_lane(dst, lane), op_mem(src), {}, {}}} }
emit_vld1_dlist_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, regs: u16, src: Memory) { append(instructions, inst_vld1_dlist_mem(regs, src)) }
@@ -2209,6 +2211,8 @@ inst_vdup :: proc{ inst_vdup_d_r, inst_vdup_d_dlane
emit_vdup :: proc{ emit_vdup_d_r, emit_vdup_d_dlane }
inst_vswp :: inst_vswp_d_d
emit_vswp :: emit_vswp_d_d
inst_vmov_lane :: inst_vmov_lane_dlane_r
emit_vmov_lane :: emit_vmov_lane_dlane_r
inst_vld1 :: proc{ inst_vld1_dlist_mem, inst_vld1_dlane_mem }
emit_vld1 :: proc{ emit_vld1_dlist_mem, emit_vld1_dlane_mem }
inst_vld2 :: inst_vld2_dlist_mem

7
core/rexcode/arm32/tablegen/encoding_table.odin
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@@ -3680,6 +3680,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
{.VQRDMULH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}},
{.VQRDMULH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}},
},
// VMOV (ARM core register to scalar): Dd[lane], Rt. The lane bits depend on
// the element size (see VMOV_LANE_8/16/32); bit22/bit5 carry the size.
.VMOV_LANE = {
{.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_8, .RT_A32, .NONE, .NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}},
{.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_16, .RT_A32, .NONE, .NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}},
{.VMOV_LANE, {.DPR_ELEM, .GPR, .NONE, .NONE}, {.VMOV_LANE_32, .RT_A32, .NONE, .NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}},
},
// SPECGEN:BEGIN
.VADDL = {

1545
core/rexcode/arm32/tablegen/generated/decode_tables.odin
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File diff suppressed because it is too large Load Diff

498
core/rexcode/arm32/tablegen/generated/encode_tables.odin
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@@ -8,7 +8,7 @@ package rexcode_arm32_generated
import lib "../.."
@(rodata)
ENCODE_FORMS := [1668]lib.Encoding{
ENCODE_FORMS := [1671]lib.Encoding{
// .AND
{ .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {} },
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {} },
@@ -1720,6 +1720,10 @@ ENCODE_FORMS := [1668]lib.Encoding{
// .VSWP
{ .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {} },
{ .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {} },
// .VMOV_LANE
{ .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {} },
{ .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {} },
{ .VMOV_LANE, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {} },
// .VLD1
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {} },
{ .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {} },
@@ -2691,250 +2695,250 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
.VZIP = { 1310, 5},
.VDUP = { 1315, 5},
.VSWP = { 1320, 2},
.VMOV_LANE = { 1322, 0},
.VLD1 = { 1322, 8},
.VLD2 = { 1330, 3},
.VLD3 = { 1333, 2},
.VLD4 = { 1335, 2},
.VST1 = { 1337, 7},
.VST2 = { 1344, 3},
.VST3 = { 1347, 2},
.VST4 = { 1349, 2},
.AESE = { 1351, 1},
.AESD = { 1352, 1},
.AESMC = { 1353, 1},
.AESIMC = { 1354, 1},
.SHA1H = { 1355, 1},
.SHA1SU0 = { 1356, 1},
.SHA1SU1 = { 1357, 1},
.SHA1C = { 1358, 1},
.SHA1M = { 1359, 1},
.SHA1P = { 1360, 1},
.SHA256H = { 1361, 1},
.SHA256H2 = { 1362, 1},
.SHA256SU0 = { 1363, 1},
.SHA256SU1 = { 1364, 1},
.VRINT = { 1365, 0},
.VJCVT = { 1365, 1},
.VSDOT = { 1366, 2},
.VUDOT = { 1368, 2},
.VSDOT_LANE = { 1370, 2},
.VUDOT_LANE = { 1372, 2},
.VCVT_BF16 = { 1374, 1},
.VDOT_BF16 = { 1375, 2},
.VFMA_BF16 = { 1377, 1},
.VMMLA_BF16 = { 1378, 1},
.VFMAL = { 1379, 2},
.VFMSL = { 1381, 2},
.VCMLA = { 1383, 2},
.VCADD = { 1385, 2},
.VCMLA_LANE = { 1387, 2},
.VSMMLA = { 1389, 1},
.VUMMLA = { 1390, 1},
.VUSMMLA = { 1391, 1},
.VSUDOT = { 1392, 1},
.VUSDOT = { 1393, 2},
.VSUDOT_LANE = { 1395, 1},
.VUSDOT_LANE = { 1396, 2},
.VMUL_LANE = { 1398, 6},
.VMLA_LANE = { 1404, 6},
.VMLS_LANE = { 1410, 6},
.VMULL_LANE = { 1416, 4},
.VMLAL_LANE = { 1420, 4},
.VMLSL_LANE = { 1424, 4},
.VQDMULL_LANE = { 1428, 2},
.VQDMLAL_LANE = { 1430, 2},
.VQDMLSL_LANE = { 1432, 2},
.VFMA_LANE = { 1434, 2},
.VFMS_LANE = { 1436, 2},
.VQRDMLAH_LANE = { 1438, 4},
.VQRDMLSH_LANE = { 1442, 4},
.VQABS = { 1446, 1},
.VQNEG = { 1447, 1},
.VMOVX = { 1448, 1},
.VINS = { 1449, 1},
.VLDRB_GATHER = { 1450, 1},
.VLDRH_GATHER = { 1451, 1},
.VLDRW_GATHER = { 1452, 1},
.VLDRD_GATHER = { 1453, 1},
.VSTRB_SCATTER = { 1454, 1},
.VSTRH_SCATTER = { 1455, 1},
.VSTRW_SCATTER = { 1456, 1},
.VSTRD_SCATTER = { 1457, 1},
.VCEQ_Z = { 1458, 4},
.VCGE_Z = { 1462, 4},
.VCGT_Z = { 1466, 4},
.VCLE_Z = { 1470, 4},
.VCLT_Z = { 1474, 4},
.VLD2R = { 1478, 1},
.VLD3R = { 1479, 1},
.VLD4R = { 1480, 1},
.VLD1_LANE = { 1481, 3},
.VLD2_LANE = { 1484, 3},
.VLD3_LANE = { 1487, 3},
.VLD4_LANE = { 1490, 3},
.VST1_LANE = { 1493, 3},
.VST2_LANE = { 1496, 3},
.VST3_LANE = { 1499, 3},
.VST4_LANE = { 1502, 3},
.VCVT_FIXED = { 1505, 10},
.IT = { 1515, 1},
.TT = { 1516, 1},
.TTT = { 1517, 1},
.TTA = { 1518, 1},
.TTAT = { 1519, 1},
.SG = { 1520, 1},
.BXNS = { 1521, 1},
.BLXNS = { 1522, 1},
.PAC = { 1523, 1},
.PACBTI = { 1524, 1},
.AUT = { 1525, 1},
.AUTG = { 1526, 1},
.BTI = { 1527, 1},
.WLS = { 1528, 1},
.WLSTP = { 1529, 1},
.DLS = { 1530, 1},
.DLSTP = { 1531, 1},
.LE = { 1532, 1},
.LETP = { 1533, 1},
.LCTP = { 1534, 1},
.BF = { 1535, 0},
.BFI_BR = { 1535, 0},
.BFL = { 1535, 0},
.BFLX = { 1535, 0},
.BFCSEL = { 1535, 0},
.CX1 = { 1535, 1},
.CX1A = { 1536, 1},
.CX1D = { 1537, 1},
.CX1DA = { 1538, 1},
.CX2 = { 1539, 1},
.CX2A = { 1540, 1},
.CX2D = { 1541, 1},
.CX2DA = { 1542, 1},
.CX3 = { 1543, 1},
.CX3A = { 1544, 1},
.CX3D = { 1545, 1},
.CX3DA = { 1546, 1},
.VCX1 = { 1547, 2},
.VCX1A = { 1549, 2},
.VCX2 = { 1551, 2},
.VCX2A = { 1553, 2},
.VCX3 = { 1555, 2},
.VCX3A = { 1557, 2},
.VPT = { 1559, 1},
.VPST = { 1560, 1},
.VPSEL = { 1561, 1},
.VPNOT = { 1562, 1},
.VCTP = { 1563, 1},
.VADDV = { 1564, 1},
.VADDVA = { 1565, 1},
.VADDLV = { 1566, 1},
.VADDLVA = { 1567, 1},
.VMAXV = { 1568, 1},
.VMAXAV = { 1569, 1},
.VMINV = { 1570, 1},
.VMINAV = { 1571, 1},
.VMAXNMV = { 1572, 1},
.VMAXNMAV = { 1573, 1},
.VMINNMV = { 1574, 1},
.VMINNMAV = { 1575, 1},
.VABAV = { 1576, 1},
.VMLADAV = { 1577, 1},
.VMLADAVA = { 1578, 1},
.VMLADAVX = { 1579, 1},
.VMLADAVAX = { 1580, 1},
.VMLALDAV = { 1581, 1},
.VMLALDAVA = { 1582, 1},
.VMLALDAVX = { 1583, 1},
.VMLALDAVAX = { 1584, 1},
.VMLSDAV = { 1585, 1},
.VMLSDAVA = { 1586, 1},
.VMLSDAVX = { 1587, 1},
.VMLSDAVAX = { 1588, 1},
.VMLSLDAV = { 1589, 1},
.VMLSLDAVA = { 1590, 1},
.VMLSLDAVX = { 1591, 1},
.VMLSLDAVAX = { 1592, 1},
.VRMLALDAVH = { 1593, 1},
.VRMLALDAVHA = { 1594, 1},
.VRMLALDAVHX = { 1595, 1},
.VRMLALDAVHAX = { 1596, 1},
.VRMLSLDAVH = { 1597, 1},
.VRMLSLDAVHA = { 1598, 1},
.VRMLSLDAVHX = { 1599, 1},
.VRMLSLDAVHAX = { 1600, 1},
.VMLAV = { 1601, 1},
.VMLAVA = { 1602, 1},
.VMLSV = { 1603, 0},
.VMLSVA = { 1603, 0},
.VCMUL = { 1603, 1},
.VHCADD = { 1604, 1},
.VBRSR = { 1605, 1},
.VSHLC = { 1606, 1},
.VRSHL_MVE = { 1607, 0},
.VDDUP = { 1607, 1},
.VIDUP = { 1608, 1},
.VDWDUP = { 1609, 1},
.VIWDUP = { 1610, 1},
.VMOVNB = { 1611, 1},
.VMOVNT = { 1612, 1},
.VQMOVNB = { 1613, 1},
.VQMOVNT = { 1614, 1},
.VQMOVUNB = { 1615, 1},
.VQMOVUNT = { 1616, 1},
.VSHLLB = { 1617, 1},
.VSHLLT = { 1618, 1},
.VMULLB = { 1619, 1},
.VMULLT = { 1620, 1},
.VMLALB = { 1621, 1},
.VMLALT = { 1622, 1},
.VMLSLB = { 1623, 1},
.VMLSLT = { 1624, 1},
.VSHRNB = { 1625, 1},
.VSHRNT = { 1626, 1},
.VRSHRNB = { 1627, 1},
.VRSHRNT = { 1628, 1},
.VQSHRNB = { 1629, 1},
.VQSHRNT = { 1630, 1},
.VQRSHRNB = { 1631, 1},
.VQRSHRNT = { 1632, 1},
.VQSHRUNB = { 1633, 1},
.VQSHRUNT = { 1634, 1},
.VQRSHRUNB = { 1635, 1},
.VQRSHRUNT = { 1636, 1},
.VMOV_Q_R = { 1637, 1},
.VMOV_R_Q = { 1638, 1},
.VMOV_2GPR_Q = { 1639, 1},
.VQDMLADH = { 1640, 1},
.VQDMLADHX = { 1641, 1},
.VQDMLSDH = { 1642, 1},
.VQDMLSDHX = { 1643, 1},
.VQRDMLADH = { 1644, 1},
.VQRDMLADHX = { 1645, 1},
.VQRDMLSDH = { 1646, 1},
.VQRDMLSDHX = { 1647, 1},
.VPRINT = { 1648, 0},
.VHCADD_SAT = { 1648, 0},
.VCMLA_MVE = { 1648, 0},
.VLDRB = { 1648, 1},
.VLDRH = { 1649, 1},
.VLDRW = { 1650, 1},
.VLDRD = { 1651, 1},
.VSTRB = { 1652, 1},
.VSTRH = { 1653, 1},
.VSTRW = { 1654, 1},
.VSTRD = { 1655, 1},
.VLD20 = { 1656, 1},
.VLD21 = { 1657, 1},
.VLD40 = { 1658, 1},
.VLD41 = { 1659, 1},
.VLD42 = { 1660, 1},
.VLD43 = { 1661, 1},
.VST20 = { 1662, 1},
.VST21 = { 1663, 1},
.VST40 = { 1664, 1},
.VST41 = { 1665, 1},
.VST42 = { 1666, 1},
.VST43 = { 1667, 1},
._COUNT = { 1668, 0},
.VMOV_LANE = { 1322, 3},
.VLD1 = { 1325, 8},
.VLD2 = { 1333, 3},
.VLD3 = { 1336, 2},
.VLD4 = { 1338, 2},
.VST1 = { 1340, 7},
.VST2 = { 1347, 3},
.VST3 = { 1350, 2},
.VST4 = { 1352, 2},
.AESE = { 1354, 1},
.AESD = { 1355, 1},
.AESMC = { 1356, 1},
.AESIMC = { 1357, 1},
.SHA1H = { 1358, 1},
.SHA1SU0 = { 1359, 1},
.SHA1SU1 = { 1360, 1},
.SHA1C = { 1361, 1},
.SHA1M = { 1362, 1},
.SHA1P = { 1363, 1},
.SHA256H = { 1364, 1},
.SHA256H2 = { 1365, 1},
.SHA256SU0 = { 1366, 1},
.SHA256SU1 = { 1367, 1},
.VRINT = { 1368, 0},
.VJCVT = { 1368, 1},
.VSDOT = { 1369, 2},
.VUDOT = { 1371, 2},
.VSDOT_LANE = { 1373, 2},
.VUDOT_LANE = { 1375, 2},
.VCVT_BF16 = { 1377, 1},
.VDOT_BF16 = { 1378, 2},
.VFMA_BF16 = { 1380, 1},
.VMMLA_BF16 = { 1381, 1},
.VFMAL = { 1382, 2},
.VFMSL = { 1384, 2},
.VCMLA = { 1386, 2},
.VCADD = { 1388, 2},
.VCMLA_LANE = { 1390, 2},
.VSMMLA = { 1392, 1},
.VUMMLA = { 1393, 1},
.VUSMMLA = { 1394, 1},
.VSUDOT = { 1395, 1},
.VUSDOT = { 1396, 2},
.VSUDOT_LANE = { 1398, 1},
.VUSDOT_LANE = { 1399, 2},
.VMUL_LANE = { 1401, 6},
.VMLA_LANE = { 1407, 6},
.VMLS_LANE = { 1413, 6},
.VMULL_LANE = { 1419, 4},
.VMLAL_LANE = { 1423, 4},
.VMLSL_LANE = { 1427, 4},
.VQDMULL_LANE = { 1431, 2},
.VQDMLAL_LANE = { 1433, 2},
.VQDMLSL_LANE = { 1435, 2},
.VFMA_LANE = { 1437, 2},
.VFMS_LANE = { 1439, 2},
.VQRDMLAH_LANE = { 1441, 4},
.VQRDMLSH_LANE = { 1445, 4},
.VQABS = { 1449, 1},
.VQNEG = { 1450, 1},
.VMOVX = { 1451, 1},
.VINS = { 1452, 1},
.VLDRB_GATHER = { 1453, 1},
.VLDRH_GATHER = { 1454, 1},
.VLDRW_GATHER = { 1455, 1},
.VLDRD_GATHER = { 1456, 1},
.VSTRB_SCATTER = { 1457, 1},
.VSTRH_SCATTER = { 1458, 1},
.VSTRW_SCATTER = { 1459, 1},
.VSTRD_SCATTER = { 1460, 1},
.VCEQ_Z = { 1461, 4},
.VCGE_Z = { 1465, 4},
.VCGT_Z = { 1469, 4},
.VCLE_Z = { 1473, 4},
.VCLT_Z = { 1477, 4},
.VLD2R = { 1481, 1},
.VLD3R = { 1482, 1},
.VLD4R = { 1483, 1},
.VLD1_LANE = { 1484, 3},
.VLD2_LANE = { 1487, 3},
.VLD3_LANE = { 1490, 3},
.VLD4_LANE = { 1493, 3},
.VST1_LANE = { 1496, 3},
.VST2_LANE = { 1499, 3},
.VST3_LANE = { 1502, 3},
.VST4_LANE = { 1505, 3},
.VCVT_FIXED = { 1508, 10},
.IT = { 1518, 1},
.TT = { 1519, 1},
.TTT = { 1520, 1},
.TTA = { 1521, 1},
.TTAT = { 1522, 1},
.SG = { 1523, 1},
.BXNS = { 1524, 1},
.BLXNS = { 1525, 1},
.PAC = { 1526, 1},
.PACBTI = { 1527, 1},
.AUT = { 1528, 1},
.AUTG = { 1529, 1},
.BTI = { 1530, 1},
.WLS = { 1531, 1},
.WLSTP = { 1532, 1},
.DLS = { 1533, 1},
.DLSTP = { 1534, 1},
.LE = { 1535, 1},
.LETP = { 1536, 1},
.LCTP = { 1537, 1},
.BF = { 1538, 0},
.BFI_BR = { 1538, 0},
.BFL = { 1538, 0},
.BFLX = { 1538, 0},
.BFCSEL = { 1538, 0},
.CX1 = { 1538, 1},
.CX1A = { 1539, 1},
.CX1D = { 1540, 1},
.CX1DA = { 1541, 1},
.CX2 = { 1542, 1},
.CX2A = { 1543, 1},
.CX2D = { 1544, 1},
.CX2DA = { 1545, 1},
.CX3 = { 1546, 1},
.CX3A = { 1547, 1},
.CX3D = { 1548, 1},
.CX3DA = { 1549, 1},
.VCX1 = { 1550, 2},
.VCX1A = { 1552, 2},
.VCX2 = { 1554, 2},
.VCX2A = { 1556, 2},
.VCX3 = { 1558, 2},
.VCX3A = { 1560, 2},
.VPT = { 1562, 1},
.VPST = { 1563, 1},
.VPSEL = { 1564, 1},
.VPNOT = { 1565, 1},
.VCTP = { 1566, 1},
.VADDV = { 1567, 1},
.VADDVA = { 1568, 1},
.VADDLV = { 1569, 1},
.VADDLVA = { 1570, 1},
.VMAXV = { 1571, 1},
.VMAXAV = { 1572, 1},
.VMINV = { 1573, 1},
.VMINAV = { 1574, 1},
.VMAXNMV = { 1575, 1},
.VMAXNMAV = { 1576, 1},
.VMINNMV = { 1577, 1},
.VMINNMAV = { 1578, 1},
.VABAV = { 1579, 1},
.VMLADAV = { 1580, 1},
.VMLADAVA = { 1581, 1},
.VMLADAVX = { 1582, 1},
.VMLADAVAX = { 1583, 1},
.VMLALDAV = { 1584, 1},
.VMLALDAVA = { 1585, 1},
.VMLALDAVX = { 1586, 1},
.VMLALDAVAX = { 1587, 1},
.VMLSDAV = { 1588, 1},
.VMLSDAVA = { 1589, 1},
.VMLSDAVX = { 1590, 1},
.VMLSDAVAX = { 1591, 1},
.VMLSLDAV = { 1592, 1},
.VMLSLDAVA = { 1593, 1},
.VMLSLDAVX = { 1594, 1},
.VMLSLDAVAX = { 1595, 1},
.VRMLALDAVH = { 1596, 1},
.VRMLALDAVHA = { 1597, 1},
.VRMLALDAVHX = { 1598, 1},
.VRMLALDAVHAX = { 1599, 1},
.VRMLSLDAVH = { 1600, 1},
.VRMLSLDAVHA = { 1601, 1},
.VRMLSLDAVHX = { 1602, 1},
.VRMLSLDAVHAX = { 1603, 1},
.VMLAV = { 1604, 1},
.VMLAVA = { 1605, 1},
.VMLSV = { 1606, 0},
.VMLSVA = { 1606, 0},
.VCMUL = { 1606, 1},
.VHCADD = { 1607, 1},
.VBRSR = { 1608, 1},
.VSHLC = { 1609, 1},
.VRSHL_MVE = { 1610, 0},
.VDDUP = { 1610, 1},
.VIDUP = { 1611, 1},
.VDWDUP = { 1612, 1},
.VIWDUP = { 1613, 1},
.VMOVNB = { 1614, 1},
.VMOVNT = { 1615, 1},
.VQMOVNB = { 1616, 1},
.VQMOVNT = { 1617, 1},
.VQMOVUNB = { 1618, 1},
.VQMOVUNT = { 1619, 1},
.VSHLLB = { 1620, 1},
.VSHLLT = { 1621, 1},
.VMULLB = { 1622, 1},
.VMULLT = { 1623, 1},
.VMLALB = { 1624, 1},
.VMLALT = { 1625, 1},
.VMLSLB = { 1626, 1},
.VMLSLT = { 1627, 1},
.VSHRNB = { 1628, 1},
.VSHRNT = { 1629, 1},
.VRSHRNB = { 1630, 1},
.VRSHRNT = { 1631, 1},
.VQSHRNB = { 1632, 1},
.VQSHRNT = { 1633, 1},
.VQRSHRNB = { 1634, 1},
.VQRSHRNT = { 1635, 1},
.VQSHRUNB = { 1636, 1},
.VQSHRUNT = { 1637, 1},
.VQRSHRUNB = { 1638, 1},
.VQRSHRUNT = { 1639, 1},
.VMOV_Q_R = { 1640, 1},
.VMOV_R_Q = { 1641, 1},
.VMOV_2GPR_Q = { 1642, 1},
.VQDMLADH = { 1643, 1},
.VQDMLADHX = { 1644, 1},
.VQDMLSDH = { 1645, 1},
.VQDMLSDHX = { 1646, 1},
.VQRDMLADH = { 1647, 1},
.VQRDMLADHX = { 1648, 1},
.VQRDMLSDH = { 1649, 1},
.VQRDMLSDHX = { 1650, 1},
.VPRINT = { 1651, 0},
.VHCADD_SAT = { 1651, 0},
.VCMLA_MVE = { 1651, 0},
.VLDRB = { 1651, 1},
.VLDRH = { 1652, 1},
.VLDRW = { 1653, 1},
.VLDRD = { 1654, 1},
.VSTRB = { 1655, 1},
.VSTRH = { 1656, 1},
.VSTRW = { 1657, 1},
.VSTRD = { 1658, 1},
.VLD20 = { 1659, 1},
.VLD21 = { 1660, 1},
.VLD40 = { 1661, 1},
.VLD41 = { 1662, 1},
.VLD42 = { 1663, 1},
.VLD43 = { 1664, 1},
.VST20 = { 1665, 1},
.VST21 = { 1666, 1},
.VST40 = { 1667, 1},
.VST41 = { 1668, 1},
.VST42 = { 1669, 1},
.VST43 = { 1670, 1},
._COUNT = { 1671, 0},
}

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