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rexcode/arm32: VMOV (ARM core register to scalar) Dd[lane], Rt

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New VMOV_LANE_8/16/32 encodings: Dd at bits 19:16+bit7, lane bits per
element size (.8 = bit21:bit6:bit5 with bit22 size marker; .16 =
bit21:bit6 with bit5 marker; .32 = bit21). Verify round-trips all three
sizes; spot-checked .8 byte-exact incl. max lane; 600 tests green.
This commit is contained in:
Brendan Punsky
2026-06-18 01:34:48 -04:00
committed by Flāvius
parent 5df81b5117
commit 55463b6719
16 changed files with 1066 additions and 1018 deletions
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11
core/rexcode/arm32/decoder.odin
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@@ -341,6 +341,17 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
return op_dpr_lane(Register(REG_DPR | u16(word & 0x7)), u8(lane))
case .NEON_VM_SCALAR32:
return op_dpr_lane(Register(REG_DPR | u16(word & 0xF)), u8((word >> 5) & 1))
case .VMOV_LANE_8, .VMOV_LANE_16, .VMOV_LANE_32:
n := ((word >> 7) & 1) << 4 | ((word >> 16) & 0xF)
lane: u32 = 0
if enc == .VMOV_LANE_8 {
lane = ((word >> 21) & 1) << 2 | ((word >> 6) & 1) << 1 | ((word >> 5) & 1)
} else if enc == .VMOV_LANE_16 {
lane = ((word >> 21) & 1) << 1 | ((word >> 6) & 1)
} else {
lane = (word >> 21) & 1
}
return op_dpr_lane(Register(REG_DPR | u16(n)), u8(lane))
case .VD_Q:
n := (((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)) >> 1
return op_reg(Register(REG_QPR | u16(n)))