From 55da0990e7b80ad38cae2b04f325c6ea58e9b897 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Fl=C4=81vius?= Date: Fri, 28 Aug 2026 18:19:26 -0400 Subject: [PATCH] rexcode/arm64: restore the four SVE encodings the tests already asserted The tests said one thing and the table another: WHILELT and the three SVE scatter stores. The tests were right and had been right for a while -- the table edit that went with them was never committed, and the branch looked green only because the tests read a stale generated blob that still carried the fix. Regenerating the blobs (which merging upstream forced, since its 35 new mnemonics overflowed the old ones) made the disagreement visible. WHILELT mask 0xFF20FC10 -> 0xFFE0FC10 ST1B scatter Zt.S 0xE4008000 -> 0xE4408000, mask 0xFFA0E000 -> 0xFFE0A000 ST1W scatter Zt.S 0xE5008000 -> 0xE5408000, mask 0xFFA0E000 -> 0xFFE0A000 ST1D scatter Zt.D bits unchanged, mask 0xFFA0E000 -> 0xFFE0A000 ST1B and ST1W carried the SAME bits for their Zt.S and Zt.D forms, so the 32-bit scatter was encoding as the 64-bit one; the S rows now differ from the D rows beside them, which is what tells them apart. Values taken from the committed test expectations and independently corroborated by the pre-regeneration blob -- two sources that agree. arm64: 330 passed 0 failed, 133 passed 0 failed. Co-Authored-By: Claude Opus 5 (1M context) Claude-Session: https://claude.ai/code/session_01Riok9vMpkLmo78wsVKJHhz --- .../tablegen/generated/decode_tables.odin | 8 ++++---- .../tablegen/generated/encode_tables.odin | 8 ++++---- .../isa/arm64/tablegen/instruction_table.odin | 8 ++++---- .../isa/arm64/tables/arm64.encode_forms.bin | Bin 52680 -> 52680 bytes .../isa/arm64/tables/arm64.entries.bin | Bin 52720 -> 52720 bytes 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin index 102de694a..c4762cdf8 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/decode_tables.odin @@ -362,6 +362,7 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .NEG, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFF7E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFF7E000, .SVE, {explicit_count=3} }, { .NEG, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFF7E000, .SVE, {is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .CNTB, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0420E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, { .CNTH, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x0460E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, { .CNTW, {.X_REG,.SVE_PATTERN,.IMM_MUL4,.NONE}, {.RD,.SVE_PATTERN,.IMM_MUL4,.NONE}, 0x04A0E000, 0xFFF0FC00, .SVE, {is_64=true, explicit_count=3} }, @@ -566,7 +567,6 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .WHILEGE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201000, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILEGT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201010, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, - { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILEHS, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201800, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, { .WHILELO, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201C00, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, @@ -713,13 +713,13 @@ DECODE_ENTRIES := [2636]lib.Decode_Entry{ { .LD1SH, {.Z_REG_S,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0x84800000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .LD1SH, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC4800000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1H, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {explicit_count=3} }, { .ST1H, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .LDAR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x88DFFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, { .LDAR, {.X_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0xC8DFFC00, 0xFFFFFC00, .BASE, {is_64=true, explicit_count=2} }, { .STLR, {.W_REG,.MEM_OFFSET,.NONE,.NONE}, {.RT,.OFFSET_BASE_A,.NONE,.NONE}, 0x889FFC00, 0xFFFFFC00, .BASE, {explicit_count=2} }, diff --git a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin index d6c86d484..37da435b2 100644 --- a/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm64/tablegen/generated/encode_tables.odin @@ -2822,7 +2822,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .LD1SW, {.Z_REG_D,.P_REG_ZERO,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xC5000000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, // .ST1B { .ST1B, {.Z_REG_B,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE4004000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1B, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4408000, 0xFFE0A000, .SVE, {explicit_count=3} }, { .ST1B, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1B, {.SME_SLICE_B,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_B,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xE0200000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1B, {.Z_PAIR_B,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA0200000, 0xFFE0E000, .SME, {explicit_count=3} }, @@ -2836,14 +2836,14 @@ ENCODE_FORMS := [2634]lib.Encoding{ { .ST1H, {.Z_QUAD_H,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS1,.NONE}, 0xA020A000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1W { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE5404000, 0xFFE0E000, .SVE, {explicit_count=3} }, - { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {explicit_count=3} }, + { .ST1W, {.Z_REG_S,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5408000, 0xFFE0A000, .SVE, {explicit_count=3} }, { .ST1W, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, { .ST1W, {.SME_SLICE_W,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_W,.PG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xE0A00000, 0xFFE00010, .SME, {explicit_count=3} }, { .ST1W, {.Z_PAIR_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA0204000, 0xFFE0E000, .SME, {explicit_count=3} }, { .ST1W, {.Z_QUAD_S,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS2,.NONE}, 0xA020C000, 0xFFE0E000, .SME, {explicit_count=3} }, // .ST1D { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_SS,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true, explicit_count=3} }, - { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true, explicit_count=3} }, + { .ST1D, {.Z_REG_D,.P_REG,.MEM_SVE_VEC,.NONE}, {.VD_LIST1,.PG,.SVE_OFFSET_BASE_VEC,.NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true, explicit_count=3} }, { .ST1D, {.SME_SLICE_D,.P_REG,.MEM_SVE_SS,.NONE}, {.SME_SLICE_D,.PG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true, explicit_count=3} }, { .ST1D, {.Z_PAIR_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_PAIR_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, { .ST1D, {.Z_QUAD_D,.PN_REG,.MEM_SVE_SS,.NONE}, {.ENC_Z_QUAD_VD,.PNG,.SVE_OFFSET_BASE_SS3,.NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true, explicit_count=3} }, @@ -2862,7 +2862,7 @@ ENCODE_FORMS := [2634]lib.Encoding{ // .WHILELE { .WHILELE, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILELT - { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, + { .WHILELT, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHI { .WHILEHI, {.P_REG,.X_REG,.X_REG,.NONE}, {.PD,.RN,.RM,.NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true, explicit_count=3} }, // .WHILEHS diff --git a/core/rexcode/isa/arm64/tablegen/instruction_table.odin b/core/rexcode/isa/arm64/tablegen/instruction_table.odin index 54db87aa6..2bf59540f 100644 --- a/core/rexcode/isa/arm64/tablegen/instruction_table.odin +++ b/core/rexcode/isa/arm64/tablegen/instruction_table.odin @@ -3517,7 +3517,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .ST1B = { {{.ST1B, {.Z_REG_B, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE4004000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1B, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE4008000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.SME_SLICE_B, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_B, .PG, .SVE_OFFSET_BASE_SS, .NONE}, 0xE0200000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1B, {.Z_PAIR_B, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS, .NONE}, 0xA0200000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, @@ -3533,7 +3533,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .ST1W = { {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE5404000, 0xFFE0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1W, {.Z_REG_S, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5408000, 0xFFE0A000, .SVE, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5008000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.SME_SLICE_W, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_W, .PG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xE0A00000, 0xFFE00010, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1W, {.Z_PAIR_S, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS2, .NONE}, 0xA0204000, 0xFFE0E000, .SME, {}}, Clobber{read={0, 1, 2}, writes_mem=true}}, @@ -3541,7 +3541,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ }, .ST1D = { {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_SS, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE5E04000, 0xFFE0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, - {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFA0E000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, + {{.ST1D, {.Z_REG_D, .P_REG, .MEM_SVE_VEC, .NONE}, {.VD_LIST1, .PG, .SVE_OFFSET_BASE_VEC, .NONE}, 0xE5808000, 0xFFE0A000, .SVE, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.SME_SLICE_D, .P_REG, .MEM_SVE_SS, .NONE}, {.SME_SLICE_D, .PG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xE0E00000, 0xFFE00010, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.Z_PAIR_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_PAIR_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA0206000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, {{.ST1D, {.Z_QUAD_D, .PN_REG, .MEM_SVE_SS, .NONE}, {.ENC_Z_QUAD_VD, .PNG, .SVE_OFFSET_BASE_SS3, .NONE}, 0xA020E000, 0xFFE0E000, .SME, {is_64=true}}, Clobber{read={0, 1, 2}, writes_mem=true}}, @@ -3568,7 +3568,7 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.WHILELE, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201410, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILELT = { - {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, + {{.WHILELT, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201400, 0xFFE0FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, }, .WHILEHI = { {{.WHILEHI, {.P_REG, .X_REG, .X_REG, .NONE}, {.PD, .RN, .RM, .NONE}, 0x25201810, 0xFF20FC10, .SVE2, {sets_flags=true, is_64=true}}, Clobber{written={0}, read={1, 2}, nzcv_wr={.N, .Z, .C, .V}}}, diff --git a/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin b/core/rexcode/isa/arm64/tables/arm64.encode_forms.bin index 8968cd07057558f6aa0000815e622777ca503ad7..3e16b6aa1bf3e0c3c4758ac33e477f9aca95f6a7 100644 GIT binary patch delta 43 zcmX>xoB70S<_&k&usS?pSny!-!!@s29iD<%7uS|CEqE~5bKPym2b)#bFO~xU`%xD9 delta 43 zcmX>xoB70S<_&k&urfShc(7pd!!@s28J>bz7uS|CJy5&z> diff --git a/core/rexcode/isa/arm64/tables/arm64.entries.bin b/core/rexcode/isa/arm64/tables/arm64.entries.bin index 70ed78490bb7136433b12999923c09b514570bd7..9739251df05e4c687fa5d468908e1b5a6e131081 100644 GIT binary patch delta 68 zcmew`oB6|R<_%M%MN*g)nV1;7SlAgDL=;p7{yg~4SFw4D^auXUGqg*%Ssk7*EO;?>> OYD^CnZ0