diff --git a/core/rexcode/isa/x86/aliases.odin b/core/rexcode/isa/x86/aliases.odin new file mode 100644 index 000000000..42c8077a4 --- /dev/null +++ b/core/rexcode/isa/x86/aliases.odin @@ -0,0 +1,130 @@ +// rexcode · Brendan Punsky (dotbmp@github), original author + +package rexcode_x86 + +// ============================================================================= +// MNEMONIC ALIASES — which of several names for one encoding a disassembler prints +// ============================================================================= +// +// Some x86 instructions have several legal mnemonics for ONE encoding. SHL and +// SAL are both ModRM.reg=4 in the shift group; JE and JZ are both 0x74; there +// are 57 such pairs. A decoder has nothing to tell them apart with — the bytes +// are identical — so it must simply pick a name, and that choice has to be +// DECLARED. Left undeclared it falls out of wherever the entry happened to land +// in the (unstably sorted) decode table: correct, arbitrary, and free to move on +// any table regeneration. It did move once, and four tests that had always +// passed began reporting `SAL != expected SHL`. +// +// The canonical name here is the one **llvm-mc prints**, measured rather than +// chosen: llvm-mc is the ground truth every verifier in this library diffs +// against, so agreeing with it is what makes a disassembly comparable. Before +// this table, 52 of the 74 aliased encodings decoded to a name llvm-mc does not +// use (`0F 84` → JZ where it says JE, `A4` → MOVS where it says MOVSB, `DB E2` → +// FCLEX where it says FNCLEX). +// +// An alias stays fully ENCODABLE — `inst_r_r(.SAL, …)` emits the same bytes it +// always did. Only the decode direction is narrowed, and only where the +// canonical name covers the byte-identical encoding: that condition is what lets +// MOV be the alias at the `A0`-`A3`/`B8` moffs forms while remaining the only +// name for `88`/`89`. `tablegen/gen.odin` applies it when it collects decode +// entries, so an aliased mnemonic never reaches the decode tables at all. +// +// Adding an instruction whose mnemonic aliases another one's encoding requires a +// row here; `run_alias_table_test` in tests/ recomputes the ambiguity from the +// built tables and fails by name if one is missing, so it cannot be forgotten. + +Mnemonic_Alias :: struct { + alias: Mnemonic, // never produced by the decoder + canonical: Mnemonic, // produced instead, at the byte-identical encoding +} + +@(rodata) +MNEMONIC_ALIASES := [?]Mnemonic_Alias{ + // -- Jcc, both the short 0x7x and near 0x0F 8x forms -------------------- + {.JNAE, .JB}, {.JC, .JB}, + {.JNB, .JAE}, {.JNC, .JAE}, + {.JZ, .JE}, + {.JNZ, .JNE}, + {.JNA, .JBE}, + {.JNBE, .JA}, + {.JPE, .JP}, + {.JPO, .JNP}, + {.JNGE, .JL}, + {.JNL, .JGE}, + {.JNG, .JLE}, + {.JNLE, .JG}, + + // -- CMOVcc (0x0F 4x) --------------------------------------------------- + {.CMOVNAE, .CMOVB}, {.CMOVC, .CMOVB}, + {.CMOVNB, .CMOVAE}, {.CMOVNC, .CMOVAE}, + {.CMOVZ, .CMOVE}, + {.CMOVNZ, .CMOVNE}, + {.CMOVNA, .CMOVBE}, + {.CMOVNBE, .CMOVA}, + {.CMOVPE, .CMOVP}, + {.CMOVPO, .CMOVNP}, + {.CMOVNGE, .CMOVL}, + {.CMOVNL, .CMOVGE}, + {.CMOVNG, .CMOVLE}, + {.CMOVNLE, .CMOVG}, + + // -- SETcc (0x0F 9x) ---------------------------------------------------- + {.SETNAE, .SETB}, {.SETC, .SETB}, + {.SETNB, .SETAE}, {.SETNC, .SETAE}, + {.SETZ, .SETE}, + {.SETNZ, .SETNE}, + {.SETNA, .SETBE}, + {.SETNBE, .SETA}, + {.SETPE, .SETP}, + {.SETPO, .SETNP}, + {.SETNGE, .SETL}, + {.SETNL, .SETGE}, + {.SETNG, .SETLE}, + {.SETNLE, .SETG}, + + // -- Shift group: SAL and SHL are both /4, the same encoding ------------ + {.SAL, .SHL}, + + // -- String ops: the bare name against the explicitly byte-sized one ---- + {.CMPS, .CMPSB}, + {.LODS, .LODSB}, + {.MOVS, .MOVSB}, + {.SCAS, .SCASB}, + {.STOS, .STOSB}, + + // -- x87: the assembler's wait-prefixed spelling of a no-wait opcode ---- + // (FSTENV is really `9B D9 /6`; the table gives it the bare `D9 /6`, which + // is FNSTENV. Modelling the 9B prefix is a separate question — until then + // the bare encoding decodes as the no-wait name, which is what it is.) + {.FCLEX, .FNCLEX}, + {.FINIT, .FNINIT}, + {.FSAVE, .FNSAVE}, + {.FSTCW, .FNSTCW}, + {.FSTENV, .FNSTENV}, + {.FSTSW, .FNSTSW}, + + // -- Odds -------------------------------------------------------------- + {.FWAIT, .WAIT}, + {.XLAT, .XLATB}, + // MOV aliases MOVABS only at the moffs (`A0`-`A3`) and imm64 (`B8+r`) + // forms; the coverage rule leaves every other MOV encoding untouched. + {.MOV, .MOVABS}, +} + +// The name a disassembler prints for `m`'s encoding — `m` itself unless it is a +// declared alias. Useful to an assembler front-end that accepts either spelling +// and wants to compare against decoder output. +canonical_mnemonic :: proc "contextless" (m: Mnemonic) -> Mnemonic { + for entry in MNEMONIC_ALIASES { + if entry.alias == m { return entry.canonical } + } + return m +} + +// Is `m` a name the decoder never produces? +is_mnemonic_alias :: proc "contextless" (m: Mnemonic) -> bool { + for entry in MNEMONIC_ALIASES { + if entry.alias == m { return true } + } + return false +} diff --git a/core/rexcode/isa/x86/decoder.odin b/core/rexcode/isa/x86/decoder.odin index e883944ab..69127337f 100644 --- a/core/rexcode/isa/x86/decoder.odin +++ b/core/rexcode/isa/x86/decoder.odin @@ -565,6 +565,21 @@ decode_opcode :: proc(state: ^Decoder_State) -> (entry: ^Decode_Entry, vex_entry } if !has_modrm_byte { + // ADDRESS-size variants first: a form declaring one is picked by which + // address size is in effect (mode default vs 67h), an axis the operand- + // size scan below cannot see -- it reads REX.W and 66h, and neither + // affects address size. 0xE3 is the case: JRCXZ/JECXZ/JCXZ are one + // opcode telling RCX/ECX/CX apart, and nothing else in the bytes says + // which. Checked before the operand-size pass so a REX.W-prefixed E3 + // (legal, and ignored by the CPU for address size) still reads as JRCXZ. + addr_want := effective_addr_size(state.mode, state.prefix_67) + for i in 0.. FS, // 0F A8/A9 -> GS), so a form only matches when the user's segment agrees -- // otherwise `push gs` would take the first {SREG} form (FS) and mis-encode. diff --git a/core/rexcode/isa/x86/encoding_types.odin b/core/rexcode/isa/x86/encoding_types.odin index d4958d284..c756f65c7 100644 --- a/core/rexcode/isa/x86/encoding_types.odin +++ b/core/rexcode/isa/x86/encoding_types.odin @@ -241,6 +241,48 @@ VEX_L :: enum u8 { L2, // L = 2 (512-bit, EVEX only) } +/* + The ADDRESS size a form requires -- a different axis from operand size (66h / + REX.W), selected by 67h against the mode's default: 64-bit in long mode and + 32-bit under 67h; 32-bit in protected mode and 16-bit under 67h. + + Almost every instruction is DEFAULT (it works at whatever address size is in + effect). It matters where address size picks the MNEMONIC: 0xE3 is JRCXZ, + JECXZ or JCXZ purely by which counter register it tests, and nothing else in + the encoding says which. Modelling that as REX.W (which does not affect + address size at all) made `48 E3 cb` the encoding of JRCXZ, where the correct + one is a bare `E3 cb`, and left the decoder unable to tell the three apart. +*/ +Addr_Size :: enum u8 { + DEFAULT, // whatever the mode/prefix selects; the form does not care + A16, // 16-bit addressing (CX) + A32, // 32-bit addressing (ECX) + A64, // 64-bit addressing (RCX); long mode only +} + +// The address size in effect for `mode` with/without a 67h override. +effective_addr_size :: #force_inline proc "contextless" (mode: Mode, prefix_67: bool) -> Addr_Size { + if mode == ._64 { + return prefix_67 ? .A32 : .A64 + } + return prefix_67 ? .A16 : .A32 +} + +// Does reaching `want` in `mode` require a 67h prefix, and is it reachable at all? +addr_size_prefix :: #force_inline proc "contextless" (want: Addr_Size, mode: Mode) -> (prefix_67: bool, ok: bool) { + if want == .DEFAULT { + return false, true + } + if want == effective_addr_size(mode, false) { + return false, true + } + if want == effective_addr_size(mode, true) { + return true, true + } + // e.g. JCXZ (A16) in long mode: 67h there gives 32-bit, never 16-bit. + return false, false +} + // ----------------------------------------------------------------------------- // SECTION: 6.5 Encoding Flags // ----------------------------------------------------------------------------- @@ -259,6 +301,7 @@ Encoding_Flags :: bit_field u32 { rep_ok: bool | 1, // REP prefix valid modrm_reg_ext: bool | 1, // ModR/M reg field is opcode extension (use ext field) mode_32_only: bool | 1, // only valid in Mode._32 (e.g. short-form INC/DEC at 0x40-0x4F) + addr_size: Addr_Size | 2, // required ADDRESS size (67h axis); selects JCXZ/JECXZ/JRCXZ explicit_count: u8 | 3, // 0..<4 non-implicit operands has_implicit: bool | 1, // any implicit operand @@ -302,8 +345,9 @@ encoding_flags :: #force_inline proc "contextless" ( no_rex: bool = false, lock_ok: bool = false, rep_ok: bool = false, - modrm_reg_ext: bool = false, - mode_32_only: bool = false, + modrm_reg_ext: bool = false, + mode_32_only: bool = false, + addr_size: Addr_Size = .DEFAULT, ) -> Encoding_Flags { return Encoding_Flags{ esc = esc, @@ -319,6 +363,7 @@ encoding_flags :: #force_inline proc "contextless" ( rep_ok = rep_ok, modrm_reg_ext = modrm_reg_ext, mode_32_only = mode_32_only, + addr_size = addr_size, } } diff --git a/core/rexcode/isa/x86/tablegen/gen.odin b/core/rexcode/isa/x86/tablegen/gen.odin index 41346c4ff..7b8b47275 100644 --- a/core/rexcode/isa/x86/tablegen/gen.odin +++ b/core/rexcode/isa/x86/tablegen/gen.odin @@ -267,6 +267,9 @@ emit_decode_tables :: proc() -> (n_legacy, n_vex, n_evex: int) { } } } + drop_aliased(&legacy) + drop_aliased(&vex) + drop_aliased(&evex) slice.sort_by(legacy[:], entry_less) slice.sort_by(vex[:], entry_less) slice.sort_by(evex[:], entry_less) @@ -290,6 +293,73 @@ emit_decode_tables :: proc() -> (n_legacy, n_vex, n_evex: int) { return len(legacy), len(vex), len(evex) } +/* + Several mnemonics can name ONE encoding (SHL and SAL are both /4 in the shift + group; JE and JZ are both 0x74). The decoder reads bytes, so it cannot tell + them apart and must simply print one name -- which means the choice has to be + declared, or it falls out of wherever the entry lands in the sort below. + + lib.MNEMONIC_ALIASES declares it. An alias entry is dropped here, before the + tables are written, so the name never reaches the decoder at all; it stays + fully encodable, since ENCODE_FORMS is built from the same table separately. + + The drop is CONDITIONAL on the canonical name covering the byte-identical + encoding. That is what keeps the rule safe for a mnemonic that is an alias at + one opcode and the only name at another: MOV aliases MOVABS at the `A0`-`A3` + moffs and `B8+r` imm64 forms, and dropping it unconditionally would leave + `88`/`89` -- ordinary register MOV -- with no decode entry at all. +*/ +drop_aliased :: proc(entries: ^[dynamic]Collected_Entry) { + Key :: struct { + esc: lib.Escape, + prefix: u8, + opcode: u8, + ext: u8, + ops: [4]lib.Operand_Type, + enc: [4]lib.Operand_Encoding, + flags: lib.Encoding_Flags, + vex_w: lib.VEX_W, + vex_l: lib.VEX_L, + } + key_of :: proc(e: Collected_Entry) -> Key { + return Key{e.esc, e.prefix, e.opcode, e.ext, e.ops, e.enc, e.flags, e.vex_w, e.vex_l} + } + /* Which mnemonics each indistinguishable encoding is spelled by. */ + names := make(map[Key][dynamic]lib.Mnemonic) + defer { + for _, list in names { delete(list) } + delete(names) + } + for e in entries { + key := key_of(e) + list, present := &names[key] + if !present { + names[key] = make([dynamic]lib.Mnemonic) + list = &names[key] + } + append(list, e.mnemonic) + } + + kept := 0 + for e in entries { + drop := false + for entry in lib.MNEMONIC_ALIASES { + if entry.alias != e.mnemonic { continue } + for spelling in names[key_of(e)] { + if spelling == entry.canonical { + drop = true + break + } + } + if drop { break } + } + if drop { continue } + entries[kept] = e + kept += 1 + } + resize(entries, kept) +} + entry_less :: proc(a, b: Collected_Entry) -> bool { if a.esc != b.esc { return int(a.esc) < int(b.esc) } if a.prefix != b.prefix { return a.prefix < b.prefix } @@ -470,6 +540,12 @@ write_flags :: proc(sb: ^strings.Builder, enc: union{lib.Encoding, Collected_Ent if flags.rep_ok { append(&parts, "rep_ok=true") } if flags.modrm_reg_ext { append(&parts, "modrm_reg_ext=true") } if flags.mode_32_only { append(&parts, "mode_32_only=true") } + if flags.addr_size != .DEFAULT { append(&parts, fmt.tprintf("addr_size=.%v", flags.addr_size)) } + /* EVERY Encoding_Flags field must be listed above. This enumerates the + struct by hand, so a field added there and forgotten here is silently + dropped from the generated tables -- the flag reads back as its zero value + and the instruction is quietly mis-modelled, with nothing to see in the + diff but its absence. `addr_size` was added and did exactly that. */ switch e in enc { case lib.Encoding: diff --git a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin index 7dec7ce02..9e62a84bb 100644 --- a/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/decode_tables.odin @@ -144,27 +144,27 @@ SIB_TABLE := [256]lib.SIB_Info{ } @(rodata) -LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ +LEGACY_DECODE_ENTRIES := [1231]lib.Decode_Entry{ {.NONE, 0, 0x00, 0xFF, .ADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x01, 0xFF, .ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x01, 0xFF, .ADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x01, 0xFF, .ADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x02, 0xFF, .ADD, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x03, 0xFF, .ADD, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x04, 0xFF, .ADD, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x05, 0xFF, .ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x05, 0xFF, .ADD, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x05, 0xFF, .ADD, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x08, 0xFF, .OR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x09, 0xFF, .OR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x09, 0xFF, .OR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x09, 0xFF, .OR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0A, 0xFF, .OR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0B, 0xFF, .OR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x0B, 0xFF, .OR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x0C, 0xFF, .OR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x0D, 0xFF, .OR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x0D, 0xFF, .OR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, @@ -182,115 +182,101 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0x15, 0xFF, .ADC, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x15, 0xFF, .ADC, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x18, 0xFF, .SBB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x19, 0xFF, .SBB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x19, 0xFF, .SBB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1A, 0xFF, .SBB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x1B, 0xFF, .SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x1B, 0xFF, .SBB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1B, 0xFF, .SBB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x1C, 0xFF, .SBB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x1D, 0xFF, .SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x1D, 0xFF, .SBB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x1D, 0xFF, .SBB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x20, 0xFF, .AND, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x21, 0xFF, .AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x21, 0xFF, .AND, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x21, 0xFF, .AND, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x22, 0xFF, .AND, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x23, 0xFF, .AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x23, 0xFF, .AND, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x23, 0xFF, .AND, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x23, 0xFF, .AND, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x24, 0xFF, .AND, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0x25, 0xFF, .AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x25, 0xFF, .AND, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x25, 0xFF, .AND, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x25, 0xFF, .AND, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x28, 0xFF, .SUB, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x29, 0xFF, .SUB, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2A, 0xFF, .SUB, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2B, 0xFF, .SUB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2B, 0xFF, .SUB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x2B, 0xFF, .SUB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x2C, 0xFF, .SUB, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x2D, 0xFF, .SUB, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x30, 0xFF, .XOR, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x31, 0xFF, .XOR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x31, 0xFF, .XOR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x31, 0xFF, .XOR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x32, 0xFF, .XOR, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x33, 0xFF, .XOR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x34, 0xFF, .XOR, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x35, 0xFF, .XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x35, 0xFF, .XOR, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x35, 0xFF, .XOR, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x35, 0xFF, .XOR, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x38, 0xFF, .CMP, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x39, 0xFF, .CMP, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x39, 0xFF, .CMP, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3A, 0xFF, .CMP, {.R8, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3B, 0xFF, .CMP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x3B, 0xFF, .CMP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x3C, 0xFF, .CMP, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, + {.NONE, 0, 0x3D, 0xFF, .CMP, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x3D, 0xFF, .CMP, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0x40, 0xFF, .INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x40, 0xFF, .INC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, + {.NONE, 0, 0x40, 0xFF, .INC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x48, 0xFF, .DEC, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, {.NONE, 0, 0x48, 0xFF, .DEC, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {mode_32_only=true, op_count=1}}, - {.NONE, 0, 0x50, 0xFF, .PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x50, 0xFF, .PUSH, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, - {.NONE, 0, 0x58, 0xFF, .POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, + {.NONE, 0, 0x50, 0xFF, .PUSH, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x58, 0xFF, .POP, {.R16, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x58, 0xFF, .POP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {default_64=true, op_count=1}}, {.NONE, 0, 0x62, 0xFF, .BOUND, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {mode_32_only=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x62, 0xFF, .BOUND, {.R16, .M16_16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {mode_32_only=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x63, 0xFF, .MOVSXD, {.R64, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x63, 0xFF, .ARPL, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x68, 0xFF, .PUSH, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x69, 0xFF, .IMUL, {.R32, .RM32, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x69, 0xFF, .IMUL, {.R16, .RM16, .IMM16, .NONE}, {.REG, .MR, .IW, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x69, 0xFF, .IMUL, {.R64, .RM64, .IMM32, .NONE}, {.REG, .MR, .ID, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6A, 0xFF, .PUSH, {.IMM8SX, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R16, .RM16, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R64, .RM64, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {force_rex_w=true, op_count=3, needs_modrm=true}}, - {.NONE, 0, 0x6B, 0xFF, .IMUL, {.R32, .RM32, .IMM8SX, .NONE}, {.REG, .MR, .IB, .NONE}, {op_count=3, needs_modrm=true}}, {.NONE, 0, 0x70, 0xFF, .JO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x71, 0xFF, .JNO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x72, 0xFF, .JNAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x72, 0xFF, .JC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x72, 0xFF, .JB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x73, 0xFF, .JAE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x73, 0xFF, .JNB, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x73, 0xFF, .JNC, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x74, 0xFF, .JE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x74, 0xFF, .JZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x75, 0xFF, .JNZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x75, 0xFF, .JNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x76, 0xFF, .JBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x76, 0xFF, .JNA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x77, 0xFF, .JNBE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x77, 0xFF, .JA, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x78, 0xFF, .JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x79, 0xFF, .JNS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7A, 0xFF, .JPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7A, 0xFF, .JP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7B, 0xFF, .JNP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7B, 0xFF, .JPO, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7C, 0xFF, .JNGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7C, 0xFF, .JL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7D, 0xFF, .JNL, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7D, 0xFF, .JGE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7E, 0xFF, .JLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7E, 0xFF, .JNG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0x7F, 0xFF, .JNLE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x7F, 0xFF, .JG, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0x80, 0x00, .ADD, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x80, 0x01, .OR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -301,60 +287,60 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0x80, 0x06, .XOR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x80, 0x07, .CMP, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x00, .ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x00, .ADD, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x00, .ADD, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x01, .OR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x01, .OR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x02, .ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x02, .ADC, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x02, .ADC, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x03, .SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x03, .SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x03, .SBB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x03, .SBB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x03, .SBB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x04, .AND, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x05, .SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x05, .SUB, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x05, .SUB, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x06, .XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x06, .XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x06, .XOR, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x06, .XOR, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x06, .XOR, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x81, 0x07, .CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x07, .CMP, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x81, 0x07, .CMP, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x81, 0x07, .CMP, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x00, .ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x00, .ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x00, .ADD, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x00, .ADD, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x00, .ADD, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x01, .OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x01, .OR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x01, .OR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x01, .OR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x02, .ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x02, .ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x02, .ADC, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x03, .SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x03, .SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x02, .ADC, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x02, .ADC, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x03, .SBB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x04, .AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x03, .SBB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x03, .SBB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x04, .AND, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x04, .AND, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x04, .AND, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x05, .SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x05, .SUB, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x05, .SUB, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x83, 0x06, .XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x06, .XOR, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x83, 0x06, .XOR, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x06, .XOR, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM32, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM64, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x83, 0x07, .CMP, {.RM16, .IMM8SX, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x84, 0xFF, .TEST, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x85, 0xFF, .TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x85, 0xFF, .TEST, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x85, 0xFF, .TEST, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x85, 0xFF, .TEST, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x86, 0xFF, .XCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x87, 0xFF, .XCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x88, 0xFF, .MOV, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x89, 0xFF, .MOV, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, @@ -369,71 +355,57 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0x8D, 0xFF, .LEA, {.R64, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0x8D, 0xFF, .LEA, {.R16, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x8D, 0xFF, .LEA, {.R32, .M, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {force_rex_w=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0x8F, 0x00, .POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0x8E, 0xFF, .MOV, {.SREG, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {op_count=2, needs_modrm=true}}, {.NONE, 0, 0x8F, 0x00, .POP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0x8F, 0x00, .POP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.EAX_IMPL, .R32, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.AX_IMPL, .R16, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0x90, 0xFF, .XCHG, {.RAX_IMPL, .R64, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0x90, 0xFF, .NOP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x98, 0xFF, .CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x98, 0xFF, .CDQE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0x98, 0xFF, .CBW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, - {.NONE, 0, 0x98, 0xFF, .CWDE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x99, 0xFF, .CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0x99, 0xFF, .CDQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x99, 0xFF, .CWD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, - {.NONE, 0, 0x99, 0xFF, .CQO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0x9B, 0xFF, .WAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0x9B, 0xFF, .FWAIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9C, 0xFF, .PUSHFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, - {.NONE, 0, 0x9C, 0xFF, .PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9C, 0xFF, .PUSHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, - {.NONE, 0, 0x9D, 0xFF, .POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0x9C, 0xFF, .PUSHFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9D, 0xFF, .POPFQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {default_64=true}}, + {.NONE, 0, 0x9D, 0xFF, .POPFD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9D, 0xFF, .POPF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0x9E, 0xFF, .SAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0x9F, 0xFF, .LAHF, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xA0, 0xFF, .MOVABS, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA0, 0xFF, .MOV, {.AL_IMPL, .MOFFS8, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA1, 0xFF, .MOVABS, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0xA1, 0xFF, .MOV, {.EAX_IMPL, .MOFFS32, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA1, 0xFF, .MOV, {.AX_IMPL, .MOFFS16, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA1, 0xFF, .MOV, {.RAX_IMPL, .MOFFS64, .NONE, .NONE}, {.IMPL, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xA2, 0xFF, .MOVABS, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA2, 0xFF, .MOV, {.MOFFS8, .AL_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS32, .EAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA3, 0xFF, .MOV, {.MOFFS64, .RAX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0xA4, 0xFF, .MOVS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA3, 0xFF, .MOVABS, {.MOFFS16, .AX_IMPL, .NONE, .NONE}, {.IQ, .IMPL, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA4, 0xFF, .MOVSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xA5, 0xFF, .MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA5, 0xFF, .MOVSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA5, 0xFF, .MOVSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xA6, 0xFF, .CMPSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xA6, 0xFF, .CMPS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, - {.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA7, 0xFF, .CMPSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA7, 0xFF, .CMPSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xA8, 0xFF, .TEST, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.AX_IMPL, .IMM16, .NONE, .NONE}, {.IMPL, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xA9, 0xFF, .TEST, {.RAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, - {.NONE, 0, 0xAA, 0xFF, .STOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xA9, 0xFF, .TEST, {.EAX_IMPL, .IMM32, .NONE, .NONE}, {.IMPL, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xAA, 0xFF, .STOSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAB, 0xFF, .STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAB, 0xFF, .STOSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, {.NONE, 0, 0xAB, 0xFF, .STOSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAC, 0xFF, .LODSB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAC, 0xFF, .LODS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, - {.NONE, 0, 0xAD, 0xFF, .LODSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAD, 0xFF, .LODSW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, - {.NONE, 0, 0xAE, 0xFF, .SCAS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, + {.NONE, 0, 0xAD, 0xFF, .LODSQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true, rep_ok=true}}, {.NONE, 0, 0xAE, 0xFF, .SCASB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {rep_ok=true}}, {.NONE, 0, 0xAF, 0xFF, .SCASW, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true, rep_ok=true}}, @@ -442,119 +414,105 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xB8, 0xFF, .MOVABS, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOV, {.R32, .IMM32, .NONE, .NONE}, {.OP_R, .ID, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xB8, 0xFF, .MOV, {.R16, .IMM16, .NONE, .NONE}, {.OP_R, .IW, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xB8, 0xFF, .MOV, {.R64, .IMM64, .NONE, .NONE}, {.OP_R, .IQ, .NONE, .NONE}, {force_rex_w=true, op_count=2}}, {.NONE, 0, 0xC0, 0x00, .ROL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x01, .ROR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x02, .RCL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x03, .RCR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x04, .SHL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC0, 0x04, .SAL, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x05, .SHR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC0, 0x07, .SAR, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x00, .ROL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x01, .ROR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x01, .ROR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x02, .RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x02, .RCL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x02, .RCL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x03, .RCR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x03, .RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x03, .RCR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x04, .SAL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x04, .SAL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x04, .SAL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x04, .SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x04, .SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x03, .RCR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x04, .SHL, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x04, .SHL, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x04, .SHL, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x05, .SHR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x05, .SHR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x05, .SHR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC1, 0x07, .SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x07, .SAR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC1, 0x07, .SAR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC1, 0x07, .SAR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC2, 0xFF, .RET, {.IMM16, .NONE, .NONE, .NONE}, {.IW, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xC3, 0xFF, .RET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xC6, 0x00, .MOV, {.RM8, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xC7, 0x00, .MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC7, 0x00, .MOV, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC7, 0x00, .MOV, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xC7, 0x00, .MOV, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xC8, 0xFF, .ENTER, {.IMM16, .IMM8, .NONE, .NONE}, {.IW, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xC9, 0xFF, .LEAVE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCC, 0xFF, .INT3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xCD, 0xFF, .INT, {.IMM8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xCE, 0xFF, .INTO, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xCF, 0xFF, .IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0xCF, 0xFF, .IRETD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xCF, 0xFF, .IRET, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {opsize_16=true}}, {.NONE, 0, 0xCF, 0xFF, .IRETQ, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {force_rex_w=true}}, {.NONE, 0, 0xD0, 0x00, .ROL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x01, .ROR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x02, .RCL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x03, .RCR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x04, .SHL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD0, 0x04, .SAL, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x05, .SHR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD0, 0x07, .SAR, {.RM8, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x00, .ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x00, .ROL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x00, .ROL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x01, .ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x01, .ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x00, .ROL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x01, .ROR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x01, .ROR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x01, .ROR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x02, .RCL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x02, .RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x02, .RCL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x03, .RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x03, .RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x02, .RCL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x03, .RCR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x04, .SAL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x04, .SAL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x04, .SAL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x04, .SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x03, .RCR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x03, .RCR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x04, .SHL, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x04, .SHL, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x04, .SHL, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x05, .SHR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x05, .SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x05, .SHR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x07, .SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD1, 0x07, .SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x05, .SHR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD1, 0x07, .SAR, {.RM32, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x07, .SAR, {.RM16, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD1, 0x07, .SAR, {.RM64, .ONE_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x00, .ROL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x01, .ROR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x02, .RCL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x03, .RCR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD2, 0x04, .SAL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x04, .SHL, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x05, .SHR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD2, 0x07, .SAR, {.RM8, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x00, .ROL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x00, .ROL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x00, .ROL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x01, .ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x01, .ROR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x01, .ROR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x01, .ROR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x02, .RCL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x02, .RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x02, .RCL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x02, .RCL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x03, .RCR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x03, .RCR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x03, .RCR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x04, .SAL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x04, .SAL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x04, .SAL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x04, .SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x04, .SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x04, .SHL, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x04, .SHL, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x04, .SHL, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x05, .SHR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x05, .SHR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x05, .SHR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xD3, 0x07, .SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x07, .SAR, {.RM32, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD3, 0x07, .SAR, {.RM16, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xD3, 0x07, .SAR, {.RM64, .CL_IMPL, .NONE, .NONE}, {.MR, .IMPL, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xD7, 0xFF, .XLATB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD7, 0xFF, .XLAT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD8, 0x01, .FMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD8, 0x02, .FCOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD8, 0x03, .FCOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -578,8 +536,6 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0x04, .FLDENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x05, .FLDCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x06, .FNSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xD9, 0x06, .FSTENV, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xD9, 0x07, .FSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0x07, .FNSTCW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0xC0, .FLD, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xD9, 0xC8, .FXCH, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -611,8 +567,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xD9, 0xFC, .FRNDINT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFD, .FSCALE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xD9, 0xFE, .FSIN, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xD9, 0xFF, .FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, {.NONE, 0, 0xD9, 0xFF, .FCOS, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, + {.NONE, 0, 0xD9, 0xFF, .FLD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x01, .FIMUL, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x02, .FICOM, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDA, 0x03, .FICOMP, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -635,10 +591,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xDB, 0xC8, .FCMOVNE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xD0, .FCMOVNBE, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xD8, .FCMOVNU, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xDB, 0xE2, .FCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE2, .FNCLEX, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE3, .FNINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, - {.NONE, 0, 0xDB, 0xE3, .FINIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xDB, 0xE8, .FUCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xF0, .FCOMI, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDB, 0xFF, .FILD, {.M32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, @@ -661,8 +615,6 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xDD, 0x03, .FSTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x04, .FRSTOR, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x06, .FNSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xDD, 0x06, .FSAVE, {.M, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xDD, 0x07, .FSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0x07, .FNSTSW, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDD, 0xC0, .FFREE, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDD, 0xD0, .FST, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -702,22 +654,21 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xDF, 0x07, .FISTP, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xDF, 0xC0, .FFREEP, {.STI, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDF, 0xE0, .FNSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0xDF, 0xE0, .FSTSW, {.AX_IMPL, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xDF, 0xE8, .FUCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDF, 0xF0, .FCOMIP, {.ST0_IMPL, .STI, .NONE, .NONE}, {.IMPL, .OP_R, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xDF, 0xFF, .FILD, {.M16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {op_count=1, needs_modrm=true}}, {.NONE, 0, 0xE0, 0xFF, .LOOPNE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xE1, 0xFF, .LOOPE, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xE2, 0xFF, .LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0xE3, 0xFF, .JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {force_rex_w=true, op_count=1}}, - {.NONE, 0, 0xE3, 0xFF, .JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, - {.NONE, 0, 0xE3, 0xFF, .JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, + {.NONE, 0, 0xE3, 0xFF, .JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {addr_size=.A64, op_count=1}}, + {.NONE, 0, 0xE3, 0xFF, .JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {addr_size=.A16, op_count=1}}, + {.NONE, 0, 0xE3, 0xFF, .JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {addr_size=.A32, op_count=1}}, {.NONE, 0, 0xE4, 0xFF, .IN, {.AL_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xE5, 0xFF, .IN, {.EAX_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {op_count=2}}, {.NONE, 0, 0xE5, 0xFF, .IN, {.AX_IMPL, .IMM8, .NONE, .NONE}, {.IMPL, .IB, .NONE, .NONE}, {opsize_16=true, op_count=2}}, {.NONE, 0, 0xE6, 0xFF, .OUT, {.IMM8, .AL_IMPL, .NONE, .NONE}, {.IB, .IMPL, .NONE, .NONE}, {op_count=2}}, - {.NONE, 0, 0xE7, 0xFF, .OUT, {.IMM8, .AX_IMPL, .NONE, .NONE}, {.IB, .IMPL, .NONE, .NONE}, {opsize_16=true, op_count=2}}, {.NONE, 0, 0xE7, 0xFF, .OUT, {.IMM8, .EAX_IMPL, .NONE, .NONE}, {.IB, .IMPL, .NONE, .NONE}, {op_count=2}}, + {.NONE, 0, 0xE7, 0xFF, .OUT, {.IMM8, .AX_IMPL, .NONE, .NONE}, {.IB, .IMPL, .NONE, .NONE}, {opsize_16=true, op_count=2}}, {.NONE, 0, 0xE8, 0xFF, .CALL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xE9, 0xFF, .JMP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {op_count=1}}, {.NONE, 0, 0xEB, 0xFF, .JMP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, {op_count=1}}, @@ -737,18 +688,18 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xF6, 0x05, .IMUL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF6, 0x06, .DIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF6, 0x07, .IDIV, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xF7, 0x00, .TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x00, .TEST, {.RM32, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x00, .TEST, {.RM16, .IMM16, .NONE, .NONE}, {.MR, .IW, .NONE, .NONE}, {modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x00, .TEST, {.RM64, .IMM32, .NONE, .NONE}, {.MR, .ID, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {.NONE, 0, 0xF7, 0x02, .NOT, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xF7, 0x02, .NOT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x02, .NOT, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xF7, 0x03, .NEG, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x02, .NOT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x02, .NOT, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x03, .NEG, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x03, .NEG, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xF7, 0x04, .MUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x03, .NEG, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x04, .MUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x04, .MUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xF7, 0x04, .MUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xF7, 0x05, .IMUL, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -766,16 +717,16 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xFD, 0xFF, .STD, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {}}, {.NONE, 0, 0xFE, 0x00, .INC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFE, 0x01, .DEC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xFF, 0x00, .INC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xFF, 0x00, .INC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x00, .INC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x00, .INC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x00, .INC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x01, .DEC, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x01, .DEC, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x01, .DEC, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x02, .CALL, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {.NONE, 0, 0xFF, 0x03, .CALL, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x04, .JMP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {default_64=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 0, 0xFF, 0x05, .JMP, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -784,11 +735,11 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {.NONE, 0, 0xFF, 0x06, .PUSH, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {.NONE, 2, 0x90, 0xFF, .PAUSE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {prefix=2}}, {._0F, 0, 0x00, 0x00, .SLDT, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x00, .SLDT, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x00, .SLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x01, .STR, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x00, 0x01, .STR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x02, .LLDT, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x03, .LTR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x00, 0x04, .VERR, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -797,8 +748,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0x01, 0x00, .SGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x01, .SIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x01, .SIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x01, 0x02, .LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x02, .LGDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x01, 0x02, .LGDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x03, .LIDT, {.M16_64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x03, .LIDT, {.M16_32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x01, 0x04, .SMSW, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -842,8 +793,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0x01, 0xFE, .INVLPGB, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x01, 0xFF, .TLBSYNC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x02, 0xFF, .LAR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x02, 0xFF, .LAR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x02, 0xFF, .LAR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x03, 0xFF, .LSL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -857,22 +808,22 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0x0D, 0x01, .PREFETCHW, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x10, 0xFF, .MOVUPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x11, 0xFF, .MOVUPS, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x12, 0xFF, .MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x12, 0xFF, .MOVHLPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x12, 0xFF, .MOVLPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x13, 0xFF, .MOVLPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x14, 0xFF, .UNPCKLPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x15, 0xFF, .UNPCKHPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x16, 0xFF, .MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x16, 0xFF, .MOVLHPS, {.XMM, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x16, 0xFF, .MOVHPS, {.XMM, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x17, 0xFF, .MOVHPS, {.M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x18, 0x00, .PREFETCHNTA, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x18, 0x01, .PREFETCHT0, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x18, 0x02, .PREFETCHT1, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x18, 0x03, .PREFETCHT2, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1C, 0x00, .CLDEMOTE, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x1F, 0x00, .NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x1F, 0x00, .NOP, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x1F, 0x00, .NOP, {.RM16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0x1F, 0x00, .NOP, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0x20, 0xFF, .MOV, {.R64, .CR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x21, 0xFF, .MOV, {.R64, .DR, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x22, 0xFF, .MOV, {.CR, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -888,96 +839,54 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0x33, 0xFF, .RDPMC, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x34, 0xFF, .SYSENTER, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0x35, 0xFF, .SYSEXIT, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0x40, 0xFF, .CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x40, 0xFF, .CMOVO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x40, 0xFF, .CMOVO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x40, 0xFF, .CMOVO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x41, 0xFF, .CMOVNO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVNAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x42, 0xFF, .CMOVB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x42, 0xFF, .CMOVC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNC, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVNB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVB, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x42, 0xFF, .CMOVB, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x43, 0xFF, .CMOVAE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x44, 0xFF, .CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x44, 0xFF, .CMOVE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x44, 0xFF, .CMOVE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x44, 0xFF, .CMOVE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x44, 0xFF, .CMOVZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x45, 0xFF, .CMOVNZ, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x45, 0xFF, .CMOVNE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x46, 0xFF, .CMOVNA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x46, 0xFF, .CMOVBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVNBE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x47, 0xFF, .CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x47, 0xFF, .CMOVA, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x47, 0xFF, .CMOVA, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x47, 0xFF, .CMOVA, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x48, 0xFF, .CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x48, 0xFF, .CMOVS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x48, 0xFF, .CMOVS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x48, 0xFF, .CMOVS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVPE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x49, 0xFF, .CMOVNS, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVPO, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4A, 0xFF, .CMOVP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVNGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4B, 0xFF, .CMOVNP, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4C, 0xFF, .CMOVL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVNL, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVNG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4D, 0xFF, .CMOVGE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4F, 0xFF, .CMOVNLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4E, 0xFF, .CMOVLE, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0x4F, 0xFF, .CMOVG, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R64, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0x50, 0xFF, .MOVMSKPS, {.R32, .XMM, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x51, 0xFF, .SQRTPS, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -1004,88 +913,60 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0x7F, 0xFF, .MOVQ, {.MM_M64, .MM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0x80, 0xFF, .JO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x81, 0xFF, .JNO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x82, 0xFF, .JC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x82, 0xFF, .JB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x82, 0xFF, .JNAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x83, 0xFF, .JNC, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x83, 0xFF, .JNB, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x83, 0xFF, .JAE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x84, 0xFF, .JZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x84, 0xFF, .JE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x85, 0xFF, .JNZ, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x85, 0xFF, .JNE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x86, 0xFF, .JBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x86, 0xFF, .JNA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x87, 0xFF, .JNBE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x87, 0xFF, .JA, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x88, 0xFF, .JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x89, 0xFF, .JNS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8A, 0xFF, .JP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8A, 0xFF, .JPE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8B, 0xFF, .JPO, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8B, 0xFF, .JNP, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8C, 0xFF, .JNGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8C, 0xFF, .JL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8D, 0xFF, .JNL, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8D, 0xFF, .JGE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8E, 0xFF, .JNG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8E, 0xFF, .JLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, - {._0F, 0, 0x8F, 0xFF, .JNLE, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x8F, 0xFF, .JG, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0x90, 0xFF, .SETO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x91, 0xFF, .SETNO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x92, 0xFF, .SETNAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x92, 0xFF, .SETC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x92, 0xFF, .SETB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x93, 0xFF, .SETNC, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x93, 0xFF, .SETNB, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x93, 0xFF, .SETAE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x94, 0xFF, .SETZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x94, 0xFF, .SETE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x95, 0xFF, .SETNZ, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x95, 0xFF, .SETNE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x96, 0xFF, .SETNA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x96, 0xFF, .SETBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x97, 0xFF, .SETNBE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x97, 0xFF, .SETA, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x98, 0xFF, .SETS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x99, 0xFF, .SETNS, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9A, 0xFF, .SETPE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9A, 0xFF, .SETP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9B, 0xFF, .SETPO, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9B, 0xFF, .SETNP, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9C, 0xFF, .SETNGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9C, 0xFF, .SETL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9D, 0xFF, .SETNL, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9D, 0xFF, .SETGE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9E, 0xFF, .SETNG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9E, 0xFF, .SETLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, - {._0F, 0, 0x9F, 0xFF, .SETNLE, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0x9F, 0xFF, .SETG, {.RM8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1, needs_modrm=true}}, {._0F, 0, 0xA0, 0xFF, .PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xA1, 0xFF, .POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xA2, 0xFF, .CPUID, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0xA3, 0xFF, .BT, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xA3, 0xFF, .BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xA3, 0xFF, .BT, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xA3, 0xFF, .BT, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA4, 0xFF, .SHLD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xA5, 0xFF, .SHLD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xA8, 0xFF, .PUSH, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xA9, 0xFF, .POP, {.SREG, .NONE, .NONE, .NONE}, {.IMPL, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xAA, 0xFF, .RSM, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, - {._0F, 0, 0xAB, 0xFF, .BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xAB, 0xFF, .BTS, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xAB, 0xFF, .BTS, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAB, 0xFF, .BTS, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM64, .R64, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM16, .R16, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAC, 0xFF, .SHRD, {.RM32, .R32, .IMM8, .NONE}, {.MR, .REG, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, + {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM16, .R16, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM32, .R32, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xAD, 0xFF, .SHRD, {.RM64, .R64, .CL_IMPL, .NONE}, {.MR, .REG, .IMPL, .NONE}, {esc=._0F, force_rex_w=true, op_count=3, needs_modrm=true}}, {._0F, 0, 0xAE, 0x00, .FXSAVE, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x00, .FXSAVE64, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x01, .FXRSTOR, {.M512, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -1094,8 +975,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0xAE, 0x04, .XSAVE64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x05, .XRSTOR, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x05, .XRSTOR64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xAE, 0x06, .XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x06, .XSAVEOPT64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xAE, 0x06, .XSAVEOPT, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0x07, .CLFLUSH, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xAE, 0xE8, .LFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, {._0F, 0, 0xAE, 0xF0, .MFENCE, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F}}, @@ -1105,65 +986,65 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 0, 0xAF, 0xFF, .IMUL, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB0, 0xFF, .CMPXCHG, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xB3, 0xFF, .BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB1, 0xFF, .CMPXCHG, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB3, 0xFF, .BTR, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB3, 0xFF, .BTR, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB3, 0xFF, .BTR, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xB6, 0xFF, .MOVZX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB7, 0xFF, .MOVZX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB7, 0xFF, .MOVZX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xB9, 0xFF, .UD1, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBA, 0x04, .BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x04, .BT, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x04, .BT, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x04, .BT, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x05, .BTS, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x05, .BTS, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x05, .BTS, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBA, 0x06, .BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBA, 0x06, .BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x06, .BTR, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x06, .BTR, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x06, .BTR, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x07, .BTC, {.RM64, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBA, 0x07, .BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBA, 0x07, .BTC, {.RM16, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBB, 0xFF, .BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBA, 0x07, .BTC, {.RM32, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBB, 0xFF, .BTC, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBB, 0xFF, .BTC, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBB, 0xFF, .BTC, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBC, 0xFF, .BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBC, 0xFF, .BSF, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBC, 0xFF, .BSF, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBC, 0xFF, .BSF, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBD, 0xFF, .BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBD, 0xFF, .BSR, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBD, 0xFF, .BSR, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBD, 0xFF, .BSR, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R16, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBE, 0xFF, .MOVSX, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R64, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xBF, 0xFF, .MOVSX, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC0, 0xFF, .XADD, {.RM8, .R8, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, + {._0F, 0, 0xC1, 0xFF, .XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC1, 0xFF, .XADD, {.RM64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC1, 0xFF, .XADD, {.RM16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, - {._0F, 0, 0xC1, 0xFF, .XADD, {.RM32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, lock_ok=true, op_count=2, needs_modrm=true}}, {._0F, 0, 0xC2, 0xFF, .CMPPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, {._0F, 0, 0xC6, 0xFF, .SHUFPS, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, op_count=3, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x01, .CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x01, .CMPXCHG16B, {.M128, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x03, .XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x01, .CMPXCHG8B, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, lock_ok=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x03, .XRSTORS, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x04, .XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x03, .XRSTORS64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x04, .XSAVEC, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x05, .XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x04, .XSAVEC64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x05, .XSAVES64, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x05, .XSAVES, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .VMPTRLD, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .RDRAND, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .RDRAND, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x06, .RDRAND, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x07, .RDSEED, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 0, 0xC7, 0x07, .RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x07, .RDSEED, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC7, 0x07, .VMPTRST, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 0, 0xC7, 0x07, .RDSEED, {.R16, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R64, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, force_rex_w=true, op_count=1}}, {._0F, 0, 0xC8, 0xFF, .BSWAP, {.R32, .NONE, .NONE, .NONE}, {.OP_R, .NONE, .NONE, .NONE}, {esc=._0F, op_count=1}}, {._0F, 0, 0xFF, 0xFF, .UD0, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, op_count=2, needs_modrm=true}}, @@ -1209,8 +1090,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 1, 0x6B, 0xFF, .PACKSSDW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6C, 0xFF, .PUNPCKLQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6D, 0xFF, .PUNPCKHQDQ, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x6E, 0xFF, .MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6E, 0xFF, .MOVD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x6E, 0xFF, .MOVQ, {.XMM, .R64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x6F, 0xFF, .MOVDQA, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x70, 0xFF, .PSHUFD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0x71, 0x02, .PSRLW, {.XMM, .IMM8, .NONE, .NONE}, {.MR, .IB, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=2, needs_modrm=true}}, @@ -1226,8 +1107,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 1, 0x76, 0xFF, .PCMPEQD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7C, 0xFF, .HADDPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7D, 0xFF, .HSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, - {._0F, 1, 0x7E, 0xFF, .MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7E, 0xFF, .MOVD, {.RM32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, + {._0F, 1, 0x7E, 0xFF, .MOVQ, {.R64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 1, 0x7F, 0xFF, .MOVDQA, {.XMM_M128, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, {._0F, 1, 0xAE, 0x06, .TPAUSE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 1, 0xAE, 0x06, .CLWB, {.M8, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -1235,8 +1116,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 1, 0xC2, 0xFF, .CMPPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .M16, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC4, 0xFF, .PINSRW, {.XMM, .R32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, - {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R64, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, force_rex_w=true, op_count=3, needs_modrm=true}}, + {._0F, 1, 0xC5, 0xFF, .PEXTRW, {.R32, .XMM, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC6, 0xFF, .SHUFPD, {.XMM, .XMM_M128, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=1, op_count=3, needs_modrm=true}}, {._0F, 1, 0xC7, 0x06, .VMCLEAR, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=1, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 1, 0xD0, 0xFF, .ADDSUBPD, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=1, op_count=2, needs_modrm=true}}, @@ -1297,16 +1178,16 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 2, 0x11, 0xFF, .MOVSS, {.XMM_M32, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x12, 0xFF, .MOVSLDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x16, 0xFF, .MOVSHDUP, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0x1E, 0x01, .RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0x1E, 0x01, .RDSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0x1E, 0x01, .RDSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0x1E, 0xFA, .ENDBR64, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, {._0F, 2, 0x1E, 0xFB, .ENDBR32, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2}}, - {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2A, 0xFF, .CVTSI2SS, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2C, 0xFF, .CVTTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R32, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0x2D, 0xFF, .CVTSS2SI, {.R64, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0x51, 0xFF, .SQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x52, 0xFF, .RSQRTSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0x53, 0xFF, .RCPSS, {.XMM, .XMM_M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, @@ -1326,25 +1207,25 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 2, 0xAE, 0x00, .RDFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x01, .RDGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x01, .RDGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 2, 0xAE, 0x02, .WRFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x02, .WRFSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x02, .WRFSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x03, .WRGSBASE, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x03, .WRGSBASE, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x04, .PTWRITE, {.RM32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x04, .PTWRITE, {.RM64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, - {._0F, 2, 0xAE, 0x05, .INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x05, .INCSSPQ, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, + {._0F, 2, 0xAE, 0x05, .INCSSPD, {.R32, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x06, .UMONITOR, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xAE, 0x06, .CLRSSBSY, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0xB8, 0xFF, .POPCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBC, 0xFF, .TZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, + {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R16, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, op_count=2, needs_modrm=true}}, - {._0F, 2, 0xBD, 0xFF, .LZCNT, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 2, 0xC2, 0xFF, .CMPSS, {.XMM, .XMM_M32, .IMM8, .NONE}, {.REG, .MR, .IB, .NONE}, {esc=._0F, prefix=2, op_count=3, needs_modrm=true}}, {._0F, 2, 0xC7, 0x06, .VMXON, {.M64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, {._0F, 2, 0xC7, 0x07, .RDPID, {.R64, .NONE, .NONE, .NONE}, {.MR, .NONE, .NONE, .NONE}, {esc=._0F, prefix=2, modrm_reg_ext=true, op_count=1, needs_modrm=true}}, @@ -1354,8 +1235,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F, 3, 0x10, 0xFF, .MOVSD, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x11, 0xFF, .MOVSD, {.XMM_M64, .XMM, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x12, 0xFF, .MOVDDUP, {.XMM, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, - {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, + {._0F, 3, 0x2A, 0xFF, .CVTSI2SD, {.XMM, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2C, 0xFF, .CVTTSD2SI, {.R64, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F, 3, 0x2D, 0xFF, .CVTSD2SI, {.R32, .XMM_M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F, prefix=3, op_count=2, needs_modrm=true}}, @@ -1385,9 +1266,9 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R64, .M64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R16, .M16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF0, 0xFF, .MOVBE, {.R32, .M32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, - {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M16, .R16, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, + {._0F38, 0, 0xF1, 0xFF, .MOVBE, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF6, 0xFF, .WRSSD, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF6, 0xFF, .WRSSQ, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 0, 0xF9, 0xFF, .MOVDIRI, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, op_count=2, needs_modrm=true}}, @@ -1442,8 +1323,8 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F38, 1, 0x41, 0xFF, .PHMINPOSUW, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x80, 0xFF, .INVEPT, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x81, 0xFF, .INVVPID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, - {._0F38, 1, 0x82, 0xFF, .INVPCID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0x82, 0xFF, .INVPCID, {.R32, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, + {._0F38, 1, 0x82, 0xFF, .INVPCID, {.R64, .M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xDB, 0xFF, .AESIMC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xDC, 0xFF, .AESENC, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, {._0F38, 1, 0xDD, 0xFF, .AESENCLAST, {.XMM, .XMM_M128, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=1, op_count=2, needs_modrm=true}}, @@ -1463,9 +1344,9 @@ LEGACY_DECODE_ENTRIES := [1350]lib.Decode_Entry{ {._0F38, 2, 0xFC, 0xFF, .AXOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=2, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R32, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF0, 0xFF, .CRC32, {.R64, .RM8, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, - {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM32, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R32, .RM16, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, + {._0F38, 3, 0xF1, 0xFF, .CRC32, {.R64, .RM64, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xF8, 0xFF, .ENQCMD, {.R64, .M512, .NONE, .NONE}, {.REG, .MR, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xFC, 0xFF, .AOR, {.M64, .R64, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=3, force_rex_w=true, op_count=2, needs_modrm=true}}, {._0F38, 3, 0xFC, 0xFF, .AOR, {.M32, .R32, .NONE, .NONE}, {.MR, .REG, .NONE, .NONE}, {esc=._0F38, prefix=3, op_count=2, needs_modrm=true}}, @@ -2696,119 +2577,119 @@ DECODE_INDEX_LEGACY := [4][256]lib.Decode_Index{ 0x6B = { 114, 3}, 0x70 = { 117, 1}, 0x71 = { 118, 1}, - 0x72 = { 119, 3}, - 0x73 = { 122, 3}, - 0x74 = { 125, 2}, - 0x75 = { 127, 2}, - 0x76 = { 129, 2}, - 0x77 = { 131, 2}, - 0x78 = { 133, 1}, - 0x79 = { 134, 1}, - 0x7A = { 135, 2}, - 0x7B = { 137, 2}, - 0x7C = { 139, 2}, - 0x7D = { 141, 2}, - 0x7E = { 143, 2}, - 0x7F = { 145, 2}, - 0x80 = { 147, 8}, - 0x81 = { 155, 24}, - 0x83 = { 179, 24}, - 0x84 = { 203, 1}, - 0x85 = { 204, 3}, - 0x86 = { 207, 1}, - 0x87 = { 208, 3}, - 0x88 = { 211, 1}, - 0x89 = { 212, 3}, - 0x8A = { 215, 1}, - 0x8B = { 216, 3}, - 0x8C = { 219, 2}, - 0x8D = { 221, 3}, - 0x8E = { 224, 2}, - 0x8F = { 226, 2}, - 0x90 = { 228, 4}, - 0x98 = { 232, 3}, - 0x99 = { 235, 3}, - 0x9B = { 238, 2}, - 0x9C = { 240, 3}, - 0x9D = { 243, 3}, - 0x9E = { 246, 1}, - 0x9F = { 247, 1}, - 0xA0 = { 248, 2}, - 0xA1 = { 250, 6}, - 0xA2 = { 256, 2}, - 0xA3 = { 258, 6}, - 0xA4 = { 264, 2}, - 0xA5 = { 266, 3}, - 0xA6 = { 269, 2}, - 0xA7 = { 271, 3}, - 0xA8 = { 274, 1}, - 0xA9 = { 275, 3}, - 0xAA = { 278, 2}, - 0xAB = { 280, 3}, - 0xAC = { 283, 2}, - 0xAD = { 285, 3}, - 0xAE = { 288, 2}, - 0xAF = { 290, 3}, - 0xB0 = { 293, 1}, - 0xB8 = { 294, 4}, - 0xC0 = { 298, 8}, - 0xC1 = { 306, 24}, - 0xC2 = { 330, 1}, - 0xC3 = { 331, 1}, - 0xC6 = { 332, 1}, - 0xC7 = { 333, 3}, - 0xC8 = { 336, 1}, - 0xC9 = { 337, 1}, - 0xCC = { 338, 1}, - 0xCD = { 339, 1}, - 0xCE = { 340, 1}, - 0xCF = { 341, 3}, - 0xD0 = { 344, 8}, - 0xD1 = { 352, 24}, - 0xD2 = { 376, 8}, - 0xD3 = { 384, 24}, - 0xD7 = { 408, 2}, - 0xD8 = { 410, 18}, - 0xD9 = { 428, 40}, - 0xDA = { 468, 13}, - 0xDB = { 481, 16}, - 0xDC = { 497, 14}, - 0xDD = { 511, 16}, - 0xDE = { 527, 21}, - 0xDF = { 548, 13}, - 0xE0 = { 561, 1}, - 0xE1 = { 562, 1}, - 0xE2 = { 563, 1}, - 0xE3 = { 564, 3}, - 0xE4 = { 567, 1}, - 0xE5 = { 568, 2}, - 0xE6 = { 570, 1}, - 0xE7 = { 571, 2}, - 0xE8 = { 573, 1}, - 0xE9 = { 574, 1}, - 0xEB = { 575, 1}, - 0xEC = { 576, 1}, - 0xED = { 577, 2}, - 0xEE = { 579, 1}, - 0xEF = { 580, 2}, - 0xF0 = { 582, 1}, - 0xF4 = { 583, 1}, - 0xF5 = { 584, 1}, - 0xF6 = { 585, 7}, - 0xF7 = { 592, 21}, - 0xF8 = { 613, 1}, - 0xF9 = { 614, 1}, - 0xFA = { 615, 1}, - 0xFB = { 616, 1}, - 0xFC = { 617, 1}, - 0xFD = { 618, 1}, - 0xFE = { 619, 2}, - 0xFF = { 621, 16}, + 0x72 = { 119, 1}, + 0x73 = { 120, 1}, + 0x74 = { 121, 1}, + 0x75 = { 122, 1}, + 0x76 = { 123, 1}, + 0x77 = { 124, 1}, + 0x78 = { 125, 1}, + 0x79 = { 126, 1}, + 0x7A = { 127, 1}, + 0x7B = { 128, 1}, + 0x7C = { 129, 1}, + 0x7D = { 130, 1}, + 0x7E = { 131, 1}, + 0x7F = { 132, 1}, + 0x80 = { 133, 8}, + 0x81 = { 141, 24}, + 0x83 = { 165, 24}, + 0x84 = { 189, 1}, + 0x85 = { 190, 3}, + 0x86 = { 193, 1}, + 0x87 = { 194, 3}, + 0x88 = { 197, 1}, + 0x89 = { 198, 3}, + 0x8A = { 201, 1}, + 0x8B = { 202, 3}, + 0x8C = { 205, 2}, + 0x8D = { 207, 3}, + 0x8E = { 210, 2}, + 0x8F = { 212, 2}, + 0x90 = { 214, 4}, + 0x98 = { 218, 3}, + 0x99 = { 221, 3}, + 0x9B = { 224, 1}, + 0x9C = { 225, 3}, + 0x9D = { 228, 3}, + 0x9E = { 231, 1}, + 0x9F = { 232, 1}, + 0xA0 = { 233, 1}, + 0xA1 = { 234, 3}, + 0xA2 = { 237, 1}, + 0xA3 = { 238, 3}, + 0xA4 = { 241, 1}, + 0xA5 = { 242, 3}, + 0xA6 = { 245, 1}, + 0xA7 = { 246, 3}, + 0xA8 = { 249, 1}, + 0xA9 = { 250, 3}, + 0xAA = { 253, 1}, + 0xAB = { 254, 3}, + 0xAC = { 257, 1}, + 0xAD = { 258, 3}, + 0xAE = { 261, 1}, + 0xAF = { 262, 3}, + 0xB0 = { 265, 1}, + 0xB8 = { 266, 3}, + 0xC0 = { 269, 7}, + 0xC1 = { 276, 21}, + 0xC2 = { 297, 1}, + 0xC3 = { 298, 1}, + 0xC6 = { 299, 1}, + 0xC7 = { 300, 3}, + 0xC8 = { 303, 1}, + 0xC9 = { 304, 1}, + 0xCC = { 305, 1}, + 0xCD = { 306, 1}, + 0xCE = { 307, 1}, + 0xCF = { 308, 3}, + 0xD0 = { 311, 7}, + 0xD1 = { 318, 21}, + 0xD2 = { 339, 7}, + 0xD3 = { 346, 21}, + 0xD7 = { 367, 1}, + 0xD8 = { 368, 18}, + 0xD9 = { 386, 38}, + 0xDA = { 424, 13}, + 0xDB = { 437, 14}, + 0xDC = { 451, 14}, + 0xDD = { 465, 14}, + 0xDE = { 479, 21}, + 0xDF = { 500, 12}, + 0xE0 = { 512, 1}, + 0xE1 = { 513, 1}, + 0xE2 = { 514, 1}, + 0xE3 = { 515, 3}, + 0xE4 = { 518, 1}, + 0xE5 = { 519, 2}, + 0xE6 = { 521, 1}, + 0xE7 = { 522, 2}, + 0xE8 = { 524, 1}, + 0xE9 = { 525, 1}, + 0xEB = { 526, 1}, + 0xEC = { 527, 1}, + 0xED = { 528, 2}, + 0xEE = { 530, 1}, + 0xEF = { 531, 2}, + 0xF0 = { 533, 1}, + 0xF4 = { 534, 1}, + 0xF5 = { 535, 1}, + 0xF6 = { 536, 7}, + 0xF7 = { 543, 21}, + 0xF8 = { 564, 1}, + 0xF9 = { 565, 1}, + 0xFA = { 566, 1}, + 0xFB = { 567, 1}, + 0xFC = { 568, 1}, + 0xFD = { 569, 1}, + 0xFE = { 570, 2}, + 0xFF = { 572, 16}, }, { // prefix = 66 }, { // prefix = F3 - 0x90 = { 637, 1}, + 0x90 = { 588, 1}, }, { // prefix = F2 }, @@ -2817,434 +2698,434 @@ DECODE_INDEX_LEGACY := [4][256]lib.Decode_Index{ @(rodata) DECODE_INDEX_ESC_0F := [4][256]lib.Decode_Index{ { // prefix = none - 0x00 = { 638, 10}, - 0x01 = { 648, 48}, - 0x02 = { 696, 3}, - 0x03 = { 699, 3}, - 0x05 = { 702, 1}, - 0x06 = { 703, 1}, - 0x07 = { 704, 1}, - 0x08 = { 705, 1}, - 0x09 = { 706, 1}, - 0x0B = { 707, 1}, - 0x0D = { 708, 2}, - 0x10 = { 710, 1}, - 0x11 = { 711, 1}, - 0x12 = { 712, 2}, - 0x13 = { 714, 1}, - 0x14 = { 715, 1}, - 0x15 = { 716, 1}, - 0x16 = { 717, 2}, - 0x17 = { 719, 1}, - 0x18 = { 720, 4}, - 0x1C = { 724, 1}, - 0x1F = { 725, 3}, - 0x20 = { 728, 1}, - 0x21 = { 729, 1}, - 0x22 = { 730, 1}, - 0x23 = { 731, 1}, - 0x28 = { 732, 1}, - 0x29 = { 733, 1}, - 0x2B = { 734, 1}, - 0x2E = { 735, 1}, - 0x2F = { 736, 1}, - 0x30 = { 737, 1}, - 0x31 = { 738, 1}, - 0x32 = { 739, 1}, - 0x33 = { 740, 1}, - 0x34 = { 741, 1}, - 0x35 = { 742, 1}, - 0x40 = { 743, 3}, - 0x41 = { 746, 3}, - 0x42 = { 749, 9}, - 0x43 = { 758, 9}, - 0x44 = { 767, 6}, - 0x45 = { 773, 6}, - 0x46 = { 779, 6}, - 0x47 = { 785, 6}, - 0x48 = { 791, 3}, - 0x49 = { 794, 3}, - 0x4A = { 797, 6}, - 0x4B = { 803, 6}, - 0x4C = { 809, 6}, - 0x4D = { 815, 6}, - 0x4E = { 821, 6}, - 0x4F = { 827, 6}, - 0x50 = { 833, 2}, - 0x51 = { 835, 1}, - 0x52 = { 836, 1}, - 0x53 = { 837, 1}, - 0x54 = { 838, 1}, - 0x55 = { 839, 1}, - 0x56 = { 840, 1}, - 0x57 = { 841, 1}, - 0x58 = { 842, 1}, - 0x59 = { 843, 1}, - 0x5A = { 844, 1}, - 0x5B = { 845, 1}, - 0x5C = { 846, 1}, - 0x5D = { 847, 1}, - 0x5E = { 848, 1}, - 0x5F = { 849, 1}, - 0x6E = { 850, 1}, - 0x6F = { 851, 1}, - 0x70 = { 852, 1}, - 0x78 = { 853, 1}, - 0x79 = { 854, 1}, - 0x7E = { 855, 1}, - 0x7F = { 856, 1}, - 0x80 = { 857, 1}, - 0x81 = { 858, 1}, - 0x82 = { 859, 3}, - 0x83 = { 862, 3}, - 0x84 = { 865, 2}, - 0x85 = { 867, 2}, - 0x86 = { 869, 2}, - 0x87 = { 871, 2}, - 0x88 = { 873, 1}, - 0x89 = { 874, 1}, - 0x8A = { 875, 2}, - 0x8B = { 877, 2}, - 0x8C = { 879, 2}, - 0x8D = { 881, 2}, - 0x8E = { 883, 2}, - 0x8F = { 885, 2}, - 0x90 = { 887, 1}, - 0x91 = { 888, 1}, - 0x92 = { 889, 3}, - 0x93 = { 892, 3}, - 0x94 = { 895, 2}, - 0x95 = { 897, 2}, - 0x96 = { 899, 2}, - 0x97 = { 901, 2}, - 0x98 = { 903, 1}, - 0x99 = { 904, 1}, - 0x9A = { 905, 2}, - 0x9B = { 907, 2}, - 0x9C = { 909, 2}, - 0x9D = { 911, 2}, - 0x9E = { 913, 2}, - 0x9F = { 915, 2}, - 0xA0 = { 917, 1}, - 0xA1 = { 918, 1}, - 0xA2 = { 919, 1}, - 0xA3 = { 920, 3}, - 0xA4 = { 923, 3}, - 0xA5 = { 926, 3}, - 0xA8 = { 929, 1}, - 0xA9 = { 930, 1}, - 0xAA = { 931, 1}, - 0xAB = { 932, 3}, - 0xAC = { 935, 3}, - 0xAD = { 938, 3}, - 0xAE = { 941, 14}, - 0xAF = { 955, 3}, - 0xB0 = { 958, 1}, - 0xB1 = { 959, 3}, - 0xB3 = { 962, 3}, - 0xB6 = { 965, 3}, - 0xB7 = { 968, 2}, - 0xB9 = { 970, 1}, - 0xBA = { 971, 12}, - 0xBB = { 983, 3}, - 0xBC = { 986, 3}, - 0xBD = { 989, 3}, - 0xBE = { 992, 3}, - 0xBF = { 995, 2}, - 0xC0 = { 997, 1}, - 0xC1 = { 998, 3}, - 0xC2 = {1001, 1}, - 0xC6 = {1002, 1}, - 0xC7 = {1003, 16}, - 0xC8 = {1019, 2}, - 0xFF = {1021, 1}, + 0x00 = { 589, 10}, + 0x01 = { 599, 48}, + 0x02 = { 647, 3}, + 0x03 = { 650, 3}, + 0x05 = { 653, 1}, + 0x06 = { 654, 1}, + 0x07 = { 655, 1}, + 0x08 = { 656, 1}, + 0x09 = { 657, 1}, + 0x0B = { 658, 1}, + 0x0D = { 659, 2}, + 0x10 = { 661, 1}, + 0x11 = { 662, 1}, + 0x12 = { 663, 2}, + 0x13 = { 665, 1}, + 0x14 = { 666, 1}, + 0x15 = { 667, 1}, + 0x16 = { 668, 2}, + 0x17 = { 670, 1}, + 0x18 = { 671, 4}, + 0x1C = { 675, 1}, + 0x1F = { 676, 3}, + 0x20 = { 679, 1}, + 0x21 = { 680, 1}, + 0x22 = { 681, 1}, + 0x23 = { 682, 1}, + 0x28 = { 683, 1}, + 0x29 = { 684, 1}, + 0x2B = { 685, 1}, + 0x2E = { 686, 1}, + 0x2F = { 687, 1}, + 0x30 = { 688, 1}, + 0x31 = { 689, 1}, + 0x32 = { 690, 1}, + 0x33 = { 691, 1}, + 0x34 = { 692, 1}, + 0x35 = { 693, 1}, + 0x40 = { 694, 3}, + 0x41 = { 697, 3}, + 0x42 = { 700, 3}, + 0x43 = { 703, 3}, + 0x44 = { 706, 3}, + 0x45 = { 709, 3}, + 0x46 = { 712, 3}, + 0x47 = { 715, 3}, + 0x48 = { 718, 3}, + 0x49 = { 721, 3}, + 0x4A = { 724, 3}, + 0x4B = { 727, 3}, + 0x4C = { 730, 3}, + 0x4D = { 733, 3}, + 0x4E = { 736, 3}, + 0x4F = { 739, 3}, + 0x50 = { 742, 2}, + 0x51 = { 744, 1}, + 0x52 = { 745, 1}, + 0x53 = { 746, 1}, + 0x54 = { 747, 1}, + 0x55 = { 748, 1}, + 0x56 = { 749, 1}, + 0x57 = { 750, 1}, + 0x58 = { 751, 1}, + 0x59 = { 752, 1}, + 0x5A = { 753, 1}, + 0x5B = { 754, 1}, + 0x5C = { 755, 1}, + 0x5D = { 756, 1}, + 0x5E = { 757, 1}, + 0x5F = { 758, 1}, + 0x6E = { 759, 1}, + 0x6F = { 760, 1}, + 0x70 = { 761, 1}, + 0x78 = { 762, 1}, + 0x79 = { 763, 1}, + 0x7E = { 764, 1}, + 0x7F = { 765, 1}, + 0x80 = { 766, 1}, + 0x81 = { 767, 1}, + 0x82 = { 768, 1}, + 0x83 = { 769, 1}, + 0x84 = { 770, 1}, + 0x85 = { 771, 1}, + 0x86 = { 772, 1}, + 0x87 = { 773, 1}, + 0x88 = { 774, 1}, + 0x89 = { 775, 1}, + 0x8A = { 776, 1}, + 0x8B = { 777, 1}, + 0x8C = { 778, 1}, + 0x8D = { 779, 1}, + 0x8E = { 780, 1}, + 0x8F = { 781, 1}, + 0x90 = { 782, 1}, + 0x91 = { 783, 1}, + 0x92 = { 784, 1}, + 0x93 = { 785, 1}, + 0x94 = { 786, 1}, + 0x95 = { 787, 1}, + 0x96 = { 788, 1}, + 0x97 = { 789, 1}, + 0x98 = { 790, 1}, + 0x99 = { 791, 1}, + 0x9A = { 792, 1}, + 0x9B = { 793, 1}, + 0x9C = { 794, 1}, + 0x9D = { 795, 1}, + 0x9E = { 796, 1}, + 0x9F = { 797, 1}, + 0xA0 = { 798, 1}, + 0xA1 = { 799, 1}, + 0xA2 = { 800, 1}, + 0xA3 = { 801, 3}, + 0xA4 = { 804, 3}, + 0xA5 = { 807, 3}, + 0xA8 = { 810, 1}, + 0xA9 = { 811, 1}, + 0xAA = { 812, 1}, + 0xAB = { 813, 3}, + 0xAC = { 816, 3}, + 0xAD = { 819, 3}, + 0xAE = { 822, 14}, + 0xAF = { 836, 3}, + 0xB0 = { 839, 1}, + 0xB1 = { 840, 3}, + 0xB3 = { 843, 3}, + 0xB6 = { 846, 3}, + 0xB7 = { 849, 2}, + 0xB9 = { 851, 1}, + 0xBA = { 852, 12}, + 0xBB = { 864, 3}, + 0xBC = { 867, 3}, + 0xBD = { 870, 3}, + 0xBE = { 873, 3}, + 0xBF = { 876, 2}, + 0xC0 = { 878, 1}, + 0xC1 = { 879, 3}, + 0xC2 = { 882, 1}, + 0xC6 = { 883, 1}, + 0xC7 = { 884, 16}, + 0xC8 = { 900, 2}, + 0xFF = { 902, 1}, }, { // prefix = 66 - 0x10 = {1022, 1}, - 0x11 = {1023, 1}, - 0x12 = {1024, 1}, - 0x13 = {1025, 1}, - 0x14 = {1026, 1}, - 0x15 = {1027, 1}, - 0x16 = {1028, 1}, - 0x17 = {1029, 1}, - 0x28 = {1030, 1}, - 0x29 = {1031, 1}, - 0x2B = {1032, 1}, - 0x2E = {1033, 1}, - 0x2F = {1034, 1}, - 0x50 = {1035, 2}, - 0x51 = {1037, 1}, - 0x54 = {1038, 1}, - 0x55 = {1039, 1}, - 0x56 = {1040, 1}, - 0x57 = {1041, 1}, - 0x58 = {1042, 1}, - 0x59 = {1043, 1}, - 0x5A = {1044, 1}, - 0x5B = {1045, 1}, - 0x5C = {1046, 1}, - 0x5D = {1047, 1}, - 0x5E = {1048, 1}, - 0x5F = {1049, 1}, - 0x60 = {1050, 1}, - 0x61 = {1051, 1}, - 0x62 = {1052, 1}, - 0x63 = {1053, 1}, - 0x64 = {1054, 1}, - 0x65 = {1055, 1}, - 0x66 = {1056, 1}, - 0x67 = {1057, 1}, - 0x68 = {1058, 1}, - 0x69 = {1059, 1}, - 0x6A = {1060, 1}, - 0x6B = {1061, 1}, - 0x6C = {1062, 1}, - 0x6D = {1063, 1}, - 0x6E = {1064, 2}, - 0x6F = {1066, 1}, - 0x70 = {1067, 1}, - 0x71 = {1068, 3}, - 0x72 = {1071, 3}, - 0x73 = {1074, 2}, - 0x74 = {1076, 1}, - 0x75 = {1077, 1}, - 0x76 = {1078, 1}, - 0x7C = {1079, 1}, - 0x7D = {1080, 1}, - 0x7E = {1081, 2}, - 0x7F = {1083, 1}, - 0xAE = {1084, 3}, - 0xC2 = {1087, 1}, - 0xC4 = {1088, 2}, - 0xC5 = {1090, 2}, - 0xC6 = {1092, 1}, - 0xC7 = {1093, 1}, - 0xD0 = {1094, 1}, - 0xD1 = {1095, 1}, - 0xD2 = {1096, 1}, - 0xD3 = {1097, 1}, - 0xD4 = {1098, 1}, - 0xD5 = {1099, 1}, - 0xD6 = {1100, 1}, - 0xD7 = {1101, 2}, - 0xD8 = {1103, 1}, - 0xD9 = {1104, 1}, - 0xDA = {1105, 1}, - 0xDB = {1106, 1}, - 0xDC = {1107, 1}, - 0xDD = {1108, 1}, - 0xDE = {1109, 1}, - 0xDF = {1110, 1}, - 0xE0 = {1111, 1}, - 0xE1 = {1112, 1}, - 0xE2 = {1113, 1}, - 0xE3 = {1114, 1}, - 0xE4 = {1115, 1}, - 0xE5 = {1116, 1}, - 0xE6 = {1117, 1}, - 0xE7 = {1118, 1}, - 0xE8 = {1119, 1}, - 0xE9 = {1120, 1}, - 0xEA = {1121, 1}, - 0xEB = {1122, 1}, - 0xEC = {1123, 1}, - 0xED = {1124, 1}, - 0xEE = {1125, 1}, - 0xEF = {1126, 1}, - 0xF1 = {1127, 1}, - 0xF2 = {1128, 1}, - 0xF3 = {1129, 1}, - 0xF4 = {1130, 1}, - 0xF5 = {1131, 1}, - 0xF6 = {1132, 1}, - 0xF7 = {1133, 1}, - 0xF8 = {1134, 1}, - 0xF9 = {1135, 1}, - 0xFA = {1136, 1}, - 0xFB = {1137, 1}, - 0xFC = {1138, 1}, - 0xFD = {1139, 1}, - 0xFE = {1140, 1}, + 0x10 = { 903, 1}, + 0x11 = { 904, 1}, + 0x12 = { 905, 1}, + 0x13 = { 906, 1}, + 0x14 = { 907, 1}, + 0x15 = { 908, 1}, + 0x16 = { 909, 1}, + 0x17 = { 910, 1}, + 0x28 = { 911, 1}, + 0x29 = { 912, 1}, + 0x2B = { 913, 1}, + 0x2E = { 914, 1}, + 0x2F = { 915, 1}, + 0x50 = { 916, 2}, + 0x51 = { 918, 1}, + 0x54 = { 919, 1}, + 0x55 = { 920, 1}, + 0x56 = { 921, 1}, + 0x57 = { 922, 1}, + 0x58 = { 923, 1}, + 0x59 = { 924, 1}, + 0x5A = { 925, 1}, + 0x5B = { 926, 1}, + 0x5C = { 927, 1}, + 0x5D = { 928, 1}, + 0x5E = { 929, 1}, + 0x5F = { 930, 1}, + 0x60 = { 931, 1}, + 0x61 = { 932, 1}, + 0x62 = { 933, 1}, + 0x63 = { 934, 1}, + 0x64 = { 935, 1}, + 0x65 = { 936, 1}, + 0x66 = { 937, 1}, + 0x67 = { 938, 1}, + 0x68 = { 939, 1}, + 0x69 = { 940, 1}, + 0x6A = { 941, 1}, + 0x6B = { 942, 1}, + 0x6C = { 943, 1}, + 0x6D = { 944, 1}, + 0x6E = { 945, 2}, + 0x6F = { 947, 1}, + 0x70 = { 948, 1}, + 0x71 = { 949, 3}, + 0x72 = { 952, 3}, + 0x73 = { 955, 2}, + 0x74 = { 957, 1}, + 0x75 = { 958, 1}, + 0x76 = { 959, 1}, + 0x7C = { 960, 1}, + 0x7D = { 961, 1}, + 0x7E = { 962, 2}, + 0x7F = { 964, 1}, + 0xAE = { 965, 3}, + 0xC2 = { 968, 1}, + 0xC4 = { 969, 2}, + 0xC5 = { 971, 2}, + 0xC6 = { 973, 1}, + 0xC7 = { 974, 1}, + 0xD0 = { 975, 1}, + 0xD1 = { 976, 1}, + 0xD2 = { 977, 1}, + 0xD3 = { 978, 1}, + 0xD4 = { 979, 1}, + 0xD5 = { 980, 1}, + 0xD6 = { 981, 1}, + 0xD7 = { 982, 2}, + 0xD8 = { 984, 1}, + 0xD9 = { 985, 1}, + 0xDA = { 986, 1}, + 0xDB = { 987, 1}, + 0xDC = { 988, 1}, + 0xDD = { 989, 1}, + 0xDE = { 990, 1}, + 0xDF = { 991, 1}, + 0xE0 = { 992, 1}, + 0xE1 = { 993, 1}, + 0xE2 = { 994, 1}, + 0xE3 = { 995, 1}, + 0xE4 = { 996, 1}, + 0xE5 = { 997, 1}, + 0xE6 = { 998, 1}, + 0xE7 = { 999, 1}, + 0xE8 = {1000, 1}, + 0xE9 = {1001, 1}, + 0xEA = {1002, 1}, + 0xEB = {1003, 1}, + 0xEC = {1004, 1}, + 0xED = {1005, 1}, + 0xEE = {1006, 1}, + 0xEF = {1007, 1}, + 0xF1 = {1008, 1}, + 0xF2 = {1009, 1}, + 0xF3 = {1010, 1}, + 0xF4 = {1011, 1}, + 0xF5 = {1012, 1}, + 0xF6 = {1013, 1}, + 0xF7 = {1014, 1}, + 0xF8 = {1015, 1}, + 0xF9 = {1016, 1}, + 0xFA = {1017, 1}, + 0xFB = {1018, 1}, + 0xFC = {1019, 1}, + 0xFD = {1020, 1}, + 0xFE = {1021, 1}, }, { // prefix = F3 - 0x01 = {1141, 6}, - 0x09 = {1147, 1}, - 0x10 = {1148, 1}, - 0x11 = {1149, 1}, - 0x12 = {1150, 1}, - 0x16 = {1151, 1}, - 0x1E = {1152, 4}, - 0x2A = {1156, 2}, - 0x2C = {1158, 2}, - 0x2D = {1160, 2}, - 0x51 = {1162, 1}, - 0x52 = {1163, 1}, - 0x53 = {1164, 1}, - 0x58 = {1165, 1}, - 0x59 = {1166, 1}, - 0x5A = {1167, 1}, - 0x5B = {1168, 1}, - 0x5C = {1169, 1}, - 0x5D = {1170, 1}, - 0x5E = {1171, 1}, - 0x5F = {1172, 1}, - 0x6F = {1173, 1}, - 0x70 = {1174, 1}, - 0x7E = {1175, 1}, - 0x7F = {1176, 1}, - 0xAE = {1177, 14}, - 0xB8 = {1191, 3}, - 0xBC = {1194, 3}, - 0xBD = {1197, 3}, - 0xC2 = {1200, 1}, - 0xC7 = {1201, 2}, - 0xE6 = {1203, 1}, + 0x01 = {1022, 6}, + 0x09 = {1028, 1}, + 0x10 = {1029, 1}, + 0x11 = {1030, 1}, + 0x12 = {1031, 1}, + 0x16 = {1032, 1}, + 0x1E = {1033, 4}, + 0x2A = {1037, 2}, + 0x2C = {1039, 2}, + 0x2D = {1041, 2}, + 0x51 = {1043, 1}, + 0x52 = {1044, 1}, + 0x53 = {1045, 1}, + 0x58 = {1046, 1}, + 0x59 = {1047, 1}, + 0x5A = {1048, 1}, + 0x5B = {1049, 1}, + 0x5C = {1050, 1}, + 0x5D = {1051, 1}, + 0x5E = {1052, 1}, + 0x5F = {1053, 1}, + 0x6F = {1054, 1}, + 0x70 = {1055, 1}, + 0x7E = {1056, 1}, + 0x7F = {1057, 1}, + 0xAE = {1058, 14}, + 0xB8 = {1072, 3}, + 0xBC = {1075, 3}, + 0xBD = {1078, 3}, + 0xC2 = {1081, 1}, + 0xC7 = {1082, 2}, + 0xE6 = {1084, 1}, }, { // prefix = F2 - 0x01 = {1204, 2}, - 0x10 = {1206, 1}, - 0x11 = {1207, 1}, - 0x12 = {1208, 1}, - 0x2A = {1209, 2}, - 0x2C = {1211, 2}, - 0x2D = {1213, 2}, - 0x51 = {1215, 1}, - 0x58 = {1216, 1}, - 0x59 = {1217, 1}, - 0x5A = {1218, 1}, - 0x5C = {1219, 1}, - 0x5D = {1220, 1}, - 0x5E = {1221, 1}, - 0x5F = {1222, 1}, - 0x70 = {1223, 1}, - 0x7C = {1224, 1}, - 0x7D = {1225, 1}, - 0xAE = {1226, 1}, - 0xC2 = {1227, 1}, - 0xD0 = {1228, 1}, - 0xE6 = {1229, 1}, - 0xF0 = {1230, 1}, + 0x01 = {1085, 2}, + 0x10 = {1087, 1}, + 0x11 = {1088, 1}, + 0x12 = {1089, 1}, + 0x2A = {1090, 2}, + 0x2C = {1092, 2}, + 0x2D = {1094, 2}, + 0x51 = {1096, 1}, + 0x58 = {1097, 1}, + 0x59 = {1098, 1}, + 0x5A = {1099, 1}, + 0x5C = {1100, 1}, + 0x5D = {1101, 1}, + 0x5E = {1102, 1}, + 0x5F = {1103, 1}, + 0x70 = {1104, 1}, + 0x7C = {1105, 1}, + 0x7D = {1106, 1}, + 0xAE = {1107, 1}, + 0xC2 = {1108, 1}, + 0xD0 = {1109, 1}, + 0xE6 = {1110, 1}, + 0xF0 = {1111, 1}, }, } @(rodata) DECODE_INDEX_ESC_0F38 := [4][256]lib.Decode_Index{ { // prefix = none - 0xC8 = {1231, 1}, - 0xC9 = {1232, 1}, - 0xCA = {1233, 1}, - 0xCB = {1234, 1}, - 0xCC = {1235, 1}, - 0xCD = {1236, 1}, - 0xF0 = {1237, 3}, - 0xF1 = {1240, 3}, - 0xF6 = {1243, 2}, - 0xF9 = {1245, 2}, - 0xFC = {1247, 2}, + 0xC8 = {1112, 1}, + 0xC9 = {1113, 1}, + 0xCA = {1114, 1}, + 0xCB = {1115, 1}, + 0xCC = {1116, 1}, + 0xCD = {1117, 1}, + 0xF0 = {1118, 3}, + 0xF1 = {1121, 3}, + 0xF6 = {1124, 2}, + 0xF9 = {1126, 2}, + 0xFC = {1128, 2}, }, { // prefix = 66 - 0x00 = {1249, 1}, - 0x01 = {1250, 1}, - 0x02 = {1251, 1}, - 0x03 = {1252, 1}, - 0x04 = {1253, 1}, - 0x05 = {1254, 1}, - 0x06 = {1255, 1}, - 0x07 = {1256, 1}, - 0x08 = {1257, 1}, - 0x09 = {1258, 1}, - 0x0A = {1259, 1}, - 0x0B = {1260, 1}, - 0x10 = {1261, 1}, - 0x14 = {1262, 1}, - 0x15 = {1263, 1}, - 0x17 = {1264, 1}, - 0x1C = {1265, 1}, - 0x1D = {1266, 1}, - 0x1E = {1267, 1}, - 0x20 = {1268, 1}, - 0x21 = {1269, 1}, - 0x22 = {1270, 1}, - 0x23 = {1271, 1}, - 0x24 = {1272, 1}, - 0x25 = {1273, 1}, - 0x28 = {1274, 1}, - 0x29 = {1275, 1}, - 0x2A = {1276, 1}, - 0x2B = {1277, 1}, - 0x30 = {1278, 1}, - 0x31 = {1279, 1}, - 0x32 = {1280, 1}, - 0x33 = {1281, 1}, - 0x34 = {1282, 1}, - 0x35 = {1283, 1}, - 0x37 = {1284, 1}, - 0x38 = {1285, 1}, - 0x39 = {1286, 1}, - 0x3A = {1287, 1}, - 0x3B = {1288, 1}, - 0x3C = {1289, 1}, - 0x3D = {1290, 1}, - 0x3E = {1291, 1}, - 0x3F = {1292, 1}, - 0x40 = {1293, 1}, - 0x41 = {1294, 1}, - 0x80 = {1295, 1}, - 0x81 = {1296, 1}, - 0x82 = {1297, 2}, - 0xDB = {1299, 1}, - 0xDC = {1300, 1}, - 0xDD = {1301, 1}, - 0xDE = {1302, 1}, - 0xDF = {1303, 1}, - 0xF5 = {1304, 2}, - 0xF6 = {1306, 2}, - 0xF8 = {1308, 1}, - 0xFC = {1309, 2}, + 0x00 = {1130, 1}, + 0x01 = {1131, 1}, + 0x02 = {1132, 1}, + 0x03 = {1133, 1}, + 0x04 = {1134, 1}, + 0x05 = {1135, 1}, + 0x06 = {1136, 1}, + 0x07 = {1137, 1}, + 0x08 = {1138, 1}, + 0x09 = {1139, 1}, + 0x0A = {1140, 1}, + 0x0B = {1141, 1}, + 0x10 = {1142, 1}, + 0x14 = {1143, 1}, + 0x15 = {1144, 1}, + 0x17 = {1145, 1}, + 0x1C = {1146, 1}, + 0x1D = {1147, 1}, + 0x1E = {1148, 1}, + 0x20 = {1149, 1}, + 0x21 = {1150, 1}, + 0x22 = {1151, 1}, + 0x23 = {1152, 1}, + 0x24 = {1153, 1}, + 0x25 = {1154, 1}, + 0x28 = {1155, 1}, + 0x29 = {1156, 1}, + 0x2A = {1157, 1}, + 0x2B = {1158, 1}, + 0x30 = {1159, 1}, + 0x31 = {1160, 1}, + 0x32 = {1161, 1}, + 0x33 = {1162, 1}, + 0x34 = {1163, 1}, + 0x35 = {1164, 1}, + 0x37 = {1165, 1}, + 0x38 = {1166, 1}, + 0x39 = {1167, 1}, + 0x3A = {1168, 1}, + 0x3B = {1169, 1}, + 0x3C = {1170, 1}, + 0x3D = {1171, 1}, + 0x3E = {1172, 1}, + 0x3F = {1173, 1}, + 0x40 = {1174, 1}, + 0x41 = {1175, 1}, + 0x80 = {1176, 1}, + 0x81 = {1177, 1}, + 0x82 = {1178, 2}, + 0xDB = {1180, 1}, + 0xDC = {1181, 1}, + 0xDD = {1182, 1}, + 0xDE = {1183, 1}, + 0xDF = {1184, 1}, + 0xF5 = {1185, 2}, + 0xF6 = {1187, 2}, + 0xF8 = {1189, 1}, + 0xFC = {1190, 2}, }, { // prefix = F3 - 0xF6 = {1311, 2}, - 0xF8 = {1313, 1}, - 0xFC = {1314, 2}, + 0xF6 = {1192, 2}, + 0xF8 = {1194, 1}, + 0xFC = {1195, 2}, }, { // prefix = F2 - 0xF0 = {1316, 2}, - 0xF1 = {1318, 3}, - 0xF8 = {1321, 1}, - 0xFC = {1322, 2}, + 0xF0 = {1197, 2}, + 0xF1 = {1199, 3}, + 0xF8 = {1202, 1}, + 0xFC = {1203, 2}, }, } @(rodata) DECODE_INDEX_ESC_0F3A := [4][256]lib.Decode_Index{ { // prefix = none - 0xCC = {1324, 1}, + 0xCC = {1205, 1}, }, { // prefix = 66 - 0x08 = {1325, 1}, - 0x09 = {1326, 1}, - 0x0A = {1327, 1}, - 0x0B = {1328, 1}, - 0x0C = {1329, 1}, - 0x0D = {1330, 1}, - 0x0E = {1331, 1}, - 0x0F = {1332, 1}, - 0x14 = {1333, 1}, - 0x16 = {1334, 2}, - 0x17 = {1336, 1}, - 0x20 = {1337, 1}, - 0x21 = {1338, 1}, - 0x22 = {1339, 2}, - 0x40 = {1341, 1}, - 0x41 = {1342, 1}, - 0x42 = {1343, 1}, - 0x44 = {1344, 1}, - 0x60 = {1345, 1}, - 0x61 = {1346, 1}, - 0x62 = {1347, 1}, - 0x63 = {1348, 1}, - 0xDF = {1349, 1}, + 0x08 = {1206, 1}, + 0x09 = {1207, 1}, + 0x0A = {1208, 1}, + 0x0B = {1209, 1}, + 0x0C = {1210, 1}, + 0x0D = {1211, 1}, + 0x0E = {1212, 1}, + 0x0F = {1213, 1}, + 0x14 = {1214, 1}, + 0x16 = {1215, 2}, + 0x17 = {1217, 1}, + 0x20 = {1218, 1}, + 0x21 = {1219, 1}, + 0x22 = {1220, 2}, + 0x40 = {1222, 1}, + 0x41 = {1223, 1}, + 0x42 = {1224, 1}, + 0x44 = {1225, 1}, + 0x60 = {1226, 1}, + 0x61 = {1227, 1}, + 0x62 = {1228, 1}, + 0x63 = {1229, 1}, + 0xDF = {1230, 1}, }, { // prefix = F3 }, diff --git a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin index 3eb58e95a..a459d52cb 100644 --- a/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/x86/tablegen/generated/encode_tables.odin @@ -585,11 +585,11 @@ ENCODE_FORMS := [2478]lib.Encoding{ {.JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x78, 0, {explicit_count=1}}, {.JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x88, 0, {esc=._0F, explicit_count=1}}, // .JCXZ - {.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {explicit_count=1}}, + {.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A16, explicit_count=1}}, // .JECXZ - {.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {explicit_count=1}}, + {.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A32, explicit_count=1}}, // .JRCXZ - {.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {force_rex_w=true, explicit_count=1}}, + {.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A64, explicit_count=1}}, // .LOOP {.LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE2, 0, {explicit_count=1}}, // .LOOPE diff --git a/core/rexcode/isa/x86/tablegen/instruction_table.odin b/core/rexcode/isa/x86/tablegen/instruction_table.odin index 11e897138..e586a3f65 100644 --- a/core/rexcode/isa/x86/tablegen/instruction_table.odin +++ b/core/rexcode/isa/x86/tablegen/instruction_table.odin @@ -733,14 +733,20 @@ INSTRUCTION_TABLE := [Mnemonic][]Form{ {{.JS, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0x78, 0, {}}, {flags_rd={.SF}, side_effects={.CONTROL}}}, {{.JS, {.REL32, .NONE, .NONE, .NONE}, {.ID, .NONE, .NONE, .NONE}, 0x88, 0, {esc=._0F}}, {flags_rd={.SF}, side_effects={.CONTROL}}}, }, + /* 0xE3 is ONE opcode whose mnemonic is chosen by ADDRESS size -- which + counter register it tests -- not by operand size. So the three are told + apart by `addr_size` (67h against the mode default), never by REX.W, which + does not affect address size at all: JRCXZ is a bare `E3 cb` in long mode + and JECXZ is `67 E3 cb`; in protected mode JECXZ is bare and JCXZ takes + the prefix, while JCXZ is unreachable in long mode and JRCXZ outside it. */ .JCXZ = { - {{.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, + {{.JCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A16}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, }, .JECXZ = { - {{.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, + {{.JECXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A32}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, }, .JRCXZ = { - {{.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {force_rex_w=true}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, + {{.JRCXZ, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE3, 0, {addr_size=.A64}}, {implicit_rd={.RCX}, side_effects={.CONTROL}}}, }, .LOOP = { {{.LOOP, {.REL8, .NONE, .NONE, .NONE}, {.IB, .NONE, .NONE, .NONE}, 0xE2, 0, {}}, {implicit_wr={.RCX}, implicit_rd={.RCX}, side_effects={.CONTROL}}}, diff --git a/core/rexcode/isa/x86/tables/x86.encode_forms.bin b/core/rexcode/isa/x86/tables/x86.encode_forms.bin index a71e55be9..3e03ddfdb 100644 Binary files a/core/rexcode/isa/x86/tables/x86.encode_forms.bin and b/core/rexcode/isa/x86/tables/x86.encode_forms.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.encode_recipes.bin b/core/rexcode/isa/x86/tables/x86.encode_recipes.bin index 4b55c24fc..fbbba14d1 100644 Binary files a/core/rexcode/isa/x86/tables/x86.encode_recipes.bin and b/core/rexcode/isa/x86/tables/x86.encode_recipes.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.evex.bin b/core/rexcode/isa/x86/tables/x86.evex.bin index ff07490c1..a6d378ecb 100644 Binary files a/core/rexcode/isa/x86/tables/x86.evex.bin and b/core/rexcode/isa/x86/tables/x86.evex.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.idx_0f.bin b/core/rexcode/isa/x86/tables/x86.idx_0f.bin index ddcbc62e1..844850302 100644 Binary files a/core/rexcode/isa/x86/tables/x86.idx_0f.bin and b/core/rexcode/isa/x86/tables/x86.idx_0f.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.idx_0f38.bin b/core/rexcode/isa/x86/tables/x86.idx_0f38.bin index 654558711..6188bf858 100644 Binary files a/core/rexcode/isa/x86/tables/x86.idx_0f38.bin and b/core/rexcode/isa/x86/tables/x86.idx_0f38.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.idx_0f3a.bin b/core/rexcode/isa/x86/tables/x86.idx_0f3a.bin index 8805f356a..f3d489d59 100644 Binary files a/core/rexcode/isa/x86/tables/x86.idx_0f3a.bin and b/core/rexcode/isa/x86/tables/x86.idx_0f3a.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.idx_legacy.bin b/core/rexcode/isa/x86/tables/x86.idx_legacy.bin index fda086bfd..769fda98d 100644 Binary files a/core/rexcode/isa/x86/tables/x86.idx_legacy.bin and b/core/rexcode/isa/x86/tables/x86.idx_legacy.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.legacy.bin b/core/rexcode/isa/x86/tables/x86.legacy.bin index d0b0f1c6b..39a3c2793 100644 Binary files a/core/rexcode/isa/x86/tables/x86.legacy.bin and b/core/rexcode/isa/x86/tables/x86.legacy.bin differ diff --git a/core/rexcode/isa/x86/tables/x86.vex.bin b/core/rexcode/isa/x86/tables/x86.vex.bin index 9508af84c..b5f0346d4 100644 Binary files a/core/rexcode/isa/x86/tables/x86.vex.bin and b/core/rexcode/isa/x86/tables/x86.vex.bin differ diff --git a/core/rexcode/isa/x86/tests/test.odin b/core/rexcode/isa/x86/tests/test.odin index 5bf116daa..bf5ffc457 100644 --- a/core/rexcode/isa/x86/tests/test.odin +++ b/core/rexcode/isa/x86/tests/test.odin @@ -666,35 +666,195 @@ print_highlighted :: proc(text: string, tokens: []x86.Token) { // SECTION 4: MNEMONIC EQUIVALENCE // ============================================================================= +/* + Several x86 mnemonics name ONE encoding -- SHL and SAL are both /4 in the + shift group, JE and JZ are both 0x74. Which name a decode returns is declared + by x86.MNEMONIC_ALIASES and enforced by the generator, which drops the + aliased spelling before the decode tables are written; so encoding SAL and + decoding it back yields SHL, and a round-trip compares canonical forms. + + This used to be a second alias table maintained BY HAND here, and that is how + SHL/SAL went missing: the shift group was never listed, nothing checked, and + it stayed invisible until a table regeneration moved SAL ahead of SHL and + four long-passing tests began reporting `SAL != expected SHL`. There is now + one table, in the library, and run_alias_table_test below proves it complete + against the built tables rather than against anyone's memory. +*/ mnemonics_eq :: proc(a, b: x86.Mnemonic) -> bool { - if a == b { return true } - aliases := [][2]x86.Mnemonic{ - // MOV/MOVABS - {.MOV, .MOVABS}, - // CMOVcc aliases - {.CMOVE, .CMOVZ}, {.CMOVNE, .CMOVNZ}, - {.CMOVG, .CMOVNLE}, {.CMOVGE, .CMOVNL}, - {.CMOVL, .CMOVNGE}, {.CMOVLE, .CMOVNG}, - {.CMOVA, .CMOVNBE}, {.CMOVAE, .CMOVNB}, {.CMOVAE, .CMOVNC}, - {.CMOVB, .CMOVNAE}, {.CMOVB, .CMOVC}, {.CMOVBE, .CMOVNA}, - // SETcc aliases - {.SETE, .SETZ}, {.SETNE, .SETNZ}, - {.SETG, .SETNLE}, {.SETGE, .SETNL}, - {.SETL, .SETNGE}, {.SETLE, .SETNG}, - {.SETA, .SETNBE}, {.SETAE, .SETNB}, {.SETAE, .SETNC}, - {.SETB, .SETNAE}, {.SETB, .SETC}, {.SETBE, .SETNA}, - // Jcc aliases - {.JE, .JZ}, {.JNE, .JNZ}, - {.JB, .JC}, {.JAE, .JNC}, - {.JG, .JNLE}, {.JGE, .JNL}, - {.JL, .JNGE}, {.JLE, .JNG}, - {.JA, .JNBE}, {.JAE, .JNB}, - {.JB, .JNAE}, {.JBE, .JNA}, + return a == b || x86.canonical_mnemonic(a) == x86.canonical_mnemonic(b) +} + +/* + No encoding may be spelled by two mnemonics that both survive into the decode + tables -- because the decoder would then have to choose between them with + nothing to choose on, which is the defect x86.MNEMONIC_ALIASES exists to + remove. Two entries are indistinguishable exactly when they agree on every + field the decoder can read, so the property is computable from the tables + themselves, and this recomputes it. + + It is what makes the declaration maintainable: an instruction added with a + mnemonic that aliases another's encoding fails here BY NAME, with the row to + write, instead of silently decoding as whichever spelling the sort happened + to put first. +*/ +run_alias_table_test :: proc() { + Group_Key :: struct { + esc: x86.Escape, + prefix: u8, + opcode: u8, + ext: u8, + ops: [4]x86.Operand_Type, + enc: [4]x86.Operand_Encoding, + flags: x86.Encoding_Flags, } - for alias in aliases { - if (a == alias[0] && b == alias[1]) || (a == alias[1] && b == alias[0]) { return true } + groups := make(map[Group_Key][dynamic]x86.Mnemonic) + defer { + for _, list in groups { delete(list) } + delete(groups) + } + for e in x86.LEGACY_DECODE_ENTRIES { + key := Group_Key{e.esc, e.prefix, e.opcode, e.ext, e.ops, e.enc, e.flags} + list, present := &groups[key] + if !present { + groups[key] = make([dynamic]x86.Mnemonic) + list = &groups[key] + } + known := false + for m in list { + if m == e.mnemonic { + known = true + break + } + } + if !known { append(list, e.mnemonic) } + } + + ambiguous := 0 + for key, list in groups { + if len(list) < 2 { continue } + ambiguous += 1 + if ambiguous <= 10 { + fmt.printf(" %sFAIL%s esc=%v prefix=%d opcode=%02X ext=%02X is spelled by", + RED, RESET, key.esc, key.prefix, key.opcode, key.ext) + for m in list { fmt.printf(" %v", m) } + fmt.printf(",\n and the decoder has nothing to choose between them. Declare one in\n") + fmt.printf(" x86.MNEMONIC_ALIASES (isa/x86/aliases.odin), then regenerate:\n") + fmt.printf(" odin run core/rexcode/isa/x86/tablegen && odin run core/rexcode/isa/x86/tablegen/generated\n") + } + } + if ambiguous > 10 { + fmt.printf(" ... and %d further ambiguous encoding(s).\n", ambiguous - 10) + } + if ambiguous > 0 { + g_stats.failed += 1 + return + } + g_stats.passed += 1 + g_stats.cases_validated += 1 +} + +/* + 0xE3 is one opcode whose MNEMONIC is chosen by address size -- which counter + register it tests -- and address size is the 67h axis, not REX.W. Modelling + JRCXZ as `force_rex_w` made its encoding `48 E3 cb` (llvm-mc emits a bare + `E3 cb`, and REX.W does not affect address size at all), gave JECXZ the bare + encoding that is really JRCXZ in long mode, and left the decoder with three + indistinguishable entries to guess between. + + Both directions and both modes are asserted here, refusals included: JCXZ is + unreachable in long mode (67h selects 32-bit there, never 16-bit) and JRCXZ + outside it. Every expectation below was measured against llvm-mc. +*/ +run_addr_size_tests :: proc() { + Decode_Case :: struct { + bytes: []u8, + mode: x86.Mode, + want: x86.Mnemonic, + note: string, + } + decodes := []Decode_Case{ + {{0xE3, 0x00}, ._64, .JRCXZ, "long mode default address size is 64-bit"}, + {{0x67, 0xE3, 0x00}, ._64, .JECXZ, "67h drops long mode to 32-bit"}, + {{0x48, 0xE3, 0x00}, ._64, .JRCXZ, "REX.W is ignored for address size"}, + {{0xE3, 0x00}, ._32, .JECXZ, "protected mode default is 32-bit"}, + {{0x67, 0xE3, 0x00}, ._32, .JCXZ, "67h drops protected mode to 16-bit"}, + } + for c in decodes { + insts := make([dynamic]x86.Instruction) + info := make([dynamic]x86.Instruction_Info) + labels := make([dynamic]x86.Label_Definition) + errors := make([dynamic]x86.Error) + defer { + delete(insts); delete(info); delete(labels); delete(errors) + } + _, ok := x86.decode(c.bytes, nil, &insts, &info, &labels, &errors, c.mode) + if !ok || len(insts) == 0 { + g_stats.failed += 1 + fmt.printf(" %sFAIL%s %v decode failed in %v (%s)\n", RED, RESET, c.bytes, c.mode, c.note) + continue + } + if insts[0].mnemonic != c.want { + g_stats.failed += 1 + fmt.printf(" %sFAIL%s %v in %v decoded %v, expected %v -- %s\n", + RED, RESET, c.bytes, c.mode, insts[0].mnemonic, c.want, c.note) + continue + } + g_stats.passed += 1 + g_stats.cases_validated += 1 + } + + Encode_Case :: struct { + mnemonic: x86.Mnemonic, + mode: x86.Mode, + want: []u8, // empty = must be refused; this mode cannot express it + } + encodes := []Encode_Case{ + {.JRCXZ, ._64, {0xE3, 0x00}}, + {.JECXZ, ._64, {0x67, 0xE3, 0x00}}, + {.JCXZ, ._64, {}}, + {.JECXZ, ._32, {0xE3, 0x00}}, + {.JCXZ, ._32, {0x67, 0xE3, 0x00}}, + {.JRCXZ, ._32, {}}, + } + for c in encodes { + insts := []x86.Instruction{x86.inst_rel_offset(c.mnemonic, 0, 1)} + code := make([]u8, 32) + relocs := make([dynamic]x86.Relocation) + errors := make([dynamic]x86.Error) + defer { + delete(code); delete(relocs); delete(errors) + } + count, ok := x86.encode(insts, nil, code, &relocs, &errors, true, 0, c.mode) + if len(c.want) == 0 { + if ok && count > 0 { + g_stats.failed += 1 + fmt.printf(" %sFAIL%s %v encoded to %02X in %v, but that mode cannot express its address size\n", + RED, RESET, c.mnemonic, code[:count], c.mode) + continue + } + g_stats.passed += 1 + g_stats.cases_validated += 1 + continue + } + if !ok || int(count) != len(c.want) { + g_stats.failed += 1 + fmt.printf(" %sFAIL%s %v in %v encoded %d byte(s), expected %d\n", + RED, RESET, c.mnemonic, c.mode, count, len(c.want)) + continue + } + same := true + for want, i in c.want { + if code[i] != want { same = false; break } + } + if !same { + g_stats.failed += 1 + fmt.printf(" %sFAIL%s %v in %v encoded % 02X, expected % 02X\n", + RED, RESET, c.mnemonic, c.mode, code[:count], c.want) + continue + } + g_stats.passed += 1 + g_stats.cases_validated += 1 } - return false } // ============================================================================= @@ -3630,6 +3790,12 @@ main :: proc() { log_header("TYPED BUILDER CONSISTENCY") run_typed_builder_tests() + log_header("MNEMONIC ALIAS TABLE") + run_alias_table_test() + + log_header("ADDRESS-SIZE SELECTED MNEMONICS") + run_addr_size_tests() + log_header("I386 (32-BIT MODE) TESTS") run_i386_tests()