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rexcode/arm32: VQDMULH/VQRDMULH by-scalar-lane

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New NEON_VM_SCALAR16/32 encodings for the Dm[lane] scalar operand: .16
places Dm in D0..D7 (bits 2:0) with the lane split bit5:bit3, .32 places
Dm in D0..D15 (bits 3:0) with the lane at bit5. VQDMULH_LANE and
VQRDMULH_LANE across .s16/.s32, D and Q destinations (8 forms). Verify
round-trips; spot-checked byte-exact incl. max register/lane and
decode-clean; 600 tests green.
This commit is contained in:
Brendan Punsky
2026-06-18 01:29:19 -04:00
committed by Flāvius
parent acc14864f3
commit 5df81b5117
16 changed files with 1463 additions and 1404 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
core/rexcode/arm32/decoder.odin
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@@ -336,6 +336,11 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
case .VM_D:
n := ((word >> 5) & 1) << 4 | (word & 0xF)
return op_reg(Register(REG_DPR | u16(n)))
case .NEON_VM_SCALAR16:
lane := ((word >> 5) & 1) << 1 | ((word >> 3) & 1)
return op_dpr_lane(Register(REG_DPR | u16(word & 0x7)), u8(lane))
case .NEON_VM_SCALAR32:
return op_dpr_lane(Register(REG_DPR | u16(word & 0xF)), u8((word >> 5) & 1))
case .VD_Q:
n := (((word >> 22) & 1) << 4 | ((word >> 12) & 0xF)) >> 1
return op_reg(Register(REG_QPR | u16(n)))

6
core/rexcode/arm32/encoder.odin
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@@ -418,6 +418,12 @@ pack_operand_inline :: #force_inline proc(
n := u32(reg_hw(op.reg)) & 0x1F
if reg_class(op.reg) == REG_QPR { n = (n & 0xF) * 2 }
return (n & 0xF) | ((n >> 4) & 1) << 5
case .NEON_VM_SCALAR16:
// Dm in D0..D7 at bits 2:0; lane = bit5(lane[1]) : bit3(lane[0]).
return (u32(reg_hw(op.reg)) & 0x7) | ((u32(op.lane) >> 1) & 1) << 5 | (u32(op.lane) & 1) << 3
case .NEON_VM_SCALAR32:
// Dm in D0..D15 at bits 3:0; lane = bit5.
return (u32(reg_hw(op.reg)) & 0xF) | (u32(op.lane) & 1) << 5
case .VFP_IMM8:
// Run the VFP 8-bit float encoder; the user supplies the wire-format
// 32-bit float bit pattern (for F32). The encoder finds the abcdefgh.

5
core/rexcode/arm32/encoding_types.odin
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@@ -300,6 +300,11 @@ Operand_Encoding :: enum u8 {
VD_Q, // Q<reg>: D=bit 22, Vd<3:0>=bits 15-12 (must be even)
VN_Q, // Q<reg>: N=bit 7, Vn<3:0>=bits 19-16 (must be even)
VM_Q, // Q<reg>: M=bit 5, Vm<3:0>=bits 3-0 (must be even)
// NEON by-element scalar Dm[lane] (VQDMULH/VQRDMULH-by-scalar):
// .16: Dm in D0..D7 at bits 2:0, lane = bit5:bit3
// .32: Dm in D0..D15 at bits 3:0, lane = bit5
NEON_VM_SCALAR16,
NEON_VM_SCALAR32,
VFP_IMM8, // VFP immediate (VMOV.F32/F64 #imm)
NEON_IMM8_ABCDEFGH, // bits 18-16 (abc) + bits 3-0 (defgh)
NEON_CMODE, // bits 11-8 (cmode for VMOV/VMVN immediate)

8
core/rexcode/arm32/mnemonic_builders.odin
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@@ -794,6 +794,10 @@ inst_vqdmulh_d_d_d :: #force_inline proc "contextless" (dst: Regis
emit_vqdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqdmulh_d_d_d(dst, src, src2)) }
inst_vqrdmulh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMULH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_vqrdmulh_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmulh_d_d_d(dst, src, src2)) }
inst_vqdmulh_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQDMULH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
emit_vqdmulh_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqdmulh_lane_d_d_dlane(dst, src, src2, lane)) }
inst_vqrdmulh_lane_d_d_dlane :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register, lane: u8) -> Instruction { return Instruction{mnemonic = .VQRDMULH_LANE, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_dpr_lane(src2, lane), {}}} }
emit_vqrdmulh_lane_d_d_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register, lane: u8) { append(instructions, inst_vqrdmulh_lane_d_d_dlane(dst, src, src2, lane)) }
inst_vqrdmlah_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLAH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
emit_vqrdmlah_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vqrdmlah_d_d_d(dst, src, src2)) }
inst_vqrdmlsh_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VQRDMLSH, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} }
@@ -2053,6 +2057,10 @@ inst_vqdmulh :: inst_vqdmulh_d_d_d
emit_vqdmulh :: emit_vqdmulh_d_d_d
inst_vqrdmulh :: inst_vqrdmulh_d_d_d
emit_vqrdmulh :: emit_vqrdmulh_d_d_d
inst_vqdmulh_lane :: inst_vqdmulh_lane_d_d_dlane
emit_vqdmulh_lane :: emit_vqdmulh_lane_d_d_dlane
inst_vqrdmulh_lane :: inst_vqrdmulh_lane_d_d_dlane
emit_vqrdmulh_lane :: emit_vqrdmulh_lane_d_d_dlane
inst_vqrdmlah :: inst_vqrdmlah_d_d_d
emit_vqrdmlah :: emit_vqrdmlah_d_d_d
inst_vqrdmlsh :: inst_vqrdmlsh_d_d_d

15
core/rexcode/arm32/tablegen/encoding_table.odin
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@@ -3666,6 +3666,21 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{
.DCPS2 = { {.DCPS2, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8002, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}} },
.DCPS3 = { {.DCPS3, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF78F8003, 0xFFFFFFFF, .V8, .T32, {thumb32=true, cond_in_28=false}} },
// NEON (saturating) doubling multiply-high by scalar Dm[lane]:
// .16 -> Dm in D0..D7 (bits 2:0), lane at bit5:bit3; .32 -> D0..D15, lane bit5.
.VQDMULH_LANE = {
{.VQDMULH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}},
{.VQDMULH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}},
{.VQDMULH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}},
{.VQDMULH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}},
},
.VQRDMULH_LANE = {
{.VQRDMULH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR16, .NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}},
{.VQRDMULH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR16, .NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}},
{.VQRDMULH_LANE, {.DPR, .DPR, .DPR_ELEM, .NONE}, {.VD_D, .VN_D, .NEON_VM_SCALAR32, .NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}},
{.VQRDMULH_LANE, {.QPR, .QPR, .DPR_ELEM, .NONE}, {.VD_Q, .VN_Q, .NEON_VM_SCALAR32, .NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {cond_in_28=false}},
},
// SPECGEN:BEGIN
.VADDL = {
{.VADDL, {.QPR, .DPR, .DPR, .NONE}, {.VD_Q, .VN_D, .VM_D, .NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {cond_in_28=false}},

2172
core/rexcode/arm32/tablegen/generated/decode_tables.odin
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File diff suppressed because it is too large Load Diff

656
core/rexcode/arm32/tablegen/generated/encode_tables.odin
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@@ -8,7 +8,7 @@ package rexcode_arm32_generated
import lib "../.."
@(rodata)
ENCODE_FORMS := [1660]lib.Encoding{
ENCODE_FORMS := [1668]lib.Encoding{
// .AND
{ .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {} },
{ .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {} },
@@ -1272,6 +1272,16 @@ ENCODE_FORMS := [1660]lib.Encoding{
{ .VQRDMULH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B00, 0xFFB00F10, .NEON, .A32, {} },
{ .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3100B40, 0xFFB00F50, .NEON, .A32, {} },
{ .VQRDMULH, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200B40, 0xFFB00F50, .NEON, .A32, {} },
// .VQDMULH_LANE
{ .VQDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900C40, 0xFFB00F50, .NEON, .A32, {} },
{ .VQDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900C40, 0xFFB11F50, .NEON, .A32, {} },
{ .VQDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {} },
{ .VQDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00C40, 0xFFB11F50, .NEON, .A32, {} },
// .VQRDMULH_LANE
{ .VQRDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR16,.NONE}, 0xF2900D40, 0xFFB00F50, .NEON, .A32, {} },
{ .VQRDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR16,.NONE}, 0xF3900D40, 0xFFB11F50, .NEON, .A32, {} },
{ .VQRDMULH_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {} },
{ .VQRDMULH_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR32,.NONE}, 0xF3A00D40, 0xFFB11F50, .NEON, .A32, {} },
// .VQRDMLAH
{ .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3100B10, 0xFFB00F10, .V8, .A32, {} },
{ .VQRDMLAH, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3200B10, 0xFFB00F10, .V8, .A32, {} },
@@ -2605,326 +2615,326 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{
.VQDMLSL = { 940, 2},
.VQDMULH = { 942, 4},
.VQRDMULH = { 946, 4},
.VQDMULH_LANE = { 950, 0},
.VQRDMULH_LANE = { 950, 0},
.VQRDMLAH = { 950, 4},
.VQRDMLSH = { 954, 4},
.VABA = { 958, 8},
.VABAL = { 966, 6},
.VABD = { 972, 10},
.VABDL = { 982, 6},
.VAND = { 988, 3},
.VBIC = { 991, 3},
.VORR = { 994, 3},
.VORN = { 997, 3},
.VEOR = { 1000, 3},
.VBSL = { 1003, 2},
.VBIT = { 1005, 2},
.VBIF = { 1007, 2},
.VMVN = { 1009, 13},
.VMOVN = { 1022, 3},
.VQMOVN = { 1025, 6},
.VQMOVUN = { 1031, 3},
.VMOVL = { 1034, 6},
.VTST = { 1040, 6},
.VCEQ = { 1046, 10},
.VCGE = { 1056, 12},
.VCGT = { 1068, 12},
.VCLE = { 1080, 14},
.VCLT = { 1094, 14},
.VACGE = { 1108, 2},
.VACGT = { 1110, 2},
.VACLE = { 1112, 2},
.VACLT = { 1114, 2},
.VMAX = { 1116, 13},
.VMIN = { 1129, 13},
.VPMAX = { 1142, 5},
.VPMIN = { 1147, 5},
.VPADD = { 1152, 4},
.VPADDL = { 1156, 6},
.VPADAL = { 1162, 4},
.VRECPE = { 1166, 4},
.VRECPS = { 1170, 2},
.VRSQRTE = { 1172, 4},
.VRSQRTS = { 1176, 2},
.VSHL = { 1178, 9},
.VSHR = { 1187, 5},
.VSRA = { 1192, 5},
.VRSHL = { 1197, 5},
.VRSHR = { 1202, 5},
.VRSRA = { 1207, 2},
.VSLI = { 1209, 2},
.VSRI = { 1211, 2},
.VQSHL = { 1213, 7},
.VQSHRN = { 1220, 2},
.VQSHRUN = { 1222, 1},
.VQRSHL = { 1223, 16},
.VQRSHRN = { 1239, 2},
.VQRSHRUN = { 1241, 1},
.VSHRN = { 1242, 1},
.VRSHRN = { 1243, 1},
.VSHLL = { 1244, 5},
.VCLS = { 1249, 6},
.VCLZ = { 1255, 6},
.VCNT = { 1261, 2},
.VPADD_F = { 1263, 2},
.VRECPE_F = { 1265, 2},
.VRSQRTE_F = { 1267, 2},
.VREV16 = { 1269, 2},
.VREV32 = { 1271, 4},
.VREV64 = { 1275, 6},
.VEXT = { 1281, 2},
.VTBL = { 1283, 4},
.VTBX = { 1287, 4},
.VTRN = { 1291, 6},
.VUZP = { 1297, 5},
.VZIP = { 1302, 5},
.VDUP = { 1307, 5},
.VSWP = { 1312, 2},
.VMOV_LANE = { 1314, 0},
.VLD1 = { 1314, 8},
.VLD2 = { 1322, 3},
.VLD3 = { 1325, 2},
.VLD4 = { 1327, 2},
.VST1 = { 1329, 7},
.VST2 = { 1336, 3},
.VST3 = { 1339, 2},
.VST4 = { 1341, 2},
.AESE = { 1343, 1},
.AESD = { 1344, 1},
.AESMC = { 1345, 1},
.AESIMC = { 1346, 1},
.SHA1H = { 1347, 1},
.SHA1SU0 = { 1348, 1},
.SHA1SU1 = { 1349, 1},
.SHA1C = { 1350, 1},
.SHA1M = { 1351, 1},
.SHA1P = { 1352, 1},
.SHA256H = { 1353, 1},
.SHA256H2 = { 1354, 1},
.SHA256SU0 = { 1355, 1},
.SHA256SU1 = { 1356, 1},
.VRINT = { 1357, 0},
.VJCVT = { 1357, 1},
.VSDOT = { 1358, 2},
.VUDOT = { 1360, 2},
.VSDOT_LANE = { 1362, 2},
.VUDOT_LANE = { 1364, 2},
.VCVT_BF16 = { 1366, 1},
.VDOT_BF16 = { 1367, 2},
.VFMA_BF16 = { 1369, 1},
.VMMLA_BF16 = { 1370, 1},
.VFMAL = { 1371, 2},
.VFMSL = { 1373, 2},
.VCMLA = { 1375, 2},
.VCADD = { 1377, 2},
.VCMLA_LANE = { 1379, 2},
.VSMMLA = { 1381, 1},
.VUMMLA = { 1382, 1},
.VUSMMLA = { 1383, 1},
.VSUDOT = { 1384, 1},
.VUSDOT = { 1385, 2},
.VSUDOT_LANE = { 1387, 1},
.VUSDOT_LANE = { 1388, 2},
.VMUL_LANE = { 1390, 6},
.VMLA_LANE = { 1396, 6},
.VMLS_LANE = { 1402, 6},
.VMULL_LANE = { 1408, 4},
.VMLAL_LANE = { 1412, 4},
.VMLSL_LANE = { 1416, 4},
.VQDMULL_LANE = { 1420, 2},
.VQDMLAL_LANE = { 1422, 2},
.VQDMLSL_LANE = { 1424, 2},
.VFMA_LANE = { 1426, 2},
.VFMS_LANE = { 1428, 2},
.VQRDMLAH_LANE = { 1430, 4},
.VQRDMLSH_LANE = { 1434, 4},
.VQABS = { 1438, 1},
.VQNEG = { 1439, 1},
.VMOVX = { 1440, 1},
.VINS = { 1441, 1},
.VLDRB_GATHER = { 1442, 1},
.VLDRH_GATHER = { 1443, 1},
.VLDRW_GATHER = { 1444, 1},
.VLDRD_GATHER = { 1445, 1},
.VSTRB_SCATTER = { 1446, 1},
.VSTRH_SCATTER = { 1447, 1},
.VSTRW_SCATTER = { 1448, 1},
.VSTRD_SCATTER = { 1449, 1},
.VCEQ_Z = { 1450, 4},
.VCGE_Z = { 1454, 4},
.VCGT_Z = { 1458, 4},
.VCLE_Z = { 1462, 4},
.VCLT_Z = { 1466, 4},
.VLD2R = { 1470, 1},
.VLD3R = { 1471, 1},
.VLD4R = { 1472, 1},
.VLD1_LANE = { 1473, 3},
.VLD2_LANE = { 1476, 3},
.VLD3_LANE = { 1479, 3},
.VLD4_LANE = { 1482, 3},
.VST1_LANE = { 1485, 3},
.VST2_LANE = { 1488, 3},
.VST3_LANE = { 1491, 3},
.VST4_LANE = { 1494, 3},
.VCVT_FIXED = { 1497, 10},
.IT = { 1507, 1},
.TT = { 1508, 1},
.TTT = { 1509, 1},
.TTA = { 1510, 1},
.TTAT = { 1511, 1},
.SG = { 1512, 1},
.BXNS = { 1513, 1},
.BLXNS = { 1514, 1},
.PAC = { 1515, 1},
.PACBTI = { 1516, 1},
.AUT = { 1517, 1},
.AUTG = { 1518, 1},
.BTI = { 1519, 1},
.WLS = { 1520, 1},
.WLSTP = { 1521, 1},
.DLS = { 1522, 1},
.DLSTP = { 1523, 1},
.LE = { 1524, 1},
.LETP = { 1525, 1},
.LCTP = { 1526, 1},
.BF = { 1527, 0},
.BFI_BR = { 1527, 0},
.BFL = { 1527, 0},
.BFLX = { 1527, 0},
.BFCSEL = { 1527, 0},
.CX1 = { 1527, 1},
.CX1A = { 1528, 1},
.CX1D = { 1529, 1},
.CX1DA = { 1530, 1},
.CX2 = { 1531, 1},
.CX2A = { 1532, 1},
.CX2D = { 1533, 1},
.CX2DA = { 1534, 1},
.CX3 = { 1535, 1},
.CX3A = { 1536, 1},
.CX3D = { 1537, 1},
.CX3DA = { 1538, 1},
.VCX1 = { 1539, 2},
.VCX1A = { 1541, 2},
.VCX2 = { 1543, 2},
.VCX2A = { 1545, 2},
.VCX3 = { 1547, 2},
.VCX3A = { 1549, 2},
.VPT = { 1551, 1},
.VPST = { 1552, 1},
.VPSEL = { 1553, 1},
.VPNOT = { 1554, 1},
.VCTP = { 1555, 1},
.VADDV = { 1556, 1},
.VADDVA = { 1557, 1},
.VADDLV = { 1558, 1},
.VADDLVA = { 1559, 1},
.VMAXV = { 1560, 1},
.VMAXAV = { 1561, 1},
.VMINV = { 1562, 1},
.VMINAV = { 1563, 1},
.VMAXNMV = { 1564, 1},
.VMAXNMAV = { 1565, 1},
.VMINNMV = { 1566, 1},
.VMINNMAV = { 1567, 1},
.VABAV = { 1568, 1},
.VMLADAV = { 1569, 1},
.VMLADAVA = { 1570, 1},
.VMLADAVX = { 1571, 1},
.VMLADAVAX = { 1572, 1},
.VMLALDAV = { 1573, 1},
.VMLALDAVA = { 1574, 1},
.VMLALDAVX = { 1575, 1},
.VMLALDAVAX = { 1576, 1},
.VMLSDAV = { 1577, 1},
.VMLSDAVA = { 1578, 1},
.VMLSDAVX = { 1579, 1},
.VMLSDAVAX = { 1580, 1},
.VMLSLDAV = { 1581, 1},
.VMLSLDAVA = { 1582, 1},
.VMLSLDAVX = { 1583, 1},
.VMLSLDAVAX = { 1584, 1},
.VRMLALDAVH = { 1585, 1},
.VRMLALDAVHA = { 1586, 1},
.VRMLALDAVHX = { 1587, 1},
.VRMLALDAVHAX = { 1588, 1},
.VRMLSLDAVH = { 1589, 1},
.VRMLSLDAVHA = { 1590, 1},
.VRMLSLDAVHX = { 1591, 1},
.VRMLSLDAVHAX = { 1592, 1},
.VMLAV = { 1593, 1},
.VMLAVA = { 1594, 1},
.VMLSV = { 1595, 0},
.VMLSVA = { 1595, 0},
.VCMUL = { 1595, 1},
.VHCADD = { 1596, 1},
.VBRSR = { 1597, 1},
.VSHLC = { 1598, 1},
.VRSHL_MVE = { 1599, 0},
.VDDUP = { 1599, 1},
.VIDUP = { 1600, 1},
.VDWDUP = { 1601, 1},
.VIWDUP = { 1602, 1},
.VMOVNB = { 1603, 1},
.VMOVNT = { 1604, 1},
.VQMOVNB = { 1605, 1},
.VQMOVNT = { 1606, 1},
.VQMOVUNB = { 1607, 1},
.VQMOVUNT = { 1608, 1},
.VSHLLB = { 1609, 1},
.VSHLLT = { 1610, 1},
.VMULLB = { 1611, 1},
.VMULLT = { 1612, 1},
.VMLALB = { 1613, 1},
.VMLALT = { 1614, 1},
.VMLSLB = { 1615, 1},
.VMLSLT = { 1616, 1},
.VSHRNB = { 1617, 1},
.VSHRNT = { 1618, 1},
.VRSHRNB = { 1619, 1},
.VRSHRNT = { 1620, 1},
.VQSHRNB = { 1621, 1},
.VQSHRNT = { 1622, 1},
.VQRSHRNB = { 1623, 1},
.VQRSHRNT = { 1624, 1},
.VQSHRUNB = { 1625, 1},
.VQSHRUNT = { 1626, 1},
.VQRSHRUNB = { 1627, 1},
.VQRSHRUNT = { 1628, 1},
.VMOV_Q_R = { 1629, 1},
.VMOV_R_Q = { 1630, 1},
.VMOV_2GPR_Q = { 1631, 1},
.VQDMLADH = { 1632, 1},
.VQDMLADHX = { 1633, 1},
.VQDMLSDH = { 1634, 1},
.VQDMLSDHX = { 1635, 1},
.VQRDMLADH = { 1636, 1},
.VQRDMLADHX = { 1637, 1},
.VQRDMLSDH = { 1638, 1},
.VQRDMLSDHX = { 1639, 1},
.VPRINT = { 1640, 0},
.VHCADD_SAT = { 1640, 0},
.VCMLA_MVE = { 1640, 0},
.VLDRB = { 1640, 1},
.VLDRH = { 1641, 1},
.VLDRW = { 1642, 1},
.VLDRD = { 1643, 1},
.VSTRB = { 1644, 1},
.VSTRH = { 1645, 1},
.VSTRW = { 1646, 1},
.VSTRD = { 1647, 1},
.VLD20 = { 1648, 1},
.VLD21 = { 1649, 1},
.VLD40 = { 1650, 1},
.VLD41 = { 1651, 1},
.VLD42 = { 1652, 1},
.VLD43 = { 1653, 1},
.VST20 = { 1654, 1},
.VST21 = { 1655, 1},
.VST40 = { 1656, 1},
.VST41 = { 1657, 1},
.VST42 = { 1658, 1},
.VST43 = { 1659, 1},
._COUNT = { 1660, 0},
.VQDMULH_LANE = { 950, 4},
.VQRDMULH_LANE = { 954, 4},
.VQRDMLAH = { 958, 4},
.VQRDMLSH = { 962, 4},
.VABA = { 966, 8},
.VABAL = { 974, 6},
.VABD = { 980, 10},
.VABDL = { 990, 6},
.VAND = { 996, 3},
.VBIC = { 999, 3},
.VORR = { 1002, 3},
.VORN = { 1005, 3},
.VEOR = { 1008, 3},
.VBSL = { 1011, 2},
.VBIT = { 1013, 2},
.VBIF = { 1015, 2},
.VMVN = { 1017, 13},
.VMOVN = { 1030, 3},
.VQMOVN = { 1033, 6},
.VQMOVUN = { 1039, 3},
.VMOVL = { 1042, 6},
.VTST = { 1048, 6},
.VCEQ = { 1054, 10},
.VCGE = { 1064, 12},
.VCGT = { 1076, 12},
.VCLE = { 1088, 14},
.VCLT = { 1102, 14},
.VACGE = { 1116, 2},
.VACGT = { 1118, 2},
.VACLE = { 1120, 2},
.VACLT = { 1122, 2},
.VMAX = { 1124, 13},
.VMIN = { 1137, 13},
.VPMAX = { 1150, 5},
.VPMIN = { 1155, 5},
.VPADD = { 1160, 4},
.VPADDL = { 1164, 6},
.VPADAL = { 1170, 4},
.VRECPE = { 1174, 4},
.VRECPS = { 1178, 2},
.VRSQRTE = { 1180, 4},
.VRSQRTS = { 1184, 2},
.VSHL = { 1186, 9},
.VSHR = { 1195, 5},
.VSRA = { 1200, 5},
.VRSHL = { 1205, 5},
.VRSHR = { 1210, 5},
.VRSRA = { 1215, 2},
.VSLI = { 1217, 2},
.VSRI = { 1219, 2},
.VQSHL = { 1221, 7},
.VQSHRN = { 1228, 2},
.VQSHRUN = { 1230, 1},
.VQRSHL = { 1231, 16},
.VQRSHRN = { 1247, 2},
.VQRSHRUN = { 1249, 1},
.VSHRN = { 1250, 1},
.VRSHRN = { 1251, 1},
.VSHLL = { 1252, 5},
.VCLS = { 1257, 6},
.VCLZ = { 1263, 6},
.VCNT = { 1269, 2},
.VPADD_F = { 1271, 2},
.VRECPE_F = { 1273, 2},
.VRSQRTE_F = { 1275, 2},
.VREV16 = { 1277, 2},
.VREV32 = { 1279, 4},
.VREV64 = { 1283, 6},
.VEXT = { 1289, 2},
.VTBL = { 1291, 4},
.VTBX = { 1295, 4},
.VTRN = { 1299, 6},
.VUZP = { 1305, 5},
.VZIP = { 1310, 5},
.VDUP = { 1315, 5},
.VSWP = { 1320, 2},
.VMOV_LANE = { 1322, 0},
.VLD1 = { 1322, 8},
.VLD2 = { 1330, 3},
.VLD3 = { 1333, 2},
.VLD4 = { 1335, 2},
.VST1 = { 1337, 7},
.VST2 = { 1344, 3},
.VST3 = { 1347, 2},
.VST4 = { 1349, 2},
.AESE = { 1351, 1},
.AESD = { 1352, 1},
.AESMC = { 1353, 1},
.AESIMC = { 1354, 1},
.SHA1H = { 1355, 1},
.SHA1SU0 = { 1356, 1},
.SHA1SU1 = { 1357, 1},
.SHA1C = { 1358, 1},
.SHA1M = { 1359, 1},
.SHA1P = { 1360, 1},
.SHA256H = { 1361, 1},
.SHA256H2 = { 1362, 1},
.SHA256SU0 = { 1363, 1},
.SHA256SU1 = { 1364, 1},
.VRINT = { 1365, 0},
.VJCVT = { 1365, 1},
.VSDOT = { 1366, 2},
.VUDOT = { 1368, 2},
.VSDOT_LANE = { 1370, 2},
.VUDOT_LANE = { 1372, 2},
.VCVT_BF16 = { 1374, 1},
.VDOT_BF16 = { 1375, 2},
.VFMA_BF16 = { 1377, 1},
.VMMLA_BF16 = { 1378, 1},
.VFMAL = { 1379, 2},
.VFMSL = { 1381, 2},
.VCMLA = { 1383, 2},
.VCADD = { 1385, 2},
.VCMLA_LANE = { 1387, 2},
.VSMMLA = { 1389, 1},
.VUMMLA = { 1390, 1},
.VUSMMLA = { 1391, 1},
.VSUDOT = { 1392, 1},
.VUSDOT = { 1393, 2},
.VSUDOT_LANE = { 1395, 1},
.VUSDOT_LANE = { 1396, 2},
.VMUL_LANE = { 1398, 6},
.VMLA_LANE = { 1404, 6},
.VMLS_LANE = { 1410, 6},
.VMULL_LANE = { 1416, 4},
.VMLAL_LANE = { 1420, 4},
.VMLSL_LANE = { 1424, 4},
.VQDMULL_LANE = { 1428, 2},
.VQDMLAL_LANE = { 1430, 2},
.VQDMLSL_LANE = { 1432, 2},
.VFMA_LANE = { 1434, 2},
.VFMS_LANE = { 1436, 2},
.VQRDMLAH_LANE = { 1438, 4},
.VQRDMLSH_LANE = { 1442, 4},
.VQABS = { 1446, 1},
.VQNEG = { 1447, 1},
.VMOVX = { 1448, 1},
.VINS = { 1449, 1},
.VLDRB_GATHER = { 1450, 1},
.VLDRH_GATHER = { 1451, 1},
.VLDRW_GATHER = { 1452, 1},
.VLDRD_GATHER = { 1453, 1},
.VSTRB_SCATTER = { 1454, 1},
.VSTRH_SCATTER = { 1455, 1},
.VSTRW_SCATTER = { 1456, 1},
.VSTRD_SCATTER = { 1457, 1},
.VCEQ_Z = { 1458, 4},
.VCGE_Z = { 1462, 4},
.VCGT_Z = { 1466, 4},
.VCLE_Z = { 1470, 4},
.VCLT_Z = { 1474, 4},
.VLD2R = { 1478, 1},
.VLD3R = { 1479, 1},
.VLD4R = { 1480, 1},
.VLD1_LANE = { 1481, 3},
.VLD2_LANE = { 1484, 3},
.VLD3_LANE = { 1487, 3},
.VLD4_LANE = { 1490, 3},
.VST1_LANE = { 1493, 3},
.VST2_LANE = { 1496, 3},
.VST3_LANE = { 1499, 3},
.VST4_LANE = { 1502, 3},
.VCVT_FIXED = { 1505, 10},
.IT = { 1515, 1},
.TT = { 1516, 1},
.TTT = { 1517, 1},
.TTA = { 1518, 1},
.TTAT = { 1519, 1},
.SG = { 1520, 1},
.BXNS = { 1521, 1},
.BLXNS = { 1522, 1},
.PAC = { 1523, 1},
.PACBTI = { 1524, 1},
.AUT = { 1525, 1},
.AUTG = { 1526, 1},
.BTI = { 1527, 1},
.WLS = { 1528, 1},
.WLSTP = { 1529, 1},
.DLS = { 1530, 1},
.DLSTP = { 1531, 1},
.LE = { 1532, 1},
.LETP = { 1533, 1},
.LCTP = { 1534, 1},
.BF = { 1535, 0},
.BFI_BR = { 1535, 0},
.BFL = { 1535, 0},
.BFLX = { 1535, 0},
.BFCSEL = { 1535, 0},
.CX1 = { 1535, 1},
.CX1A = { 1536, 1},
.CX1D = { 1537, 1},
.CX1DA = { 1538, 1},
.CX2 = { 1539, 1},
.CX2A = { 1540, 1},
.CX2D = { 1541, 1},
.CX2DA = { 1542, 1},
.CX3 = { 1543, 1},
.CX3A = { 1544, 1},
.CX3D = { 1545, 1},
.CX3DA = { 1546, 1},
.VCX1 = { 1547, 2},
.VCX1A = { 1549, 2},
.VCX2 = { 1551, 2},
.VCX2A = { 1553, 2},
.VCX3 = { 1555, 2},
.VCX3A = { 1557, 2},
.VPT = { 1559, 1},
.VPST = { 1560, 1},
.VPSEL = { 1561, 1},
.VPNOT = { 1562, 1},
.VCTP = { 1563, 1},
.VADDV = { 1564, 1},
.VADDVA = { 1565, 1},
.VADDLV = { 1566, 1},
.VADDLVA = { 1567, 1},
.VMAXV = { 1568, 1},
.VMAXAV = { 1569, 1},
.VMINV = { 1570, 1},
.VMINAV = { 1571, 1},
.VMAXNMV = { 1572, 1},
.VMAXNMAV = { 1573, 1},
.VMINNMV = { 1574, 1},
.VMINNMAV = { 1575, 1},
.VABAV = { 1576, 1},
.VMLADAV = { 1577, 1},
.VMLADAVA = { 1578, 1},
.VMLADAVX = { 1579, 1},
.VMLADAVAX = { 1580, 1},
.VMLALDAV = { 1581, 1},
.VMLALDAVA = { 1582, 1},
.VMLALDAVX = { 1583, 1},
.VMLALDAVAX = { 1584, 1},
.VMLSDAV = { 1585, 1},
.VMLSDAVA = { 1586, 1},
.VMLSDAVX = { 1587, 1},
.VMLSDAVAX = { 1588, 1},
.VMLSLDAV = { 1589, 1},
.VMLSLDAVA = { 1590, 1},
.VMLSLDAVX = { 1591, 1},
.VMLSLDAVAX = { 1592, 1},
.VRMLALDAVH = { 1593, 1},
.VRMLALDAVHA = { 1594, 1},
.VRMLALDAVHX = { 1595, 1},
.VRMLALDAVHAX = { 1596, 1},
.VRMLSLDAVH = { 1597, 1},
.VRMLSLDAVHA = { 1598, 1},
.VRMLSLDAVHX = { 1599, 1},
.VRMLSLDAVHAX = { 1600, 1},
.VMLAV = { 1601, 1},
.VMLAVA = { 1602, 1},
.VMLSV = { 1603, 0},
.VMLSVA = { 1603, 0},
.VCMUL = { 1603, 1},
.VHCADD = { 1604, 1},
.VBRSR = { 1605, 1},
.VSHLC = { 1606, 1},
.VRSHL_MVE = { 1607, 0},
.VDDUP = { 1607, 1},
.VIDUP = { 1608, 1},
.VDWDUP = { 1609, 1},
.VIWDUP = { 1610, 1},
.VMOVNB = { 1611, 1},
.VMOVNT = { 1612, 1},
.VQMOVNB = { 1613, 1},
.VQMOVNT = { 1614, 1},
.VQMOVUNB = { 1615, 1},
.VQMOVUNT = { 1616, 1},
.VSHLLB = { 1617, 1},
.VSHLLT = { 1618, 1},
.VMULLB = { 1619, 1},
.VMULLT = { 1620, 1},
.VMLALB = { 1621, 1},
.VMLALT = { 1622, 1},
.VMLSLB = { 1623, 1},
.VMLSLT = { 1624, 1},
.VSHRNB = { 1625, 1},
.VSHRNT = { 1626, 1},
.VRSHRNB = { 1627, 1},
.VRSHRNT = { 1628, 1},
.VQSHRNB = { 1629, 1},
.VQSHRNT = { 1630, 1},
.VQRSHRNB = { 1631, 1},
.VQRSHRNT = { 1632, 1},
.VQSHRUNB = { 1633, 1},
.VQSHRUNT = { 1634, 1},
.VQRSHRUNB = { 1635, 1},
.VQRSHRUNT = { 1636, 1},
.VMOV_Q_R = { 1637, 1},
.VMOV_R_Q = { 1638, 1},
.VMOV_2GPR_Q = { 1639, 1},
.VQDMLADH = { 1640, 1},
.VQDMLADHX = { 1641, 1},
.VQDMLSDH = { 1642, 1},
.VQDMLSDHX = { 1643, 1},
.VQRDMLADH = { 1644, 1},
.VQRDMLADHX = { 1645, 1},
.VQRDMLSDH = { 1646, 1},
.VQRDMLSDHX = { 1647, 1},
.VPRINT = { 1648, 0},
.VHCADD_SAT = { 1648, 0},
.VCMLA_MVE = { 1648, 0},
.VLDRB = { 1648, 1},
.VLDRH = { 1649, 1},
.VLDRW = { 1650, 1},
.VLDRD = { 1651, 1},
.VSTRB = { 1652, 1},
.VSTRH = { 1653, 1},
.VSTRW = { 1654, 1},
.VSTRD = { 1655, 1},
.VLD20 = { 1656, 1},
.VLD21 = { 1657, 1},
.VLD40 = { 1658, 1},
.VLD41 = { 1659, 1},
.VLD42 = { 1660, 1},
.VLD43 = { 1661, 1},
.VST20 = { 1662, 1},
.VST21 = { 1663, 1},
.VST40 = { 1664, 1},
.VST41 = { 1665, 1},
.VST42 = { 1666, 1},
.VST43 = { 1667, 1},
._COUNT = { 1668, 0},
}

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