From 7002c94a63c58aa0ac5a5d74b1fffd1511aeb699 Mon Sep 17 00:00:00 2001 From: gingerBill Date: Wed, 25 May 2022 23:34:41 +0100 Subject: [PATCH] Add `intrinsics.simd_select` --- core/simd/simd.odin | 1 + src/check_builtin.cpp | 51 +++++++++++++++++++++++++++++++++++ src/checker_builtin_procs.hpp | 2 ++ src/llvm_backend_proc.cpp | 12 +++++++++ 4 files changed, 66 insertions(+) diff --git a/core/simd/simd.odin b/core/simd/simd.odin index b5207e154..1819f3951 100644 --- a/core/simd/simd.odin +++ b/core/simd/simd.odin @@ -74,6 +74,7 @@ reduce_xor :: intrinsics.simd_reduce_xor swizzle :: builtin.swizzle shuffle :: intrinsics.simd_shuffle +select :: intrinsics.simd_select splat :: #force_inline proc "contextless" ($T: typeid/#simd[$LANES]$E, value: E) -> T { return T{0..args[0]); if (cond.mode == Addressing_Invalid) { return false; } + + if (!is_type_simd_vector(cond.type)) { + error(cond.expr, "'%.*s' expected a simd vector boolean type", LIT(builtin_name)); + return false; + } + if (!is_type_boolean(base_array_type(cond.type))) { + error(cond.expr, "'%.*s' expected a simd vector boolean type", LIT(builtin_name)); + return false; + } + + Operand x = {}; + Operand y = {}; + check_expr(c, &x, ce->args[1]); if (x.mode == Addressing_Invalid) { return false; } + check_expr_with_type_hint(c, &y, ce->args[2], x.type); if (y.mode == Addressing_Invalid) { return false; } + convert_to_typed(c, &y, x.type); + if (!is_type_simd_vector(x.type)) { + error(x.expr, "'%.*s' expected a simd vector type", LIT(builtin_name)); + return false; + } + if (!is_type_simd_vector(y.type)) { + error(y.expr, "'%.*s' expected a simd vector type", LIT(builtin_name)); + return false; + } + if (!are_types_identical(x.type, y.type)) { + gbString xs = type_to_string(x.type); + gbString ys = type_to_string(y.type); + error(x.expr, "'%.*s' expected 2 results of the same type, got '%s' vs '%s'", LIT(builtin_name), xs, ys); + gb_string_free(ys); + gb_string_free(xs); + return false; + } + + if (cond.type->SimdVector.count != x.type->SimdVector.count) { + error(x.expr, "'%.*s' expected condition vector to match the length of the result lengths, got '%lld' vs '%lld'", + LIT(builtin_name), + cast(long long)cond.type->SimdVector.count, + cast(long long)x.type->SimdVector.count); + return false; + } + + + operand->mode = Addressing_Value; + operand->type = x.type; + return true; + } + + // case BuiltinProc_simd_rotate_left: // { diff --git a/src/checker_builtin_procs.hpp b/src/checker_builtin_procs.hpp index 722bbec84..2fb355e91 100644 --- a/src/checker_builtin_procs.hpp +++ b/src/checker_builtin_procs.hpp @@ -159,6 +159,7 @@ BuiltinProc__simd_begin, BuiltinProc_simd_reduce_xor, BuiltinProc_simd_shuffle, + BuiltinProc_simd_select, BuiltinProc__simd_end, // Platform specific intrinsics @@ -421,6 +422,7 @@ gb_global BuiltinProc builtin_procs[BuiltinProc_COUNT] = { {STR_LIT("simd_reduce_xor"), 1, false, Expr_Expr, BuiltinProcPkg_intrinsics}, {STR_LIT("simd_shuffle"), 3, false, Expr_Expr, BuiltinProcPkg_intrinsics}, + {STR_LIT("simd_select"), 3, false, Expr_Expr, BuiltinProcPkg_intrinsics}, {STR_LIT(""), 0, false, Expr_Stmt, BuiltinProcPkg_intrinsics}, diff --git a/src/llvm_backend_proc.cpp b/src/llvm_backend_proc.cpp index 1b5d15d9b..7a86427d4 100644 --- a/src/llvm_backend_proc.cpp +++ b/src/llvm_backend_proc.cpp @@ -1296,6 +1296,18 @@ lbValue lb_build_builtin_simd_proc(lbProcedure *p, Ast *expr, TypeAndValue const res.value = LLVMBuildShuffleVector(p->builder, arg0.value, arg1.value, mask, ""); return res; } + + case BuiltinProc_simd_select: + { + LLVMValueRef cond = arg0.value; + LLVMValueRef x = lb_build_expr(p, ce->args[1]).value; + LLVMValueRef y = lb_build_expr(p, ce->args[2]).value; + + cond = LLVMBuildICmp(p->builder, LLVMIntNE, cond, LLVMConstNull(LLVMTypeOf(cond)), ""); + res.value = LLVMBuildSelect(p->builder, cond, x, y, ""); + return res; + } + } GB_PANIC("Unhandled simd intrinsic: '%.*s'", LIT(builtin_procs[builtin_id].name));