From 70daf40cb1058b5717baedd916f99ef2f84082a4 Mon Sep 17 00:00:00 2001 From: flysand7 Date: Sun, 2 Mar 2025 20:42:13 +1100 Subject: [PATCH] Fix documentation for simd_shuffle --- core/simd/simd.odin | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/core/simd/simd.odin b/core/simd/simd.odin index e91b12a4d..0bce4e16a 100644 --- a/core/simd/simd.odin +++ b/core/simd/simd.odin @@ -2013,7 +2013,7 @@ Example: // Since lanes 0, 1, 4, 7 contain negative numbers, the most significant // bits for them will be set. - v := #simd[8]i32 { -1, -2, +3, +4, -5, +6, +7, -8 } + v := #simd [8]i32 { -1, -2, +3, +4, -5, +6, +7, -8 } fmt.println(simd.extract_msbs(v)) Output: @@ -2052,7 +2052,7 @@ Example: // Since lanes 0, 2, 4, 6 contain odd integers, the least significant bits // for these lanes are set. - v := #simd[8]i32 { -1, -2, +3, +4, -5, +6, +7, -8 } + v := #simd [8]i32 { -1, -2, +3, +4, -5, +6, +7, -8 } fmt.println(simd.extract_lsbs(v)) Output: @@ -2100,8 +2100,7 @@ Example: a := #simd [4]f32 { 1, 2, 3, 4 } b := #simd [4]f32 { 5, 6, 7, 8 } - indices := #simd[4] - res := simd.swizzle(x, 0, 4, 2, 5) + res := simd.shuffle(a, b, 0, 4, 2, 5) fmt.println("res") Output: @@ -2164,7 +2163,6 @@ Example: // The following example selects values from the two input vectors, `a` and `b` // into a single vector. - a := #simd [4] f64 { 1,2,3,4 } b := #simd [4] f64 { 5,6,7,8 } cond := #simd[4] int { 1, 0, 1, 0 }