diff --git a/core/rexcode/arm32/instructions.odin b/core/rexcode/arm32/instructions.odin
index 690eeddf0..16d3f5761 100644
--- a/core/rexcode/arm32/instructions.odin
+++ b/core/rexcode/arm32/instructions.odin
@@ -21,7 +21,7 @@ Instruction_Flags :: bit_field u8 {
 }
 
 Instruction :: struct #packed {
-	ops:           [4]Operand `fmt:"v,operand_count"`, // 4 * 17 = 68
+	ops:           [4]Operand `fmt:"v,operand_count"`, // 4 * 22 = 88
 	mnemonic:      Mnemonic,                           // 2
 	cond:          u8,                                 // 0..15 (AL=14)
 	operand_count: u8,                                 // 0..4
@@ -36,7 +36,8 @@ Instruction :: struct #packed {
 	// falls back to first-shape-match. Stored as u16 over the two padding bytes.
 	form_id:       u16,
 }
-// 68 + 9 = 77 bytes (packed)
+#assert(size_of(Instruction) == 97)
+// 88 + 9 = 97 bytes (packed)
 
 // =============================================================================
 // Builders
diff --git a/core/rexcode/arm32/operands.odin b/core/rexcode/arm32/operands.odin
index 513716156..6cb81b6a3 100644
--- a/core/rexcode/arm32/operands.odin
+++ b/core/rexcode/arm32/operands.odin
@@ -106,9 +106,9 @@ Operand :: struct #packed {
 	shift_amt:  u8,           // immediate shift amount 0..31 (or Rs index for RSR)
 	lane:       u8,           // SIMD lane index for DPR_ELEM / QPR_ELEM
 	cond:       u8,           // condition code 0..15 (default = AL = 14)
-	_:          u8,
 }
-// 10-byte raw_union (Memory is largest) + 7 bytes of trailing fields = 17 bytes
+#assert(size_of(Operand) == 22)
+// 16-byte raw_union (Memory is largest) + 6 bytes of trailing fields = 22 bytes
 // (packed; no alignment padding).
 
 // ---- Operand builders ------------------------------------------------------