From 7ebe0422777e4bfd92f1aabc81d463a4305a9441 Mon Sep 17 00:00:00 2001 From: Brendan Punsky Date: Mon, 15 Jun 2026 21:22:07 -0400 Subject: [PATCH] rexcode/arm64: NEON wide / narrow / XTN encode forms Adds 24 more mixed-arrangement mnemonics (72 forms) via specgen: three-different wide (SADDW/UADDW/SSUBW/USUBW), narrowing-halving (ADDHN/SUBHN/RADDHN/RSUBHN), and two-register narrowing (XTN/SQXTN/UQXTN/SQXTUN), plus their high-half '2' variants. All register-only (VD/VN/VM or VD/VN), no encoder change. specgen refactored to a general arrangement-tuple mechanism (uniform + long/wide/narrow/XTN share one emit path). Verified: decode round-trips (SADDW/ADDHN/XTN/SQXTUN2), arm64 check + 461 tests pass. --- core/rexcode/arm64/mnemonic_builders.odin | 96 ++ .../arm64/tablegen/encoding_table.odin | 126 ++ .../tablegen/generated/decode_tables.odin | 476 +++--- .../tablegen/generated/encode_tables.odin | 1450 +++++++++-------- core/rexcode/arm64/tablegen/specgen.lua | 238 +-- .../arm64/tables/arm64.encode_forms.bin | Bin 30360 -> 31800 bytes .../arm64/tables/arm64.encode_runs.bin | Bin 8960 -> 8960 bytes core/rexcode/arm64/tables/arm64.entries.bin | Bin 30400 -> 31840 bytes core/rexcode/arm64/tables/arm64.idx_op0.bin | Bin 64 -> 64 bytes 9 files changed, 1393 insertions(+), 993 deletions(-) diff --git a/core/rexcode/arm64/mnemonic_builders.odin b/core/rexcode/arm64/mnemonic_builders.odin index 2cbb6dae7..a6f0c751f 100644 --- a/core/rexcode/arm64/mnemonic_builders.odin +++ b/core/rexcode/arm64/mnemonic_builders.odin @@ -805,6 +805,54 @@ inst_usubl_r_r_r :: #force_inline proc "contextless" (dst: Regist emit_usubl_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl_r_r_r(dst, src, src2)) } inst_usubl2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBL2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } emit_usubl2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubl2_r_r_r(dst, src, src2)) } +inst_saddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_saddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw_r_r_r(dst, src, src2)) } +inst_saddw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SADDW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_saddw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_saddw2_r_r_r(dst, src, src2)) } +inst_uaddw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_uaddw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw_r_r_r(dst, src, src2)) } +inst_uaddw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .UADDW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_uaddw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_uaddw2_r_r_r(dst, src, src2)) } +inst_ssubw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_ssubw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw_r_r_r(dst, src, src2)) } +inst_ssubw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SSUBW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_ssubw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_ssubw2_r_r_r(dst, src, src2)) } +inst_usubw_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } +emit_usubw_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw_r_r_r(dst, src, src2)) } +inst_usubw2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .USUBW2, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } +emit_usubw2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_usubw2_r_r_r(dst, src, src2)) } +inst_raddhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_raddhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn_r_r_r(dst, src, src2)) } +inst_raddhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_raddhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_raddhn2_r_r_r(dst, src, src2)) } +inst_rsubhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_rsubhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn_r_r_r(dst, src, src2)) } +inst_rsubhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .RSUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_rsubhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_rsubhn2_r_r_r(dst, src, src2)) } +inst_addhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_addhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn_r_r_r(dst, src, src2)) } +inst_addhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .ADDHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_addhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_addhn2_r_r_r(dst, src, src2)) } +inst_subhn_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN, operand_count = 3, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_subhn_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn_r_r_r(dst, src, src2)) } +inst_subhn2_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SUBHN2, operand_count = 3, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), op_v_8h(u8(reg_hw(src2))), {}}} } +emit_subhn2_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_subhn2_r_r_r(dst, src, src2)) } +inst_xtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_xtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn_r_r(dst, src)) } +inst_xtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .XTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_xtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_xtn2_r_r(dst, src)) } +inst_sqxtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_sqxtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn_r_r(dst, src)) } +inst_sqxtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_sqxtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtn2_r_r(dst, src)) } +inst_uqxtn_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_uqxtn_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn_r_r(dst, src)) } +inst_uqxtn2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .UQXTN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_uqxtn2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_uqxtn2_r_r(dst, src)) } +inst_sqxtun_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN, operand_count = 2, length = 4, ops = {op_v_8b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_sqxtun_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun_r_r(dst, src)) } +inst_sqxtun2_r_r :: #force_inline proc "contextless" (dst: Register, src: Register) -> Instruction { return Instruction{mnemonic = .SQXTUN2, operand_count = 2, length = 4, ops = {op_v_16b(u8(reg_hw(dst))), op_v_8h(u8(reg_hw(src))), {}, {}}} } +emit_sqxtun2_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register) { append(instructions, inst_sqxtun2_r_r(dst, src)) } inst_smull_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL_V, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_8b(u8(reg_hw(src))), op_v_8b(u8(reg_hw(src2))), {}}} } emit_smull_v_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_smull_v_r_r_r(dst, src, src2)) } inst_smull2_v_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SMULL2_V, operand_count = 3, length = 4, ops = {op_v_8h(u8(reg_hw(dst))), op_v_16b(u8(reg_hw(src))), op_v_16b(u8(reg_hw(src2))), {}}} } @@ -2508,6 +2556,54 @@ inst_usubl :: inst_usubl_r_r_r emit_usubl :: emit_usubl_r_r_r inst_usubl2 :: inst_usubl2_r_r_r emit_usubl2 :: emit_usubl2_r_r_r +inst_saddw :: inst_saddw_r_r_r +emit_saddw :: emit_saddw_r_r_r +inst_saddw2 :: inst_saddw2_r_r_r +emit_saddw2 :: emit_saddw2_r_r_r +inst_uaddw :: inst_uaddw_r_r_r +emit_uaddw :: emit_uaddw_r_r_r +inst_uaddw2 :: inst_uaddw2_r_r_r +emit_uaddw2 :: emit_uaddw2_r_r_r +inst_ssubw :: inst_ssubw_r_r_r +emit_ssubw :: emit_ssubw_r_r_r +inst_ssubw2 :: inst_ssubw2_r_r_r +emit_ssubw2 :: emit_ssubw2_r_r_r +inst_usubw :: inst_usubw_r_r_r +emit_usubw :: emit_usubw_r_r_r +inst_usubw2 :: inst_usubw2_r_r_r +emit_usubw2 :: emit_usubw2_r_r_r +inst_raddhn :: inst_raddhn_r_r_r +emit_raddhn :: emit_raddhn_r_r_r +inst_raddhn2 :: inst_raddhn2_r_r_r +emit_raddhn2 :: emit_raddhn2_r_r_r +inst_rsubhn :: inst_rsubhn_r_r_r +emit_rsubhn :: emit_rsubhn_r_r_r +inst_rsubhn2 :: inst_rsubhn2_r_r_r +emit_rsubhn2 :: emit_rsubhn2_r_r_r +inst_addhn :: inst_addhn_r_r_r +emit_addhn :: emit_addhn_r_r_r +inst_addhn2 :: inst_addhn2_r_r_r +emit_addhn2 :: emit_addhn2_r_r_r +inst_subhn :: inst_subhn_r_r_r +emit_subhn :: emit_subhn_r_r_r +inst_subhn2 :: inst_subhn2_r_r_r +emit_subhn2 :: emit_subhn2_r_r_r +inst_xtn :: inst_xtn_r_r +emit_xtn :: emit_xtn_r_r +inst_xtn2 :: inst_xtn2_r_r +emit_xtn2 :: emit_xtn2_r_r +inst_sqxtn :: inst_sqxtn_r_r +emit_sqxtn :: emit_sqxtn_r_r +inst_sqxtn2 :: inst_sqxtn2_r_r +emit_sqxtn2 :: emit_sqxtn2_r_r +inst_uqxtn :: inst_uqxtn_r_r +emit_uqxtn :: emit_uqxtn_r_r +inst_uqxtn2 :: inst_uqxtn2_r_r +emit_uqxtn2 :: emit_uqxtn2_r_r +inst_sqxtun :: inst_sqxtun_r_r +emit_sqxtun :: emit_sqxtun_r_r +inst_sqxtun2 :: inst_sqxtun2_r_r +emit_sqxtun2 :: emit_sqxtun2_r_r inst_smull_v :: inst_smull_v_r_r_r emit_smull_v :: emit_smull_v_r_r_r inst_smull2_v :: inst_smull2_v_r_r_r diff --git a/core/rexcode/arm64/tablegen/encoding_table.odin b/core/rexcode/arm64/tablegen/encoding_table.odin index fe9c468fd..6b268c92d 100644 --- a/core/rexcode/arm64/tablegen/encoding_table.odin +++ b/core/rexcode/arm64/tablegen/encoding_table.odin @@ -3441,5 +3441,131 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.SQDMLSL2, {.V_4S, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {}}, {.SQDMLSL2, {.V_2D, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {}}, }, + + // Advanced SIMD three-different (wide). + .SADDW = { + {.SADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {}}, + {.SADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {}}, + {.SADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {}}, + }, + .SADDW2 = { + {.SADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {}}, + {.SADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {}}, + {.SADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {}}, + }, + .UADDW = { + {.UADDW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {}}, + {.UADDW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {}}, + {.UADDW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {}}, + }, + .UADDW2 = { + {.UADDW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {}}, + {.UADDW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {}}, + {.UADDW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {}}, + }, + .SSUBW = { + {.SSUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {}}, + {.SSUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {}}, + {.SSUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {}}, + }, + .SSUBW2 = { + {.SSUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {}}, + {.SSUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {}}, + {.SSUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {}}, + }, + .USUBW = { + {.USUBW, {.V_8H, .V_8H, .V_8B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {}}, + {.USUBW, {.V_4S, .V_4S, .V_4H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {}}, + {.USUBW, {.V_2D, .V_2D, .V_2S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {}}, + }, + .USUBW2 = { + {.USUBW2, {.V_8H, .V_8H, .V_16B, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {}}, + {.USUBW2, {.V_4S, .V_4S, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {}}, + {.USUBW2, {.V_2D, .V_2D, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {}}, + }, + + // Advanced SIMD three-different (narrow, halving). + .ADDHN = { + {.ADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {}}, + {.ADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {}}, + {.ADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {}}, + }, + .ADDHN2 = { + {.ADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {}}, + {.ADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {}}, + {.ADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {}}, + }, + .SUBHN = { + {.SUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {}}, + {.SUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {}}, + {.SUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {}}, + }, + .SUBHN2 = { + {.SUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {}}, + {.SUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {}}, + {.SUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {}}, + }, + .RADDHN = { + {.RADDHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {}}, + {.RADDHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {}}, + {.RADDHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {}}, + }, + .RADDHN2 = { + {.RADDHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {}}, + {.RADDHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {}}, + {.RADDHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {}}, + }, + .RSUBHN = { + {.RSUBHN, {.V_8B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {}}, + {.RSUBHN, {.V_4H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {}}, + {.RSUBHN, {.V_2S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {}}, + }, + .RSUBHN2 = { + {.RSUBHN2, {.V_16B, .V_8H, .V_8H, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {}}, + {.RSUBHN2, {.V_8H, .V_4S, .V_4S, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {}}, + {.RSUBHN2, {.V_4S, .V_2D, .V_2D, .NONE}, {.VD, .VN, .VM, .NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {}}, + }, + + // Advanced SIMD two-register narrowing (XTN). + .XTN = { + {.XTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {}}, + {.XTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {}}, + {.XTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {}}, + }, + .XTN2 = { + {.XTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {}}, + {.XTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {}}, + {.XTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {}}, + }, + .SQXTN = { + {.SQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {}}, + {.SQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {}}, + {.SQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {}}, + }, + .SQXTN2 = { + {.SQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {}}, + {.SQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {}}, + {.SQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {}}, + }, + .UQXTN = { + {.UQXTN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {}}, + {.UQXTN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {}}, + {.UQXTN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {}}, + }, + .UQXTN2 = { + {.UQXTN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {}}, + {.UQXTN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {}}, + {.UQXTN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {}}, + }, + .SQXTUN = { + {.SQXTUN, {.V_8B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {}}, + {.SQXTUN, {.V_4H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {}}, + {.SQXTUN, {.V_2S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {}}, + }, + .SQXTUN2 = { + {.SQXTUN2, {.V_16B, .V_8H, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {}}, + {.SQXTUN2, {.V_8H, .V_4S, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {}}, + {.SQXTUN2, {.V_4S, .V_2D, .NONE, .NONE}, {.VD, .VN, .NONE, .NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {}}, + }, // SPECGEN:END } diff --git a/core/rexcode/arm64/tablegen/generated/decode_tables.odin b/core/rexcode/arm64/tablegen/generated/decode_tables.odin index 4b4ed277c..12c972fc5 100644 --- a/core/rexcode/arm64/tablegen/generated/decode_tables.odin +++ b/core/rexcode/arm64/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [1520]lib.Decode_Entry{ +DECODE_ENTRIES := [1592]lib.Decode_Entry{ { .AMX_SET, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201220, 0xFFFFFFFF, .AMX, {} }, { .AMX_CLR, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x00201240, 0xFFFFFFFF, .AMX, {} }, { .AMX_LDX, {.X_REG,.NONE,.NONE,.NONE}, {.RT,.NONE,.NONE,.NONE}, 0x00201000, 0xFFFFFFE0, .AMX, {is_64=true} }, @@ -60,14 +60,14 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .SME_FMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_S}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x80800010, 0xFFE08010, .SME, {} }, { .SME_BFMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800000, 0xFFE08010, .SME, {} }, { .SME_BFMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0x81800010, 0xFFE08010, .SME, {} }, - { .SME_SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, { .SME_SMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800000, 0xFFE08010, .SME, {} }, + { .SME_SMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00000, 0xFFE08010, .SME, {is_64=true} }, { .SME_SMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA0C00010, 0xFFE08010, .SME, {is_64=true} }, { .SME_SMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0800010, 0xFFE08010, .SME, {} }, { .SME_UMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00000, 0xFFE08010, .SME, {} }, { .SME_UMOPA, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00000, 0xFFE08010, .SME, {is_64=true} }, - { .SME_UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {} }, { .SME_UMOPS, {.ZA_TILE_D,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_H}, {.ZA_TILE_NUM_D,.PG,.PM3,.VN}, 0xA1E00010, 0xFFE08010, .SME, {is_64=true} }, + { .SME_UMOPS, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1A00010, 0xFFE08010, .SME, {} }, { .SME_USMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA1800000, 0xFFE08010, .SME, {} }, { .SME_SUMOPA, {.ZA_TILE_S,.P_REG_MERGE,.P_REG_MERGE,.Z_REG_B}, {.ZA_TILE_NUM_S,.PG,.PM3,.VN}, 0xA0A00000, 0xFFE08010, .SME, {} }, { .SME_MOVA_Z_FROM_TILE, {.Z_REG_B,.P_REG_MERGE,.SME_SLICE_B,.NONE}, {.VD,.PG,.SME_SLICE_B,.NONE}, 0xC0020000, 0xFFE08010, .SME, {} }, @@ -92,12 +92,12 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .SVE_REV_P, {.P_REG,.P_REG,.NONE,.NONE}, {.PD,.PN,.NONE,.NONE}, 0x05344000, 0xFFFFFE10, .SVE, {} }, { .SVE_PTRUE, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2518E000, 0xFFFFFC10, .SVE, {} }, { .SVE_PTRUES, {.P_REG,.SVE_PATTERN,.NONE,.NONE}, {.PD,.SVE_PATTERN,.NONE,.NONE}, 0x2519E000, 0xFFFFFC10, .SVE, {sets_flags=true} }, - { .SVE_DUP_Z, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} }, + { .SVE_DUP_Z, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, { .SVE_DUP_Z, {.Z_REG_H,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05603800, 0xFFFFFC00, .SVE, {} }, { .SVE_DUP_Z, {.Z_REG_D,.X_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05E03800, 0xFFFFFC00, .SVE, {is_64=true} }, - { .SVE_DUP_Z, {.Z_REG_B,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05203800, 0xFFFFFC00, .SVE, {} }, - { .SVE_REV_Z, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {} }, + { .SVE_DUP_Z, {.Z_REG_S,.W_REG,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05A03800, 0xFFFFFC00, .SVE, {} }, { .SVE_REV_Z, {.Z_REG_H,.Z_REG_H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05783800, 0xFFFFFC00, .SVE, {} }, + { .SVE_REV_Z, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05383800, 0xFFFFFC00, .SVE, {} }, { .SVE_REV_Z, {.Z_REG_D,.Z_REG_D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05F83800, 0xFFFFFC00, .SVE, {is_64=true} }, { .SVE_REV_Z, {.Z_REG_S,.Z_REG_S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x05B83800, 0xFFFFFC00, .SVE, {} }, { .SVE_AESE, {.Z_REG_B,.Z_REG_B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4522E000, 0xFFFFFC00, .SVE2, {} }, @@ -116,86 +116,86 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .SVE_SPLICE, {.Z_REG_B,.P_REG_GOV,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VN}, 0x052C8000, 0xFFFFE000, .SVE, {} }, { .SVE_BFCVT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658AA000, 0xFFFFE000, .SVE, {} }, { .SVE_BFCVTNT, {.Z_REG_H,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x648AA000, 0xFFFFE000, .SVE, {} }, + { .SVE_ADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} }, + { .SVE_ADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {} }, { .SVE_ADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_ADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200000, 0xFFE0FC00, .SVE, {} }, - { .SVE_ADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00000, 0xFFE0FC00, .SVE, {} }, - { .SVE_SUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_SUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} }, { .SVE_SUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A00400, 0xFFE0FC00, .SVE, {} }, + { .SVE_SUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04200400, 0xFFE0FC00, .SVE, {} }, + { .SVE_SUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04600400, 0xFFE0FC00, .SVE, {} }, + { .SVE_SUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E00400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_SQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_SQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601000, 0xFFE0FC00, .SVE, {} }, { .SVE_SQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201000, 0xFFE0FC00, .SVE, {} }, { .SVE_SQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01000, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_UQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, { .SVE_UQADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_UQADD_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201400, 0xFFE0FC00, .SVE, {} }, + { .SVE_UQADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601400, 0xFFE0FC00, .SVE, {} }, { .SVE_UQADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01400, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, - { .SVE_SQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_SQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01800, 0xFFE0FC00, .SVE, {} }, + { .SVE_SQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_SQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201800, 0xFFE0FC00, .SVE, {} }, { .SVE_SQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_UQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, { .SVE_UQSUB_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04201C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} }, + { .SVE_UQSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04601C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_UQSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04A01C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_UQSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x04E01C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_FADD_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_FADD_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400000, 0xFFE0FC00, .SVE, {} }, { .SVE_FADD_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800000, 0xFFE0FC00, .SVE, {} }, { .SVE_FSUB_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800400, 0xFFE0FC00, .SVE, {} }, { .SVE_FSUB_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400400, 0xFFE0FC00, .SVE, {} }, { .SVE_FSUB_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00400, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_FMUL_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, { .SVE_FMUL_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_FMUL_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800800, 0xFFE0FC00, .SVE, {} }, { .SVE_FMUL_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, { .SVE_FRECPS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01800, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_FRECPS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801800, 0xFFE0FC00, .SVE, {} }, { .SVE_FRECPS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401800, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, { .SVE_FRSQRTS, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C01C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_FRSQRTS, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65801C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_FRSQRTS, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65401C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, { .SVE_FTSMUL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65C00C00, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_FTSMUL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65400C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_FTSMUL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x65800C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, { .SVE_TBL, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05603000, 0xFFE0FC00, .SVE, {} }, { .SVE_TBL, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05203000, 0xFFE0FC00, .SVE, {} }, { .SVE_TBL, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E03000, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_TBL, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A03000, 0xFFE0FC00, .SVE, {} }, { .SVE_ZIP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206000, 0xFFE0FC00, .SVE, {} }, { .SVE_ZIP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606000, 0xFFE0FC00, .SVE, {} }, { .SVE_ZIP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06000, 0xFFE0FC00, .SVE, {} }, { .SVE_ZIP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_ZIP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, - { .SVE_ZIP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_ZIP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206400, 0xFFE0FC00, .SVE, {} }, { .SVE_ZIP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06400, 0xFFE0FC00, .SVE, {} }, + { .SVE_ZIP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606400, 0xFFE0FC00, .SVE, {} }, + { .SVE_ZIP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06400, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_UZP1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06800, 0xFFE0FC00, .SVE, {} }, { .SVE_UZP1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06800, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_UZP1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206800, 0xFFE0FC00, .SVE, {} }, { .SVE_UZP1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606800, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_UZP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_UZP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, { .SVE_UZP2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A06C00, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, + { .SVE_UZP2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E06C00, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_UZP2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05606C00, 0xFFE0FC00, .SVE, {} }, + { .SVE_UZP2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05206C00, 0xFFE0FC00, .SVE, {} }, { .SVE_TRN1_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07000, 0xFFE0FC00, .SVE, {is_64=true} }, - { .SVE_TRN1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, + { .SVE_TRN1_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607000, 0xFFE0FC00, .SVE, {} }, { .SVE_TRN1_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207000, 0xFFE0FC00, .SVE, {} }, + { .SVE_TRN1_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07000, 0xFFE0FC00, .SVE, {} }, + { .SVE_TRN2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, + { .SVE_TRN2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, { .SVE_TRN2_Z, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05A07400, 0xFFE0FC00, .SVE, {} }, { .SVE_TRN2_Z, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05607400, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN2_Z, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05207400, 0xFFE0FC00, .SVE, {} }, - { .SVE_TRN2_Z, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x05E07400, 0xFFE0FC00, .SVE, {is_64=true} }, { .SVE_SQRDMLAH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SVE_SQRDMLAH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} }, { .SVE_SQRDMLAH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007000, 0xFFE0FC00, .SVE2, {} }, - { .SVE_SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, + { .SVE_SQRDMLAH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807000, 0xFFE0FC00, .SVE2, {} }, { .SVE_SQRDMLSH, {.Z_REG_B,.Z_REG_B,.Z_REG_B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44007400, 0xFFE0FC00, .SVE2, {} }, { .SVE_SQRDMLSH, {.Z_REG_H,.Z_REG_H,.Z_REG_H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44407400, 0xFFE0FC00, .SVE2, {} }, + { .SVE_SQRDMLSH, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44807400, 0xFFE0FC00, .SVE2, {} }, { .SVE_SQRDMLSH, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x44C07400, 0xFFE0FC00, .SVE2, {is_64=true} }, - { .SVE_ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SVE_ADCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D000, 0xFFE0FC00, .SVE2, {} }, + { .SVE_ADCLB, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D000, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SVE_ADCLT, {.Z_REG_D,.Z_REG_D,.Z_REG_D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4540D400, 0xFFE0FC00, .SVE2, {is_64=true} }, { .SVE_ADCLT, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4500D400, 0xFFE0FC00, .SVE2, {} }, { .SVE_SBCLB, {.Z_REG_S,.Z_REG_S,.Z_REG_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4580D000, 0xFFE0FC00, .SVE2, {} }, @@ -246,22 +246,22 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .SVE_BICS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404010, 0xFFE0C210, .SVE, {sets_flags=true} }, { .SVE_ORRS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25C04000, 0xFFE0C210, .SVE, {sets_flags=true} }, { .SVE_EORS_P, {.P_REG,.P_REG_ZERO,.P_REG,.P_REG}, {.PD,.PG4,.PN,.PM}, 0x25404200, 0xFFE0C210, .SVE, {sets_flags=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, - { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .SVE_CMPNE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408000, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008000, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPGE, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24008010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24808010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24408010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPGT, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C08010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000010, 0xFFE0E010, .SVE, {sets_flags=true} }, - { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00010, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x24400010, 0xFFE0E010, .SVE, {sets_flags=true} }, + { .SVE_CMPHI, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800010, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x24000000, 0xFFE0E010, .SVE, {sets_flags=true} }, { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C00000, 0xFFE0E010, .SVE, {sets_flags=true, is_64=true} }, { .SVE_CMPHS, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x24800000, 0xFFE0E010, .SVE, {sets_flags=true} }, @@ -272,139 +272,139 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .SVE_MATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608000, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .SVE_NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x45208010, 0xFFE0E010, .SVE2, {sets_flags=true} }, { .SVE_NMATCH, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x45608010, 0xFFE0E010, .SVE2, {sets_flags=true} }, - { .SVE_ADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} }, { .SVE_ADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_ADD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, { .SVE_ADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04800000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUB_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} }, + { .SVE_ADD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04000000, 0xFFE0E000, .SVE, {} }, + { .SVE_ADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04400000, 0xFFE0E000, .SVE, {} }, { .SVE_SUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C10000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04810000, 0xFFE0E000, .SVE, {} }, + { .SVE_SUB_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04010000, 0xFFE0E000, .SVE, {} }, + { .SVE_SUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04410000, 0xFFE0E000, .SVE, {} }, { .SVE_SUBR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04030000, 0xFFE0E000, .SVE, {} }, { .SVE_SUBR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04430000, 0xFFE0E000, .SVE, {} }, - { .SVE_SUBR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SUBR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04830000, 0xFFE0E000, .SVE, {} }, + { .SVE_SUBR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C30000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_MUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D00000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_MUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, { .SVE_MUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04900000, 0xFFE0E000, .SVE, {} }, { .SVE_MUL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04100000, 0xFFE0E000, .SVE, {} }, - { .SVE_MUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04500000, 0xFFE0E000, .SVE, {} }, + { .SVE_SMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {} }, + { .SVE_SMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {} }, { .SVE_SMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04120000, 0xFFE0E000, .SVE, {} }, { .SVE_SMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D20000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04520000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04920000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_UMULH_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04930000, 0xFFE0E000, .SVE, {} }, { .SVE_UMULH_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04130000, 0xFFE0E000, .SVE, {} }, { .SVE_UMULH_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04530000, 0xFFE0E000, .SVE, {} }, - { .SVE_SDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_UMULH_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D30000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_SDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04940000, 0xFFE0E000, .SVE, {} }, + { .SVE_SDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D40000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_UDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04950000, 0xFFE0E000, .SVE, {} }, { .SVE_UDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D50000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, { .SVE_SMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04480000, 0xFFE0E000, .SVE, {} }, { .SVE_SMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C80000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_SMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04080000, 0xFFE0E000, .SVE, {} }, { .SVE_SMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04880000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, { .SVE_UMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04C90000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_UMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04490000, 0xFFE0E000, .SVE, {} }, + { .SVE_UMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04890000, 0xFFE0E000, .SVE, {} }, { .SVE_UMAX_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04090000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, { .SVE_SMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040A0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, + { .SVE_SMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044A0000, 0xFFE0E000, .SVE, {} }, + { .SVE_SMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048A0000, 0xFFE0E000, .SVE, {} }, + { .SVE_SMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CA0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_UMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CB0000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_UMIN_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040B0000, 0xFFE0E000, .SVE, {} }, { .SVE_UMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048B0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_SABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, - { .SVE_SABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, + { .SVE_UMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044B0000, 0xFFE0E000, .SVE, {} }, { .SVE_SABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048C0000, 0xFFE0E000, .SVE, {} }, - { .SVE_UABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, + { .SVE_SABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044C0000, 0xFFE0E000, .SVE, {} }, + { .SVE_SABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040C0000, 0xFFE0E000, .SVE, {} }, + { .SVE_SABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CC0000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_UABD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x048D0000, 0xFFE0E000, .SVE, {} }, { .SVE_UABD_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x040D0000, 0xFFE0E000, .SVE, {} }, + { .SVE_UABD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x044D0000, 0xFFE0E000, .SVE, {} }, { .SVE_UABD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04CD0000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_ASR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, - { .SVE_ASR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_ASR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04908000, 0xFFE0E000, .SVE, {} }, + { .SVE_ASR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D08000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_ASR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04508000, 0xFFE0E000, .SVE, {} }, { .SVE_ASR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04108000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {} }, { .SVE_LSL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04538000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_LSL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04938000, 0xFFE0E000, .SVE, {} }, { .SVE_LSL_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04138000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_LSL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D38000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_LSR_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x04918000, 0xFFE0E000, .SVE, {} }, - { .SVE_LSR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, + { .SVE_LSR_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x04D18000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_LSR_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.Z_REG_B}, {.VD,.PG,.VD,.VM}, 0x04118000, 0xFFE0E000, .SVE, {} }, - { .SVE_ABS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, + { .SVE_LSR_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x04518000, 0xFFE0E000, .SVE, {} }, { .SVE_ABS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0496A000, 0xFFE0E000, .SVE, {} }, - { .SVE_ABS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_ABS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0416A000, 0xFFE0E000, .SVE, {} }, + { .SVE_ABS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D6A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_ABS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0456A000, 0xFFE0E000, .SVE, {} }, { .SVE_NEG_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0457A000, 0xFFE0E000, .SVE, {} }, - { .SVE_NEG_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, { .SVE_NEG_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0417A000, 0xFFE0E000, .SVE, {} }, { .SVE_NEG_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D7A000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_NEG_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0497A000, 0xFFE0E000, .SVE, {} }, { .SVE_CLS_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0418A000, 0xFFE0E000, .SVE, {} }, + { .SVE_CLS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {} }, { .SVE_CLS_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0458A000, 0xFFE0E000, .SVE, {} }, { .SVE_CLS_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D8A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_CLS_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0498A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLZ_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLZ_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {} }, - { .SVE_CLZ_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} }, { .SVE_CLZ_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04D9A000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_CNT_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_CNT_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, + { .SVE_CLZ_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0459A000, 0xFFE0E000, .SVE, {} }, + { .SVE_CLZ_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0499A000, 0xFFE0E000, .SVE, {} }, + { .SVE_CLZ_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x0419A000, 0xFFE0E000, .SVE, {} }, { .SVE_CNT_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049AA000, 0xFFE0E000, .SVE, {} }, { .SVE_CNT_PRED, {.Z_REG_B,.P_REG_MERGE,.Z_REG_B,.NONE}, {.VD,.PG,.VN,.NONE}, 0x041AA000, 0xFFE0E000, .SVE, {} }, + { .SVE_CNT_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045AA000, 0xFFE0E000, .SVE, {} }, + { .SVE_CNT_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DAA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, { .SVE_FADD_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65808000, 0xFFE0E000, .SVE, {} }, { .SVE_FADD_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C08000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FADD_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65408000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} }, { .SVE_FSUB_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C18000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FSUB_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65818000, 0xFFE0E000, .SVE, {} }, + { .SVE_FSUB_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65418000, 0xFFE0E000, .SVE, {} }, { .SVE_FMUL_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65828000, 0xFFE0E000, .SVE, {} }, - { .SVE_FDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FDIV_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMUL_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C28000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FMUL_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65428000, 0xFFE0E000, .SVE, {} }, { .SVE_FDIV_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x658D8000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, + { .SVE_FDIV_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x654D8000, 0xFFE0E000, .SVE, {} }, + { .SVE_FDIV_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65CD8000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMAX_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65468000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMAX_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65868000, 0xFFE0E000, .SVE, {} }, { .SVE_FMAX_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C68000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMIN_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65878000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMIN_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C78000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMIN_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65478000, 0xFFE0E000, .SVE, {} }, { .SVE_FMAXNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65448000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMAXNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMAXNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65848000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMINNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMINNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMAXNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C48000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FMINNM_PRED, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VD,.VM}, 0x65C58000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FMINNM_PRED, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VD,.VM}, 0x65458000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMINNM_PRED, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VD,.VM}, 0x65858000, 0xFFE0E000, .SVE, {} }, + { .SVE_FABS_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} }, { .SVE_FABS_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DCA000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FABS_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045CA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FABS_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049CA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNEG_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} }, { .SVE_FNEG_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x049DA000, 0xFFE0E000, .SVE, {} }, + { .SVE_FNEG_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x045DA000, 0xFFE0E000, .SVE, {} }, { .SVE_FNEG_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x04DDA000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FSQRT_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, { .SVE_FSQRT_Z, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.NONE}, {.VD,.PG,.VN,.NONE}, 0x65CDA000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FSQRT_Z, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.NONE}, {.VD,.PG,.VN,.NONE}, 0x654DA000, 0xFFE0E000, .SVE, {} }, - { .SVE_FSQRT_Z, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.NONE}, {.VD,.PG,.VN,.NONE}, 0x658DA000, 0xFFE0E000, .SVE, {} }, { .SVE_FMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65600000, 0xFFE0E000, .SVE, {} }, - { .SVE_FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, { .SVE_FMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E00000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A00000, 0xFFE0E000, .SVE, {} }, { .SVE_FMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65602000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A02000, 0xFFE0E000, .SVE, {} }, + { .SVE_FMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E02000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FNMLA, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65604000, 0xFFE0E000, .SVE, {} }, - { .SVE_FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} }, + { .SVE_FNMLA, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A04000, 0xFFE0E000, .SVE, {} }, + { .SVE_FNMLA, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E04000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FNMLS, {.Z_REG_S,.P_REG_MERGE,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x65A06000, 0xFFE0E000, .SVE, {} }, + { .SVE_FNMLS, {.Z_REG_D,.P_REG_MERGE,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x65E06000, 0xFFE0E000, .SVE, {is_64=true} }, { .SVE_FNMLS, {.Z_REG_H,.P_REG_MERGE,.Z_REG_H,.Z_REG_H}, {.VD,.PG,.VN,.VM}, 0x65606000, 0xFFE0E000, .SVE, {} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, - { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} }, { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.PD,.PG,.VN,.VM}, 0x24C0A000, 0xFFE0E000, .SVE, {sets_flags=true, is_64=true} }, + { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_H,.Z_REG_H}, {.PD,.PG,.VN,.VM}, 0x2440A000, 0xFFE0E000, .SVE, {sets_flags=true} }, + { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.PD,.PG,.VN,.VM}, 0x2480A000, 0xFFE0E000, .SVE, {sets_flags=true} }, + { .SVE_CMPEQ, {.P_REG,.P_REG_ZERO,.Z_REG_B,.Z_REG_B}, {.PD,.PG,.VN,.VM}, 0x2400A000, 0xFFE0E000, .SVE, {sets_flags=true} }, { .SVE_LD1B, {.Z_REG_B,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4004000, 0xFFE0E000, .SVE, {} }, { .SVE_LD1H, {.Z_REG_H,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A04000, 0xFFE0E000, .SVE, {} }, { .SVE_LD1W, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5404000, 0xFFE0E000, .SVE, {} }, @@ -422,8 +422,8 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .SVE_LDFF1H, {.Z_REG_H,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA4A06000, 0xFFE0E000, .SVE, {} }, { .SVE_LDFF1W, {.Z_REG_S,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5406000, 0xFFE0E000, .SVE, {} }, { .SVE_LDFF1D, {.Z_REG_D,.P_REG_ZERO,.MEM,.NONE}, {.VD,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0xA5E06000, 0xFFE0E000, .SVE, {is_64=true} }, - { .SVE_HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true} }, { .SVE_HISTCNT, {.Z_REG_S,.P_REG_ZERO,.Z_REG_S,.Z_REG_S}, {.VD,.PG,.VN,.VM}, 0x45A0C000, 0xFFE0E000, .SVE2, {} }, + { .SVE_HISTCNT, {.Z_REG_D,.P_REG_ZERO,.Z_REG_D,.Z_REG_D}, {.VD,.PG,.VN,.VM}, 0x45E0C000, 0xFFE0E000, .SVE2, {is_64=true} }, { .SVE_PRFB, {.IMM_4,.P_REG_GOV,.MEM,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8400C000, 0xFFE0E000, .SVE, {} }, { .SVE_PRFH, {.IMM_4,.P_REG_GOV,.MEM,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8480C000, 0xFFE0E000, .SVE, {} }, { .SVE_PRFW, {.IMM_4,.P_REG_GOV,.MEM,.NONE}, {.ENC_SVE_PRFOP,.PG,.SVE_OFFSET_BASE_SS,.NONE}, 0x8500C000, 0xFFE0E000, .SVE, {} }, @@ -541,22 +541,22 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .STGP, {.X_REG,.X_REG,.MEM,.NONE}, {.RT,.RT2,.OFFSET_BASE_S9,.NONE}, 0x69000000, 0xFFC00000, .MTE, {is_64=true} }, { .MOV_REG, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, { .MOV_REG, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A0003E0, 0xFFE0FFE0, .BASE, {} }, - { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} }, { .MVN, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xAA2003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, + { .MVN, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x2A2003E0, 0xFFE0FFE0, .BASE, {} }, { .CMP_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, { .CMP_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, - { .CMN_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, { .CMN_ER, {.WSP_REG,.W_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B20001F, 0xFFE0001F, .BASE, {sets_flags=true} }, - { .NEG_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, + { .CMN_ER, {.XSP_REG,.X_EXTENDED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB20001F, 0xFFE0001F, .BASE, {sets_flags=true, is_64=true} }, { .NEG_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x4B0003E0, 0xFF2003E0, .BASE, {} }, - { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, + { .NEG_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xCB0003E0, 0xFF2003E0, .BASE, {is_64=true} }, { .NEGS, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xEB0003E0, 0xFF2003E0, .BASE, {sets_flags=true, is_64=true} }, + { .NEGS, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x6B0003E0, 0xFF2003E0, .BASE, {sets_flags=true} }, { .CMP_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, { .CMP_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, - { .CMN_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, { .CMN_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x2B00001F, 0xFF20001F, .BASE, {sets_flags=true} }, - { .TST_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, + { .CMN_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xAB00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, { .TST_SR, {.X_REG,.X_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0xEA00001F, 0xFF20001F, .BASE, {sets_flags=true, is_64=true} }, + { .TST_SR, {.W_REG,.W_SHIFTED,.NONE,.NONE}, {.RN,.RM,.NONE,.NONE}, 0x6A00001F, 0xFF20001F, .BASE, {sets_flags=true} }, { .ADD_ER, {.XSP_REG,.XSP_REG,.X_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x8B200000, 0xFFE00000, .BASE, {is_64=true} }, { .ADD_ER, {.WSP_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x0B200000, 0xFFE00000, .BASE, {} }, { .ADDS_ER, {.W_REG,.WSP_REG,.W_EXTENDED,.NONE}, {.RD,.RN,.RM,.NONE}, 0x2B200000, 0xFFE00000, .BASE, {sets_flags=true} }, @@ -605,40 +605,64 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .SM4E, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0xCEC08400, 0xFFFFFC00, .CRYPTO, {} }, { .BFCVTN, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA16800, 0xFFFFFC00, .BF16, {} }, { .BFCVTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA16800, 0xFFFFFC00, .BF16, {} }, + { .XTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {} }, + { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {} }, + { .XTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {} }, + { .XTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {} }, + { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {} }, + { .XTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {} }, { .NOT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, { .NOT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, - { .RBIT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {} }, { .RBIT_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E605800, 0xFFFFFC00, .NEON, {} }, + { .RBIT_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E605800, 0xFFFFFC00, .NEON, {} }, { .REV16_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E201800, 0xFFFFFC00, .NEON, {} }, { .REV16_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E201800, 0xFFFFFC00, .NEON, {} }, - { .REV32_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {} }, { .REV32_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E600800, 0xFFFFFC00, .NEON, {} }, - { .REV32_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {} }, + { .REV32_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E200800, 0xFFFFFC00, .NEON, {} }, { .REV32_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E200800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {} }, - { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {} }, + { .REV32_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E600800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA00800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E600800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E200800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E600800, 0xFFFFFC00, .NEON, {} }, { .REV64, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E200800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {} }, - { .CLS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {} }, + { .REV64, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA00800, 0xFFFFFC00, .NEON, {} }, { .CLS_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E604800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E204800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA04800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E604800, 0xFFFFFC00, .NEON, {} }, + { .CLS_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA04800, 0xFFFFFC00, .NEON, {} }, { .CLS_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E204800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {} }, - { .CLZ_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, { .CLZ_V, {.V_8H,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E604800, 0xFFFFFC00, .NEON, {} }, { .CLZ_V, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E204800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_4H,.V_4H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E604800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E204800, 0xFFFFFC00, .NEON, {} }, { .CLZ_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA04800, 0xFFFFFC00, .NEON, {} }, - { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {} }, + { .CLZ_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA04800, 0xFFFFFC00, .NEON, {} }, { .CNT, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E205800, 0xFFFFFC00, .NEON, {} }, - { .URECPE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} }, + { .CNT, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E205800, 0xFFFFFC00, .NEON, {} }, { .URECPE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA1C800, 0xFFFFFC00, .NEON, {} }, - { .URSQRTE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URECPE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA1C800, 0xFFFFFC00, .NEON, {} }, { .URSQRTE_V, {.V_4S,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA1C800, 0xFFFFFC00, .NEON, {} }, + { .URSQRTE_V, {.V_2S,.V_2S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA1C800, 0xFFFFFC00, .NEON, {} }, { .NOT_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E205800, 0xFFFFFC00, .NEON, {} }, { .NOT_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E205800, 0xFFFFFC00, .NEON, {} }, { .SHA512H, {.Q_REG,.Q_REG,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE608000, 0xFFE0FC00, .CRYPTO, {} }, @@ -849,21 +873,69 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {} }, { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {} }, { .USUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {} }, - { .SMULL_V, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {} }, + { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {} }, + { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {} }, + { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {} }, + { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {} }, + { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {} }, + { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {} }, + { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {} }, + { .UADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {} }, + { .UADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {} }, + { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {} }, + { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {} }, + { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {} }, + { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {} }, + { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {} }, + { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {} }, + { .USUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {} }, + { .USUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {} }, + { .USUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {} }, { .SMULL_V, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {} }, { .SMULL_V, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {} }, - { .SMULL2_V, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {} }, - { .SMULL2_V, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {} }, + { .SMULL_V, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0C000, 0xFFE0FC00, .NEON, {} }, { .SMULL2_V, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0C000, 0xFFE0FC00, .NEON, {} }, + { .SMULL2_V, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20C000, 0xFFE0FC00, .NEON, {} }, + { .SMULL2_V, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60C000, 0xFFE0FC00, .NEON, {} }, { .UMULL_V, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0C000, 0xFFE0FC00, .NEON, {} }, - { .UMULL_V, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {} }, { .UMULL_V, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20C000, 0xFFE0FC00, .NEON, {} }, + { .UMULL_V, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60C000, 0xFFE0FC00, .NEON, {} }, + { .UMULL2_V, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {} }, { .UMULL2_V, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60C000, 0xFFE0FC00, .NEON, {} }, { .UMULL2_V, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20C000, 0xFFE0FC00, .NEON, {} }, - { .UMULL2_V, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0C000, 0xFFE0FC00, .NEON, {} }, - { .SMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {} }, - { .SMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {} }, { .SMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08000, 0xFFE0FC00, .NEON, {} }, + { .SMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208000, 0xFFE0FC00, .NEON, {} }, + { .SMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608000, 0xFFE0FC00, .NEON, {} }, { .SMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08000, 0xFFE0FC00, .NEON, {} }, { .SMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208000, 0xFFE0FC00, .NEON, {} }, { .SMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608000, 0xFFE0FC00, .NEON, {} }, @@ -871,88 +943,88 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .UMLAL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E208000, 0xFFE0FC00, .NEON, {} }, { .UMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E608000, 0xFFE0FC00, .NEON, {} }, { .UMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08000, 0xFFE0FC00, .NEON, {} }, - { .UMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {} }, { .UMLAL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208000, 0xFFE0FC00, .NEON, {} }, + { .UMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608000, 0xFFE0FC00, .NEON, {} }, { .SMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0A000, 0xFFE0FC00, .NEON, {} }, - { .SMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {} }, { .SMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60A000, 0xFFE0FC00, .NEON, {} }, - { .SMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {} }, + { .SMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20A000, 0xFFE0FC00, .NEON, {} }, { .SMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20A000, 0xFFE0FC00, .NEON, {} }, { .SMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60A000, 0xFFE0FC00, .NEON, {} }, - { .UMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {} }, - { .UMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {} }, + { .SMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0A000, 0xFFE0FC00, .NEON, {} }, { .UMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0A000, 0xFFE0FC00, .NEON, {} }, + { .UMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60A000, 0xFFE0FC00, .NEON, {} }, + { .UMLSL, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20A000, 0xFFE0FC00, .NEON, {} }, + { .UMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {} }, { .UMLSL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20A000, 0xFFE0FC00, .NEON, {} }, { .UMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0A000, 0xFFE0FC00, .NEON, {} }, - { .UMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60A000, 0xFFE0FC00, .NEON, {} }, { .SQDMULL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D000, 0xFFE0FC00, .NEON, {} }, { .SQDMULL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60D000, 0xFFE0FC00, .NEON, {} }, - { .SQDMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {} }, { .SQDMULL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D000, 0xFFE0FC00, .NEON, {} }, + { .SQDMULL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D000, 0xFFE0FC00, .NEON, {} }, { .SQDMLAL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA09000, 0xFFE0FC00, .NEON, {} }, { .SQDMLAL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E609000, 0xFFE0FC00, .NEON, {} }, - { .SQDMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {} }, { .SQDMLAL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA09000, 0xFFE0FC00, .NEON, {} }, - { .SQDMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {} }, + { .SQDMLAL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E609000, 0xFFE0FC00, .NEON, {} }, { .SQDMLSL, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B000, 0xFFE0FC00, .NEON, {} }, - { .SQDMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {} }, + { .SQDMLSL, {.V_2D,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B000, 0xFFE0FC00, .NEON, {} }, { .SQDMLSL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B000, 0xFFE0FC00, .NEON, {} }, + { .SQDMLSL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B000, 0xFFE0FC00, .NEON, {} }, { .SQDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0B400, 0xFFE0FC00, .NEON, {} }, - { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {} }, { .SQDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60B400, 0xFFE0FC00, .NEON, {} }, + { .SQDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60B400, 0xFFE0FC00, .NEON, {} }, { .SQDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0B400, 0xFFE0FC00, .NEON, {} }, - { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {} }, { .SQRDMULH, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E60B400, 0xFFE0FC00, .NEON, {} }, { .SQRDMULH, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60B400, 0xFFE0FC00, .NEON, {} }, + { .SQRDMULH, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA0B400, 0xFFE0FC00, .NEON, {} }, { .SQRDMULH, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA0B400, 0xFFE0FC00, .NEON, {} }, { .SDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E809400, 0xFFE0FC00, .DOT, {} }, { .SDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E809400, 0xFFE0FC00, .DOT, {} }, - { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {} }, { .UDOT, {.V_4S,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E809400, 0xFFE0FC00, .DOT, {} }, + { .UDOT, {.V_2S,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E809400, 0xFFE0FC00, .DOT, {} }, { .FADD_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60D400, 0xFFE0FC00, .NEON, {} }, { .FADD_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20D400, 0xFFE0FC00, .NEON, {} }, { .FADD_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20D400, 0xFFE0FC00, .NEON, {} }, - { .FSUB_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {} }, - { .FSUB_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {} }, { .FSUB_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0D400, 0xFFE0FC00, .NEON, {} }, - { .FMUL_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {} }, - { .FMUL_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {} }, + { .FSUB_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA0D400, 0xFFE0FC00, .NEON, {} }, + { .FSUB_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0D400, 0xFFE0FC00, .NEON, {} }, { .FMUL_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60DC00, 0xFFE0FC00, .NEON, {} }, - { .FDIV_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {} }, - { .FDIV_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {} }, + { .FMUL_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20DC00, 0xFFE0FC00, .NEON, {} }, + { .FMUL_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20DC00, 0xFFE0FC00, .NEON, {} }, { .FDIV_V, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E20FC00, 0xFFE0FC00, .NEON, {} }, + { .FDIV_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E20FC00, 0xFFE0FC00, .NEON, {} }, + { .FDIV_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E60FC00, 0xFFE0FC00, .NEON, {} }, { .FMLA_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E60CC00, 0xFFE0FC00, .NEON, {} }, { .FMLA_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E20CC00, 0xFFE0FC00, .NEON, {} }, { .FMLS_V, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA0CC00, 0xFFE0FC00, .NEON, {} }, { .FMLS_V, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE0CC00, 0xFFE0FC00, .NEON, {} }, - { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {} }, - { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {} }, { .CMEQ, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE08C00, 0xFFE0FC00, .NEON, {} }, + { .CMEQ, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA08C00, 0xFFE0FC00, .NEON, {} }, { .CMEQ, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E208C00, 0xFFE0FC00, .NEON, {} }, - { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {} }, + { .CMEQ, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E608C00, 0xFFE0FC00, .NEON, {} }, + { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {} }, { .CMGE, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603C00, 0xFFE0FC00, .NEON, {} }, { .CMGE, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603C00, 0xFFE0FC00, .NEON, {} }, { .CMGE, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03C00, 0xFFE0FC00, .NEON, {} }, + { .CMGE, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03C00, 0xFFE0FC00, .NEON, {} }, { .CMGE, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203C00, 0xFFE0FC00, .NEON, {} }, { .CMGE, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203C00, 0xFFE0FC00, .NEON, {} }, - { .CMGE, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03C00, 0xFFE0FC00, .NEON, {} }, - { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {} }, { .CMGT, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE03400, 0xFFE0FC00, .NEON, {} }, + { .CMGT, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203400, 0xFFE0FC00, .NEON, {} }, { .CMHI, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203400, 0xFFE0FC00, .NEON, {} }, { .CMHI, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03400, 0xFFE0FC00, .NEON, {} }, - { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {} }, - { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {} }, - { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {} }, - { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {} }, { .CMHS, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603C00, 0xFFE0FC00, .NEON, {} }, - { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {} }, + { .CMHS, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603C00, 0xFFE0FC00, .NEON, {} }, + { .CMHS, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03C00, 0xFFE0FC00, .NEON, {} }, { .CMHS, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203C00, 0xFFE0FC00, .NEON, {} }, + { .CMHS, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203C00, 0xFFE0FC00, .NEON, {} }, + { .CMHS, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03C00, 0xFFE0FC00, .NEON, {} }, + { .CMHS, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE03C00, 0xFFE0FC00, .NEON, {} }, { .CMTST, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE08C00, 0xFFE0FC00, .NEON, {} }, { .CMTST, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA08C00, 0xFFE0FC00, .NEON, {} }, - { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {} }, - { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {} }, - { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {} }, { .CMTST, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E608C00, 0xFFE0FC00, .NEON, {} }, + { .CMTST, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E208C00, 0xFFE0FC00, .NEON, {} }, + { .CMTST, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E208C00, 0xFFE0FC00, .NEON, {} }, + { .CMTST, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E608C00, 0xFFE0FC00, .NEON, {} }, { .CMTST, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA08C00, 0xFFE0FC00, .NEON, {} }, { .AND_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201C00, 0xFFE0FC00, .NEON, {} }, { .ORR_V, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, @@ -963,35 +1035,35 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .BIF, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE01C00, 0xFFE0FC00, .NEON, {} }, { .BSL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601C00, 0xFFE0FC00, .NEON, {} }, { .SRSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE05400, 0xFFE0FC00, .NEON, {} }, - { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {} }, + { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {} }, { .SRSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E605400, 0xFFE0FC00, .NEON, {} }, - { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {} }, { .SRSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E205400, 0xFFE0FC00, .NEON, {} }, { .SRSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E605400, 0xFFE0FC00, .NEON, {} }, - { .SRSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA05400, 0xFFE0FC00, .NEON, {} }, + { .SRSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA05400, 0xFFE0FC00, .NEON, {} }, + { .SRSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E205400, 0xFFE0FC00, .NEON, {} }, + { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {} }, { .URSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA05400, 0xFFE0FC00, .NEON, {} }, { .URSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E605400, 0xFFE0FC00, .NEON, {} }, { .URSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA05400, 0xFFE0FC00, .NEON, {} }, - { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {} }, { .URSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E205400, 0xFFE0FC00, .NEON, {} }, + { .URSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E205400, 0xFFE0FC00, .NEON, {} }, { .URSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E605400, 0xFFE0FC00, .NEON, {} }, - { .URSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE05400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {} }, - { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EE04400, 0xFFE0FC00, .NEON, {} }, { .SSHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {} }, + { .SSHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_2D,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EE04400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} }, - { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {} }, { .USHL, {.V_16B,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204400, 0xFFE0FC00, .NEON, {} }, - { .MOV_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_8B,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_4H,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_8H,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_2S,.V_2S,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04400, 0xFFE0FC00, .NEON, {} }, + { .USHL, {.V_4S,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04400, 0xFFE0FC00, .NEON, {} }, { .MOV_V_ALIAS, {.V_16B,.V_16B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA01C00, 0xFFE0FC00, .NEON, {} }, + { .MOV_V_ALIAS, {.V_8B,.V_8B,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA01C00, 0xFFE0FC00, .NEON, {} }, { .SM3TT1A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408000, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT1B, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408400, 0xFFE0CC00, .CRYPTO, {} }, { .SM3TT2A, {.V_4S,.V_4S,.V_ELEM_S,.NONE}, {.VD,.VN,.VM,.NONE}, 0xCE408800, 0xFFE0CC00, .CRYPTO, {} }, @@ -1040,14 +1112,14 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .MOV_BITMASK, {.X_REG,.BITMASK_IMM,.NONE,.NONE}, {.RD,.BITMASK_FIELD,.NONE,.NONE}, 0xB20003E0, 0xFF8003E0, .BASE, {is_64=true} }, { .EXTR, {.W_REG,.W_REG,.W_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x13800000, 0xFFE08000, .BASE, {} }, { .EXTR, {.X_REG,.X_REG,.X_REG,.IMM_6}, {.RD,.RN,.RM,.IMM6}, 0x93C00000, 0xFFE08000, .BASE, {is_64=true} }, - { .ROR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true} }, { .ROR_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x13800000, 0xFFE00000, .BASE, {} }, + { .ROR_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.ENC_DUAL_RN_RM,.ENC_ROR_SHIFT,.NONE}, 0x93C00000, 0xFFE00000, .BASE, {is_64=true} }, { .AND_IMM, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x12000000, 0xFFC00000, .BASE, {} }, { .ANDS_IMM, {.W_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x72000000, 0xFFC00000, .BASE, {sets_flags=true} }, { .ORR_IMM, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x32000000, 0xFFC00000, .BASE, {} }, { .EOR_IMM, {.WSP_REG,.W_REG,.BITMASK_IMM,.NONE}, {.RD,.RN,.BITMASK_FIELD,.NONE}, 0x52000000, 0xFFC00000, .BASE, {} }, - { .LSL_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true} }, { .LSL_IMM, {.W_REG,.W_REG,.IMM_5,.NONE}, {.RD,.RN,.ENC_LSL_IMM_W,.NONE}, 0x53000000, 0xFFC00000, .BASE, {} }, + { .LSL_IMM, {.X_REG,.X_REG,.IMM_6,.NONE}, {.RD,.RN,.ENC_LSL_IMM_X,.NONE}, 0xD3400000, 0xFFC00000, .BASE, {is_64=true} }, { .MOVZ, {.X_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0xD2800000, 0xFF800000, .BASE, {is_64=true} }, { .MOVZ, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x52800000, 0xFF800000, .BASE, {} }, { .MOVN, {.W_REG,.IMM_16,.HW_SHIFT,.NONE}, {.RD,.IMM16,.IMM_HW,.NONE}, 0x12800000, 0xFF800000, .BASE, {} }, @@ -1302,8 +1374,8 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .STLURH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59000000, 0xFFE00C00, .BASE, {} }, { .LDAPURSB, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19800000, 0xFFE00C00, .BASE, {is_64=true} }, { .LDAPURSB, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x19C00000, 0xFFE00C00, .BASE, {} }, - { .LDAPURSH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {} }, { .LDAPURSH, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59800000, 0xFFE00C00, .BASE, {is_64=true} }, + { .LDAPURSH, {.W_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x59C00000, 0xFFE00C00, .BASE, {} }, { .LDAPURSW, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0x99800000, 0xFFE00C00, .BASE, {is_64=true} }, { .PRFUM, {.IMM_5,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_S9,.NONE,.NONE}, 0xF8800000, 0xFFE00C00, .BASE, {is_64=true} }, { .LDRAA, {.X_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xF8200400, 0xFFA00C00, .PAC, {is_64=true} }, @@ -1358,8 +1430,8 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .AUTDB, {.X_REG,.XSP_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0xDAC11C00, 0xFFFFFC00, .PAC, {is_64=true} }, { .NGC, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x5A0003E0, 0xFFE0FFE0, .BASE, {} }, { .NGC, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xDA0003E0, 0xFFE0FFE0, .BASE, {is_64=true} }, - { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true} }, { .NGCS, {.W_REG,.W_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0x7A0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true} }, + { .NGCS, {.X_REG,.X_REG,.NONE,.NONE}, {.RD,.RM,.NONE,.NONE}, 0xFA0003E0, 0xFFE0FFE0, .BASE, {sets_flags=true, is_64=true} }, { .LSLV, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1AC02000, 0xFFE0FC00, .BASE, {} }, { .LSLV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02000, 0xFFE0FC00, .BASE, {is_64=true} }, { .LSRV, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC02400, 0xFFE0FC00, .BASE, {is_64=true} }, @@ -1389,12 +1461,12 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .CRC32CX, {.W_REG,.W_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9AC05C00, 0xFFE0FC00, .CRC32, {is_64=true} }, { .ADC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1A000000, 0xFFE0FC00, .BASE, {} }, { .ADC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x9A000000, 0xFFE0FC00, .BASE, {is_64=true} }, - { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, { .ADCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x3A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, - { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true} }, + { .ADCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xBA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, { .SBC, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x5A000000, 0xFFE0FC00, .BASE, {} }, - { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, + { .SBC, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xDA000000, 0xFFE0FC00, .BASE, {is_64=true} }, { .SBCS, {.W_REG,.W_REG,.W_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x7A000000, 0xFFE0FC00, .BASE, {sets_flags=true} }, + { .SBCS, {.X_REG,.X_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0xFA000000, 0xFFE0FC00, .BASE, {sets_flags=true, is_64=true} }, { .CCMP_REG, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xFA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, { .CCMP_REG, {.W_REG,.W_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0x7A400000, 0xFFE00C10, .BASE, {sets_flags=true} }, { .CCMN_REG, {.X_REG,.X_REG,.NZCV_IMM,.COND}, {.RN,.RM,.NZCV_FIELD,.COND_HI}, 0xBA400000, 0xFFE00C10, .BASE, {sets_flags=true, is_64=true} }, @@ -1419,14 +1491,14 @@ DECODE_ENTRIES := [1520]lib.Decode_Entry{ { .CPYM, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D400400, 0xFFE03C00, .BASE, {is_64=true} }, { .CPYE, {.XSP_REG,.XSP_REG,.X_REG,.NONE}, {.RD,.RN,.RM,.NONE}, 0x1D800400, 0xFFE03C00, .BASE, {is_64=true} }, { .LDR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3DC00000, 0xFFC00000, .FP, {} }, - { .LDR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {} }, + { .LDR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {} }, { .LDR_V, {.B_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D400000, 0xFFC00000, .FP, {} }, { .LDR_V, {.H_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D400000, 0xFFC00000, .FP, {} }, - { .LDR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD400000, 0xFFC00000, .FP, {} }, + { .LDR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD400000, 0xFFC00000, .FP, {} }, { .STR_V, {.Q_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D800000, 0xFFC00000, .FP, {} }, { .STR_V, {.D_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xFD000000, 0xFFC00000, .FP, {} }, - { .STR_V, {.H_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {} }, { .STR_V, {.B_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x3D000000, 0xFFC00000, .FP, {} }, + { .STR_V, {.H_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0x7D000000, 0xFFC00000, .FP, {} }, { .STR_V, {.S_REG,.MEM,.NONE,.NONE}, {.RT,.OFFSET_BASE_U12,.NONE,.NONE}, 0xBD000000, 0xFFC00000, .FP, {} }, { .FMOV_REG, {.S_REG,.S_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E204000, 0xFFFFFC00, .FP, {} }, { .FMOV_REG, {.D_REG,.D_REG,.NONE,.NONE}, {.RD,.RN,.NONE,.NONE}, 0x1E604000, 0xFFFFFC00, .FP, {} }, @@ -1538,14 +1610,14 @@ DECODE_INDEX_OP0 := [16]lib.Decode_Index{ 0x04 = { 454, 76}, 0x05 = { 530, 50}, 0x06 = { 580, 8}, - 0x07 = { 588, 411}, - 0x08 = { 999, 16}, - 0x09 = {1015, 34}, - 0x0A = {1049, 98}, - 0x0B = {1147, 21}, - 0x0C = {1168, 150}, - 0x0D = {1318, 88}, - 0x0E = {1406, 13}, - 0x0F = {1419, 101}, + 0x07 = { 588, 483}, + 0x08 = {1071, 16}, + 0x09 = {1087, 34}, + 0x0A = {1121, 98}, + 0x0B = {1219, 21}, + 0x0C = {1240, 150}, + 0x0D = {1390, 88}, + 0x0E = {1478, 13}, + 0x0F = {1491, 101}, } diff --git a/core/rexcode/arm64/tablegen/generated/encode_tables.odin b/core/rexcode/arm64/tablegen/generated/encode_tables.odin index b845646ab..6c657e69e 100644 --- a/core/rexcode/arm64/tablegen/generated/encode_tables.odin +++ b/core/rexcode/arm64/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm64_generated import lib "../.." @(rodata) -ENCODE_FORMS := [1518]lib.Encoding{ +ENCODE_FORMS := [1590]lib.Encoding{ // .ADD_IMM { .ADD_IMM, {.WSP_REG,.WSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x11000000, 0xFF800000, .BASE, {} }, { .ADD_IMM, {.XSP_REG,.XSP_REG,.IMM_12,.NONE}, {.RD,.RN,.IMM12,.NONE}, 0x91000000, 0xFF800000, .BASE, {is_64=true} }, @@ -1115,6 +1115,102 @@ ENCODE_FORMS := [1518]lib.Encoding{ { .USUBL2, {.V_8H,.V_16B,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E202000, 0xFFE0FC00, .NEON, {} }, { .USUBL2, {.V_4S,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E602000, 0xFFE0FC00, .NEON, {} }, { .USUBL2, {.V_2D,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA02000, 0xFFE0FC00, .NEON, {} }, + // .SADDW + { .SADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E201000, 0xFFE0FC00, .NEON, {} }, + { .SADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E601000, 0xFFE0FC00, .NEON, {} }, + { .SADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA01000, 0xFFE0FC00, .NEON, {} }, + // .SADDW2 + { .SADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E201000, 0xFFE0FC00, .NEON, {} }, + { .SADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E601000, 0xFFE0FC00, .NEON, {} }, + { .SADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA01000, 0xFFE0FC00, .NEON, {} }, + // .UADDW + { .UADDW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E201000, 0xFFE0FC00, .NEON, {} }, + { .UADDW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E601000, 0xFFE0FC00, .NEON, {} }, + { .UADDW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA01000, 0xFFE0FC00, .NEON, {} }, + // .UADDW2 + { .UADDW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E201000, 0xFFE0FC00, .NEON, {} }, + { .UADDW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E601000, 0xFFE0FC00, .NEON, {} }, + { .UADDW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA01000, 0xFFE0FC00, .NEON, {} }, + // .SSUBW + { .SSUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E203000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E603000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA03000, 0xFFE0FC00, .NEON, {} }, + // .SSUBW2 + { .SSUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E203000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E603000, 0xFFE0FC00, .NEON, {} }, + { .SSUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA03000, 0xFFE0FC00, .NEON, {} }, + // .USUBW + { .USUBW, {.V_8H,.V_8H,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E203000, 0xFFE0FC00, .NEON, {} }, + { .USUBW, {.V_4S,.V_4S,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E603000, 0xFFE0FC00, .NEON, {} }, + { .USUBW, {.V_2D,.V_2D,.V_2S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA03000, 0xFFE0FC00, .NEON, {} }, + // .USUBW2 + { .USUBW2, {.V_8H,.V_8H,.V_16B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E203000, 0xFFE0FC00, .NEON, {} }, + { .USUBW2, {.V_4S,.V_4S,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E603000, 0xFFE0FC00, .NEON, {} }, + { .USUBW2, {.V_2D,.V_2D,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA03000, 0xFFE0FC00, .NEON, {} }, + // .RADDHN + { .RADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E204000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E604000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA04000, 0xFFE0FC00, .NEON, {} }, + // .RADDHN2 + { .RADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E204000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E604000, 0xFFE0FC00, .NEON, {} }, + { .RADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA04000, 0xFFE0FC00, .NEON, {} }, + // .RSUBHN + { .RSUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E206000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2E606000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x2EA06000, 0xFFE0FC00, .NEON, {} }, + // .RSUBHN2 + { .RSUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E206000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6E606000, 0xFFE0FC00, .NEON, {} }, + { .RSUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x6EA06000, 0xFFE0FC00, .NEON, {} }, + // .ADDHN + { .ADDHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E204000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E604000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA04000, 0xFFE0FC00, .NEON, {} }, + // .ADDHN2 + { .ADDHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E204000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E604000, 0xFFE0FC00, .NEON, {} }, + { .ADDHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA04000, 0xFFE0FC00, .NEON, {} }, + // .SUBHN + { .SUBHN, {.V_8B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E206000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN, {.V_4H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E606000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN, {.V_2S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0EA06000, 0xFFE0FC00, .NEON, {} }, + // .SUBHN2 + { .SUBHN2, {.V_16B,.V_8H,.V_8H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E206000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN2, {.V_8H,.V_4S,.V_4S,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4E606000, 0xFFE0FC00, .NEON, {} }, + { .SUBHN2, {.V_4S,.V_2D,.V_2D,.NONE}, {.VD,.VN,.VM,.NONE}, 0x4EA06000, 0xFFE0FC00, .NEON, {} }, + // .XTN + { .XTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E212800, 0xFFFFFC00, .NEON, {} }, + { .XTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E612800, 0xFFFFFC00, .NEON, {} }, + { .XTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA12800, 0xFFFFFC00, .NEON, {} }, + // .XTN2 + { .XTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E212800, 0xFFFFFC00, .NEON, {} }, + { .XTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E612800, 0xFFFFFC00, .NEON, {} }, + { .XTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA12800, 0xFFFFFC00, .NEON, {} }, + // .SQXTN + { .SQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E214800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0E614800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x0EA14800, 0xFFFFFC00, .NEON, {} }, + // .SQXTN2 + { .SQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E214800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4E614800, 0xFFFFFC00, .NEON, {} }, + { .SQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x4EA14800, 0xFFFFFC00, .NEON, {} }, + // .UQXTN + { .UQXTN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E214800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E614800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA14800, 0xFFFFFC00, .NEON, {} }, + // .UQXTN2 + { .UQXTN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E214800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E614800, 0xFFFFFC00, .NEON, {} }, + { .UQXTN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA14800, 0xFFFFFC00, .NEON, {} }, + // .SQXTUN + { .SQXTUN, {.V_8B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E212800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN, {.V_4H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2E612800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN, {.V_2S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x2EA12800, 0xFFFFFC00, .NEON, {} }, + // .SQXTUN2 + { .SQXTUN2, {.V_16B,.V_8H,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E212800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN2, {.V_8H,.V_4S,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6E612800, 0xFFFFFC00, .NEON, {} }, + { .SQXTUN2, {.V_4S,.V_2D,.NONE,.NONE}, {.VD,.VN,.NONE,.NONE}, 0x6EA12800, 0xFFFFFC00, .NEON, {} }, // .SMULL_V { .SMULL_V, {.V_8H,.V_8B,.V_8B,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E20C000, 0xFFE0FC00, .NEON, {} }, { .SMULL_V, {.V_4S,.V_4H,.V_4H,.NONE}, {.VD,.VN,.VM,.NONE}, 0x0E60C000, 0xFFE0FC00, .NEON, {} }, @@ -2824,680 +2920,680 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .SSUBL2 = { 706, 3}, .USUBL = { 709, 3}, .USUBL2 = { 712, 3}, - .SADDW = { 715, 0}, - .SADDW2 = { 715, 0}, - .UADDW = { 715, 0}, - .UADDW2 = { 715, 0}, - .SSUBW = { 715, 0}, - .SSUBW2 = { 715, 0}, - .USUBW = { 715, 0}, - .USUBW2 = { 715, 0}, - .RADDHN = { 715, 0}, - .RADDHN2 = { 715, 0}, - .RSUBHN = { 715, 0}, - .RSUBHN2 = { 715, 0}, - .ADDHN = { 715, 0}, - .ADDHN2 = { 715, 0}, - .SUBHN = { 715, 0}, - .SUBHN2 = { 715, 0}, - .XTN = { 715, 0}, - .XTN2 = { 715, 0}, - .SQXTN = { 715, 0}, - .SQXTN2 = { 715, 0}, - .UQXTN = { 715, 0}, - .UQXTN2 = { 715, 0}, - .SQXTUN = { 715, 0}, - .SQXTUN2 = { 715, 0}, - .SMULL_V = { 715, 3}, - .SMULL2_V = { 718, 3}, - .UMULL_V = { 721, 3}, - .UMULL2_V = { 724, 3}, - .SMLAL = { 727, 3}, - .SMLAL2 = { 730, 3}, - .UMLAL = { 733, 3}, - .UMLAL2 = { 736, 3}, - .SMLSL = { 739, 3}, - .SMLSL2 = { 742, 3}, - .UMLSL = { 745, 3}, - .UMLSL2 = { 748, 3}, - .SQDMULL = { 751, 2}, - .SQDMULL2 = { 753, 2}, - .SQDMLAL = { 755, 2}, - .SQDMLAL2 = { 757, 2}, - .SQDMLSL = { 759, 2}, - .SQDMLSL2 = { 761, 2}, - .SQDMULH = { 763, 4}, - .SQRDMULH = { 767, 4}, - .SDOT = { 771, 2}, - .UDOT = { 773, 2}, - .USDOT = { 775, 0}, - .FADD_V = { 775, 3}, - .FSUB_V = { 778, 3}, - .FMUL_V = { 781, 3}, - .FDIV_V = { 784, 3}, - .FNEG_V = { 787, 0}, - .FABS_V = { 787, 0}, - .FSQRT_V = { 787, 0}, - .FMLA_V = { 787, 2}, - .FMLS_V = { 789, 2}, - .FMULX = { 791, 0}, - .FMAX_V = { 791, 0}, - .FMIN_V = { 791, 0}, - .FMAXNM_V = { 791, 0}, - .FMINNM_V = { 791, 0}, - .FMAXP_V = { 791, 0}, - .FMINP_V = { 791, 0}, - .FMAXNMP = { 791, 0}, - .FMINNMP = { 791, 0}, - .FMAXV_V = { 791, 0}, - .FMINV_V = { 791, 0}, - .FMAXNMV = { 791, 0}, - .FMINNMV = { 791, 0}, - .FRECPE = { 791, 0}, - .FRSQRTE = { 791, 0}, - .FRECPS = { 791, 0}, - .FRSQRTS = { 791, 0}, - .FRECPX = { 791, 0}, - .FADDP_V = { 791, 0}, - .FRINTA_V = { 791, 0}, - .FRINTI_V = { 791, 0}, - .FRINTM_V = { 791, 0}, - .FRINTN_V = { 791, 0}, - .FRINTP_V = { 791, 0}, - .FRINTX_V = { 791, 0}, - .FRINTZ_V = { 791, 0}, - .SCVTF_V = { 791, 0}, - .UCVTF_V = { 791, 0}, - .FCVTAS_V = { 791, 0}, - .FCVTAU_V = { 791, 0}, - .FCVTMS_V = { 791, 0}, - .FCVTMU_V = { 791, 0}, - .FCVTNS_V = { 791, 0}, - .FCVTNU_V = { 791, 0}, - .FCVTPS_V = { 791, 0}, - .FCVTPU_V = { 791, 0}, - .FCVTZS_V = { 791, 0}, - .FCVTZU_V = { 791, 0}, - .FCVTL = { 791, 0}, - .FCVTL2 = { 791, 0}, - .FCVTN = { 791, 0}, - .FCVTN2 = { 791, 0}, - .FCVTXN = { 791, 0}, - .FCVTXN2 = { 791, 0}, - .FCMEQ = { 791, 0}, - .FCMGE = { 791, 0}, - .FCMGT = { 791, 0}, - .FCMLE = { 791, 0}, - .FCMLT = { 791, 0}, - .FACGE = { 791, 0}, - .FACGT = { 791, 0}, - .CMEQ = { 791, 4}, - .CMGE = { 795, 7}, - .CMGT = { 802, 2}, - .CMHI = { 804, 2}, - .CMHS = { 806, 7}, - .CMLE = { 813, 0}, - .CMLT = { 813, 0}, - .CMTST = { 813, 7}, - .AND_V = { 820, 1}, - .ORR_V = { 821, 1}, - .EOR_V = { 822, 1}, - .BIC_V = { 823, 1}, - .ORN_V = { 824, 1}, - .MVN_V = { 825, 0}, - .BIT = { 825, 1}, - .BIF = { 826, 1}, - .BSL = { 827, 1}, - .SHL_V = { 828, 0}, - .SQSHL_V = { 828, 0}, - .SQSHLU = { 828, 0}, - .SRSHL = { 828, 7}, - .URSHL = { 835, 7}, - .SSHR = { 842, 0}, - .USHR = { 842, 0}, - .SSRA = { 842, 0}, - .USRA = { 842, 0}, - .SRSHR = { 842, 0}, - .URSHR = { 842, 0}, - .SRSRA = { 842, 0}, - .URSRA = { 842, 0}, - .SSHL = { 842, 7}, - .USHL = { 849, 7}, - .SLI = { 856, 0}, - .SRI = { 856, 0}, - .SSHLL = { 856, 0}, - .SSHLL2 = { 856, 0}, - .USHLL = { 856, 0}, - .USHLL2 = { 856, 0}, - .SXTL = { 856, 0}, - .SXTL2 = { 856, 0}, - .UXTL = { 856, 0}, - .UXTL2 = { 856, 0}, - .SHRN = { 856, 0}, - .SHRN2 = { 856, 0}, - .RSHRN = { 856, 0}, - .RSHRN2 = { 856, 0}, - .SQSHRN = { 856, 0}, - .SQSHRN2 = { 856, 0}, - .UQSHRN = { 856, 0}, - .UQSHRN2 = { 856, 0}, - .SQRSHRN = { 856, 0}, - .SQRSHRN2 = { 856, 0}, - .UQRSHRN = { 856, 0}, - .UQRSHRN2 = { 856, 0}, - .SQSHRUN = { 856, 0}, - .SQSHRUN2 = { 856, 0}, - .SQRSHRUN = { 856, 0}, - .SQRSHRUN2 = { 856, 0}, - .DUP_V = { 856, 0}, - .INS = { 856, 0}, - .MOV_V = { 856, 0}, - .EXT_V = { 856, 0}, - .TBL = { 856, 0}, - .TBX = { 856, 0}, - .ZIP1 = { 856, 0}, - .ZIP2 = { 856, 0}, - .UZP1 = { 856, 0}, - .UZP2 = { 856, 0}, - .TRN1 = { 856, 0}, - .TRN2 = { 856, 0}, - .NOT_V = { 856, 2}, - .RBIT_V = { 858, 2}, - .REV16_V = { 860, 2}, - .REV32_V = { 862, 4}, - .REV64 = { 866, 6}, - .CLS_V = { 872, 6}, - .CLZ_V = { 878, 6}, - .CNT = { 884, 2}, - .URECPE_V = { 886, 2}, - .URSQRTE_V = { 888, 2}, - .MOVI = { 890, 0}, - .MVNI = { 890, 0}, - .FMOV_V_IMM = { 890, 0}, - .LD1 = { 890, 4}, - .LD2 = { 894, 0}, - .LD3 = { 894, 0}, - .LD4 = { 894, 0}, - .ST1 = { 894, 4}, - .ST2 = { 898, 0}, - .ST3 = { 898, 0}, - .ST4 = { 898, 0}, - .LD1R = { 898, 0}, - .LD2R = { 898, 0}, - .LD3R = { 898, 0}, - .LD4R = { 898, 0}, - .LD1_LANE = { 898, 0}, - .LD2_LANE = { 898, 0}, - .LD3_LANE = { 898, 0}, - .LD4_LANE = { 898, 0}, - .ST1_LANE = { 898, 0}, - .ST2_LANE = { 898, 0}, - .ST3_LANE = { 898, 0}, - .ST4_LANE = { 898, 0}, - .LDR_V = { 898, 5}, - .STR_V = { 903, 5}, - .LDP_V = { 908, 0}, - .STP_V = { 908, 0}, - .LDUR_V = { 908, 0}, - .STUR_V = { 908, 0}, - .SVE_ADD_Z = { 908, 4}, - .SVE_SUB_Z = { 912, 4}, - .SVE_SQADD_Z = { 916, 4}, - .SVE_UQADD_Z = { 920, 4}, - .SVE_SQSUB_Z = { 924, 4}, - .SVE_UQSUB_Z = { 928, 4}, - .SVE_ADD_PRED = { 932, 4}, - .SVE_SUB_PRED = { 936, 4}, - .SVE_SUBR_PRED = { 940, 4}, - .SVE_MUL_PRED = { 944, 4}, - .SVE_SMULH_PRED = { 948, 4}, - .SVE_UMULH_PRED = { 952, 4}, - .SVE_SDIV_PRED = { 956, 2}, - .SVE_UDIV_PRED = { 958, 2}, - .SVE_SMAX_PRED = { 960, 4}, - .SVE_UMAX_PRED = { 964, 4}, - .SVE_SMIN_PRED = { 968, 4}, - .SVE_UMIN_PRED = { 972, 4}, - .SVE_SABD_PRED = { 976, 4}, - .SVE_UABD_PRED = { 980, 4}, - .SVE_AND_PRED = { 984, 1}, - .SVE_ORR_PRED = { 985, 1}, - .SVE_EOR_PRED = { 986, 1}, - .SVE_BIC_PRED = { 987, 1}, - .SVE_ASR_PRED = { 988, 4}, - .SVE_LSL_PRED = { 992, 4}, - .SVE_LSR_PRED = { 996, 4}, - .SVE_ASRR_PRED = { 1000, 0}, - .SVE_LSLR_PRED = { 1000, 0}, - .SVE_LSRR_PRED = { 1000, 0}, - .SVE_ABS_PRED = { 1000, 4}, - .SVE_NEG_PRED = { 1004, 4}, - .SVE_CLS_PRED = { 1008, 4}, - .SVE_CLZ_PRED = { 1012, 4}, - .SVE_CNT_PRED = { 1016, 4}, - .SVE_MOV_PRED = { 1020, 0}, - .SVE_FADD_Z = { 1020, 3}, - .SVE_FSUB_Z = { 1023, 3}, - .SVE_FMUL_Z = { 1026, 3}, - .SVE_FRECPS = { 1029, 3}, - .SVE_FRSQRTS = { 1032, 3}, - .SVE_FTSMUL = { 1035, 3}, - .SVE_FADD_PRED = { 1038, 3}, - .SVE_FSUB_PRED = { 1041, 3}, - .SVE_FSUBR_PRED = { 1044, 0}, - .SVE_FMUL_PRED = { 1044, 3}, - .SVE_FDIV_PRED = { 1047, 3}, - .SVE_FDIVR_PRED = { 1050, 0}, - .SVE_FMAX_PRED = { 1050, 3}, - .SVE_FMIN_PRED = { 1053, 3}, - .SVE_FMAXNM_PRED = { 1056, 3}, - .SVE_FMINNM_PRED = { 1059, 3}, - .SVE_FABS_Z = { 1062, 3}, - .SVE_FNEG_Z = { 1065, 3}, - .SVE_FSQRT_Z = { 1068, 3}, - .SVE_FRECPX_Z = { 1071, 0}, - .SVE_FRINTN = { 1071, 0}, - .SVE_FRINTP = { 1071, 0}, - .SVE_FRINTM = { 1071, 0}, - .SVE_FRINTZ = { 1071, 0}, - .SVE_FRINTA = { 1071, 0}, - .SVE_FRINTX = { 1071, 0}, - .SVE_FRINTI = { 1071, 0}, - .SVE_FMLA = { 1071, 3}, - .SVE_FMLS = { 1074, 3}, - .SVE_FNMLA = { 1077, 3}, - .SVE_FNMLS = { 1080, 3}, - .SVE_AND_P = { 1083, 1}, - .SVE_BIC_P = { 1084, 1}, - .SVE_ORR_P = { 1085, 1}, - .SVE_EOR_P = { 1086, 1}, - .SVE_NAND_P = { 1087, 1}, - .SVE_NOR_P = { 1088, 1}, - .SVE_ORN_P = { 1089, 1}, - .SVE_SEL_P = { 1090, 1}, - .SVE_ANDS_P = { 1091, 1}, - .SVE_BICS_P = { 1092, 1}, - .SVE_ORRS_P = { 1093, 1}, - .SVE_EORS_P = { 1094, 1}, - .SVE_NANDS_P = { 1095, 0}, - .SVE_NORS_P = { 1095, 0}, - .SVE_ORNS_P = { 1095, 0}, - .SVE_NOT_P = { 1095, 0}, - .SVE_MOV_P = { 1095, 0}, - .SVE_MOVS_P = { 1095, 0}, - .SVE_PTRUE = { 1095, 1}, - .SVE_PTRUES = { 1096, 1}, - .SVE_PFALSE = { 1097, 1}, - .SVE_PFIRST = { 1098, 1}, - .SVE_PNEXT = { 1099, 1}, - .SVE_BRKA = { 1100, 0}, - .SVE_BRKB = { 1100, 0}, - .SVE_BRKAS = { 1100, 0}, - .SVE_BRKBS = { 1100, 0}, - .SVE_BRKPA = { 1100, 0}, - .SVE_BRKPB = { 1100, 0}, - .SVE_BRKN = { 1100, 0}, - .SVE_RDFFR = { 1100, 0}, - .SVE_WRFFR = { 1100, 0}, - .SVE_SETFFR = { 1100, 0}, - .SVE_CMPEQ = { 1100, 4}, - .SVE_CMPNE = { 1104, 4}, - .SVE_CMPGE = { 1108, 4}, - .SVE_CMPGT = { 1112, 4}, - .SVE_CMPLE = { 1116, 0}, - .SVE_CMPLT = { 1116, 0}, - .SVE_CMPHI = { 1116, 4}, - .SVE_CMPHS = { 1120, 4}, - .SVE_CMPLO = { 1124, 0}, - .SVE_CMPLS = { 1124, 0}, - .SVE_FCMEQ = { 1124, 0}, - .SVE_FCMNE = { 1124, 0}, - .SVE_FCMGE = { 1124, 0}, - .SVE_FCMGT = { 1124, 0}, - .SVE_FCMLE = { 1124, 0}, - .SVE_FCMLT = { 1124, 0}, - .SVE_FCMUO = { 1124, 0}, - .SVE_DUP_Z = { 1124, 4}, - .SVE_INSR = { 1128, 0}, - .SVE_REV_Z = { 1128, 4}, - .SVE_REV_P = { 1132, 1}, - .SVE_TBL = { 1133, 4}, - .SVE_ZIP1_Z = { 1137, 4}, - .SVE_ZIP2_Z = { 1141, 4}, - .SVE_UZP1_Z = { 1145, 4}, - .SVE_UZP2_Z = { 1149, 4}, - .SVE_TRN1_Z = { 1153, 4}, - .SVE_TRN2_Z = { 1157, 4}, - .SVE_ZIP1_P = { 1161, 1}, - .SVE_ZIP2_P = { 1162, 1}, - .SVE_UZP1_P = { 1163, 1}, - .SVE_UZP2_P = { 1164, 1}, - .SVE_TRN1_P = { 1165, 1}, - .SVE_TRN2_P = { 1166, 1}, - .SVE_CPY_Z = { 1167, 0}, - .SVE_COMPACT = { 1167, 0}, - .SVE_EXT_Z = { 1167, 0}, - .SVE_LD1B = { 1167, 1}, - .SVE_LD1H = { 1168, 1}, - .SVE_LD1W = { 1169, 1}, - .SVE_LD1D = { 1170, 1}, - .SVE_LD1SB = { 1171, 1}, - .SVE_LD1SH = { 1172, 1}, - .SVE_LD1SW = { 1173, 1}, - .SVE_ST1B = { 1174, 1}, - .SVE_ST1H = { 1175, 1}, - .SVE_ST1W = { 1176, 1}, - .SVE_ST1D = { 1177, 1}, - .SVE_LDR_Z = { 1178, 1}, - .SVE_STR_Z = { 1179, 1}, - .SVE_LDR_P = { 1180, 1}, - .SVE_STR_P = { 1181, 1}, - .SVE_LDFF1B = { 1182, 1}, - .SVE_LDFF1H = { 1183, 1}, - .SVE_LDFF1W = { 1184, 1}, - .SVE_LDFF1D = { 1185, 1}, - .SVE_WHILEGE = { 1186, 1}, - .SVE_WHILEGT = { 1187, 1}, - .SVE_WHILELE = { 1188, 1}, - .SVE_WHILELT = { 1189, 1}, - .SVE_WHILEHI = { 1190, 1}, - .SVE_WHILEHS = { 1191, 1}, - .SVE_WHILELO = { 1192, 1}, - .SVE_WHILELS = { 1193, 1}, - .SVE_SQRDMLAH = { 1194, 4}, - .SVE_SQRDMLSH = { 1198, 4}, - .SVE_ADCLB = { 1202, 2}, - .SVE_ADCLT = { 1204, 2}, - .SVE_SBCLB = { 1206, 2}, - .SVE_SBCLT = { 1208, 2}, - .SVE_TBL2 = { 1210, 1}, - .SVE_TBX = { 1211, 1}, - .SVE_AESE = { 1212, 1}, - .SVE_AESD = { 1213, 1}, - .SVE_AESMC = { 1214, 1}, - .SVE_AESIMC = { 1215, 1}, - .SVE_BCAX_Z = { 1216, 0}, - .SVE_XAR_Z = { 1216, 0}, - .SVE_EOR3_Z = { 1216, 0}, - .SVE_MATCH = { 1216, 2}, - .SVE_NMATCH = { 1218, 2}, - .SVE_HISTCNT = { 1220, 2}, - .SVE_HISTSEG = { 1222, 1}, - .SME_SMSTART = { 1223, 1}, - .SME_SMSTOP = { 1224, 1}, - .SME_RDSVL = { 1225, 1}, - .SME_ADDHA = { 1226, 0}, - .SME_ADDVA = { 1226, 0}, - .SME_ZERO = { 1226, 1}, - .SME_FMOPA = { 1227, 1}, - .SME_FMOPS = { 1228, 1}, - .SME_BFMOPA = { 1229, 1}, - .SME_BFMOPS = { 1230, 1}, - .SME_SMOPA = { 1231, 2}, - .SME_SMOPS = { 1233, 2}, - .SME_UMOPA = { 1235, 2}, - .SME_UMOPS = { 1237, 2}, - .SME_USMOPA = { 1239, 1}, - .SME_SUMOPA = { 1240, 1}, - .SME_MOVA_TO_Z = { 1241, 0}, - .SME_MOVA_TO_ZA = { 1241, 0}, - .SME_LD1B_ZA = { 1241, 0}, - .SME_LD1H_ZA = { 1241, 0}, - .SME_LD1W_ZA = { 1241, 0}, - .SME_LD1D_ZA = { 1241, 0}, - .SME_LD1Q_ZA = { 1241, 0}, - .SME_ST1B_ZA = { 1241, 0}, - .SME_ST1H_ZA = { 1241, 0}, - .SME_ST1W_ZA = { 1241, 0}, - .SME_ST1D_ZA = { 1241, 0}, - .SME_ST1Q_ZA = { 1241, 0}, - .SME_LDR_ZA = { 1241, 1}, - .SME_STR_ZA = { 1242, 1}, - .SVE_FMLA_IDX_H = { 1243, 1}, - .SVE_FMLA_IDX_S = { 1244, 1}, - .SVE_FMLA_IDX_D = { 1245, 1}, - .SVE_FMLS_IDX_H = { 1246, 1}, - .SVE_FMLS_IDX_S = { 1247, 1}, - .SVE_FMLS_IDX_D = { 1248, 1}, - .SVE_LD1B_GATHER_S = { 1249, 1}, - .SVE_LD1B_GATHER_D = { 1250, 1}, - .SVE_LD1H_GATHER_S = { 1251, 1}, - .SVE_LD1H_GATHER_D = { 1252, 1}, - .SVE_LD1W_GATHER_S = { 1253, 1}, - .SVE_LD1W_GATHER_D = { 1254, 1}, - .SVE_LD1D_GATHER_D = { 1255, 1}, - .SVE_LD1SB_GATHER_S = { 1256, 1}, - .SVE_LD1SB_GATHER_D = { 1257, 1}, - .SVE_LD1SH_GATHER_S = { 1258, 1}, - .SVE_LD1SH_GATHER_D = { 1259, 1}, - .SVE_LD1SW_GATHER_D = { 1260, 1}, - .SVE_ST1B_SCATTER_S = { 1261, 1}, - .SVE_ST1B_SCATTER_D = { 1262, 1}, - .SVE_ST1H_SCATTER_S = { 1263, 1}, - .SVE_ST1H_SCATTER_D = { 1264, 1}, - .SVE_ST1W_SCATTER_S = { 1265, 1}, - .SVE_ST1W_SCATTER_D = { 1266, 1}, - .SVE_ST1D_SCATTER_D = { 1267, 1}, - .SME_LD1B_TILE = { 1268, 1}, - .SME_LD1H_TILE = { 1269, 1}, - .SME_LD1W_TILE = { 1270, 1}, - .SME_LD1D_TILE = { 1271, 1}, - .SME_LD1Q_TILE = { 1272, 1}, - .SME_ST1B_TILE = { 1273, 1}, - .SME_ST1H_TILE = { 1274, 1}, - .SME_ST1W_TILE = { 1275, 1}, - .SME_ST1D_TILE = { 1276, 1}, - .SME_ST1Q_TILE = { 1277, 1}, - .SME_MOVA_Z_FROM_TILE = { 1278, 1}, - .SME_MOVA_TILE_FROM_Z = { 1279, 1}, - .FCMLA_4H = { 1280, 1}, - .FCMLA_8H = { 1281, 1}, - .FCMLA_4S = { 1282, 1}, - .FCMLA_2D = { 1283, 1}, - .FCADD_4H = { 1284, 1}, - .FCADD_8H = { 1285, 1}, - .FCADD_4S = { 1286, 1}, - .FCADD_2D = { 1287, 1}, - .SVE_PRFB = { 1288, 1}, - .SVE_PRFH = { 1289, 1}, - .SVE_PRFW = { 1290, 1}, - .SVE_PRFD = { 1291, 1}, - .SVE_LDNT1B = { 1292, 1}, - .SVE_LDNT1H = { 1293, 1}, - .SVE_LDNT1W = { 1294, 1}, - .SVE_LDNT1D = { 1295, 1}, - .SVE_STNT1B = { 1296, 1}, - .SVE_STNT1H = { 1297, 1}, - .SVE_STNT1W = { 1298, 1}, - .SVE_STNT1D = { 1299, 1}, - .SVE_EXT = { 1300, 1}, - .SVE_SPLICE = { 1301, 1}, - .SVE_INDEX_II = { 1302, 1}, - .SVE_INDEX_IR = { 1303, 1}, - .SVE_INDEX_RI = { 1304, 1}, - .SVE_INDEX_RR = { 1305, 1}, - .SVE_BSL = { 1306, 1}, - .SVE_BSL1N = { 1307, 1}, - .SVE_BSL2N = { 1308, 1}, - .SVE_NBSL = { 1309, 1}, - .SVE_PMUL_VEC = { 1310, 1}, - .SVE_PMULLB = { 1311, 1}, - .SVE_PMULLT = { 1312, 1}, - .SVE_BFCVT = { 1313, 1}, - .SVE_BFCVTNT = { 1314, 1}, - .LDRAA = { 1315, 1}, - .LDRAB = { 1316, 1}, - .LDRAA_PRE = { 1317, 1}, - .LDRAB_PRE = { 1318, 1}, - .TSTART = { 1319, 1}, - .TCOMMIT = { 1320, 1}, - .TCANCEL = { 1321, 1}, - .TTEST = { 1322, 1}, - .WFET = { 1323, 1}, - .WFIT = { 1324, 1}, - .BC_COND = { 1325, 1}, - .UXTB = { 1326, 1}, - .UXTH = { 1327, 1}, - .UXTW = { 1328, 1}, - .SXTB = { 1329, 1}, - .SXTH = { 1330, 1}, - .SXTW = { 1331, 1}, - .ADC = { 1332, 2}, - .ADCS = { 1334, 2}, - .SBC = { 1336, 2}, - .SBCS = { 1338, 2}, - .NGC = { 1340, 2}, - .NGCS = { 1342, 2}, - .LDAPUR = { 1344, 2}, - .STLUR = { 1346, 2}, - .LDAPURB = { 1348, 1}, - .STLURB = { 1349, 1}, - .LDAPURH = { 1350, 1}, - .STLURH = { 1351, 1}, - .LDAPURSB = { 1352, 2}, - .LDAPURSH = { 1354, 2}, - .LDAPURSW = { 1356, 1}, - .SVE_BFADD = { 1357, 1}, - .SVE_BFSUB = { 1358, 1}, - .SVE_BFMUL = { 1359, 1}, - .SVE_BFMLA = { 1360, 1}, - .SVE_BFMLS = { 1361, 1}, - .SB = { 1362, 1}, - .CSDB = { 1363, 1}, - .DGH = { 1364, 1}, - .PSB_CSYNC = { 1365, 1}, - .TSB_CSYNC = { 1366, 1}, - .BTI_J = { 1367, 1}, - .BTI_C = { 1368, 1}, - .BTI_JC = { 1369, 1}, - .MOV_V_ALIAS = { 1370, 2}, - .NOT_V_ALIAS = { 1372, 2}, - .LSL_IMM = { 1374, 2}, - .LSR_IMM = { 1376, 2}, - .ASR_IMM = { 1378, 2}, - .ROR_IMM = { 1380, 2}, - .SVE_BFADD_UNPRED = { 1382, 1}, - .SVE_BFSUB_UNPRED = { 1383, 1}, - .SVE_BFMUL_UNPRED = { 1384, 1}, - .SVE_BFCLAMP = { 1385, 1}, - .SVE_BFMAXNM = { 1386, 1}, - .SVE_BFMINNM = { 1387, 1}, - .SME2_LUTI2_B = { 1388, 1}, - .SME2_LUTI4_B = { 1389, 1}, - .SME2_LD1B_X2 = { 1390, 1}, - .SME2_LD1H_X2 = { 1391, 1}, - .SME2_LD1W_X2 = { 1392, 1}, - .SME2_LD1D_X2 = { 1393, 1}, - .SME2_LD1B_X4 = { 1394, 1}, - .SME2_LD1H_X4 = { 1395, 1}, - .SME2_LD1W_X4 = { 1396, 1}, - .SME2_LD1D_X4 = { 1397, 1}, - .SME2_ST1B_X2 = { 1398, 1}, - .SME2_ST1H_X2 = { 1399, 1}, - .SME2_ST1W_X2 = { 1400, 1}, - .SME2_ST1D_X2 = { 1401, 1}, - .SME2_ST1B_X4 = { 1402, 1}, - .SME2_ST1H_X4 = { 1403, 1}, - .SME2_ST1W_X4 = { 1404, 1}, - .SME2_ST1D_X4 = { 1405, 1}, - .SME2_ZIP_3 = { 1406, 1}, - .SME2_ZIP_4 = { 1407, 1}, - .SME2_UZP_3 = { 1408, 1}, - .SME2_UZP_4 = { 1409, 1}, - .TLBI_RPALOS = { 1410, 1}, - .TLBI_RPAOS = { 1411, 1}, - .AT_S1E1A = { 1412, 1}, - .DC_CIPAPA = { 1413, 1}, - .DC_CIGDPAPA = { 1414, 1}, - .TLBI_PAALL = { 1415, 1}, - .TLBI_PAALLOS = { 1416, 1}, - .AMX_LDX = { 1417, 1}, - .AMX_LDY = { 1418, 1}, - .AMX_STX = { 1419, 1}, - .AMX_STY = { 1420, 1}, - .AMX_LDZ = { 1421, 1}, - .AMX_STZ = { 1422, 1}, - .AMX_LDZI = { 1423, 1}, - .AMX_STZI = { 1424, 1}, - .AMX_EXTRX = { 1425, 1}, - .AMX_EXTRY = { 1426, 1}, - .AMX_FMA64 = { 1427, 1}, - .AMX_FMS64 = { 1428, 1}, - .AMX_FMA32 = { 1429, 1}, - .AMX_FMS32 = { 1430, 1}, - .AMX_MAC16 = { 1431, 1}, - .AMX_FMA16 = { 1432, 1}, - .AMX_FMS16 = { 1433, 1}, - .AMX_SET = { 1434, 1}, - .AMX_CLR = { 1435, 1}, - .AMX_VECINT = { 1436, 1}, - .AMX_VECFP = { 1437, 1}, - .AMX_MATINT = { 1438, 1}, - .AMX_MATFP = { 1439, 1}, - .AMX_GENLUT = { 1440, 1}, - .CPYP = { 1441, 1}, - .CPYM = { 1442, 1}, - .CPYE = { 1443, 1}, - .CPYFP = { 1444, 1}, - .CPYFM = { 1445, 1}, - .CPYFE = { 1446, 1}, - .SETP = { 1447, 1}, - .SETM = { 1448, 1}, - .SETE = { 1449, 1}, - .DC_IVAC = { 1450, 1}, - .DC_ISW = { 1451, 1}, - .DC_CSW = { 1452, 1}, - .DC_CISW = { 1453, 1}, - .DC_ZVA = { 1454, 1}, - .DC_CVAC = { 1455, 1}, - .DC_CVAU = { 1456, 1}, - .DC_CIVAC = { 1457, 1}, - .IC_IALLUIS = { 1458, 1}, - .IC_IALLU = { 1459, 1}, - .IC_IVAU = { 1460, 1}, - .AT_S1E1R = { 1461, 1}, - .AT_S1E1W = { 1462, 1}, - .AT_S1E0R = { 1463, 1}, - .AT_S1E0W = { 1464, 1}, - .AT_S1E2R = { 1465, 1}, - .AT_S1E2W = { 1466, 1}, - .AT_S1E3R = { 1467, 1}, - .AT_S1E3W = { 1468, 1}, - .AT_S12E1R = { 1469, 1}, - .AT_S12E1W = { 1470, 1}, - .AT_S12E0R = { 1471, 1}, - .AT_S12E0W = { 1472, 1}, - .TLBI_VMALLE1 = { 1473, 1}, - .TLBI_VMALLE1IS = { 1474, 1}, - .TLBI_VAE1 = { 1475, 1}, - .TLBI_VAE1IS = { 1476, 1}, - .TLBI_ASIDE1 = { 1477, 1}, - .TLBI_ASIDE1IS = { 1478, 1}, - .TLBI_VAAE1 = { 1479, 1}, - .TLBI_VAAE1IS = { 1480, 1}, - .TLBI_VALE1 = { 1481, 1}, - .TLBI_VALE1IS = { 1482, 1}, - .TLBI_VAALE1 = { 1483, 1}, - .TLBI_VAALE1IS = { 1484, 1}, - .TLBI_ALLE1 = { 1485, 1}, - .TLBI_ALLE1IS = { 1486, 1}, - .TLBI_ALLE2 = { 1487, 1}, - .TLBI_ALLE2IS = { 1488, 1}, - .TLBI_ALLE3 = { 1489, 1}, - .TLBI_ALLE3IS = { 1490, 1}, - .PRFM = { 1491, 1}, - .PRFUM = { 1492, 1}, - .PRFM_LIT = { 1493, 1}, - .MOV_REG = { 1494, 2}, - .MOV_BITMASK = { 1496, 2}, - .MVN = { 1498, 2}, - .NEG_SR = { 1500, 2}, - .NEGS = { 1502, 2}, - .CMP_SR = { 1504, 2}, - .CMP_ER = { 1506, 2}, - .CMP_IMM = { 1508, 2}, - .CMN_SR = { 1510, 2}, - .CMN_ER = { 1512, 2}, - .CMN_IMM = { 1514, 2}, - .TST_SR = { 1516, 2}, + .SADDW = { 715, 3}, + .SADDW2 = { 718, 3}, + .UADDW = { 721, 3}, + .UADDW2 = { 724, 3}, + .SSUBW = { 727, 3}, + .SSUBW2 = { 730, 3}, + .USUBW = { 733, 3}, + .USUBW2 = { 736, 3}, + .RADDHN = { 739, 3}, + .RADDHN2 = { 742, 3}, + .RSUBHN = { 745, 3}, + .RSUBHN2 = { 748, 3}, + .ADDHN = { 751, 3}, + .ADDHN2 = { 754, 3}, + .SUBHN = { 757, 3}, + .SUBHN2 = { 760, 3}, + .XTN = { 763, 3}, + .XTN2 = { 766, 3}, + .SQXTN = { 769, 3}, + .SQXTN2 = { 772, 3}, + .UQXTN = { 775, 3}, + .UQXTN2 = { 778, 3}, + .SQXTUN = { 781, 3}, + .SQXTUN2 = { 784, 3}, + .SMULL_V = { 787, 3}, + .SMULL2_V = { 790, 3}, + .UMULL_V = { 793, 3}, + .UMULL2_V = { 796, 3}, + .SMLAL = { 799, 3}, + .SMLAL2 = { 802, 3}, + .UMLAL = { 805, 3}, + .UMLAL2 = { 808, 3}, + .SMLSL = { 811, 3}, + .SMLSL2 = { 814, 3}, + .UMLSL = { 817, 3}, + .UMLSL2 = { 820, 3}, + .SQDMULL = { 823, 2}, + .SQDMULL2 = { 825, 2}, + .SQDMLAL = { 827, 2}, + .SQDMLAL2 = { 829, 2}, + .SQDMLSL = { 831, 2}, + .SQDMLSL2 = { 833, 2}, + .SQDMULH = { 835, 4}, + .SQRDMULH = { 839, 4}, + .SDOT = { 843, 2}, + .UDOT = { 845, 2}, + .USDOT = { 847, 0}, + .FADD_V = { 847, 3}, + .FSUB_V = { 850, 3}, + .FMUL_V = { 853, 3}, + .FDIV_V = { 856, 3}, + .FNEG_V = { 859, 0}, + .FABS_V = { 859, 0}, + .FSQRT_V = { 859, 0}, + .FMLA_V = { 859, 2}, + .FMLS_V = { 861, 2}, + .FMULX = { 863, 0}, + .FMAX_V = { 863, 0}, + .FMIN_V = { 863, 0}, + .FMAXNM_V = { 863, 0}, + .FMINNM_V = { 863, 0}, + .FMAXP_V = { 863, 0}, + .FMINP_V = { 863, 0}, + .FMAXNMP = { 863, 0}, + .FMINNMP = { 863, 0}, + .FMAXV_V = { 863, 0}, + .FMINV_V = { 863, 0}, + .FMAXNMV = { 863, 0}, + .FMINNMV = { 863, 0}, + .FRECPE = { 863, 0}, + .FRSQRTE = { 863, 0}, + .FRECPS = { 863, 0}, + .FRSQRTS = { 863, 0}, + .FRECPX = { 863, 0}, + .FADDP_V = { 863, 0}, + .FRINTA_V = { 863, 0}, + .FRINTI_V = { 863, 0}, + .FRINTM_V = { 863, 0}, + .FRINTN_V = { 863, 0}, + .FRINTP_V = { 863, 0}, + .FRINTX_V = { 863, 0}, + .FRINTZ_V = { 863, 0}, + .SCVTF_V = { 863, 0}, + .UCVTF_V = { 863, 0}, + .FCVTAS_V = { 863, 0}, + .FCVTAU_V = { 863, 0}, + .FCVTMS_V = { 863, 0}, + .FCVTMU_V = { 863, 0}, + .FCVTNS_V = { 863, 0}, + .FCVTNU_V = { 863, 0}, + .FCVTPS_V = { 863, 0}, + .FCVTPU_V = { 863, 0}, + .FCVTZS_V = { 863, 0}, + .FCVTZU_V = { 863, 0}, + .FCVTL = { 863, 0}, + .FCVTL2 = { 863, 0}, + .FCVTN = { 863, 0}, + .FCVTN2 = { 863, 0}, + .FCVTXN = { 863, 0}, + .FCVTXN2 = { 863, 0}, + .FCMEQ = { 863, 0}, + .FCMGE = { 863, 0}, + .FCMGT = { 863, 0}, + .FCMLE = { 863, 0}, + .FCMLT = { 863, 0}, + .FACGE = { 863, 0}, + .FACGT = { 863, 0}, + .CMEQ = { 863, 4}, + .CMGE = { 867, 7}, + .CMGT = { 874, 2}, + .CMHI = { 876, 2}, + .CMHS = { 878, 7}, + .CMLE = { 885, 0}, + .CMLT = { 885, 0}, + .CMTST = { 885, 7}, + .AND_V = { 892, 1}, + .ORR_V = { 893, 1}, + .EOR_V = { 894, 1}, + .BIC_V = { 895, 1}, + .ORN_V = { 896, 1}, + .MVN_V = { 897, 0}, + .BIT = { 897, 1}, + .BIF = { 898, 1}, + .BSL = { 899, 1}, + .SHL_V = { 900, 0}, + .SQSHL_V = { 900, 0}, + .SQSHLU = { 900, 0}, + .SRSHL = { 900, 7}, + .URSHL = { 907, 7}, + .SSHR = { 914, 0}, + .USHR = { 914, 0}, + .SSRA = { 914, 0}, + .USRA = { 914, 0}, + .SRSHR = { 914, 0}, + .URSHR = { 914, 0}, + .SRSRA = { 914, 0}, + .URSRA = { 914, 0}, + .SSHL = { 914, 7}, + .USHL = { 921, 7}, + .SLI = { 928, 0}, + .SRI = { 928, 0}, + .SSHLL = { 928, 0}, + .SSHLL2 = { 928, 0}, + .USHLL = { 928, 0}, + .USHLL2 = { 928, 0}, + .SXTL = { 928, 0}, + .SXTL2 = { 928, 0}, + .UXTL = { 928, 0}, + .UXTL2 = { 928, 0}, + .SHRN = { 928, 0}, + .SHRN2 = { 928, 0}, + .RSHRN = { 928, 0}, + .RSHRN2 = { 928, 0}, + .SQSHRN = { 928, 0}, + .SQSHRN2 = { 928, 0}, + .UQSHRN = { 928, 0}, + .UQSHRN2 = { 928, 0}, + .SQRSHRN = { 928, 0}, + .SQRSHRN2 = { 928, 0}, + .UQRSHRN = { 928, 0}, + .UQRSHRN2 = { 928, 0}, + .SQSHRUN = { 928, 0}, + .SQSHRUN2 = { 928, 0}, + .SQRSHRUN = { 928, 0}, + .SQRSHRUN2 = { 928, 0}, + .DUP_V = { 928, 0}, + .INS = { 928, 0}, + .MOV_V = { 928, 0}, + .EXT_V = { 928, 0}, + .TBL = { 928, 0}, + .TBX = { 928, 0}, + .ZIP1 = { 928, 0}, + .ZIP2 = { 928, 0}, + .UZP1 = { 928, 0}, + .UZP2 = { 928, 0}, + .TRN1 = { 928, 0}, + .TRN2 = { 928, 0}, + .NOT_V = { 928, 2}, + .RBIT_V = { 930, 2}, + .REV16_V = { 932, 2}, + .REV32_V = { 934, 4}, + .REV64 = { 938, 6}, + .CLS_V = { 944, 6}, + .CLZ_V = { 950, 6}, + .CNT = { 956, 2}, + .URECPE_V = { 958, 2}, + .URSQRTE_V = { 960, 2}, + .MOVI = { 962, 0}, + .MVNI = { 962, 0}, + .FMOV_V_IMM = { 962, 0}, + .LD1 = { 962, 4}, + .LD2 = { 966, 0}, + .LD3 = { 966, 0}, + .LD4 = { 966, 0}, + .ST1 = { 966, 4}, + .ST2 = { 970, 0}, + .ST3 = { 970, 0}, + .ST4 = { 970, 0}, + .LD1R = { 970, 0}, + .LD2R = { 970, 0}, + .LD3R = { 970, 0}, + .LD4R = { 970, 0}, + .LD1_LANE = { 970, 0}, + .LD2_LANE = { 970, 0}, + .LD3_LANE = { 970, 0}, + .LD4_LANE = { 970, 0}, + .ST1_LANE = { 970, 0}, + .ST2_LANE = { 970, 0}, + .ST3_LANE = { 970, 0}, + .ST4_LANE = { 970, 0}, + .LDR_V = { 970, 5}, + .STR_V = { 975, 5}, + .LDP_V = { 980, 0}, + .STP_V = { 980, 0}, + .LDUR_V = { 980, 0}, + .STUR_V = { 980, 0}, + .SVE_ADD_Z = { 980, 4}, + .SVE_SUB_Z = { 984, 4}, + .SVE_SQADD_Z = { 988, 4}, + .SVE_UQADD_Z = { 992, 4}, + .SVE_SQSUB_Z = { 996, 4}, + .SVE_UQSUB_Z = { 1000, 4}, + .SVE_ADD_PRED = { 1004, 4}, + .SVE_SUB_PRED = { 1008, 4}, + .SVE_SUBR_PRED = { 1012, 4}, + .SVE_MUL_PRED = { 1016, 4}, + .SVE_SMULH_PRED = { 1020, 4}, + .SVE_UMULH_PRED = { 1024, 4}, + .SVE_SDIV_PRED = { 1028, 2}, + .SVE_UDIV_PRED = { 1030, 2}, + .SVE_SMAX_PRED = { 1032, 4}, + .SVE_UMAX_PRED = { 1036, 4}, + .SVE_SMIN_PRED = { 1040, 4}, + .SVE_UMIN_PRED = { 1044, 4}, + .SVE_SABD_PRED = { 1048, 4}, + .SVE_UABD_PRED = { 1052, 4}, + .SVE_AND_PRED = { 1056, 1}, + .SVE_ORR_PRED = { 1057, 1}, + .SVE_EOR_PRED = { 1058, 1}, + .SVE_BIC_PRED = { 1059, 1}, + .SVE_ASR_PRED = { 1060, 4}, + .SVE_LSL_PRED = { 1064, 4}, + .SVE_LSR_PRED = { 1068, 4}, + .SVE_ASRR_PRED = { 1072, 0}, + .SVE_LSLR_PRED = { 1072, 0}, + .SVE_LSRR_PRED = { 1072, 0}, + .SVE_ABS_PRED = { 1072, 4}, + .SVE_NEG_PRED = { 1076, 4}, + .SVE_CLS_PRED = { 1080, 4}, + .SVE_CLZ_PRED = { 1084, 4}, + .SVE_CNT_PRED = { 1088, 4}, + .SVE_MOV_PRED = { 1092, 0}, + .SVE_FADD_Z = { 1092, 3}, + .SVE_FSUB_Z = { 1095, 3}, + .SVE_FMUL_Z = { 1098, 3}, + .SVE_FRECPS = { 1101, 3}, + .SVE_FRSQRTS = { 1104, 3}, + .SVE_FTSMUL = { 1107, 3}, + .SVE_FADD_PRED = { 1110, 3}, + .SVE_FSUB_PRED = { 1113, 3}, + .SVE_FSUBR_PRED = { 1116, 0}, + .SVE_FMUL_PRED = { 1116, 3}, + .SVE_FDIV_PRED = { 1119, 3}, + .SVE_FDIVR_PRED = { 1122, 0}, + .SVE_FMAX_PRED = { 1122, 3}, + .SVE_FMIN_PRED = { 1125, 3}, + .SVE_FMAXNM_PRED = { 1128, 3}, + .SVE_FMINNM_PRED = { 1131, 3}, + .SVE_FABS_Z = { 1134, 3}, + .SVE_FNEG_Z = { 1137, 3}, + .SVE_FSQRT_Z = { 1140, 3}, + .SVE_FRECPX_Z = { 1143, 0}, + .SVE_FRINTN = { 1143, 0}, + .SVE_FRINTP = { 1143, 0}, + .SVE_FRINTM = { 1143, 0}, + .SVE_FRINTZ = { 1143, 0}, + .SVE_FRINTA = { 1143, 0}, + .SVE_FRINTX = { 1143, 0}, + .SVE_FRINTI = { 1143, 0}, + .SVE_FMLA = { 1143, 3}, + .SVE_FMLS = { 1146, 3}, + .SVE_FNMLA = { 1149, 3}, + .SVE_FNMLS = { 1152, 3}, + .SVE_AND_P = { 1155, 1}, + .SVE_BIC_P = { 1156, 1}, + .SVE_ORR_P = { 1157, 1}, + .SVE_EOR_P = { 1158, 1}, + .SVE_NAND_P = { 1159, 1}, + .SVE_NOR_P = { 1160, 1}, + .SVE_ORN_P = { 1161, 1}, + .SVE_SEL_P = { 1162, 1}, + .SVE_ANDS_P = { 1163, 1}, + .SVE_BICS_P = { 1164, 1}, + .SVE_ORRS_P = { 1165, 1}, + .SVE_EORS_P = { 1166, 1}, + .SVE_NANDS_P = { 1167, 0}, + .SVE_NORS_P = { 1167, 0}, + .SVE_ORNS_P = { 1167, 0}, + .SVE_NOT_P = { 1167, 0}, + .SVE_MOV_P = { 1167, 0}, + .SVE_MOVS_P = { 1167, 0}, + .SVE_PTRUE = { 1167, 1}, + .SVE_PTRUES = { 1168, 1}, + .SVE_PFALSE = { 1169, 1}, + .SVE_PFIRST = { 1170, 1}, + .SVE_PNEXT = { 1171, 1}, + .SVE_BRKA = { 1172, 0}, + .SVE_BRKB = { 1172, 0}, + .SVE_BRKAS = { 1172, 0}, + .SVE_BRKBS = { 1172, 0}, + .SVE_BRKPA = { 1172, 0}, + .SVE_BRKPB = { 1172, 0}, + .SVE_BRKN = { 1172, 0}, + .SVE_RDFFR = { 1172, 0}, + .SVE_WRFFR = { 1172, 0}, + .SVE_SETFFR = { 1172, 0}, + .SVE_CMPEQ = { 1172, 4}, + .SVE_CMPNE = { 1176, 4}, + .SVE_CMPGE = { 1180, 4}, + .SVE_CMPGT = { 1184, 4}, + .SVE_CMPLE = { 1188, 0}, + .SVE_CMPLT = { 1188, 0}, + .SVE_CMPHI = { 1188, 4}, + .SVE_CMPHS = { 1192, 4}, + .SVE_CMPLO = { 1196, 0}, + .SVE_CMPLS = { 1196, 0}, + .SVE_FCMEQ = { 1196, 0}, + .SVE_FCMNE = { 1196, 0}, + .SVE_FCMGE = { 1196, 0}, + .SVE_FCMGT = { 1196, 0}, + .SVE_FCMLE = { 1196, 0}, + .SVE_FCMLT = { 1196, 0}, + .SVE_FCMUO = { 1196, 0}, + .SVE_DUP_Z = { 1196, 4}, + .SVE_INSR = { 1200, 0}, + .SVE_REV_Z = { 1200, 4}, + .SVE_REV_P = { 1204, 1}, + .SVE_TBL = { 1205, 4}, + .SVE_ZIP1_Z = { 1209, 4}, + .SVE_ZIP2_Z = { 1213, 4}, + .SVE_UZP1_Z = { 1217, 4}, + .SVE_UZP2_Z = { 1221, 4}, + .SVE_TRN1_Z = { 1225, 4}, + .SVE_TRN2_Z = { 1229, 4}, + .SVE_ZIP1_P = { 1233, 1}, + .SVE_ZIP2_P = { 1234, 1}, + .SVE_UZP1_P = { 1235, 1}, + .SVE_UZP2_P = { 1236, 1}, + .SVE_TRN1_P = { 1237, 1}, + .SVE_TRN2_P = { 1238, 1}, + .SVE_CPY_Z = { 1239, 0}, + .SVE_COMPACT = { 1239, 0}, + .SVE_EXT_Z = { 1239, 0}, + .SVE_LD1B = { 1239, 1}, + .SVE_LD1H = { 1240, 1}, + .SVE_LD1W = { 1241, 1}, + .SVE_LD1D = { 1242, 1}, + .SVE_LD1SB = { 1243, 1}, + .SVE_LD1SH = { 1244, 1}, + .SVE_LD1SW = { 1245, 1}, + .SVE_ST1B = { 1246, 1}, + .SVE_ST1H = { 1247, 1}, + .SVE_ST1W = { 1248, 1}, + .SVE_ST1D = { 1249, 1}, + .SVE_LDR_Z = { 1250, 1}, + .SVE_STR_Z = { 1251, 1}, + .SVE_LDR_P = { 1252, 1}, + .SVE_STR_P = { 1253, 1}, + .SVE_LDFF1B = { 1254, 1}, + .SVE_LDFF1H = { 1255, 1}, + .SVE_LDFF1W = { 1256, 1}, + .SVE_LDFF1D = { 1257, 1}, + .SVE_WHILEGE = { 1258, 1}, + .SVE_WHILEGT = { 1259, 1}, + .SVE_WHILELE = { 1260, 1}, + .SVE_WHILELT = { 1261, 1}, + .SVE_WHILEHI = { 1262, 1}, + .SVE_WHILEHS = { 1263, 1}, + .SVE_WHILELO = { 1264, 1}, + .SVE_WHILELS = { 1265, 1}, + .SVE_SQRDMLAH = { 1266, 4}, + .SVE_SQRDMLSH = { 1270, 4}, + .SVE_ADCLB = { 1274, 2}, + .SVE_ADCLT = { 1276, 2}, + .SVE_SBCLB = { 1278, 2}, + .SVE_SBCLT = { 1280, 2}, + .SVE_TBL2 = { 1282, 1}, + .SVE_TBX = { 1283, 1}, + .SVE_AESE = { 1284, 1}, + .SVE_AESD = { 1285, 1}, + .SVE_AESMC = { 1286, 1}, + .SVE_AESIMC = { 1287, 1}, + .SVE_BCAX_Z = { 1288, 0}, + .SVE_XAR_Z = { 1288, 0}, + .SVE_EOR3_Z = { 1288, 0}, + .SVE_MATCH = { 1288, 2}, + .SVE_NMATCH = { 1290, 2}, + .SVE_HISTCNT = { 1292, 2}, + .SVE_HISTSEG = { 1294, 1}, + .SME_SMSTART = { 1295, 1}, + .SME_SMSTOP = { 1296, 1}, + .SME_RDSVL = { 1297, 1}, + .SME_ADDHA = { 1298, 0}, + .SME_ADDVA = { 1298, 0}, + .SME_ZERO = { 1298, 1}, + .SME_FMOPA = { 1299, 1}, + .SME_FMOPS = { 1300, 1}, + .SME_BFMOPA = { 1301, 1}, + .SME_BFMOPS = { 1302, 1}, + .SME_SMOPA = { 1303, 2}, + .SME_SMOPS = { 1305, 2}, + .SME_UMOPA = { 1307, 2}, + .SME_UMOPS = { 1309, 2}, + .SME_USMOPA = { 1311, 1}, + .SME_SUMOPA = { 1312, 1}, + .SME_MOVA_TO_Z = { 1313, 0}, + .SME_MOVA_TO_ZA = { 1313, 0}, + .SME_LD1B_ZA = { 1313, 0}, + .SME_LD1H_ZA = { 1313, 0}, + .SME_LD1W_ZA = { 1313, 0}, + .SME_LD1D_ZA = { 1313, 0}, + .SME_LD1Q_ZA = { 1313, 0}, + .SME_ST1B_ZA = { 1313, 0}, + .SME_ST1H_ZA = { 1313, 0}, + .SME_ST1W_ZA = { 1313, 0}, + .SME_ST1D_ZA = { 1313, 0}, + .SME_ST1Q_ZA = { 1313, 0}, + .SME_LDR_ZA = { 1313, 1}, + .SME_STR_ZA = { 1314, 1}, + .SVE_FMLA_IDX_H = { 1315, 1}, + .SVE_FMLA_IDX_S = { 1316, 1}, + .SVE_FMLA_IDX_D = { 1317, 1}, + .SVE_FMLS_IDX_H = { 1318, 1}, + .SVE_FMLS_IDX_S = { 1319, 1}, + .SVE_FMLS_IDX_D = { 1320, 1}, + .SVE_LD1B_GATHER_S = { 1321, 1}, + .SVE_LD1B_GATHER_D = { 1322, 1}, + .SVE_LD1H_GATHER_S = { 1323, 1}, + .SVE_LD1H_GATHER_D = { 1324, 1}, + .SVE_LD1W_GATHER_S = { 1325, 1}, + .SVE_LD1W_GATHER_D = { 1326, 1}, + .SVE_LD1D_GATHER_D = { 1327, 1}, + .SVE_LD1SB_GATHER_S = { 1328, 1}, + .SVE_LD1SB_GATHER_D = { 1329, 1}, + .SVE_LD1SH_GATHER_S = { 1330, 1}, + .SVE_LD1SH_GATHER_D = { 1331, 1}, + .SVE_LD1SW_GATHER_D = { 1332, 1}, + .SVE_ST1B_SCATTER_S = { 1333, 1}, + .SVE_ST1B_SCATTER_D = { 1334, 1}, + .SVE_ST1H_SCATTER_S = { 1335, 1}, + .SVE_ST1H_SCATTER_D = { 1336, 1}, + .SVE_ST1W_SCATTER_S = { 1337, 1}, + .SVE_ST1W_SCATTER_D = { 1338, 1}, + .SVE_ST1D_SCATTER_D = { 1339, 1}, + .SME_LD1B_TILE = { 1340, 1}, + .SME_LD1H_TILE = { 1341, 1}, + .SME_LD1W_TILE = { 1342, 1}, + .SME_LD1D_TILE = { 1343, 1}, + .SME_LD1Q_TILE = { 1344, 1}, + .SME_ST1B_TILE = { 1345, 1}, + .SME_ST1H_TILE = { 1346, 1}, + .SME_ST1W_TILE = { 1347, 1}, + .SME_ST1D_TILE = { 1348, 1}, + .SME_ST1Q_TILE = { 1349, 1}, + .SME_MOVA_Z_FROM_TILE = { 1350, 1}, + .SME_MOVA_TILE_FROM_Z = { 1351, 1}, + .FCMLA_4H = { 1352, 1}, + .FCMLA_8H = { 1353, 1}, + .FCMLA_4S = { 1354, 1}, + .FCMLA_2D = { 1355, 1}, + .FCADD_4H = { 1356, 1}, + .FCADD_8H = { 1357, 1}, + .FCADD_4S = { 1358, 1}, + .FCADD_2D = { 1359, 1}, + .SVE_PRFB = { 1360, 1}, + .SVE_PRFH = { 1361, 1}, + .SVE_PRFW = { 1362, 1}, + .SVE_PRFD = { 1363, 1}, + .SVE_LDNT1B = { 1364, 1}, + .SVE_LDNT1H = { 1365, 1}, + .SVE_LDNT1W = { 1366, 1}, + .SVE_LDNT1D = { 1367, 1}, + .SVE_STNT1B = { 1368, 1}, + .SVE_STNT1H = { 1369, 1}, + .SVE_STNT1W = { 1370, 1}, + .SVE_STNT1D = { 1371, 1}, + .SVE_EXT = { 1372, 1}, + .SVE_SPLICE = { 1373, 1}, + .SVE_INDEX_II = { 1374, 1}, + .SVE_INDEX_IR = { 1375, 1}, + .SVE_INDEX_RI = { 1376, 1}, + .SVE_INDEX_RR = { 1377, 1}, + .SVE_BSL = { 1378, 1}, + .SVE_BSL1N = { 1379, 1}, + .SVE_BSL2N = { 1380, 1}, + .SVE_NBSL = { 1381, 1}, + .SVE_PMUL_VEC = { 1382, 1}, + .SVE_PMULLB = { 1383, 1}, + .SVE_PMULLT = { 1384, 1}, + .SVE_BFCVT = { 1385, 1}, + .SVE_BFCVTNT = { 1386, 1}, + .LDRAA = { 1387, 1}, + .LDRAB = { 1388, 1}, + .LDRAA_PRE = { 1389, 1}, + .LDRAB_PRE = { 1390, 1}, + .TSTART = { 1391, 1}, + .TCOMMIT = { 1392, 1}, + .TCANCEL = { 1393, 1}, + .TTEST = { 1394, 1}, + .WFET = { 1395, 1}, + .WFIT = { 1396, 1}, + .BC_COND = { 1397, 1}, + .UXTB = { 1398, 1}, + .UXTH = { 1399, 1}, + .UXTW = { 1400, 1}, + .SXTB = { 1401, 1}, + .SXTH = { 1402, 1}, + .SXTW = { 1403, 1}, + .ADC = { 1404, 2}, + .ADCS = { 1406, 2}, + .SBC = { 1408, 2}, + .SBCS = { 1410, 2}, + .NGC = { 1412, 2}, + .NGCS = { 1414, 2}, + .LDAPUR = { 1416, 2}, + .STLUR = { 1418, 2}, + .LDAPURB = { 1420, 1}, + .STLURB = { 1421, 1}, + .LDAPURH = { 1422, 1}, + .STLURH = { 1423, 1}, + .LDAPURSB = { 1424, 2}, + .LDAPURSH = { 1426, 2}, + .LDAPURSW = { 1428, 1}, + .SVE_BFADD = { 1429, 1}, + .SVE_BFSUB = { 1430, 1}, + .SVE_BFMUL = { 1431, 1}, + .SVE_BFMLA = { 1432, 1}, + .SVE_BFMLS = { 1433, 1}, + .SB = { 1434, 1}, + .CSDB = { 1435, 1}, + .DGH = { 1436, 1}, + .PSB_CSYNC = { 1437, 1}, + .TSB_CSYNC = { 1438, 1}, + .BTI_J = { 1439, 1}, + .BTI_C = { 1440, 1}, + .BTI_JC = { 1441, 1}, + .MOV_V_ALIAS = { 1442, 2}, + .NOT_V_ALIAS = { 1444, 2}, + .LSL_IMM = { 1446, 2}, + .LSR_IMM = { 1448, 2}, + .ASR_IMM = { 1450, 2}, + .ROR_IMM = { 1452, 2}, + .SVE_BFADD_UNPRED = { 1454, 1}, + .SVE_BFSUB_UNPRED = { 1455, 1}, + .SVE_BFMUL_UNPRED = { 1456, 1}, + .SVE_BFCLAMP = { 1457, 1}, + .SVE_BFMAXNM = { 1458, 1}, + .SVE_BFMINNM = { 1459, 1}, + .SME2_LUTI2_B = { 1460, 1}, + .SME2_LUTI4_B = { 1461, 1}, + .SME2_LD1B_X2 = { 1462, 1}, + .SME2_LD1H_X2 = { 1463, 1}, + .SME2_LD1W_X2 = { 1464, 1}, + .SME2_LD1D_X2 = { 1465, 1}, + .SME2_LD1B_X4 = { 1466, 1}, + .SME2_LD1H_X4 = { 1467, 1}, + .SME2_LD1W_X4 = { 1468, 1}, + .SME2_LD1D_X4 = { 1469, 1}, + .SME2_ST1B_X2 = { 1470, 1}, + .SME2_ST1H_X2 = { 1471, 1}, + .SME2_ST1W_X2 = { 1472, 1}, + .SME2_ST1D_X2 = { 1473, 1}, + .SME2_ST1B_X4 = { 1474, 1}, + .SME2_ST1H_X4 = { 1475, 1}, + .SME2_ST1W_X4 = { 1476, 1}, + .SME2_ST1D_X4 = { 1477, 1}, + .SME2_ZIP_3 = { 1478, 1}, + .SME2_ZIP_4 = { 1479, 1}, + .SME2_UZP_3 = { 1480, 1}, + .SME2_UZP_4 = { 1481, 1}, + .TLBI_RPALOS = { 1482, 1}, + .TLBI_RPAOS = { 1483, 1}, + .AT_S1E1A = { 1484, 1}, + .DC_CIPAPA = { 1485, 1}, + .DC_CIGDPAPA = { 1486, 1}, + .TLBI_PAALL = { 1487, 1}, + .TLBI_PAALLOS = { 1488, 1}, + .AMX_LDX = { 1489, 1}, + .AMX_LDY = { 1490, 1}, + .AMX_STX = { 1491, 1}, + .AMX_STY = { 1492, 1}, + .AMX_LDZ = { 1493, 1}, + .AMX_STZ = { 1494, 1}, + .AMX_LDZI = { 1495, 1}, + .AMX_STZI = { 1496, 1}, + .AMX_EXTRX = { 1497, 1}, + .AMX_EXTRY = { 1498, 1}, + .AMX_FMA64 = { 1499, 1}, + .AMX_FMS64 = { 1500, 1}, + .AMX_FMA32 = { 1501, 1}, + .AMX_FMS32 = { 1502, 1}, + .AMX_MAC16 = { 1503, 1}, + .AMX_FMA16 = { 1504, 1}, + .AMX_FMS16 = { 1505, 1}, + .AMX_SET = { 1506, 1}, + .AMX_CLR = { 1507, 1}, + .AMX_VECINT = { 1508, 1}, + .AMX_VECFP = { 1509, 1}, + .AMX_MATINT = { 1510, 1}, + .AMX_MATFP = { 1511, 1}, + .AMX_GENLUT = { 1512, 1}, + .CPYP = { 1513, 1}, + .CPYM = { 1514, 1}, + .CPYE = { 1515, 1}, + .CPYFP = { 1516, 1}, + .CPYFM = { 1517, 1}, + .CPYFE = { 1518, 1}, + .SETP = { 1519, 1}, + .SETM = { 1520, 1}, + .SETE = { 1521, 1}, + .DC_IVAC = { 1522, 1}, + .DC_ISW = { 1523, 1}, + .DC_CSW = { 1524, 1}, + .DC_CISW = { 1525, 1}, + .DC_ZVA = { 1526, 1}, + .DC_CVAC = { 1527, 1}, + .DC_CVAU = { 1528, 1}, + .DC_CIVAC = { 1529, 1}, + .IC_IALLUIS = { 1530, 1}, + .IC_IALLU = { 1531, 1}, + .IC_IVAU = { 1532, 1}, + .AT_S1E1R = { 1533, 1}, + .AT_S1E1W = { 1534, 1}, + .AT_S1E0R = { 1535, 1}, + .AT_S1E0W = { 1536, 1}, + .AT_S1E2R = { 1537, 1}, + .AT_S1E2W = { 1538, 1}, + .AT_S1E3R = { 1539, 1}, + .AT_S1E3W = { 1540, 1}, + .AT_S12E1R = { 1541, 1}, + .AT_S12E1W = { 1542, 1}, + .AT_S12E0R = { 1543, 1}, + .AT_S12E0W = { 1544, 1}, + .TLBI_VMALLE1 = { 1545, 1}, + .TLBI_VMALLE1IS = { 1546, 1}, + .TLBI_VAE1 = { 1547, 1}, + .TLBI_VAE1IS = { 1548, 1}, + .TLBI_ASIDE1 = { 1549, 1}, + .TLBI_ASIDE1IS = { 1550, 1}, + .TLBI_VAAE1 = { 1551, 1}, + .TLBI_VAAE1IS = { 1552, 1}, + .TLBI_VALE1 = { 1553, 1}, + .TLBI_VALE1IS = { 1554, 1}, + .TLBI_VAALE1 = { 1555, 1}, + .TLBI_VAALE1IS = { 1556, 1}, + .TLBI_ALLE1 = { 1557, 1}, + .TLBI_ALLE1IS = { 1558, 1}, + .TLBI_ALLE2 = { 1559, 1}, + .TLBI_ALLE2IS = { 1560, 1}, + .TLBI_ALLE3 = { 1561, 1}, + .TLBI_ALLE3IS = { 1562, 1}, + .PRFM = { 1563, 1}, + .PRFUM = { 1564, 1}, + .PRFM_LIT = { 1565, 1}, + .MOV_REG = { 1566, 2}, + .MOV_BITMASK = { 1568, 2}, + .MVN = { 1570, 2}, + .NEG_SR = { 1572, 2}, + .NEGS = { 1574, 2}, + .CMP_SR = { 1576, 2}, + .CMP_ER = { 1578, 2}, + .CMP_IMM = { 1580, 2}, + .CMN_SR = { 1582, 2}, + .CMN_ER = { 1584, 2}, + .CMN_IMM = { 1586, 2}, + .TST_SR = { 1588, 2}, } diff --git a/core/rexcode/arm64/tablegen/specgen.lua b/core/rexcode/arm64/tablegen/specgen.lua index 2196a6364..8d9ea73f8 100644 --- a/core/rexcode/arm64/tablegen/specgen.lua +++ b/core/rexcode/arm64/tablegen/specgen.lua @@ -5,14 +5,16 @@ -- into ENCODING_TABLE entries, deriving `bits` from llvm-mc (the oracle) and -- `mask` empirically: assemble each form with operand registers at 0 and at 31; -- the differing bits are operand-driven, so mask = ~(bits0 ^ bits31). Per-form --- assembly makes it robust: an arrangement llvm-mc rejects (e.g. SQADD .1D) is --- reported and skipped, never misaligned. +-- assembly makes it robust: an arrangement llvm-mc rejects is reported, skipped. -- --- The generated entries replace the SPECGEN:BEGIN..SPECGEN:END region of --- encoding_table.odin in place (the hand-written core is left untouched). Every --- bit pattern is therefore reproducible and llvm-mc-backed. +-- Output replaces the SPECGEN:BEGIN..SPECGEN:END region of encoding_table.odin +-- in place; the hand-written core is untouched. Every bit pattern is therefore +-- reproducible and llvm-mc-backed. -- --- Adding a family: pick a SHAPE (operand layout) and list {enum, llvm} pairs. +-- Two spec kinds: +-- * uniform — every operand shares one arrangement T (iterate ALL_ARR). +-- * diff — operands have different arrangements (long/wide/narrow/XTN); +-- each item lists the arrangement TUPLE per size-variant. -- -- Run: luajit tablegen/specgen.lua (from arm64/, or with a full path) @@ -21,45 +23,14 @@ local LLVM = "llvm-mc --assemble --arch=aarch64 --show-encoding" local DIR = (arg[0]:match("^(.*)/[^/]*$")) or "." local TABLE = DIR .. "/encoding_table.odin" --- arrangement token -> { vt = Operand_Type, asm = llvm suffix } local ARR = { ["8B"]={vt="V_8B",asm="8b"}, ["16B"]={vt="V_16B",asm="16b"}, ["4H"]={vt="V_4H",asm="4h"}, ["8H"] ={vt="V_8H", asm="8h"}, ["2S"]={vt="V_2S",asm="2s"}, ["4S"] ={vt="V_4S", asm="4s"}, ["1D"]={vt="V_1D",asm="1d"}, ["2D"] ={vt="V_2D", asm="2d"}, } --- over-specify; llvm-mc decides which arrangements are legal per instruction. local ALL_ARR = {"8B","16B","4H","8H","2S","4S","2D"} --- Vector shapes (all operands share one arrangement T). enc lists the register --- slots, in operand order. The encoder packs each into its 5-bit field. -local SHAPE = { - THREE_SAME = { nreg=3, enc={"VD","VN","VM"} }, -- Vd.T, Vn.T, Vm.T - TWO_SAME = { nreg=2, enc={"VD","VN"} }, -- Vd.T, Vn.T -} - --- Families: { shape, feature, items = {{enum, llvm}, ...} } -local FAMILIES = { - { shape="THREE_SAME", feature="NEON", title="Advanced SIMD three-same (integer)", items = { - {"SHADD","shadd"}, {"UHADD","uhadd"}, {"SHSUB","shsub"}, {"UHSUB","uhsub"}, - {"SRHADD","srhadd"},{"URHADD","urhadd"}, - {"SQADD","sqadd"}, {"UQADD","uqadd"}, {"SQSUB","sqsub"}, {"UQSUB","uqsub"}, - {"SMAX","smax"}, {"UMAX","umax"}, {"SMIN","smin"}, {"UMIN","umin"}, - {"SABD","sabd"}, {"UABD","uabd"}, {"SABA","saba"}, {"UABA","uaba"}, - {"MLA_V","mla"}, {"MLS_V","mls"}, - {"CMGE","cmge"}, {"CMHS","cmhs"}, {"CMTST","cmtst"}, - {"SQDMULH","sqdmulh"}, {"SQRDMULH","sqrdmulh"}, - {"ADDP_V","addp"}, {"SMAXP","smaxp"}, {"SMINP","sminp"}, {"UMAXP","umaxp"}, {"UMINP","uminp"}, - {"SSHL","sshl"}, {"USHL","ushl"}, {"SRSHL","srshl"}, {"URSHL","urshl"}, - }}, - { shape="TWO_SAME", feature="NEON", title="Advanced SIMD two-register misc", items = { - {"NOT_V","not"}, {"RBIT_V","rbit"}, - {"REV16_V","rev16"},{"REV32_V","rev32"},{"REV64","rev64"}, - {"CLS_V","cls"}, {"CLZ_V","clz"}, {"CNT","cnt"}, - {"URECPE_V","urecpe"}, {"URSQRTE_V","ursqrte"}, - }}, -} - local function word(line) local p = io.popen(string.format("printf '%%s\\n' '%s' | %s 2>/dev/null", line, LLVM)) local out = p:read("*a"); p:close() @@ -68,98 +39,137 @@ local function word(line) return tonumber(b4..b3..b2..b1, 16) end -local function padded(prefix_tokens, n) +local function padded(tokens, n) local t = {} - for i = 1, 4 do t[i] = prefix_tokens[i] or ".NONE" end + for i = 1, 4 do t[i] = tokens[i] or ".NONE" end return "{" .. table.concat(t, ", ") .. "}" end local sections, skips, n_forms, n_mnem = {}, {}, 0, 0 -for _, fam in ipairs(FAMILIES) do - local sh = SHAPE[fam.shape] - local enc_tokens = {}; for i, e in ipairs(sh.enc) do enc_tokens[i] = "."..e end - local enc_str = padded(enc_tokens, sh.nreg) - local blocks = {} - for _, it in ipairs(fam.items) do - local mnem, llvm = it[1], it[2] - local rows = {} - for _, a in ipairs(ALL_ARR) do - local s = ARR[a].asm - local function mk(reg) - local parts = {}; for i = 1, sh.nreg do parts[i] = "v"..reg.."."..s end - return llvm.." "..table.concat(parts, ", ") - end - local w0, w31 = word(mk(0)), word(mk(31)) - if w0 and w31 then - local mask = bit.band(bit.bnot(bit.bxor(w0, w31)), 0xFFFFFFFF) - local op_tokens = {}; for i = 1, sh.nreg do op_tokens[i] = "."..ARR[a].vt end - rows[#rows+1] = string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .%s, {}},", - mnem, padded(op_tokens, sh.nreg), enc_str, - bit.tohex(w0):upper(), bit.tohex(mask):upper(), fam.feature) - n_forms = n_forms + 1 - else - skips[#skips+1] = mnem.." ."..a - end + +-- Emit one mnemonic's block from a list of arrangement tuples (operand order). +-- enc_str is the prebuilt "{.VD, .VN, .VM, .NONE}" enc array text. +local function emit(mnem, llvm, enc_str, feature, variants) + local rows = {} + for _, tup in ipairs(variants) do + local function mk(r) + local parts = {} + for i, arr in ipairs(tup) do parts[i] = "v"..r.."."..ARR[arr].asm end + return llvm.." "..table.concat(parts, ", ") end - if #rows > 0 then - blocks[#blocks+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) - n_mnem = n_mnem + 1 + local w0, w31 = word(mk(0)), word(mk(31)) + if w0 and w31 then + local mask = bit.band(bit.bnot(bit.bxor(w0, w31)), 0xFFFFFFFF) + local ops = {} + for i, arr in ipairs(tup) do ops[i] = "."..ARR[arr].vt end + rows[#rows+1] = string.format("\t\t{.%s, %s, %s, 0x%s, 0x%s, .%s, {}},", + mnem, padded(ops, #tup), enc_str, bit.tohex(w0):upper(), bit.tohex(mask):upper(), feature) + n_forms = n_forms + 1 + else + skips[#skips+1] = mnem.." "..table.concat(tup, "/") end end - sections[#sections+1] = string.format("\t// %s.\n%s", fam.title, table.concat(blocks, "\n")) + if #rows == 0 then return nil end + n_mnem = n_mnem + 1 + return string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) end --- Advanced SIMD three-different (long): Vd., Vn., Vm.. --- Base mnemonics use the low-half source arrangement; the "2" variants use the --- high half. enc stays VD/VN/VM; only the operand arrangements differ. -local LONG_LOW = {{"8H","8B"},{"4S","4H"},{"2D","2S"}} -local LONG_HIGH = {{"8H","16B"},{"4S","8H"},{"2D","4S"}} -local THREE_DIFF = { - {"SADDL","saddl",LONG_LOW}, {"SADDL2","saddl2",LONG_HIGH}, - {"UADDL","uaddl",LONG_LOW}, {"UADDL2","uaddl2",LONG_HIGH}, - {"SSUBL","ssubl",LONG_LOW}, {"SSUBL2","ssubl2",LONG_HIGH}, - {"USUBL","usubl",LONG_LOW}, {"USUBL2","usubl2",LONG_HIGH}, - {"SMULL_V","smull",LONG_LOW}, {"SMULL2_V","smull2",LONG_HIGH}, - {"UMULL_V","umull",LONG_LOW}, {"UMULL2_V","umull2",LONG_HIGH}, - {"SMLAL","smlal",LONG_LOW}, {"SMLAL2","smlal2",LONG_HIGH}, - {"UMLAL","umlal",LONG_LOW}, {"UMLAL2","umlal2",LONG_HIGH}, - {"SMLSL","smlsl",LONG_LOW}, {"SMLSL2","smlsl2",LONG_HIGH}, - {"UMLSL","umlsl",LONG_LOW}, {"UMLSL2","umlsl2",LONG_HIGH}, - {"SQDMULL","sqdmull",LONG_LOW}, {"SQDMULL2","sqdmull2",LONG_HIGH}, - {"SQDMLAL","sqdmlal",LONG_LOW}, {"SQDMLAL2","sqdmlal2",LONG_HIGH}, - {"SQDMLSL","sqdmlsl",LONG_LOW}, {"SQDMLSL2","sqdmlsl2",LONG_HIGH}, +-- ---- Uniform shapes (all operands share one arrangement) ------------------- +local VD_VN_VM = padded({".VD",".VN",".VM"}, 3) +local VD_VN = padded({".VD",".VN"}, 2) + +local UNIFORM = { + { title="three-same (integer)", enc=VD_VN_VM, nreg=3, items={ + {"SHADD","shadd"},{"UHADD","uhadd"},{"SHSUB","shsub"},{"UHSUB","uhsub"}, + {"SRHADD","srhadd"},{"URHADD","urhadd"}, + {"SQADD","sqadd"},{"UQADD","uqadd"},{"SQSUB","sqsub"},{"UQSUB","uqsub"}, + {"SMAX","smax"},{"UMAX","umax"},{"SMIN","smin"},{"UMIN","umin"}, + {"SABD","sabd"},{"UABD","uabd"},{"SABA","saba"},{"UABA","uaba"}, + {"MLA_V","mla"},{"MLS_V","mls"}, + {"CMGE","cmge"},{"CMHS","cmhs"},{"CMTST","cmtst"}, + {"SQDMULH","sqdmulh"},{"SQRDMULH","sqrdmulh"}, + {"ADDP_V","addp"},{"SMAXP","smaxp"},{"SMINP","sminp"},{"UMAXP","umaxp"},{"UMINP","uminp"}, + {"SSHL","sshl"},{"USHL","ushl"},{"SRSHL","srshl"},{"URSHL","urshl"}, + }}, + { title="two-register misc", enc=VD_VN, nreg=2, items={ + {"NOT_V","not"},{"RBIT_V","rbit"}, + {"REV16_V","rev16"},{"REV32_V","rev32"},{"REV64","rev64"}, + {"CLS_V","cls"},{"CLZ_V","clz"},{"CNT","cnt"}, + {"URECPE_V","urecpe"},{"URSQRTE_V","ursqrte"}, + }}, } -do - local dblocks = {} - for _, it in ipairs(THREE_DIFF) do - local mnem, llvm, pairs = it[1], it[2], it[3] - local rows = {} - for _, pr in ipairs(pairs) do - local d, s = pr[1], pr[2] - local da, sa = ARR[d].asm, ARR[s].asm - local function mk(r) return string.format("%s v%d.%s, v%d.%s, v%d.%s", llvm, r,da, r,sa, r,sa) end - local w0, w31 = word(mk(0)), word(mk(31)) - if w0 and w31 then - local mask = bit.band(bit.bnot(bit.bxor(w0, w31)), 0xFFFFFFFF) - rows[#rows+1] = string.format( - "\t\t{.%s, {.%s, .%s, .%s, .NONE}, {.VD, .VN, .VM, .NONE}, 0x%s, 0x%s, .NEON, {}},", - mnem, ARR[d].vt, ARR[s].vt, ARR[s].vt, - bit.tohex(w0):upper(), bit.tohex(mask):upper()) - n_forms = n_forms + 1 - else - skips[#skips+1] = mnem.." "..d.."<-"..s - end - end - if #rows > 0 then - dblocks[#dblocks+1] = string.format("\t.%s = {\n%s\n\t},", mnem, table.concat(rows, "\n")) - n_mnem = n_mnem + 1 +for _, fam in ipairs(UNIFORM) do + local blk = {} + for _, it in ipairs(fam.items) do + local variants = {} + for _, a in ipairs(ALL_ARR) do + local tup = {}; for i = 1, fam.nreg do tup[i] = a end + variants[#variants+1] = tup end + local b = emit(it[1], it[2], fam.enc, "NEON", variants) + if b then blk[#blk+1] = b end end - sections[#sections+1] = "\t// Advanced SIMD three-different (long).\n" .. table.concat(dblocks, "\n") + sections[#sections+1] = "\t// Advanced SIMD "..fam.title..".\n" .. table.concat(blk, "\n") end -local region = "\t// SPECGEN:BEGIN\n" .. table.concat(sections, "\n\n") .. "\n\t// SPECGEN:END" +-- ---- Mixed-arrangement shapes (long / wide / narrow / XTN) ------------------ +-- arrangement tuples per size-variant (operand order: dst, n, [m]). Base +-- mnemonics take the low-half source, the "2" variants the high half. +local LONG_LO = {{"8H","8B","8B"},{"4S","4H","4H"},{"2D","2S","2S"}} +local LONG_HI = {{"8H","16B","16B"},{"4S","8H","8H"},{"2D","4S","4S"}} +local WIDE_LO = {{"8H","8H","8B"},{"4S","4S","4H"},{"2D","2D","2S"}} +local WIDE_HI = {{"8H","8H","16B"},{"4S","4S","8H"},{"2D","2D","4S"}} +local NARR_LO = {{"8B","8H","8H"},{"4H","4S","4S"},{"2S","2D","2D"}} +local NARR_HI = {{"16B","8H","8H"},{"8H","4S","4S"},{"4S","2D","2D"}} +local XTN_LO = {{"8B","8H"},{"4H","4S"},{"2S","2D"}} +local XTN_HI = {{"16B","8H"},{"8H","4S"},{"4S","2D"}} +local DIFF = { + { title="three-different (long)", enc=VD_VN_VM, items={ + {"SADDL","saddl",LONG_LO},{"SADDL2","saddl2",LONG_HI}, + {"UADDL","uaddl",LONG_LO},{"UADDL2","uaddl2",LONG_HI}, + {"SSUBL","ssubl",LONG_LO},{"SSUBL2","ssubl2",LONG_HI}, + {"USUBL","usubl",LONG_LO},{"USUBL2","usubl2",LONG_HI}, + {"SMULL_V","smull",LONG_LO},{"SMULL2_V","smull2",LONG_HI}, + {"UMULL_V","umull",LONG_LO},{"UMULL2_V","umull2",LONG_HI}, + {"SMLAL","smlal",LONG_LO},{"SMLAL2","smlal2",LONG_HI}, + {"UMLAL","umlal",LONG_LO},{"UMLAL2","umlal2",LONG_HI}, + {"SMLSL","smlsl",LONG_LO},{"SMLSL2","smlsl2",LONG_HI}, + {"UMLSL","umlsl",LONG_LO},{"UMLSL2","umlsl2",LONG_HI}, + {"SQDMULL","sqdmull",LONG_LO},{"SQDMULL2","sqdmull2",LONG_HI}, + {"SQDMLAL","sqdmlal",LONG_LO},{"SQDMLAL2","sqdmlal2",LONG_HI}, + {"SQDMLSL","sqdmlsl",LONG_LO},{"SQDMLSL2","sqdmlsl2",LONG_HI}, + }}, + { title="three-different (wide)", enc=VD_VN_VM, items={ + {"SADDW","saddw",WIDE_LO},{"SADDW2","saddw2",WIDE_HI}, + {"UADDW","uaddw",WIDE_LO},{"UADDW2","uaddw2",WIDE_HI}, + {"SSUBW","ssubw",WIDE_LO},{"SSUBW2","ssubw2",WIDE_HI}, + {"USUBW","usubw",WIDE_LO},{"USUBW2","usubw2",WIDE_HI}, + }}, + { title="three-different (narrow, halving)", enc=VD_VN_VM, items={ + {"ADDHN","addhn",NARR_LO},{"ADDHN2","addhn2",NARR_HI}, + {"SUBHN","subhn",NARR_LO},{"SUBHN2","subhn2",NARR_HI}, + {"RADDHN","raddhn",NARR_LO},{"RADDHN2","raddhn2",NARR_HI}, + {"RSUBHN","rsubhn",NARR_LO},{"RSUBHN2","rsubhn2",NARR_HI}, + }}, + { title="two-register narrowing (XTN)", enc=VD_VN, items={ + {"XTN","xtn",XTN_LO},{"XTN2","xtn2",XTN_HI}, + {"SQXTN","sqxtn",XTN_LO},{"SQXTN2","sqxtn2",XTN_HI}, + {"UQXTN","uqxtn",XTN_LO},{"UQXTN2","uqxtn2",XTN_HI}, + {"SQXTUN","sqxtun",XTN_LO},{"SQXTUN2","sqxtun2",XTN_HI}, + }}, +} +for _, fam in ipairs(DIFF) do + local blk = {} + for _, it in ipairs(fam.items) do + local b = emit(it[1], it[2], fam.enc, "NEON", it[3]) + if b then blk[#blk+1] = b end + end + sections[#sections+1] = "\t// Advanced SIMD "..fam.title..".\n" .. table.concat(blk, "\n") +end + +-- ---- splice into the SoT --------------------------------------------------- +local region = "\t// SPECGEN:BEGIN\n" .. table.concat(sections, "\n\n") .. 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