diff --git a/core/rexcode/arm32/decoder.odin b/core/rexcode/arm32/decoder.odin index c7b5a11d0..3e21df7e9 100644 --- a/core/rexcode/arm32/decoder.odin +++ b/core/rexcode/arm32/decoder.odin @@ -464,6 +464,22 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op imm5 := (word >> 3) & 0x1F v := (i_bit << 6) | (imm5 << 1) return op_rel_offset(i64(v)) + // ---- ARMv8.1-M Branch Future ---- + case .BF_BOFF: + imm4 := (word >> 23) & 0xF // hw0[10:7] + return op_rel_offset(i64(imm4) << 1) + case .BF_BLOC: + j := (word >> 11) & 1 // hw1[11] + imm10 := (word >> 1) & 0x3FF // hw1[10:1] + val := (imm10 << 1) | j + return op_rel_offset(i64(val) << 1) + case .BF_BELSE: + imm := (word >> 23) & 0xF + return op_rel_offset(i64(imm) << 1) + case .BF_RM: + return op_reg(Register(REG_GPR | u16((word >> 16) & 0xF))) + case .BFCSEL_COND: + return op_imm(i64((word >> 18) & 0xF)) // ---- Saturate / bit field ---- case .SAT_IMM5, .SAT_IMM5_T32, .BFI_MSB: diff --git a/core/rexcode/arm32/encoder.odin b/core/rexcode/arm32/encoder.odin index 4ba1e846d..29b72f922 100644 --- a/core/rexcode/arm32/encoder.odin +++ b/core/rexcode/arm32/encoder.odin @@ -267,7 +267,7 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op .IMM_ENDIAN, .IMM_IFLAGS, .IMM_BANKED, .IMM_SYSM, .IMM_COPROC, .IMM_COPROC_OP, .NEON_IMM, .IMM16_LO_HI: return op.kind == .IMMEDIATE - case .REL24, .REL24_T32, .REL20, .REL11, .REL8, .REL_LDR_LITERAL: + case .REL24, .REL24_T32, .REL20, .REL11, .REL8, .REL_LDR_LITERAL, .REL_BF: return op.kind == .RELATIVE case .COND: return op.kind == .IMMEDIATE @@ -561,6 +561,30 @@ pack_operand_inline :: #force_inline proc( }) return 0 + // ---- ARMv8.1-M Branch Future ------------------------------------------- + case .BF_BOFF: + append(relocs, Relocation{ + offset = pc, label_id = u32(op.relative), + type = .BF_BOFF_T32, size = 4, inst_idx = inst_idx, + }) + return 0 + case .BF_BLOC: + append(relocs, Relocation{ + offset = pc, label_id = u32(op.relative), + type = .BF_BLOC_T32, size = 4, inst_idx = inst_idx, + }) + return 0 + case .BF_BELSE: + append(relocs, Relocation{ + offset = pc, label_id = u32(op.relative), + type = .BFCSEL_ELSE_T32, size = 4, inst_idx = inst_idx, + }) + return 0 + case .BF_RM: + return (u32(reg_hw(op.reg)) & 0xF) << 16 // Rm at hw0[3:0] (word bits 19:16) + case .BFCSEL_COND: + return (u32(op.immediate) & 0xF) << 18 // cond at hw0[5:2] (word bits 21:18) + // ---- Misc -------------------------------------------------------------- case .PSR_FIELD_MASK: return encode_psr_field(u8(op.immediate)) case .SYSM_FIELD: return u32(op.immediate) & 0xFF @@ -727,6 +751,31 @@ resolve_relocation_inline :: #force_inline proc( write_u16_le(code, r.offset + 2, existing | (imm11 << 1)) return true + case .BF_BOFF_T32: + // Branch Future bf-point: imm4 = (label-(PC+4))/2 at hw0[10:7]. + rel := i32(target) - (i32(r.offset) + 4) + r.addend + if rel & 1 != 0 || rel < 0 || rel >= (1 << 5) { + append(errors, Error{inst_idx = u32(r.inst_idx), code = .LABEL_OUT_OF_RANGE}) + return true + } + imm4 := u16(u32(rel >> 1) & 0xF) + hw0 := read_u16_le(code, r.offset) + write_u16_le(code, r.offset, hw0 | (imm4 << 7)) + return true + + case .BF_BLOC_T32: + // Branch Future target: val=(label-(PC+4))/2; J at hw1[11], imm10 at hw1[10:1]. + rel := i32(target) - (i32(r.offset) + 4) + r.addend + if rel & 1 != 0 || rel < -(1 << 11) || rel >= (1 << 11) { + append(errors, Error{inst_idx = u32(r.inst_idx), code = .LABEL_OUT_OF_RANGE}) + return true + } + val := u32(rel >> 1) + hw1 := read_u16_le(code, r.offset + 2) + hw1 |= u16((val & 1) << 11) | u16(((val >> 1) & 0x3FF) << 1) + write_u16_le(code, r.offset + 2, hw1) + return true + case .LDR_LITERAL_A32: rel := i32(target) - (i32(r.offset) + 8) + r.addend u_bit: u32 = rel >= 0 ? 1 : 0 diff --git a/core/rexcode/arm32/encoding_types.odin b/core/rexcode/arm32/encoding_types.odin index 421385f6b..7bea46b5e 100644 --- a/core/rexcode/arm32/encoding_types.odin +++ b/core/rexcode/arm32/encoding_types.odin @@ -214,6 +214,7 @@ Operand_Type :: enum u8 { REL11, // T16 B REL8, // T16 conditional branch (signed 8-bit) REL_LDR_LITERAL, // PC-relative literal load offset + REL_BF, // ARMv8.1-M Branch Future label (bf-point / branch target) // ---- Condition code ---- COND, // 4-bit cond field (for IT block / B / etc.) @@ -352,6 +353,12 @@ Operand_Encoding :: enum u8 { BRANCH_11_T16, // T16 unconditional (imm11, scaled ×2, ±2KB) BRANCH_8_T16, // T16 conditional (cond + imm8, scaled ×2, ±256B) BRANCH_CBZ, // T16 CBZ/CBNZ (i + imm5 + Rn, scaled ×2) + // ARMv8.1-M Branch Future fields (T32): + BF_BOFF, // bf-point offset: imm4 at hw0[10:7], (label-PC-4)/2 + BF_BLOC, // branch target: J at hw1[11] + imm10 at hw1[10:1] + BF_BELSE, // BFCSEL else-target: imm4 at hw0[? ] (relative to bf-point) + BF_RM, // BFLX/BFX register target at hw0[3:0] + BFCSEL_COND, // BFCSEL condition at hw0[5:2] // ---- Misc ---- PSR_FIELD_MASK, // APSR fields_mask at bits 19-16 (MSR) diff --git a/core/rexcode/arm32/mnemonic_builders.odin b/core/rexcode/arm32/mnemonic_builders.odin index 053881f91..e698ffbe6 100644 --- a/core/rexcode/arm32/mnemonic_builders.odin +++ b/core/rexcode/arm32/mnemonic_builders.odin @@ -1174,6 +1174,14 @@ inst_letp_rel :: #force_inline proc "contextless" (offset: i6 emit_letp_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64) { append(instructions, inst_letp_rel(offset)) } inst_lctp_none :: #force_inline proc "contextless" () -> Instruction { return Instruction{mnemonic = .LCTP, operand_count = 0, mode = .T32, cond = 14, length = 4, ops = {{}, {}, {}, {}}} } emit_lctp_none :: #force_inline proc(instructions: ^[dynamic]Instruction) { append(instructions, inst_lctp_none()) } +inst_bf_rel_rel :: #force_inline proc "contextless" (offset: i64, offset2: i64) -> Instruction { return Instruction{mnemonic = .BF, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_rel_offset(offset2), {}, {}}} } +emit_bf_rel_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, offset2: i64) { append(instructions, inst_bf_rel_rel(offset, offset2)) } +inst_bfi_br_rel_r :: #force_inline proc "contextless" (offset: i64, src: Register) -> Instruction { return Instruction{mnemonic = .BFI_BR, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_reg(src), {}, {}}} } +emit_bfi_br_rel_r :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, src: Register) { append(instructions, inst_bfi_br_rel_r(offset, src)) } +inst_bfl_rel_rel :: #force_inline proc "contextless" (offset: i64, offset2: i64) -> Instruction { return Instruction{mnemonic = .BFL, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_rel_offset(offset2), {}, {}}} } +emit_bfl_rel_rel :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, offset2: i64) { append(instructions, inst_bfl_rel_rel(offset, offset2)) } +inst_bflx_rel_r :: #force_inline proc "contextless" (offset: i64, src: Register) -> Instruction { return Instruction{mnemonic = .BFLX, operand_count = 2, mode = .T32, cond = 14, length = 4, ops = {op_rel_offset(offset), op_reg(src), {}, {}}} } +emit_bflx_rel_r :: #force_inline proc(instructions: ^[dynamic]Instruction, offset: i64, src: Register) { append(instructions, inst_bflx_rel_r(offset, src)) } inst_cx1_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } emit_cx1_cp_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register, imm2: i64) { append(instructions, inst_cx1_cp_r_imm(imm, src, imm2)) } inst_cx1a_cp_r_imm :: #force_inline proc "contextless" (imm: i64, src: Register, imm2: i64) -> Instruction { return Instruction{mnemonic = .CX1A, operand_count = 3, mode = .T32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), op_imm(imm2), {}}} } @@ -2431,6 +2439,14 @@ inst_letp :: inst_letp_rel emit_letp :: emit_letp_rel inst_lctp :: inst_lctp_none emit_lctp :: emit_lctp_none +inst_bf :: inst_bf_rel_rel +emit_bf :: emit_bf_rel_rel +inst_bfi_br :: inst_bfi_br_rel_r +emit_bfi_br :: emit_bfi_br_rel_r +inst_bfl :: inst_bfl_rel_rel +emit_bfl :: emit_bfl_rel_rel +inst_bflx :: inst_bflx_rel_r +emit_bflx :: emit_bflx_rel_r inst_cx1 :: inst_cx1_cp_r_imm emit_cx1 :: emit_cx1_cp_r_imm inst_cx1a :: inst_cx1a_cp_r_imm diff --git a/core/rexcode/arm32/reloc.odin b/core/rexcode/arm32/reloc.odin index ce72f0086..09f56eb80 100644 --- a/core/rexcode/arm32/reloc.odin +++ b/core/rexcode/arm32/reloc.odin @@ -41,6 +41,11 @@ Relocation_Type :: enum u8 { BRANCH_T32_WLS, // WLS / WLSTP imm11 BRANCH_T32_LE, // LE / LETP imm11 + // T32 Branch Future (ARMv8.1-M) + BF_BOFF_T32, // bf-point: imm4 at hw0[10:7] = (label - (PC+4))/2 + BF_BLOC_T32, // branch target: J at hw1[11] + imm10 at hw1[10:1] + BFCSEL_ELSE_T32, // BFCSEL else-target relative to the bf-point + // Literal load (ADR / LDR PC-rel) LDR_LITERAL_A32, // signed 12-bit (U bit + imm12) LDR_LITERAL_T32, // signed 12-bit (U bit + imm12) Thumb-2 diff --git a/core/rexcode/arm32/tablegen/encoding_table.odin b/core/rexcode/arm32/tablegen/encoding_table.odin index adb65c1bc..8d38be464 100644 --- a/core/rexcode/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/arm32/tablegen/encoding_table.odin @@ -3103,13 +3103,13 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ }, .WLSTP = { // WLSTP.: bits 22:20 carry size selector (B/H/W/D) - {.WLSTP, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF000C001, 0xFE80F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + {.WLSTP, {.GPR, .REL11, .NONE, .NONE}, {.RN_T32, .MVE_LOOP_IMM, .NONE, .NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, }, .DLS = { {.DLS, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, }, .DLSTP = { - {.DLSTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E001, 0xFE80FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, + {.DLSTP, {.GPR, .NONE, .NONE, .NONE}, {.RN_T32, .NONE, .NONE, .NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, }, .LE = { {.LE, {.REL11, .NONE, .NONE, .NONE}, {.MVE_LOOP_IMM, .NONE, .NONE, .NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, @@ -3121,10 +3121,22 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.LCTP, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true, cond_in_28=false}}, }, - // BF / BFL / BFLX / BFCSEL / BFI_BR (branch future, ARMv8.1-M). - // These encodings are scattered/relative and are intentionally left as - // placeholders pending dedicated LLVM-verified bit-pattern work. The - // mnemonics remain in the enum so callers can refer to them. + // BF / BFL / BFLX / BFI_BR (Branch Future, ARMv8.1-M). T32, word = hw0<<16|hw1. + // bf-point: imm4 = (label-(PC+4))/2 at hw0[10:7]; branch target: val = + // (label-(PC+4))/2 with J at hw1[11] and imm10 at hw1[10:1]; BFLX/BFX target + // is a register Rm at hw0[3:0]. (BFCSEL has an extra else-target + condition.) + .BF = { + {.BF, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + }, + .BFL = { + {.BFL, {.REL_BF, .REL_BF, .NONE, .NONE}, {.BF_BOFF, .BF_BLOC, .NONE, .NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + }, + .BFLX = { + {.BFLX, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + }, + .BFI_BR = { + {.BFI_BR, {.REL_BF, .GPR, .NONE, .NONE}, {.BF_BOFF, .BF_RM, .NONE, .NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {thumb32=true, cond_in_28=false, branch=true}}, + }, // ========================================================================= // Custom Datapath Extension (CDE) -- Cortex-M33+ diff --git a/core/rexcode/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/arm32/tablegen/generated/decode_tables.odin index ee43a144a..6580a33d8 100644 --- a/core/rexcode/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/arm32/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [1675]lib.Decode_Entry{ +DECODE_ENTRIES := [1679]lib.Decode_Entry{ { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {} }, { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {} }, @@ -183,11 +183,11 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000350, 0xFFB11F51, .NEON, .A32, {} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000340, 0xFFB11F51, .NEON, .A32, {} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000550, 0xFFB11F51, .NEON, .A32, {} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {} }, @@ -203,8 +203,8 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000340, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000310, 0xFFB00F50, .NEON, .A32, {} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000300, 0xFFB00F50, .NEON, .A32, {} }, - { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000640, 0xFFB00F50, .NEON, .A32, {} }, + { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F40, 0xFFB00F50, .NEON, .A32, {} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000650, 0xFFB00F50, .NEON, .A32, {} }, { .VRECPS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000F50, 0xFFB00F50, .NEON, .A32, {} }, { .VSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000440, 0xFFB00F50, .NEON, .A32, {} }, @@ -212,11 +212,11 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VQSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2000450, 0xFFB00F50, .NEON, .A32, {} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2000510, 0xFFB00F50, .NEON, .A32, {} }, { .SHA1C, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C40, 0xFFB00F50, .CRYPTO, .A32, {} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D00, 0xFFB00F10, .NEON, .A32, {} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000800, 0xFFB00F10, .NEON, .A32, {} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000910, 0xFFB00F10, .NEON, .A32, {} }, - { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000D10, 0xFFB00F10, .NEON, .A32, {} }, + { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000900, 0xFFB00F10, .NEON, .A32, {} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000C10, 0xFFB00F10, .NEON, .A32, {} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000000, 0xFFB00F10, .NEON, .A32, {} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000200, 0xFFB00F10, .NEON, .A32, {} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {} }, @@ -314,8 +314,8 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {} }, { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {} }, { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {} }, @@ -337,8 +337,8 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {} }, @@ -370,40 +370,40 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E70, 0xFEB80FD0, .NEON, .A32, {} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800E50, 0xFEB80FD0, .NEON, .A32, {} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800850, 0xFEB80FD0, .NEON, .A32, {} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800050, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800F50, 0xFEB80FD0, .NEON, .A32, {} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NONE,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A10, 0xFEB80F90, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800410, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800010, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800F10, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C10, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D10, 0xFEB80F90, .NEON, .A32, {} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E10, 0xFEB80F90, .NEON, .A32, {} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800610, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800E30, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800810, 0xFEB80F90, .NEON, .A32, {} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800210, 0xFEB80F90, .NEON, .A32, {} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NONE,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {} }, @@ -466,8 +466,8 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VMUL_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A008C0, 0xFFB00F50, .NEON, .A32, {} }, { .VMLA_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {} }, { .VMLA_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A000C0, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {} }, { .VMLS_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A004C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS_LANE, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {} }, @@ -503,8 +503,8 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {} }, { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {} }, { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {} }, { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {} }, @@ -530,8 +530,8 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VABD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000700, 0xFFB00F10, .NEON, .A32, {} }, { .VEOR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000110, 0xFFB00F10, .NEON, .A32, {} }, { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000810, 0xFFB00F10, .NEON, .A32, {} }, - { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E00, 0xFFB00F10, .NEON, .A32, {} }, + { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000310, 0xFFB00F10, .NEON, .A32, {} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000300, 0xFFB00F10, .NEON, .A32, {} }, { .VACGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000E10, 0xFFB00F10, .NEON, .A32, {} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000600, 0xFFB00F10, .NEON, .A32, {} }, @@ -692,8 +692,8 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VMUL_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00840, 0xFFB00F50, .NEON, .A32, {} }, { .VMLA_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A000C0, 0xFFB00F50, .NEON, .A32, {} }, { .VMLA_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00040, 0xFFB00F50, .NEON, .A32, {} }, - { .VMLS_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {} }, { .VMLS_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A004C0, 0xFFB00F50, .NEON, .A32, {} }, + { .VMLS_LANE, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {} }, { .VMULL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {} }, { .VMLAL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {} }, { .VMLSL_LANE, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {} }, @@ -704,16 +704,16 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRECPE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {} }, - { .VRSQRTE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRECPE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {} }, { .VRSQRTE_F, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {} }, + { .VRSQRTE_F, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {} }, { .SHA1H, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B902C0, 0xFFBF0FD0, .CRYPTO, .A32, {} }, { .SHA1SU1, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0380, 0xFFBF0FD0, .CRYPTO, .A32, {} }, { .SHA256SU0, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA03C0, 0xFFBF0FD0, .CRYPTO, .A32, {} }, @@ -727,157 +727,157 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFB30FD0, .NEON, .A32, {} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFB30FD0, .NEON, .A32, {} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFB30FD0, .NEON, .A32, {} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFB30FD0, .NEON, .A32, {} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFB30FD0, .NEON, .A32, {} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VMVN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B005C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFB30FD0, .NEON, .A32, {} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFB30FD0, .NEON, .A32, {} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFB30FD0, .NEON, .A32, {} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFB30FD0, .NEON, .A32, {} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFB30FD0, .NEON, .A32, {} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFB30FD0, .NEON, .A32, {} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFB30FD0, .NEON, .A32, {} }, { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFB30FD0, .NEON, .A32, {} }, { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFB30FD0, .NEON, .A32, {} }, + { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {} }, { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFB30FD0, .NEON, .A32, {} }, { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {} }, + { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {} }, { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {} }, { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {} }, { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B20300, 0xFFB30FD0, .NEON, .A32, {} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3BA0300, 0xFFB30FD0, .NEON, .A32, {} }, { .VSHLL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B60300, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00440, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80440, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40400, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00400, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B004C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B404C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLZ, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B804C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40480, 0xFFB30FD0, .NEON, .A32, {} }, { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {} }, { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B000C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40080, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV32, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B400C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV32, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00080, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40040, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B80040, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00000, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {} }, { .VREV64, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80000, 0xFFB30FD0, .NEON, .A32, {} }, + { .VREV64, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00040, 0xFFB30FD0, .NEON, .A32, {} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BA0080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B600C0, 0xFFB30FD0, .NEON, .A32, {} }, - { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {} }, { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA00C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VTRN, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B200C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20080, 0xFFB30FD0, .NEON, .A32, {} }, { .VTRN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60080, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {} }, { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20140, 0xFFB30FD0, .NEON, .A32, {} }, - { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {} }, + { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B60140, 0xFFB30FD0, .NEON, .A32, {} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60100, 0xFFB30FD0, .NEON, .A32, {} }, { .VUZP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA0140, 0xFFB30FD0, .NEON, .A32, {} }, + { .VUZP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20100, 0xFFB30FD0, .NEON, .A32, {} }, { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B601C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B60180, 0xFFB30FD0, .NEON, .A32, {} }, - { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B201C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VZIP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BA01C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VZIP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20180, 0xFFB30FD0, .NEON, .A32, {} }, - { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {} }, { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {} }, + { .VSWP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B20000, 0xFFB30FD0, .NEON, .A32, {} }, { .AESE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00300, 0xFFB30FD0, .CRYPTO, .A32, {} }, { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {} }, { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {} }, { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {} }, - { .VCEQ_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {} }, { .VCEQ_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10140, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCEQ_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCEQ_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10100, 0xFFB30FD0, .NEON, .A32, {} }, { .VCEQ_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90500, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGE_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGE_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCEQ_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90540, 0xFFB30FD0, .NEON, .A32, {} }, { .VCGE_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B100C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGE_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B904C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VCGE_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10080, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGE_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90480, 0xFFB30FD0, .NEON, .A32, {} }, { .VCGT_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90400, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCGT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {} }, { .VCGT_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10000, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLE_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90440, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCGT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10040, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLE_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B101C0, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLE_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B905C0, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLE_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90580, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLE_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10180, 0xFFB30FD0, .NEON, .A32, {} }, - { .VCLT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLT_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10200, 0xFFB30FD0, .NEON, .A32, {} }, + { .VCLT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90640, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLT_Z, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10240, 0xFFB30FD0, .NEON, .A32, {} }, { .VCLT_Z, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90600, 0xFFB30FD0, .NEON, .A32, {} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {} }, + { .VTBL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {} }, { .VTBX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {} }, - { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {} }, { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {} }, + { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true} }, { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03C00000, 0x0FE00000, .BASE, .A32, {} }, { .BIC, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03D00000, 0x0FF00000, .BASE, .A32, {sets_flags=true} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000600, 0xFFF00F00, .NEON, .A32, {} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000200, 0xFFF00F00, .NEON, .A32, {} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000A00, 0xFFF00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000700, 0xFFF00F00, .NEON, .A32, {} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000300, 0xFFF00F00, .NEON, .A32, {} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000900, 0xFFF00F00, .NEON, .A32, {} }, - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000800, 0xFFF00F00, .NEON, .A32, {} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000500, 0xFFF00F00, .NEON, .A32, {} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000400, 0xFFF00F00, .NEON, .A32, {} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000000, 0xFFF00F00, .NEON, .A32, {} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4000100, 0xFFF00F00, .NEON, .A32, {} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200200, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200600, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200700, 0xFFF00F00, .NEON, .A32, {} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200A00, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200300, 0xFFF00F00, .NEON, .A32, {} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200800, 0xFFF00F00, .NEON, .A32, {} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200900, 0xFFF00F00, .NEON, .A32, {} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200500, 0xFFF00F00, .NEON, .A32, {} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200400, 0xFFF00F00, .NEON, .A32, {} }, - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200100, 0xFFF00F00, .NEON, .A32, {} }, - { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4200000, 0xFFF00F00, .NEON, .A32, {} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00F00, .NEON, .A32, {} }, + { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00F00, .NEON, .A32, {} }, { .VST1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00F00, .NEON, .A32, {} }, + { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {} }, { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800500, 0xFFB00D00, .NEON, .A32, {} }, { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800900, 0xFFB00D00, .NEON, .A32, {} }, - { .VST2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800100, 0xFFB00D00, .NEON, .A32, {} }, { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800A00, 0xFFB00D00, .NEON, .A32, {} }, { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800200, 0xFFB00D00, .NEON, .A32, {} }, { .VST3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800600, 0xFFB00D00, .NEON, .A32, {} }, { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800300, 0xFFB00D00, .NEON, .A32, {} }, - { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {} }, { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800B00, 0xFFB00D00, .NEON, .A32, {} }, + { .VST4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800700, 0xFFB00D00, .NEON, .A32, {} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800800, 0xFFB00C00, .NEON, .A32, {} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800400, 0xFFB00C00, .NEON, .A32, {} }, { .VST1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4800000, 0xFFB00C00, .NEON, .A32, {} }, @@ -887,17 +887,17 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VLD3R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00E0F, 0xFFB00F0F, .NEON, .A32, {} }, { .VLD4R, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00F0F, 0xFFB00F0F, .NEON, .A32, {} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00000, 0xFFB00F00, .NEON, .A32, {} }, - { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VFP_D_LIST,.RN_A32,.NONE,.NONE}, 0xF4A00C00, 0xFFB00F00, .NEON, .A32, {} }, + { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00F00, .NEON, .A32, {} }, { .VLD1, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00F00, .NEON, .A32, {} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {} }, { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00100, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00900, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD2_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00500, 0xFFB00D00, .NEON, .A32, {} }, { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00A00, 0xFFB00D00, .NEON, .A32, {} }, { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00200, 0xFFB00D00, .NEON, .A32, {} }, { .VLD3_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00600, 0xFFB00D00, .NEON, .A32, {} }, - { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {} }, { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00B00, 0xFFB00D00, .NEON, .A32, {} }, + { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00300, 0xFFB00D00, .NEON, .A32, {} }, { .VLD4_LANE, {.DPR_LIST,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00700, 0xFFB00D00, .NEON, .A32, {} }, { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00400, 0xFFB00C00, .NEON, .A32, {} }, { .VLD1_LANE, {.DPR_ELEM,.MEM,.NONE,.NONE}, {.VD_D,.RN_A32,.NONE,.NONE}, 0xF4A00800, 0xFFB00C00, .NEON, .A32, {} }, @@ -1196,14 +1196,14 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {} }, { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVT_FIXED, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, - { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, + { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBB0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, { .VCVT_FIXED, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBE0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBF0A40, 0x0FBF0FD0, .VFPV3, .A32, {} }, + { .VCVT_FIXED, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBA0940, 0x0FBF0FD0, .HALF_FP, .A32, {} }, { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0F50, .VFPV2, .A32, {} }, { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0F50, .VFPV2, .A32, {} }, { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0F50, .HALF_FP, .A32, {} }, @@ -1273,10 +1273,10 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VMOV_2GPR_Q, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true} }, { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true} }, { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true} }, - { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VADDLV, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true} }, @@ -1386,10 +1386,14 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .LCTP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, { .DLS, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true} }, { .VCTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E801, 0xFFC0FFFF, .MVE_INT, .T32, {thumb32=true} }, - { .DLSTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E001, 0xFE80FFFF, .V81M, .T32, {thumb32=true} }, + { .DLSTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true} }, + { .BFI_BR, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, + { .BFLX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, { .LE, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} }, { .LETP, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} }, { .WLS, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {branch=true, thumb32=true} }, + { .BF, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} }, + { .BFL, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} }, { .TST, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0100F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true} }, { .TEQ, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF0900F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true} }, { .CMP, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RN_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF1B00F00, 0xFBF08F00, .V6T2, .T32, {thumb32=true} }, @@ -1397,7 +1401,7 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF04F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true} }, { .MOV, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF05F0000, 0xFBEF8000, .V6T2, .T32, {sets_flags=true, thumb32=true} }, { .MVN, {.GPR,.IMM_T32_MOD,.NONE,.NONE}, {.RD_T32,.T32_IMM_MOD,.NONE,.NONE}, 0xF06F0000, 0xFBEF8000, .V6T2, .T32, {thumb32=true} }, - { .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFE80F001, .V81M, .T32, {branch=true, thumb32=true} }, + { .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {branch=true, thumb32=true} }, { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0000000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, { .AND, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0100000, 0xFBE08000, .V6T2, .T32, {sets_flags=true, thumb32=true} }, { .EOR, {.GPR,.GPR,.IMM_T32_MOD,.NONE}, {.RD_T32,.RN_T32,.T32_IMM_MOD,.NONE}, 0xF0800000, 0xFBE08000, .V6T2, .T32, {thumb32=true} }, @@ -1553,10 +1557,10 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ { .VLDRB_GATHER, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true} }, { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true} }, - { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VCX3A, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xFC800000, 0xFF300000, .CDE, .T32, {thumb32=true} }, + { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true} }, { .VPST, {.MVE_VPT_MASK,.NONE,.NONE,.NONE}, {.MVE_VPT_MASK_FIELD,.NONE,.NONE,.NONE}, 0xFE710F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true} }, { .VPNOT, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xFE310F4D, 0xFFFFFFFF, .MVE_INT, .T32, {thumb32=true} }, { .VRINTA, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xFFBA0540, 0xFFBB0FD1, .MVE_FP, .T32, {thumb32=true} }, @@ -1687,7 +1691,7 @@ DECODE_ENTRIES := [1675]lib.Decode_Entry{ } @(rodata) -DECODE_FORM_IDX := [1675]u16{ +DECODE_FORM_IDX := [1679]u16{ 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 5, 4, 0, 2, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 2, 2, 2, 1, 1, 2, 2, 2, 5, 4, 0, 0, @@ -1698,29 +1702,29 @@ DECODE_FORM_IDX := [1675]u16{ 2, 1, 0, 0, 0, 3, 3, 3, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 0, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, - 1, 1, 1, 0, 0, 0, 5, 4, 1, 1, 1, 1, 1, 1, 14, 9, - 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, - 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 5, 13, 5, 3, 9, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, + 1, 1, 1, 0, 0, 0, 5, 4, 1, 1, 1, 1, 1, 1, 9, 14, + 8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, + 0, 0, 3, 9, 3, 1, 4, 1, 1, 0, 0, 13, 5, 5, 9, 3, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4, 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, 2, 0, 6, 3, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, 1, 1, 1, 10, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, - 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, - 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, + 5, 9, 5, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, + 1, 2, 2, 0, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 0, 0, 0, 22, 25, 23, 21, 24, 0, 0, - 0, 0, 10, 11, 10, 17, 20, 14, 16, 19, 15, 12, 11, 13, 18, 0, - 6, 0, 0, 9, 4, 8, 2, 5, 7, 3, 6, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 0, 0, 0, 24, 25, 23, 22, 21, 0, 0, + 0, 0, 11, 10, 15, 12, 10, 19, 16, 17, 18, 13, 20, 14, 11, 6, + 0, 0, 0, 3, 4, 6, 2, 9, 8, 7, 5, 0, 0, 0, 0, 0, 1, 1, 1, 1, 5, 0, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, - 1, 1, 1, 2, 2, 1, 4, 1, 4, 1, 4, 1, 1, 1, 1, 1, + 1, 1, 1, 2, 2, 1, 4, 1, 4, 4, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 0, 1, 0, 3, 0, 3, 0, 3, 7, 13, 7, - 1, 9, 9, 14, 12, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, + 1, 9, 9, 14, 12, 6, 7, 7, 9, 9, 7, 7, 1, 3, 9, 7, 7, 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 13, 11, - 3, 6, 6, 8, 8, 6, 6, 0, 0, 6, 8, 6, 0, 6, 6, 4, + 3, 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 4, 3, 3, 3, 6, 2, 2, 0, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, @@ -1730,20 +1734,20 @@ DECODE_FORM_IDX := [1675]u16{ 3, 3, 3, 3, 3, 3, 0, 0, 1, 1, 1, 3, 3, 3, 1, 1, 2, 2, 2, 0, 0, 0, 4, 4, 1, 1, 4, 4, 4, 4, 4, 4, 4, 4, 2, 2, 2, 2, 2, 2, 2, 2, 3, 5, 5, 3, 3, 5, - 5, 5, 5, 5, 5, 5, 5, 5, 3, 5, 3, 3, 5, 3, 3, 3, - 1, 1, 3, 3, 0, 2, 3, 1, 0, 2, 0, 3, 1, 1, 0, 1, - 0, 0, 0, 0, 0, 6, 5, 3, 4, 9, 8, 7, 2, 4, 9, 2, - 8, 6, 5, 7, 3, 1, 0, 0, 1, 2, 2, 3, 5, 0, 4, 1, - 2, 0, 1, 2, 0, 5, 1, 4, 3, 2, 3, 1, 0, 2, 4, 3, - 0, 4, 3, 5, 2, 1, 3, 2, 0, 1, 4, 5, 1, 0, 1, 0, - 2, 3, 1, 0, 4, 5, 0, 1, 3, 2, 2, 3, 4, 0, 5, 1, - 1, 3, 2, 0, 4, 3, 1, 4, 2, 0, 0, 1, 0, 0, 0, 0, - 0, 1, 3, 2, 2, 3, 1, 0, 2, 1, 3, 0, 3, 1, 2, 0, - 3, 0, 1, 2, 1, 2, 0, 3, 0, 1, 2, 3, 3, 2, 3, 0, - 3, 0, 3, 2, 3, 1, 0, 2, 0, 1, 0, 1, 0, 1, 3, 0, - 2, 1, 1, 2, 0, 1, 0, 0, 1, 6, 4, 5, 1, 2, 0, 2, - 0, 1, 0, 1, 2, 2, 1, 0, 2, 2, 0, 0, 0, 5, 7, 4, - 6, 1, 2, 0, 2, 0, 1, 0, 2, 1, 1, 2, 0, 0, 0, 2, + 5, 5, 5, 5, 5, 5, 5, 5, 3, 5, 3, 5, 3, 3, 3, 3, + 1, 1, 3, 3, 0, 2, 3, 0, 1, 2, 3, 1, 0, 0, 1, 0, + 1, 0, 0, 0, 0, 6, 5, 3, 4, 9, 8, 7, 2, 4, 3, 9, + 2, 8, 5, 7, 6, 1, 0, 0, 2, 1, 3, 4, 2, 0, 1, 5, + 2, 0, 1, 2, 0, 3, 5, 1, 4, 1, 2, 3, 0, 2, 4, 3, + 1, 3, 5, 4, 2, 0, 0, 5, 3, 2, 4, 1, 1, 0, 1, 0, + 2, 1, 3, 0, 4, 5, 0, 1, 2, 3, 2, 4, 5, 3, 0, 1, + 2, 3, 1, 4, 0, 3, 1, 2, 4, 0, 1, 0, 0, 0, 0, 0, + 1, 0, 2, 3, 1, 3, 0, 2, 2, 0, 3, 1, 1, 3, 2, 0, + 0, 3, 1, 2, 1, 3, 0, 2, 0, 1, 3, 2, 2, 3, 3, 0, + 3, 0, 3, 2, 0, 3, 1, 2, 1, 0, 1, 0, 0, 1, 3, 2, + 0, 1, 2, 0, 1, 1, 0, 1, 0, 4, 6, 5, 0, 1, 2, 2, + 0, 1, 0, 2, 1, 2, 1, 0, 2, 2, 0, 0, 0, 5, 4, 7, + 6, 0, 2, 1, 2, 0, 1, 2, 0, 1, 1, 2, 0, 0, 0, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, @@ -1762,41 +1766,41 @@ DECODE_FORM_IDX := [1675]u16{ 3, 1, 0, 1, 0, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 2, 1, 0, 9, 7, 6, 8, 3, 2, 4, 0, 1, 5, 0, 1, 1, 0, 3, 1, 0, 2, 1, 0, 0, 1, 1, 0, - 1, 0, 0, 3, 0, 1, 2, 7, 8, 9, 6, 0, 1, 4, 0, 1, + 1, 0, 0, 7, 8, 2, 3, 6, 0, 1, 9, 0, 1, 4, 0, 1, 4, 5, 2, 3, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 6, 7, 6, 7, 4, 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8, 8, 8, 8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 1, 0, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 0, 0, 0, 0, 7, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, 10, 10, 12, 12, 8, 4, 6, 0, 0, 4, 4, 4, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 4, 3, 6, 4, 8, 9, 7, 0, 7, 8, 7, - 6, 7, 7, 7, 7, 4, 3, 1, 2, 2, 2, 2, 2, 1, 1, 1, - 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 2, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, 9, 8, 7, 7, 7, 7, - 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, 6, 6, 5, 5, 2, 1, - 2, 2, 1, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 4, 8, 9, 7, + 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, 3, 1, 2, 2, 2, 2, + 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 2, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, 9, 8, + 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, 6, 6, + 5, 5, 2, 1, 2, 2, 1, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 3, 1, 1, 0, 5, 5, 5, 4, 1, 1, 1, 1, 1, 1, 2, - 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 2, 2, - 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, 0, 0, 0, 10, 10, 12, - 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 6, 6, - 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, 3, 4, 3, 6, 6, 6, - 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, 9, 5, 7, 4, 4, 4, - 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, 5, 5, 6, 7, 0, 10, - 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, - 1, 1, 1, 0, 1, 5, 5, 1, 1, 1, 2, + 1, 1, 1, 1, 1, 3, 1, 1, 0, 5, 5, 5, 4, 1, 1, 1, + 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 1, + 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, 0, 0, + 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, 0, 15, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, + 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, 3, 4, + 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, 9, 5, + 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, 5, 5, + 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, 1, 1, + 0, 1, 1, 1, 1, 1, 1, 0, 1, 5, 5, 1, 1, 1, 2, } @(rodata) -DECODE_BUCKET_LIST := [5421]u16{ +DECODE_BUCKET_LIST := [5485]u16{ 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, 11, 8, 12, 35, 36, 37, 13, 14, 41, 42, 43, 15, 13, 16, 14, 17, 47, 18, 19, 51, 52, 53, 20, 21, 18, 19, 22, 23, 24, 25, 22, 26, @@ -1989,40 +1993,41 @@ DECODE_BUCKET_LIST := [5421]u16{ 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1346, 1347, 1348, 1349, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1367, 1368, 1369, 1370, 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, - 1381, 1382, 1383, 1384, 1386, 1385, 1387, 1388, 1390, 1389, 1391, 1392, 1393, 1394, 1395, 1396, - 1398, 1397, 1399, 1400, 1401, 1402, 1403, 1404, 1405, 1406, 1407, 1408, 1409, 1410, 1411, 1412, - 1413, 1414, 1415, 1416, 1417, 1418, 1419, 1420, 1421, 1422, 1423, 1424, 1425, 1426, 1427, 1428, - 1429, 1398, 1397, 1399, 1381, 1382, 1383, 1384, 1386, 1385, 1387, 1389, 1390, 1391, 1392, 1393, - 1394, 1395, 1396, 1397, 1398, 1399, 1430, 1431, 1432, 1433, 1428, 1429, 1398, 1397, 1399, 1434, - 1435, 1436, 1437, 1438, 1439, 1440, 1441, 1442, 1443, 1444, 1445, 1446, 1447, 1448, 1449, 1450, - 1451, 1452, 1453, 1454, 1455, 1456, 1457, 1458, 1459, 1460, 1461, 1462, 1463, 1464, 1465, 1466, - 1467, 1468, 1469, 1470, 1471, 1472, 1473, 1474, 1475, 1476, 1477, 1478, 1479, 1480, 1481, 1482, - 1483, 1484, 1485, 1486, 1487, 1488, 1489, 1490, 1491, 1492, 1493, 1494, 1495, 1496, 1497, 1498, - 1499, 1500, 1501, 1502, 1503, 1504, 1505, 1506, 1507, 1508, 1509, 1510, 1511, 1512, 1513, 1514, - 1515, 1516, 1517, 1518, 1519, 1520, 1521, 1522, 1523, 1524, 1525, 1526, 1527, 1528, 1529, 1530, - 1531, 1532, 1533, 1534, 1535, 1536, 1537, 1538, 1539, 1540, 1541, 1543, 1542, 1544, 1545, 1547, - 1546, 1548, 1549, 1270, 1271, 1272, 1273, 1274, 1275, 1550, 1551, 1552, 1553, 1554, 1555, 1556, - 1557, 1558, 1559, 1560, 1561, 1562, 1563, 1564, 1282, 1283, 1284, 1285, 1286, 1287, 1565, 1566, - 1567, 1292, 1293, 1294, 1568, 1299, 1300, 1301, 1302, 1303, 1304, 1308, 1309, 1569, 1310, 1311, - 1570, 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1571, 1572, 1573, 1574, - 1575, 1576, 1577, 1578, 1323, 1579, 1324, 1325, 1326, 1327, 1580, 1328, 1329, 1330, 1331, 1332, + 1381, 1382, 1383, 1384, 1385, 1386, 1387, 1388, 1389, 1390, 1391, 1392, 1394, 1393, 1395, 1396, + 1397, 1398, 1399, 1400, 1402, 1401, 1403, 1404, 1405, 1406, 1407, 1408, 1409, 1410, 1411, 1412, + 1413, 1414, 1415, 1416, 1417, 1418, 1419, 1420, 1421, 1422, 1423, 1378, 1379, 1424, 1425, 1426, + 1383, 1384, 1427, 1428, 1429, 1430, 1431, 1432, 1433, 1402, 1401, 1403, 1378, 1379, 1383, 1384, + 1385, 1386, 1387, 1388, 1389, 1390, 1391, 1393, 1394, 1395, 1396, 1397, 1398, 1399, 1400, 1402, + 1401, 1403, 1434, 1435, 1436, 1378, 1379, 1383, 1384, 1437, 1432, 1433, 1402, 1401, 1403, 1438, + 1439, 1440, 1441, 1442, 1443, 1444, 1445, 1446, 1447, 1448, 1449, 1450, 1451, 1452, 1453, 1454, + 1455, 1456, 1457, 1458, 1459, 1460, 1461, 1462, 1463, 1464, 1465, 1466, 1467, 1468, 1469, 1470, + 1471, 1472, 1473, 1474, 1475, 1476, 1477, 1478, 1479, 1480, 1481, 1482, 1483, 1484, 1485, 1486, + 1487, 1488, 1489, 1490, 1491, 1492, 1493, 1494, 1495, 1496, 1497, 1498, 1499, 1500, 1501, 1502, + 1503, 1504, 1505, 1506, 1507, 1508, 1509, 1510, 1511, 1512, 1513, 1514, 1515, 1516, 1517, 1518, + 1519, 1520, 1521, 1522, 1523, 1524, 1525, 1526, 1527, 1528, 1529, 1530, 1531, 1532, 1533, 1534, + 1535, 1536, 1537, 1538, 1539, 1540, 1541, 1542, 1543, 1544, 1545, 1546, 1547, 1548, 1549, 1551, + 1550, 1552, 1553, 1270, 1271, 1272, 1273, 1274, 1275, 1554, 1555, 1556, 1557, 1558, 1559, 1560, + 1561, 1562, 1563, 1564, 1565, 1566, 1567, 1568, 1282, 1283, 1284, 1285, 1286, 1287, 1569, 1570, + 1571, 1292, 1293, 1294, 1572, 1299, 1300, 1301, 1302, 1303, 1304, 1308, 1309, 1573, 1310, 1311, + 1574, 1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1575, 1576, 1577, 1578, + 1579, 1580, 1581, 1582, 1323, 1583, 1324, 1325, 1326, 1327, 1584, 1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1346, 1347, 1348, - 1349, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1581, 1582, 1583, - 1584, 1585, 1586, 1587, 1588, 1364, 1365, 1366, 1367, 1589, 1590, 1591, 1592, 1593, 1594, 1595, - 1595, 1596, 1596, 1597, 1597, 1598, 1599, 1600, 1601, 1602, 1602, 1603, 1603, 1604, 1604, 1605, - 1605, 1606, 1607, 1608, 1609, 1610, 1611, 1612, 1613, 1614, 1615, 1616, 1617, 1618, 1619, 1620, - 1621, 1622, 1623, 1624, 1625, 1626, 1627, 1628, 1629, 1629, 1630, 1631, 1632, 1633, 1634, 1635, - 1636, 1637, 1638, 1638, 1639, 1639, 1640, 1640, 1641, 1641, 1642, 1642, 1643, 1643, 1644, 1644, - 1645, 1645, 1646, 1646, 1647, 1647, 1648, 1649, 1650, 1651, 1652, 1653, 1654, 1655, 1656, 1657, - 1658, 1659, 1660, 1661, 1662, 1663, 1664, 1665, 1666, 1667, 1668, 1669, 1669, 1670, 1670, 1671, - 1671, 1671, 1672, 1673, 1671, 1674, 1674, 1217, 1218, 1219, 1220, 1225, 1231, 1221, 1230, 1231, + 1349, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1585, 1586, 1587, + 1588, 1589, 1590, 1591, 1592, 1364, 1365, 1366, 1367, 1593, 1594, 1595, 1596, 1597, 1598, 1599, + 1599, 1600, 1600, 1601, 1601, 1602, 1603, 1604, 1605, 1606, 1606, 1607, 1607, 1608, 1608, 1609, + 1609, 1610, 1611, 1612, 1613, 1614, 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1335, 1336, 1337, 1346, 1347, 1348, 1349, 1593, 1597, 1270, 1271, 1301, 1302, 1303, + 1304, 1314, 1315, 1316, 1317, 1575, 1576, 1577, 1578, 1584, 1330, 1331, 1338, 1339, 1340, 1341, + 1342, 1343, 1344, 1345, 1589, 1590, 1591, 1592, 1367, 1595, 1598, 1575, 1576, 1577, 1578, 1584, + 1330, 1331, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1595, 1598, 1575, 1576, 1577, 1578, + 1584, 1330, 1331, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1595, 1598, 1560, 1561, 1299, + 1300, 1312, 1313, 1318, 1319, 1575, 1576, 1577, 1578, 1584, 1330, 1331, 1338, 1339, 1340, 1341, + 1342, 1343, 1344, 1345, 1585, 1586, 1587, 1588, 1595, 1598, 1301, 1302, 1303, 1304, 1314, 1315, + 1316, 1317, 1575, 1576, 1577, 1578, 1584, 1330, 1331, 1338, 1339, 1340, 1341, 1342, 1343, 1344, + 1345, 1589, 1590, 1591, 1592, 1367, 1594, 1596, 1598, 1575, 1576, 1577, 1578, 1584, 1330, 1331, + 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1594, 1596, 1598, 1272, 1273, 1274, 1275, 1284, + 1285, 1286, 1287, 1575, 1576, 1577, 1578, 1584, 1330, 1331, 1338, 1339, 1340, 1341, 1342, 1343, + 1344, 1345, 1594, 1596, 1598, 1560, 1561, 1282, 1283, 1299, 1300, 1312, 1313, 1318, 1319, 1575, + 1576, 1577, 1578, 1584, 1330, 1331, 1338, 1339, 1340, 1341, 1342, 1343, 1344, 1345, 1585, 1586, + 1587, 1588, 1594, 1596, 1598, 1572, 1573, 1574, 1323, 1583, 1326, 1584, 1350, 1351, 1352, 1353, + 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1573, 1574, 1323, 1583, 1326, 1584, 1350, 1351, + 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1574, 1324, 1583, 1327, 1584, 1350, + 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1574, 1583, 1324, 1327, 1584, + 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1572, 1573, 1574, 1323, + 1583, 1326, 1584, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, 1361, 1573, + 1574, 1323, 1583, 1326, 1584, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, 1360, + 1361, 1574, 1583, 1324, 1327, 1584, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, 1359, + 1360, 1361, 1574, 1583, 1324, 1327, 1584, 1350, 1351, 1352, 1353, 1354, 1355, 1356, 1357, 1358, + 1359, 1360, 1361, 1584, 1364, 1365, 1366, 1584, 1364, 1365, 1366, 1584, 1364, 1365, 1366, 1554, + 1555, 1556, 1557, 1558, 1559, 1564, 1565, 1566, 1567, 1569, 1570, 1571, 1584, 1364, 1365, 1366, + 1584, 1364, 1365, 1366, 1584, 1364, 1365, 1366, 1584, 1364, 1365, 1366, 1554, 1555, 1556, 1557, + 1558, 1559, 1564, 1565, 1566, 1567, 1569, 1570, 1571, 1584, 1364, 1365, 1366, } DECODE_INDEX_A32 := [256]lib.Decode_Index{ @@ -2395,392 +2403,392 @@ DECODE_INDEX_T32 := [128]lib.Decode_Index{ 0x75 = { 2923, 19}, 0x76 = { 2942, 19}, 0x77 = { 2961, 104}, - 0x78 = { 3065, 26}, - 0x79 = { 3091, 33}, - 0x7A = { 3124, 18}, - 0x7B = { 3142, 9}, - 0x7C = { 3151, 20}, - 0x7D = { 3171, 71}, - 0x7E = { 3242, 23}, - 0x7F = { 3265, 126}, + 0x78 = { 3065, 30}, + 0x79 = { 3095, 37}, + 0x7A = { 3132, 22}, + 0x7B = { 3154, 13}, + 0x7C = { 3167, 20}, + 0x7D = { 3187, 71}, + 0x7E = { 3258, 23}, + 0x7F = { 3281, 126}, } DECODE_INDEX_T16 := [64]lib.Decode_Index{ - 0x00 = { 3391, 1}, - 0x01 = { 3392, 1}, - 0x02 = { 3393, 1}, - 0x03 = { 3394, 1}, - 0x04 = { 3395, 1}, - 0x05 = { 3396, 1}, - 0x06 = { 3397, 2}, - 0x07 = { 3399, 2}, - 0x08 = { 3401, 1}, - 0x09 = { 3402, 1}, - 0x0A = { 3403, 1}, - 0x0B = { 3404, 1}, - 0x0C = { 3405, 1}, - 0x0D = { 3406, 1}, - 0x0E = { 3407, 1}, - 0x0F = { 3408, 1}, - 0x10 = { 3409, 16}, - 0x11 = { 3425, 7}, - 0x12 = { 3432, 1}, - 0x13 = { 3433, 1}, - 0x14 = { 3434, 2}, - 0x15 = { 3436, 2}, - 0x16 = { 3438, 2}, - 0x17 = { 3440, 2}, - 0x18 = { 3442, 1}, - 0x19 = { 3443, 1}, - 0x1A = { 3444, 1}, - 0x1B = { 3445, 1}, - 0x1C = { 3446, 1}, - 0x1D = { 3447, 1}, - 0x1E = { 3448, 1}, - 0x1F = { 3449, 1}, - 0x20 = { 3450, 1}, - 0x21 = { 3451, 1}, - 0x22 = { 3452, 1}, - 0x23 = { 3453, 1}, - 0x24 = { 3454, 1}, - 0x25 = { 3455, 1}, - 0x26 = { 3456, 1}, - 0x27 = { 3457, 1}, - 0x28 = { 3458, 1}, - 0x29 = { 3459, 1}, - 0x2A = { 3460, 1}, - 0x2B = { 3461, 1}, - 0x2C = { 3462, 7}, - 0x2D = { 3469, 2}, - 0x2E = { 3471, 4}, - 0x2F = { 3475, 8}, - 0x30 = { 3483, 1}, - 0x31 = { 3484, 1}, - 0x32 = { 3485, 1}, - 0x33 = { 3486, 1}, - 0x34 = { 3487, 1}, - 0x35 = { 3488, 1}, - 0x36 = { 3489, 1}, - 0x37 = { 3490, 3}, - 0x38 = { 3493, 1}, - 0x39 = { 3494, 1}, + 0x00 = { 3407, 1}, + 0x01 = { 3408, 1}, + 0x02 = { 3409, 1}, + 0x03 = { 3410, 1}, + 0x04 = { 3411, 1}, + 0x05 = { 3412, 1}, + 0x06 = { 3413, 2}, + 0x07 = { 3415, 2}, + 0x08 = { 3417, 1}, + 0x09 = { 3418, 1}, + 0x0A = { 3419, 1}, + 0x0B = { 3420, 1}, + 0x0C = { 3421, 1}, + 0x0D = { 3422, 1}, + 0x0E = { 3423, 1}, + 0x0F = { 3424, 1}, + 0x10 = { 3425, 16}, + 0x11 = { 3441, 7}, + 0x12 = { 3448, 1}, + 0x13 = { 3449, 1}, + 0x14 = { 3450, 2}, + 0x15 = { 3452, 2}, + 0x16 = { 3454, 2}, + 0x17 = { 3456, 2}, + 0x18 = { 3458, 1}, + 0x19 = { 3459, 1}, + 0x1A = { 3460, 1}, + 0x1B = { 3461, 1}, + 0x1C = { 3462, 1}, + 0x1D = { 3463, 1}, + 0x1E = { 3464, 1}, + 0x1F = { 3465, 1}, + 0x20 = { 3466, 1}, + 0x21 = { 3467, 1}, + 0x22 = { 3468, 1}, + 0x23 = { 3469, 1}, + 0x24 = { 3470, 1}, + 0x25 = { 3471, 1}, + 0x26 = { 3472, 1}, + 0x27 = { 3473, 1}, + 0x28 = { 3474, 1}, + 0x29 = { 3475, 1}, + 0x2A = { 3476, 1}, + 0x2B = { 3477, 1}, + 0x2C = { 3478, 7}, + 0x2D = { 3485, 2}, + 0x2E = { 3487, 4}, + 0x2F = { 3491, 8}, + 0x30 = { 3499, 1}, + 0x31 = { 3500, 1}, + 0x32 = { 3501, 1}, + 0x33 = { 3502, 1}, + 0x34 = { 3503, 1}, + 0x35 = { 3504, 1}, + 0x36 = { 3505, 1}, + 0x37 = { 3506, 3}, + 0x38 = { 3509, 1}, + 0x39 = { 3510, 1}, } DECODE_INDEX_T32_SUB := [4096]lib.Decode_Index{ - 0xE84 = { 3495, 6}, - 0xE85 = { 3501, 2}, - 0xE86 = { 3503, 1}, - 0xE87 = { 3504, 1}, - 0xE88 = { 3505, 1}, - 0xE89 = { 3506, 1}, - 0xE8A = { 3507, 1}, - 0xE8B = { 3508, 2}, - 0xE8C = { 3510, 4}, - 0xE8D = { 3514, 6}, - 0xE8E = { 3520, 1}, - 0xE8F = { 3521, 1}, - 0xE90 = { 3522, 1}, - 0xE91 = { 3523, 1}, - 0xE92 = { 3524, 2}, - 0xE93 = { 3526, 1}, - 0xE94 = { 3527, 1}, - 0xE95 = { 3528, 1}, - 0xE96 = { 3529, 1}, - 0xE97 = { 3530, 2}, - 0xE9C = { 3532, 1}, - 0xE9D = { 3533, 1}, - 0xE9E = { 3534, 1}, - 0xE9F = { 3535, 1}, - 0xEA0 = { 3536, 2}, - 0xEA1 = { 3538, 3}, - 0xEA2 = { 3541, 1}, - 0xEA3 = { 3542, 1}, - 0xEA4 = { 3543, 7}, - 0xEA5 = { 3550, 7}, - 0xEA6 = { 3557, 1}, - 0xEA7 = { 3558, 1}, - 0xEA8 = { 3559, 1}, - 0xEA9 = { 3560, 2}, - 0xEB1 = { 3562, 1}, - 0xEB4 = { 3563, 1}, - 0xEB5 = { 3564, 1}, - 0xEB6 = { 3565, 1}, - 0xEB7 = { 3566, 1}, - 0xEBB = { 3567, 1}, - 0xEBC = { 3568, 1}, - 0xEBD = { 3569, 1}, - 0xEC0 = { 3570, 2}, - 0xEC1 = { 3572, 1}, - 0xEC2 = { 3573, 3}, - 0xEC3 = { 3576, 2}, - 0xEC4 = { 3578, 2}, - 0xEC5 = { 3580, 1}, - 0xEC6 = { 3581, 7}, - 0xEC7 = { 3588, 2}, - 0xEC8 = { 3590, 1}, - 0xEC9 = { 3591, 1}, - 0xECA = { 3592, 2}, - 0xECB = { 3594, 2}, - 0xECC = { 3596, 1}, - 0xECD = { 3597, 1}, - 0xECE = { 3598, 2}, - 0xECF = { 3600, 2}, - 0xED6 = { 3602, 4}, - 0xED8 = { 3606, 4}, - 0xED9 = { 3610, 4}, - 0xEDC = { 3614, 4}, - 0xEDD = { 3618, 4}, - 0xEE0 = { 3622, 24}, - 0xEE1 = { 3646, 23}, - 0xEE2 = { 3669, 22}, - 0xEE3 = { 3691, 29}, - 0xEE4 = { 3720, 23}, - 0xEE5 = { 3743, 22}, - 0xEE6 = { 3765, 22}, - 0xEE7 = { 3787, 29}, - 0xEE8 = { 3816, 28}, - 0xEE9 = { 3844, 12}, - 0xEEA = { 3856, 13}, - 0xEEB = { 3869, 18}, - 0xEEC = { 3887, 27}, - 0xEED = { 3914, 13}, - 0xEEE = { 3927, 22}, - 0xEEF = { 3949, 23}, - 0xEF0 = { 3972, 15}, - 0xEF1 = { 3987, 15}, - 0xEF2 = { 4002, 15}, - 0xEF3 = { 4017, 15}, - 0xEF4 = { 4032, 15}, - 0xEF5 = { 4047, 15}, - 0xEF6 = { 4062, 15}, - 0xEF7 = { 4077, 15}, - 0xEF8 = { 4092, 3}, - 0xEF9 = { 4095, 3}, - 0xEFA = { 4098, 3}, - 0xEFB = { 4101, 3}, - 0xEFC = { 4104, 3}, - 0xEFD = { 4107, 3}, - 0xEFE = { 4110, 3}, - 0xEFF = { 4113, 3}, - 0xF00 = { 4116, 10}, - 0xF01 = { 4126, 10}, - 0xF02 = { 4136, 7}, - 0xF03 = { 4143, 7}, - 0xF04 = { 4150, 10}, - 0xF05 = { 4160, 8}, - 0xF06 = { 4168, 6}, - 0xF07 = { 4174, 6}, - 0xF08 = { 4180, 4}, - 0xF09 = { 4184, 5}, - 0xF0A = { 4189, 3}, - 0xF0B = { 4192, 3}, - 0xF0C = { 4195, 3}, - 0xF0D = { 4198, 3}, - 0xF0E = { 4201, 3}, - 0xF0F = { 4204, 3}, - 0xF10 = { 4207, 5}, - 0xF11 = { 4212, 6}, - 0xF12 = { 4218, 5}, - 0xF13 = { 4223, 5}, - 0xF14 = { 4228, 6}, - 0xF15 = { 4234, 6}, - 0xF16 = { 4240, 6}, - 0xF17 = { 4246, 6}, - 0xF18 = { 4252, 3}, - 0xF19 = { 4255, 3}, - 0xF1A = { 4258, 3}, - 0xF1B = { 4261, 4}, - 0xF1C = { 4265, 4}, - 0xF1D = { 4269, 4}, - 0xF1E = { 4273, 3}, - 0xF1F = { 4276, 3}, - 0xF20 = { 4279, 3}, - 0xF21 = { 4282, 3}, - 0xF22 = { 4285, 3}, - 0xF23 = { 4288, 3}, - 0xF24 = { 4291, 4}, - 0xF25 = { 4295, 3}, - 0xF26 = { 4298, 3}, - 0xF27 = { 4301, 3}, - 0xF28 = { 4304, 3}, - 0xF29 = { 4307, 3}, - 0xF2A = { 4310, 3}, - 0xF2B = { 4313, 3}, - 0xF2C = { 4316, 4}, - 0xF2D = { 4320, 3}, - 0xF2E = { 4323, 3}, - 0xF2F = { 4326, 3}, - 0xF30 = { 4329, 4}, - 0xF31 = { 4333, 3}, - 0xF32 = { 4336, 5}, - 0xF33 = { 4341, 3}, - 0xF34 = { 4344, 4}, - 0xF35 = { 4348, 3}, - 0xF36 = { 4351, 5}, - 0xF37 = { 4356, 3}, - 0xF38 = { 4359, 5}, - 0xF39 = { 4364, 3}, - 0xF3A = { 4367, 18}, - 0xF3B = { 4385, 8}, - 0xF3C = { 4393, 4}, - 0xF3D = { 4397, 3}, - 0xF3E = { 4400, 4}, - 0xF3F = { 4404, 3}, - 0xF40 = { 4407, 5}, - 0xF41 = { 4412, 6}, - 0xF42 = { 4418, 4}, - 0xF43 = { 4422, 4}, - 0xF44 = { 4426, 6}, - 0xF45 = { 4432, 6}, - 0xF46 = { 4438, 4}, - 0xF47 = { 4442, 4}, - 0xF48 = { 4446, 4}, - 0xF49 = { 4450, 5}, - 0xF4A = { 4455, 3}, - 0xF4B = { 4458, 3}, - 0xF4C = { 4461, 3}, - 0xF4D = { 4464, 3}, - 0xF4E = { 4467, 3}, - 0xF4F = { 4470, 3}, - 0xF50 = { 4473, 3}, - 0xF51 = { 4476, 4}, - 0xF52 = { 4480, 3}, - 0xF53 = { 4483, 3}, - 0xF54 = { 4486, 4}, - 0xF55 = { 4490, 4}, - 0xF56 = { 4494, 4}, - 0xF57 = { 4498, 4}, - 0xF58 = { 4502, 3}, - 0xF59 = { 4505, 3}, - 0xF5A = { 4508, 3}, - 0xF5B = { 4511, 4}, - 0xF5C = { 4515, 4}, - 0xF5D = { 4519, 4}, - 0xF5E = { 4523, 3}, - 0xF5F = { 4526, 3}, - 0xF60 = { 4529, 3}, - 0xF61 = { 4532, 3}, - 0xF62 = { 4535, 3}, - 0xF63 = { 4538, 3}, - 0xF64 = { 4541, 4}, - 0xF65 = { 4545, 3}, - 0xF66 = { 4548, 3}, - 0xF67 = { 4551, 3}, - 0xF68 = { 4554, 3}, - 0xF69 = { 4557, 3}, - 0xF6A = { 4560, 3}, - 0xF6B = { 4563, 3}, - 0xF6C = { 4566, 4}, - 0xF6D = { 4570, 3}, - 0xF6E = { 4573, 3}, - 0xF6F = { 4576, 3}, - 0xF70 = { 4579, 3}, - 0xF71 = { 4582, 3}, - 0xF72 = { 4585, 3}, - 0xF73 = { 4588, 3}, - 0xF74 = { 4591, 3}, - 0xF75 = { 4594, 3}, - 0xF76 = { 4597, 3}, - 0xF77 = { 4600, 3}, - 0xF78 = { 4603, 6}, - 0xF79 = { 4609, 3}, - 0xF7A = { 4612, 3}, - 0xF7B = { 4615, 3}, - 0xF7C = { 4618, 3}, - 0xF7D = { 4621, 3}, - 0xF7E = { 4624, 3}, - 0xF7F = { 4627, 4}, - 0xF80 = { 4631, 1}, - 0xF81 = { 4632, 1}, - 0xF82 = { 4633, 1}, - 0xF83 = { 4634, 2}, - 0xF84 = { 4636, 1}, - 0xF85 = { 4637, 2}, - 0xF88 = { 4639, 1}, - 0xF89 = { 4640, 2}, - 0xF8A = { 4642, 1}, - 0xF8B = { 4643, 1}, - 0xF8C = { 4644, 1}, - 0xF8D = { 4645, 2}, - 0xF91 = { 4647, 1}, - 0xF93 = { 4648, 1}, - 0xF99 = { 4649, 2}, - 0xF9B = { 4651, 1}, - 0xFA0 = { 4652, 3}, - 0xFA1 = { 4655, 3}, - 0xFA2 = { 4658, 3}, - 0xFA3 = { 4661, 3}, - 0xFA4 = { 4664, 3}, - 0xFA5 = { 4667, 3}, - 0xFA6 = { 4670, 1}, - 0xFA7 = { 4671, 1}, - 0xFA8 = { 4672, 10}, - 0xFA9 = { 4682, 10}, - 0xFAA = { 4692, 6}, - 0xFAB = { 4698, 1}, - 0xFAC = { 4699, 6}, - 0xFAD = { 4705, 6}, - 0xFAE = { 4711, 6}, - 0xFB0 = { 4717, 3}, - 0xFB5 = { 4720, 1}, - 0xFB8 = { 4721, 1}, - 0xFB9 = { 4722, 1}, - 0xFBA = { 4723, 1}, - 0xFBB = { 4724, 1}, - 0xFBC = { 4725, 1}, - 0xFBE = { 4726, 1}, - 0xFC0 = { 4727, 1}, - 0xFC1 = { 4728, 1}, - 0xFC2 = { 4729, 3}, - 0xFC3 = { 4732, 3}, - 0xFC4 = { 4735, 1}, - 0xFC5 = { 4736, 1}, - 0xFC6 = { 4737, 2}, - 0xFC7 = { 4739, 2}, - 0xFC8 = { 4741, 7}, - 0xFC9 = { 4748, 11}, - 0xFCA = { 4759, 3}, - 0xFCB = { 4762, 3}, - 0xFCC = { 4765, 7}, - 0xFCD = { 4772, 7}, - 0xFCE = { 4779, 2}, - 0xFCF = { 4781, 2}, - 0xFD2 = { 4783, 1}, - 0xFD3 = { 4784, 1}, - 0xFD9 = { 4785, 4}, - 0xFDA = { 4789, 1}, - 0xFDB = { 4790, 1}, - 0xFE0 = { 4791, 28}, - 0xFE1 = { 4819, 26}, - 0xFE2 = { 4845, 26}, - 0xFE3 = { 4871, 32}, - 0xFE4 = { 4903, 29}, - 0xFE5 = { 4932, 27}, - 0xFE6 = { 4959, 27}, - 0xFE7 = { 4986, 33}, - 0xFE8 = { 5019, 32}, - 0xFE9 = { 5051, 17}, - 0xFEA = { 5068, 17}, - 0xFEB = { 5085, 29}, - 0xFEC = { 5114, 31}, - 0xFED = { 5145, 18}, - 0xFEE = { 5163, 26}, - 0xFEF = { 5189, 32}, - 0xFF0 = { 5221, 19}, - 0xFF1 = { 5240, 18}, - 0xFF2 = { 5258, 17}, - 0xFF3 = { 5275, 17}, - 0xFF4 = { 5292, 19}, - 0xFF5 = { 5311, 18}, - 0xFF6 = { 5329, 17}, - 0xFF7 = { 5346, 17}, - 0xFF8 = { 5363, 4}, - 0xFF9 = { 5367, 4}, - 0xFFA = { 5371, 4}, - 0xFFB = { 5375, 17}, - 0xFFC = { 5392, 4}, - 0xFFD = { 5396, 4}, - 0xFFE = { 5400, 4}, - 0xFFF = { 5404, 17}, + 0xE84 = { 3511, 6}, + 0xE85 = { 3517, 2}, + 0xE86 = { 3519, 1}, + 0xE87 = { 3520, 1}, + 0xE88 = { 3521, 1}, + 0xE89 = { 3522, 1}, + 0xE8A = { 3523, 1}, + 0xE8B = { 3524, 2}, + 0xE8C = { 3526, 4}, + 0xE8D = { 3530, 6}, + 0xE8E = { 3536, 1}, + 0xE8F = { 3537, 1}, + 0xE90 = { 3538, 1}, + 0xE91 = { 3539, 1}, + 0xE92 = { 3540, 2}, + 0xE93 = { 3542, 1}, + 0xE94 = { 3543, 1}, + 0xE95 = { 3544, 1}, + 0xE96 = { 3545, 1}, + 0xE97 = { 3546, 2}, + 0xE9C = { 3548, 1}, + 0xE9D = { 3549, 1}, + 0xE9E = { 3550, 1}, + 0xE9F = { 3551, 1}, + 0xEA0 = { 3552, 2}, + 0xEA1 = { 3554, 3}, + 0xEA2 = { 3557, 1}, + 0xEA3 = { 3558, 1}, + 0xEA4 = { 3559, 7}, + 0xEA5 = { 3566, 7}, + 0xEA6 = { 3573, 1}, + 0xEA7 = { 3574, 1}, + 0xEA8 = { 3575, 1}, + 0xEA9 = { 3576, 2}, + 0xEB1 = { 3578, 1}, + 0xEB4 = { 3579, 1}, + 0xEB5 = { 3580, 1}, + 0xEB6 = { 3581, 1}, + 0xEB7 = { 3582, 1}, + 0xEBB = { 3583, 1}, + 0xEBC = { 3584, 1}, + 0xEBD = { 3585, 1}, + 0xEC0 = { 3586, 2}, + 0xEC1 = { 3588, 1}, + 0xEC2 = { 3589, 3}, + 0xEC3 = { 3592, 2}, + 0xEC4 = { 3594, 2}, + 0xEC5 = { 3596, 1}, + 0xEC6 = { 3597, 7}, + 0xEC7 = { 3604, 2}, + 0xEC8 = { 3606, 1}, + 0xEC9 = { 3607, 1}, + 0xECA = { 3608, 2}, + 0xECB = { 3610, 2}, + 0xECC = { 3612, 1}, + 0xECD = { 3613, 1}, + 0xECE = { 3614, 2}, + 0xECF = { 3616, 2}, + 0xED6 = { 3618, 4}, + 0xED8 = { 3622, 4}, + 0xED9 = { 3626, 4}, + 0xEDC = { 3630, 4}, + 0xEDD = { 3634, 4}, + 0xEE0 = { 3638, 24}, + 0xEE1 = { 3662, 23}, + 0xEE2 = { 3685, 22}, + 0xEE3 = { 3707, 29}, + 0xEE4 = { 3736, 23}, + 0xEE5 = { 3759, 22}, + 0xEE6 = { 3781, 22}, + 0xEE7 = { 3803, 29}, + 0xEE8 = { 3832, 28}, + 0xEE9 = { 3860, 12}, + 0xEEA = { 3872, 13}, + 0xEEB = { 3885, 18}, + 0xEEC = { 3903, 27}, + 0xEED = { 3930, 13}, + 0xEEE = { 3943, 22}, + 0xEEF = { 3965, 23}, + 0xEF0 = { 3988, 15}, + 0xEF1 = { 4003, 15}, + 0xEF2 = { 4018, 15}, + 0xEF3 = { 4033, 15}, + 0xEF4 = { 4048, 15}, + 0xEF5 = { 4063, 15}, + 0xEF6 = { 4078, 15}, + 0xEF7 = { 4093, 15}, + 0xEF8 = { 4108, 3}, + 0xEF9 = { 4111, 3}, + 0xEFA = { 4114, 3}, + 0xEFB = { 4117, 3}, + 0xEFC = { 4120, 3}, + 0xEFD = { 4123, 3}, + 0xEFE = { 4126, 3}, + 0xEFF = { 4129, 3}, + 0xF00 = { 4132, 11}, + 0xF01 = { 4143, 10}, + 0xF02 = { 4153, 7}, + 0xF03 = { 4160, 7}, + 0xF04 = { 4167, 9}, + 0xF05 = { 4176, 6}, + 0xF06 = { 4182, 5}, + 0xF07 = { 4187, 5}, + 0xF08 = { 4192, 5}, + 0xF09 = { 4197, 5}, + 0xF0A = { 4202, 3}, + 0xF0B = { 4205, 3}, + 0xF0C = { 4208, 4}, + 0xF0D = { 4212, 3}, + 0xF0E = { 4215, 4}, + 0xF0F = { 4219, 4}, + 0xF10 = { 4223, 6}, + 0xF11 = { 4229, 6}, + 0xF12 = { 4235, 5}, + 0xF13 = { 4240, 5}, + 0xF14 = { 4245, 5}, + 0xF15 = { 4250, 4}, + 0xF16 = { 4254, 5}, + 0xF17 = { 4259, 5}, + 0xF18 = { 4264, 4}, + 0xF19 = { 4268, 3}, + 0xF1A = { 4271, 3}, + 0xF1B = { 4274, 4}, + 0xF1C = { 4278, 5}, + 0xF1D = { 4283, 4}, + 0xF1E = { 4287, 4}, + 0xF1F = { 4291, 4}, + 0xF20 = { 4295, 4}, + 0xF21 = { 4299, 3}, + 0xF22 = { 4302, 3}, + 0xF23 = { 4305, 3}, + 0xF24 = { 4308, 5}, + 0xF25 = { 4313, 3}, + 0xF26 = { 4316, 4}, + 0xF27 = { 4320, 4}, + 0xF28 = { 4324, 4}, + 0xF29 = { 4328, 3}, + 0xF2A = { 4331, 3}, + 0xF2B = { 4334, 3}, + 0xF2C = { 4337, 5}, + 0xF2D = { 4342, 3}, + 0xF2E = { 4345, 4}, + 0xF2F = { 4349, 4}, + 0xF30 = { 4353, 5}, + 0xF31 = { 4358, 3}, + 0xF32 = { 4361, 5}, + 0xF33 = { 4366, 3}, + 0xF34 = { 4369, 5}, + 0xF35 = { 4374, 3}, + 0xF36 = { 4377, 6}, + 0xF37 = { 4383, 4}, + 0xF38 = { 4387, 6}, + 0xF39 = { 4393, 3}, + 0xF3A = { 4396, 18}, + 0xF3B = { 4414, 8}, + 0xF3C = { 4422, 5}, + 0xF3D = { 4427, 3}, + 0xF3E = { 4430, 5}, + 0xF3F = { 4435, 4}, + 0xF40 = { 4439, 6}, + 0xF41 = { 4445, 6}, + 0xF42 = { 4451, 4}, + 0xF43 = { 4455, 4}, + 0xF44 = { 4459, 7}, + 0xF45 = { 4466, 6}, + 0xF46 = { 4472, 5}, + 0xF47 = { 4477, 5}, + 0xF48 = { 4482, 5}, + 0xF49 = { 4487, 5}, + 0xF4A = { 4492, 3}, + 0xF4B = { 4495, 3}, + 0xF4C = { 4498, 4}, + 0xF4D = { 4502, 3}, + 0xF4E = { 4505, 4}, + 0xF4F = { 4509, 4}, + 0xF50 = { 4513, 4}, + 0xF51 = { 4517, 4}, + 0xF52 = { 4521, 3}, + 0xF53 = { 4524, 3}, + 0xF54 = { 4527, 5}, + 0xF55 = { 4532, 4}, + 0xF56 = { 4536, 5}, + 0xF57 = { 4541, 5}, + 0xF58 = { 4546, 4}, + 0xF59 = { 4550, 3}, + 0xF5A = { 4553, 3}, + 0xF5B = { 4556, 4}, + 0xF5C = { 4560, 5}, + 0xF5D = { 4565, 4}, + 0xF5E = { 4569, 4}, + 0xF5F = { 4573, 4}, + 0xF60 = { 4577, 4}, + 0xF61 = { 4581, 3}, + 0xF62 = { 4584, 3}, + 0xF63 = { 4587, 3}, + 0xF64 = { 4590, 5}, + 0xF65 = { 4595, 3}, + 0xF66 = { 4598, 4}, + 0xF67 = { 4602, 4}, + 0xF68 = { 4606, 4}, + 0xF69 = { 4610, 3}, + 0xF6A = { 4613, 3}, + 0xF6B = { 4616, 3}, + 0xF6C = { 4619, 5}, + 0xF6D = { 4624, 3}, + 0xF6E = { 4627, 4}, + 0xF6F = { 4631, 4}, + 0xF70 = { 4635, 4}, + 0xF71 = { 4639, 3}, + 0xF72 = { 4642, 3}, + 0xF73 = { 4645, 3}, + 0xF74 = { 4648, 4}, + 0xF75 = { 4652, 3}, + 0xF76 = { 4655, 4}, + 0xF77 = { 4659, 4}, + 0xF78 = { 4663, 7}, + 0xF79 = { 4670, 3}, + 0xF7A = { 4673, 3}, + 0xF7B = { 4676, 3}, + 0xF7C = { 4679, 4}, + 0xF7D = { 4683, 3}, + 0xF7E = { 4686, 4}, + 0xF7F = { 4690, 5}, + 0xF80 = { 4695, 1}, + 0xF81 = { 4696, 1}, + 0xF82 = { 4697, 1}, + 0xF83 = { 4698, 2}, + 0xF84 = { 4700, 1}, + 0xF85 = { 4701, 2}, + 0xF88 = { 4703, 1}, + 0xF89 = { 4704, 2}, + 0xF8A = { 4706, 1}, + 0xF8B = { 4707, 1}, + 0xF8C = { 4708, 1}, + 0xF8D = { 4709, 2}, + 0xF91 = { 4711, 1}, + 0xF93 = { 4712, 1}, + 0xF99 = { 4713, 2}, + 0xF9B = { 4715, 1}, + 0xFA0 = { 4716, 3}, + 0xFA1 = { 4719, 3}, + 0xFA2 = { 4722, 3}, + 0xFA3 = { 4725, 3}, + 0xFA4 = { 4728, 3}, + 0xFA5 = { 4731, 3}, + 0xFA6 = { 4734, 1}, + 0xFA7 = { 4735, 1}, + 0xFA8 = { 4736, 10}, + 0xFA9 = { 4746, 10}, + 0xFAA = { 4756, 6}, + 0xFAB = { 4762, 1}, + 0xFAC = { 4763, 6}, + 0xFAD = { 4769, 6}, + 0xFAE = { 4775, 6}, + 0xFB0 = { 4781, 3}, + 0xFB5 = { 4784, 1}, + 0xFB8 = { 4785, 1}, + 0xFB9 = { 4786, 1}, + 0xFBA = { 4787, 1}, + 0xFBB = { 4788, 1}, + 0xFBC = { 4789, 1}, + 0xFBE = { 4790, 1}, + 0xFC0 = { 4791, 1}, + 0xFC1 = { 4792, 1}, + 0xFC2 = { 4793, 3}, + 0xFC3 = { 4796, 3}, + 0xFC4 = { 4799, 1}, + 0xFC5 = { 4800, 1}, + 0xFC6 = { 4801, 2}, + 0xFC7 = { 4803, 2}, + 0xFC8 = { 4805, 7}, + 0xFC9 = { 4812, 11}, + 0xFCA = { 4823, 3}, + 0xFCB = { 4826, 3}, + 0xFCC = { 4829, 7}, + 0xFCD = { 4836, 7}, + 0xFCE = { 4843, 2}, + 0xFCF = { 4845, 2}, + 0xFD2 = { 4847, 1}, + 0xFD3 = { 4848, 1}, + 0xFD9 = { 4849, 4}, + 0xFDA = { 4853, 1}, + 0xFDB = { 4854, 1}, + 0xFE0 = { 4855, 28}, + 0xFE1 = { 4883, 26}, + 0xFE2 = { 4909, 26}, + 0xFE3 = { 4935, 32}, + 0xFE4 = { 4967, 29}, + 0xFE5 = { 4996, 27}, + 0xFE6 = { 5023, 27}, + 0xFE7 = { 5050, 33}, + 0xFE8 = { 5083, 32}, + 0xFE9 = { 5115, 17}, + 0xFEA = { 5132, 17}, + 0xFEB = { 5149, 29}, + 0xFEC = { 5178, 31}, + 0xFED = { 5209, 18}, + 0xFEE = { 5227, 26}, + 0xFEF = { 5253, 32}, + 0xFF0 = { 5285, 19}, + 0xFF1 = { 5304, 18}, + 0xFF2 = { 5322, 17}, + 0xFF3 = { 5339, 17}, + 0xFF4 = { 5356, 19}, + 0xFF5 = { 5375, 18}, + 0xFF6 = { 5393, 17}, + 0xFF7 = { 5410, 17}, + 0xFF8 = { 5427, 4}, + 0xFF9 = { 5431, 4}, + 0xFFA = { 5435, 4}, + 0xFFB = { 5439, 17}, + 0xFFC = { 5456, 4}, + 0xFFD = { 5460, 4}, + 0xFFE = { 5464, 4}, + 0xFFF = { 5468, 17}, } diff --git a/core/rexcode/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/arm32/tablegen/generated/encode_tables.odin index 019ea1e55..866948a71 100644 --- a/core/rexcode/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/arm32/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -ENCODE_FORMS := [1675]lib.Encoding{ +ENCODE_FORMS := [1679]lib.Encoding{ // .AND { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {} }, @@ -2031,17 +2031,25 @@ ENCODE_FORMS := [1675]lib.Encoding{ // .WLS { .WLS, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF040C001, 0xFFF0F001, .V81M, .T32, {branch=true, thumb32=true} }, // .WLSTP - { .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFE80F001, .V81M, .T32, {branch=true, thumb32=true} }, + { .WLSTP, {.GPR,.REL11,.NONE,.NONE}, {.RN_T32,.MVE_LOOP_IMM,.NONE,.NONE}, 0xF000C001, 0xFEC0F001, .V81M, .T32, {branch=true, thumb32=true} }, // .DLS { .DLS, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF040E001, 0xFFF0FFFF, .V81M, .T32, {thumb32=true} }, // .DLSTP - { .DLSTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E001, 0xFE80FFFF, .V81M, .T32, {thumb32=true} }, + { .DLSTP, {.GPR,.NONE,.NONE,.NONE}, {.RN_T32,.NONE,.NONE,.NONE}, 0xF000E001, 0xFEC0FFFF, .V81M, .T32, {thumb32=true} }, // .LE { .LE, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF00FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} }, // .LETP { .LETP, {.REL11,.NONE,.NONE,.NONE}, {.MVE_LOOP_IMM,.NONE,.NONE,.NONE}, 0xF01FC001, 0xFFFFF001, .V81M, .T32, {branch=true, thumb32=true} }, // .LCTP { .LCTP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF00FE001, 0xFFFFFFFF, .V81M, .T32, {thumb32=true} }, + // .BF + { .BF, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF040E001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} }, + // .BFI_BR + { .BFI_BR, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF060E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, + // .BFL + { .BFL, {.REL_BF,.REL_BF,.NONE,.NONE}, {.BF_BOFF,.BF_BLOC,.NONE,.NONE}, 0xF000C001, 0xF87FF001, .V81M, .T32, {branch=true, thumb32=true} }, + // .BFLX + { .BFLX, {.REL_BF,.GPR,.NONE,.NONE}, {.BF_BOFF,.BF_RM,.NONE,.NONE}, 0xF070E001, 0xF870FFFF, .V81M, .T32, {branch=true, thumb32=true} }, // .CX1 { .CX1, {.IMM_COPROC,.GPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.RD_T32,.CDE_IMM_FIELD,.NONE}, 0xEE000000, 0xFF800000, .CDE, .T32, {thumb32=true} }, // .CX1A @@ -2809,141 +2817,141 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .LE = { 1535, 1}, .LETP = { 1536, 1}, .LCTP = { 1537, 1}, - .BF = { 1538, 0}, - .BFI_BR = { 1538, 0}, - .BFL = { 1538, 0}, - .BFLX = { 1538, 0}, - .BFCSEL = { 1538, 0}, - .CX1 = { 1538, 1}, - .CX1A = { 1539, 1}, - .CX1D = { 1540, 1}, - .CX1DA = { 1541, 1}, - .CX2 = { 1542, 1}, - .CX2A = { 1543, 1}, - .CX2D = { 1544, 1}, - .CX2DA = { 1545, 1}, - .CX3 = { 1546, 1}, - .CX3A = { 1547, 1}, - .CX3D = { 1548, 1}, - .CX3DA = { 1549, 1}, - .VCX1 = { 1550, 2}, - .VCX1A = { 1552, 2}, - .VCX2 = { 1554, 2}, - .VCX2A = { 1556, 2}, - .VCX3 = { 1558, 2}, - .VCX3A = { 1560, 2}, - .VPT = { 1562, 1}, - .VPST = { 1563, 1}, - .VPSEL = { 1564, 1}, - .VPNOT = { 1565, 1}, - .VCTP = { 1566, 1}, - .VADDV = { 1567, 1}, - .VADDVA = { 1568, 1}, - .VADDLV = { 1569, 1}, - .VADDLVA = { 1570, 1}, - .VMAXV = { 1571, 1}, - .VMAXAV = { 1572, 1}, - .VMINV = { 1573, 1}, - .VMINAV = { 1574, 1}, - .VMAXNMV = { 1575, 1}, - .VMAXNMAV = { 1576, 1}, - .VMINNMV = { 1577, 1}, - .VMINNMAV = { 1578, 1}, - .VABAV = { 1579, 1}, - .VMLADAV = { 1580, 1}, - .VMLADAVA = { 1581, 1}, - .VMLADAVX = { 1582, 1}, - .VMLADAVAX = { 1583, 1}, - .VMLALDAV = { 1584, 1}, - .VMLALDAVA = { 1585, 1}, - .VMLALDAVX = { 1586, 1}, - .VMLALDAVAX = { 1587, 1}, - .VMLSDAV = { 1588, 1}, - .VMLSDAVA = { 1589, 1}, - .VMLSDAVX = { 1590, 1}, - .VMLSDAVAX = { 1591, 1}, - .VMLSLDAV = { 1592, 1}, - .VMLSLDAVA = { 1593, 1}, - .VMLSLDAVX = { 1594, 1}, - .VMLSLDAVAX = { 1595, 1}, - .VRMLALDAVH = { 1596, 1}, - .VRMLALDAVHA = { 1597, 1}, - .VRMLALDAVHX = { 1598, 1}, - .VRMLALDAVHAX = { 1599, 1}, - .VRMLSLDAVH = { 1600, 1}, - .VRMLSLDAVHA = { 1601, 1}, - .VRMLSLDAVHX = { 1602, 1}, - .VRMLSLDAVHAX = { 1603, 1}, - .VMLAV = { 1604, 1}, - .VMLAVA = { 1605, 1}, - .VMLSV = { 1606, 1}, - .VMLSVA = { 1607, 1}, - .VCMUL = { 1608, 1}, - .VHCADD = { 1609, 1}, - .VBRSR = { 1610, 1}, - .VSHLC = { 1611, 1}, - .VDDUP = { 1612, 1}, - .VIDUP = { 1613, 1}, - .VDWDUP = { 1614, 1}, - .VIWDUP = { 1615, 1}, - .VMOVNB = { 1616, 1}, - .VMOVNT = { 1617, 1}, - .VQMOVNB = { 1618, 1}, - .VQMOVNT = { 1619, 1}, - .VQMOVUNB = { 1620, 1}, - .VQMOVUNT = { 1621, 1}, - .VSHLLB = { 1622, 1}, - .VSHLLT = { 1623, 1}, - .VMULLB = { 1624, 1}, - .VMULLT = { 1625, 1}, - .VMLALB = { 1626, 1}, - .VMLALT = { 1627, 1}, - .VMLSLB = { 1628, 1}, - .VMLSLT = { 1629, 1}, - .VSHRNB = { 1630, 1}, - .VSHRNT = { 1631, 1}, - .VRSHRNB = { 1632, 1}, - .VRSHRNT = { 1633, 1}, - .VQSHRNB = { 1634, 1}, - .VQSHRNT = { 1635, 1}, - .VQRSHRNB = { 1636, 1}, - .VQRSHRNT = { 1637, 1}, - .VQSHRUNB = { 1638, 1}, - .VQSHRUNT = { 1639, 1}, - .VQRSHRUNB = { 1640, 1}, - .VQRSHRUNT = { 1641, 1}, - .VMOV_Q_R = { 1642, 1}, - .VMOV_R_Q = { 1643, 1}, - .VMOV_2GPR_Q = { 1644, 1}, - .VQDMLADH = { 1645, 1}, - .VQDMLADHX = { 1646, 1}, - .VQDMLSDH = { 1647, 1}, - .VQDMLSDHX = { 1648, 1}, - .VQRDMLADH = { 1649, 1}, - .VQRDMLADHX = { 1650, 1}, - .VQRDMLSDH = { 1651, 1}, - .VQRDMLSDHX = { 1652, 1}, - .VHCADD_SAT = { 1653, 1}, - .VCMLA_MVE = { 1654, 1}, - .VLDRB = { 1655, 1}, - .VLDRH = { 1656, 1}, - .VLDRW = { 1657, 1}, - .VLDRD = { 1658, 1}, - .VSTRB = { 1659, 1}, - .VSTRH = { 1660, 1}, - .VSTRW = { 1661, 1}, - .VSTRD = { 1662, 1}, - .VLD20 = { 1663, 1}, - .VLD21 = { 1664, 1}, - .VLD40 = { 1665, 1}, - .VLD41 = { 1666, 1}, - .VLD42 = { 1667, 1}, - .VLD43 = { 1668, 1}, - .VST20 = { 1669, 1}, - .VST21 = { 1670, 1}, - .VST40 = { 1671, 1}, - .VST41 = { 1672, 1}, - .VST42 = { 1673, 1}, - .VST43 = { 1674, 1}, - ._COUNT = { 1675, 0}, + .BF = { 1538, 1}, + .BFI_BR = { 1539, 1}, + .BFL = { 1540, 1}, + .BFLX = { 1541, 1}, + .BFCSEL = { 1542, 0}, + .CX1 = { 1542, 1}, + .CX1A = { 1543, 1}, + .CX1D = { 1544, 1}, + .CX1DA = { 1545, 1}, + .CX2 = { 1546, 1}, + .CX2A = { 1547, 1}, + .CX2D = { 1548, 1}, + .CX2DA = { 1549, 1}, + .CX3 = { 1550, 1}, + .CX3A = { 1551, 1}, + .CX3D = { 1552, 1}, + .CX3DA = { 1553, 1}, + .VCX1 = { 1554, 2}, + .VCX1A = { 1556, 2}, + .VCX2 = { 1558, 2}, + .VCX2A = { 1560, 2}, + .VCX3 = { 1562, 2}, + .VCX3A = { 1564, 2}, + .VPT = { 1566, 1}, + .VPST = { 1567, 1}, + .VPSEL = { 1568, 1}, + .VPNOT = { 1569, 1}, + .VCTP = { 1570, 1}, + .VADDV = { 1571, 1}, + .VADDVA = { 1572, 1}, + .VADDLV = { 1573, 1}, + .VADDLVA = { 1574, 1}, + .VMAXV = { 1575, 1}, + .VMAXAV = { 1576, 1}, + .VMINV = { 1577, 1}, + .VMINAV = { 1578, 1}, + .VMAXNMV = { 1579, 1}, + .VMAXNMAV = { 1580, 1}, + .VMINNMV = { 1581, 1}, + .VMINNMAV = { 1582, 1}, + .VABAV = { 1583, 1}, + .VMLADAV = { 1584, 1}, + .VMLADAVA = { 1585, 1}, + .VMLADAVX = { 1586, 1}, + .VMLADAVAX = { 1587, 1}, + .VMLALDAV = { 1588, 1}, + .VMLALDAVA = { 1589, 1}, + .VMLALDAVX = { 1590, 1}, + .VMLALDAVAX = { 1591, 1}, + .VMLSDAV = { 1592, 1}, + .VMLSDAVA = { 1593, 1}, + .VMLSDAVX = { 1594, 1}, + .VMLSDAVAX = { 1595, 1}, + .VMLSLDAV = { 1596, 1}, + .VMLSLDAVA = { 1597, 1}, + .VMLSLDAVX = { 1598, 1}, + .VMLSLDAVAX = { 1599, 1}, + .VRMLALDAVH = { 1600, 1}, + .VRMLALDAVHA = { 1601, 1}, + .VRMLALDAVHX = { 1602, 1}, + .VRMLALDAVHAX = { 1603, 1}, + .VRMLSLDAVH = { 1604, 1}, + .VRMLSLDAVHA = { 1605, 1}, + .VRMLSLDAVHX = { 1606, 1}, + .VRMLSLDAVHAX = { 1607, 1}, + .VMLAV = { 1608, 1}, + .VMLAVA = { 1609, 1}, + .VMLSV = { 1610, 1}, + .VMLSVA = { 1611, 1}, + .VCMUL = { 1612, 1}, + .VHCADD = { 1613, 1}, + .VBRSR = { 1614, 1}, + .VSHLC = { 1615, 1}, + .VDDUP = { 1616, 1}, + .VIDUP = { 1617, 1}, + .VDWDUP = { 1618, 1}, + .VIWDUP = { 1619, 1}, + .VMOVNB = { 1620, 1}, + .VMOVNT = { 1621, 1}, + .VQMOVNB = { 1622, 1}, + .VQMOVNT = { 1623, 1}, + .VQMOVUNB = { 1624, 1}, + .VQMOVUNT = { 1625, 1}, + .VSHLLB = { 1626, 1}, + .VSHLLT = { 1627, 1}, + .VMULLB = { 1628, 1}, + .VMULLT = { 1629, 1}, + .VMLALB = { 1630, 1}, + .VMLALT = { 1631, 1}, + .VMLSLB = { 1632, 1}, + .VMLSLT = { 1633, 1}, + .VSHRNB = { 1634, 1}, + .VSHRNT = { 1635, 1}, + .VRSHRNB = { 1636, 1}, + .VRSHRNT = { 1637, 1}, + .VQSHRNB = { 1638, 1}, + .VQSHRNT = { 1639, 1}, + .VQRSHRNB = { 1640, 1}, + .VQRSHRNT = { 1641, 1}, + .VQSHRUNB = { 1642, 1}, + .VQSHRUNT = { 1643, 1}, + .VQRSHRUNB = { 1644, 1}, + .VQRSHRUNT = { 1645, 1}, + .VMOV_Q_R = { 1646, 1}, + .VMOV_R_Q = { 1647, 1}, + .VMOV_2GPR_Q = { 1648, 1}, + .VQDMLADH = { 1649, 1}, + .VQDMLADHX = { 1650, 1}, + .VQDMLSDH = { 1651, 1}, + .VQDMLSDHX = { 1652, 1}, + .VQRDMLADH = { 1653, 1}, + .VQRDMLADHX = { 1654, 1}, + .VQRDMLSDH = { 1655, 1}, + .VQRDMLSDHX = { 1656, 1}, + .VHCADD_SAT = { 1657, 1}, + .VCMLA_MVE = { 1658, 1}, + .VLDRB = { 1659, 1}, + .VLDRH = { 1660, 1}, + .VLDRW = { 1661, 1}, + .VLDRD = { 1662, 1}, + .VSTRB = { 1663, 1}, + .VSTRH = { 1664, 1}, + .VSTRW = { 1665, 1}, + .VSTRD = { 1666, 1}, + .VLD20 = { 1667, 1}, + .VLD21 = { 1668, 1}, + .VLD40 = { 1669, 1}, + .VLD41 = { 1670, 1}, + .VLD42 = { 1671, 1}, + .VLD43 = { 1672, 1}, + .VST20 = { 1673, 1}, + .VST21 = { 1674, 1}, + .VST40 = { 1675, 1}, + .VST41 = { 1676, 1}, + .VST42 = { 1677, 1}, + .VST43 = { 1678, 1}, + ._COUNT = { 1679, 0}, } diff --git a/core/rexcode/arm32/tables/arm32.bucket_list.bin b/core/rexcode/arm32/tables/arm32.bucket_list.bin index eef85fd70..ccae4e5f7 100644 Binary files a/core/rexcode/arm32/tables/arm32.bucket_list.bin and b/core/rexcode/arm32/tables/arm32.bucket_list.bin differ diff --git a/core/rexcode/arm32/tables/arm32.encode_forms.bin b/core/rexcode/arm32/tables/arm32.encode_forms.bin index 2db38fb82..bb7d6dbc5 100644 Binary files a/core/rexcode/arm32/tables/arm32.encode_forms.bin and b/core/rexcode/arm32/tables/arm32.encode_forms.bin differ diff --git a/core/rexcode/arm32/tables/arm32.encode_runs.bin b/core/rexcode/arm32/tables/arm32.encode_runs.bin index c5afc73b4..894ed43ce 100644 Binary files a/core/rexcode/arm32/tables/arm32.encode_runs.bin and b/core/rexcode/arm32/tables/arm32.encode_runs.bin differ diff --git a/core/rexcode/arm32/tables/arm32.entries.bin b/core/rexcode/arm32/tables/arm32.entries.bin index 3f46963f3..ce8f33b2f 100644 Binary files a/core/rexcode/arm32/tables/arm32.entries.bin and b/core/rexcode/arm32/tables/arm32.entries.bin differ diff --git a/core/rexcode/arm32/tables/arm32.form_idx.bin b/core/rexcode/arm32/tables/arm32.form_idx.bin index 8c1d371a1..1c00b775a 100644 Binary files a/core/rexcode/arm32/tables/arm32.form_idx.bin and b/core/rexcode/arm32/tables/arm32.form_idx.bin differ diff --git a/core/rexcode/arm32/tables/arm32.idx_t16.bin b/core/rexcode/arm32/tables/arm32.idx_t16.bin index b8cc67772..5aea413c7 100644 Binary files a/core/rexcode/arm32/tables/arm32.idx_t16.bin and b/core/rexcode/arm32/tables/arm32.idx_t16.bin differ diff --git a/core/rexcode/arm32/tables/arm32.idx_t32.bin b/core/rexcode/arm32/tables/arm32.idx_t32.bin index 705151faa..b5a34bcf1 100644 Binary files a/core/rexcode/arm32/tables/arm32.idx_t32.bin and b/core/rexcode/arm32/tables/arm32.idx_t32.bin differ diff --git a/core/rexcode/arm32/tables/arm32.idx_t32_sub.bin b/core/rexcode/arm32/tables/arm32.idx_t32_sub.bin index e59a91ed8..4377279cb 100644 Binary files a/core/rexcode/arm32/tables/arm32.idx_t32_sub.bin and b/core/rexcode/arm32/tables/arm32.idx_t32_sub.bin differ diff --git a/core/rexcode/arm32/tools/gen_mnemonic_builders.odin b/core/rexcode/arm32/tools/gen_mnemonic_builders.odin index 1fc045503..b3d6c547d 100644 --- a/core/rexcode/arm32/tools/gen_mnemonic_builders.odin +++ b/core/rexcode/arm32/tools/gen_mnemonic_builders.odin @@ -119,7 +119,7 @@ operand_class :: proc(ot: a.Operand_Type) -> Operand_Class { return .MEM // ---- PC-relative branch targets & low-overhead-loop targets ---- - case .REL24, .REL24_T32, .REL20, .REL11, .REL8, .REL_LDR_LITERAL, .MVE_LOOP_TGT: + case .REL24, .REL24_T32, .REL20, .REL11, .REL8, .REL_LDR_LITERAL, .MVE_LOOP_TGT, .REL_BF: return .REL // ---- Plain registers (single Register value) ---- @@ -187,6 +187,7 @@ operand_suffix :: proc(ot: a.Operand_Type) -> string { case .REL11: return "rel" case .REL8: return "rel" case .REL_LDR_LITERAL: return "rel" + case .REL_BF: return "rel" case .COPROC_REG: return "crd" case .COPROC_NUM: return "cpn" case .PSR_FIELD: return "psr"