diff --git a/core/rexcode/arm32/decoder.odin b/core/rexcode/arm32/decoder.odin
index 3e21df7e9..ad831c0b8 100644
--- a/core/rexcode/arm32/decoder.odin
+++ b/core/rexcode/arm32/decoder.odin
@@ -473,9 +473,6 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op
 		imm10 := (word >> 1)  & 0x3FF       // hw1[10:1]
 		val   := (imm10 << 1) | j
 		return op_rel_offset(i64(val) << 1)
-	case .BF_BELSE:
-		imm   := (word >> 23) & 0xF
-		return op_rel_offset(i64(imm) << 1)
 	case .BF_RM:
 		return op_reg(Register(REG_GPR | u16((word >> 16) & 0xF)))
 	case .BFCSEL_COND:
diff --git a/core/rexcode/arm32/encoder.odin b/core/rexcode/arm32/encoder.odin
index 29b72f922..5f66435f6 100644
--- a/core/rexcode/arm32/encoder.odin
+++ b/core/rexcode/arm32/encoder.odin
@@ -574,12 +574,6 @@ pack_operand_inline :: #force_inline proc(
 			type = .BF_BLOC_T32, size = 4, inst_idx = inst_idx,
 		})
 		return 0
-	case .BF_BELSE:
-		append(relocs, Relocation{
-			offset = pc, label_id = u32(op.relative),
-			type = .BFCSEL_ELSE_T32, size = 4, inst_idx = inst_idx,
-		})
-		return 0
 	case .BF_RM:
 		return (u32(reg_hw(op.reg)) & 0xF) << 16   // Rm at hw0[3:0] (word bits 19:16)
 	case .BFCSEL_COND:
diff --git a/core/rexcode/arm32/encoding_types.odin b/core/rexcode/arm32/encoding_types.odin
index 7bea46b5e..cb7bc636b 100644
--- a/core/rexcode/arm32/encoding_types.odin
+++ b/core/rexcode/arm32/encoding_types.odin
@@ -356,7 +356,6 @@ Operand_Encoding :: enum u8 {
 	// ARMv8.1-M Branch Future fields (T32):
 	BF_BOFF,               // bf-point offset: imm4 at hw0[10:7], (label-PC-4)/2
 	BF_BLOC,               // branch target: J at hw1[11] + imm10 at hw1[10:1]
-	BF_BELSE,              // BFCSEL else-target: imm4 at hw0[? ] (relative to bf-point)
 	BF_RM,                 // BFLX/BFX register target at hw0[3:0]
 	BFCSEL_COND,           // BFCSEL condition at hw0[5:2]
 
diff --git a/core/rexcode/arm32/reloc.odin b/core/rexcode/arm32/reloc.odin
index 09f56eb80..948777234 100644
--- a/core/rexcode/arm32/reloc.odin
+++ b/core/rexcode/arm32/reloc.odin
@@ -44,7 +44,6 @@ Relocation_Type :: enum u8 {
 	// T32 Branch Future (ARMv8.1-M)
 	BF_BOFF_T32,           // bf-point: imm4 at hw0[10:7] = (label - (PC+4))/2
 	BF_BLOC_T32,           // branch target: J at hw1[11] + imm10 at hw1[10:1]
-	BFCSEL_ELSE_T32,       // BFCSEL else-target relative to the bf-point
 
 	// Literal load (ADR / LDR PC-rel)
 	LDR_LITERAL_A32,       // signed 12-bit (U bit + imm12)
diff --git a/core/rexcode/arm32/tables/arm32.encode_forms.bin b/core/rexcode/arm32/tables/arm32.encode_forms.bin
index da7550d80..db36cfc97 100644
Binary files a/core/rexcode/arm32/tables/arm32.encode_forms.bin and b/core/rexcode/arm32/tables/arm32.encode_forms.bin differ
diff --git a/core/rexcode/arm32/tables/arm32.entries.bin b/core/rexcode/arm32/tables/arm32.entries.bin
index e9265d3da..be561ef37 100644
Binary files a/core/rexcode/arm32/tables/arm32.entries.bin and b/core/rexcode/arm32/tables/arm32.entries.bin differ
diff --git a/core/rexcode/mips/tablegen/specgen.lua b/core/rexcode/mips/tablegen/specgen.lua
index 6ed10233c..88b04d48a 100644
--- a/core/rexcode/mips/tablegen/specgen.lua
+++ b/core/rexcode/mips/tablegen/specgen.lua
@@ -243,10 +243,12 @@ for _, b in ipairs({{"MADD","madd"},{"MSUB","msub"},{"NMADD","nmadd"},{"NMSUB","
 end
 
 -- ---- MSA COPY (vector lane -> GPR) and INSERT (GPR -> vector lane) ----------
-for _, b in ipairs({{"COPY_S","copy_s"},{"COPY_U","copy_u"}}) do
-	for _, d in ipairs({{"B","b",15},{"H","h",7},{"W","w",3}}) do
-		local r = entry(b[1].."_"..d[1], "{.GPR,.MSA_VEC,.IMM5,.NONE}", "{.GPR_AT_6,.WS,.MSA_ELM_IDX,.NONE}", "MSA",
-			function(v) return string.format("%s.%s $%d,$w%d[%d]", b[2], d[2], v[1], v[2], v[3]) end, {31,31,d[3]})
+-- COPY_S has .B/.H/.W; COPY_U only .B/.H on mips32 (COPY_U.W is a mips64-only
+-- form, emitted in the mips64 section below).
+for _, c in ipairs({{"COPY_S","copy_s",{{"B","b",15},{"H","h",7},{"W","w",3}}}, {"COPY_U","copy_u",{{"B","b",15},{"H","h",7}}}}) do
+	for _, d in ipairs(c[3]) do
+		local r = entry(c[1].."_"..d[1], "{.GPR,.MSA_VEC,.IMM5,.NONE}", "{.GPR_AT_6,.WS,.MSA_ELM_IDX,.NONE}", "MSA",
+			function(v) return string.format("%s.%s $%d,$w%d[%d]", c[2], d[2], v[1], v[2], v[3]) end, {31,31,d[3]})
 		if r then sections[#sections+1]=r end
 	end
 end