diff --git a/core/rexcode/isa/arm32/decoder.odin b/core/rexcode/isa/arm32/decoder.odin index 893a9d70c..2adf60b19 100644 --- a/core/rexcode/isa/arm32/decoder.odin +++ b/core/rexcode/isa/arm32/decoder.odin @@ -171,7 +171,7 @@ find_and_decode :: proc(word: u32, mode: Mode, ilen: u32, inst: ^Instruction, in // LDM/STM carry the writeback in bit 21; nothing else in the operand // model records it, and without it the two forms print identically. for k in 0 ..< len(e.enc) { - if e.enc[k] == .A32_REG_LIST { + if e.enc[k] == .A32_REG_LIST || e.enc[k] == .RN_A32_WB || e.enc[k] == .IMPL_SP { inst.writeback = (word >> 21) & 1 != 0 break } @@ -455,6 +455,13 @@ unpack_operand :: proc(word: u32, enc: Operand_Encoding, ot: Operand_Type) -> Op // Only cmode 1111 expands to a float; the rest are bit patterns. if cmode == 0b1111 { return op_float_imm(v) } return op_hex_imm(v) + case .DBG_OPTION: return op_imm(i64(word & 0xF)) + case .MRS_SPEC_REG: return op_reg(Register(REG_SREG | u16(((word >> 22) & 1) * 2))) + case .VFP_SPEC_REG: return op_reg(Register(REG_FPSC | u16((word >> 16) & 0xF))) + case .SETEND_ENDIAN: return op_reg(Register(REG_ENDIAN | u16((word >> 9) & 1))) + case .IMPL_SP: return op_reg(SP) + case .MODE_IMM5: return op_imm(i64(word & 0x1F)) + case .RN_A32_WB: return op_reg(Register(REG_GPR | u16((word >> 16) & 0xF))) case .VM_S_PLUS1: // The second of a consecutive pair; only the first is encoded. return op_reg(Register(REG_SPR | u16(((word & 0xF) << 1 | ((word >> 5) & 1)) + 1))) diff --git a/core/rexcode/isa/arm32/encoder.odin b/core/rexcode/isa/arm32/encoder.odin index f05dc5e1d..bd9083589 100644 --- a/core/rexcode/isa/arm32/encoder.odin +++ b/core/rexcode/isa/arm32/encoder.odin @@ -312,7 +312,7 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op return true case .IMM, .IMM_MOD, .IMM_T32_MOD, .IMM12, .IMM5, .IMM5_W, .IMM4, .IMM4_SAT, .IMM8, .IMM3, .IMM_HINT, .IMM_BARRIER, - .IMM_ENDIAN, .IMM_IFLAGS, .IMM_BANKED, .IMM_SYSM, + .IMM_IFLAGS, .IMM_BANKED, .IMM_SYSM, .IMM_COPROC, .IMM_COPROC_OP, .NEON_IMM, .IMM16_LO_HI: // A modified immediate reaches an immediate slot as an expanded bit // pattern or a float, so all three kinds are the same slot's shape. @@ -328,8 +328,12 @@ operand_matches_inline :: #force_inline proc "contextless" (op: ^Operand, ot: Op return op.kind == .MEMORY || op.kind == .RELATIVE case .COPROC_REG, .COPROC_NUM: return op.kind == .REGISTER || op.kind == .IMMEDIATE + case .IMM_ENDIAN: + return op.kind == .REGISTER case .PSR_FIELD: - return op.kind == .IMMEDIATE + // APSR, SPSR and the endian tokens are named registers in the syntax + // even where no field encodes them. + return op.kind == .IMMEDIATE || op.kind == .REGISTER case .VPR, .QPR_MVE: return op.kind == .REGISTER && is_qpr(op.reg) case .QPR_MVE_LIST: @@ -497,6 +501,13 @@ pack_operand_inline :: #force_inline proc( return (u32(reg_hw(op.reg)) & 0x7) << 17 case .VM_Q_MVE: return (u32(reg_hw(op.reg)) & 0x7) << 1 + case .DBG_OPTION: return u32(op.immediate) & 0xF + case .MRS_SPEC_REG: return 0 // the R bit is a fixed bit of the form + case .VFP_SPEC_REG: return (u32(reg_hw(op.reg)) & 0xF) << 16 + case .SETEND_ENDIAN: return (u32(reg_hw(op.reg)) & 1) << 9 + case .IMPL_SP: return 0 + case .MODE_IMM5: return u32(op.immediate) & 0x1F + case .RN_A32_WB: return (u32(reg_hw(op.reg)) & 0xF) << 16 case .VM_S_PLUS1: return 0 // only the first of the pair is encoded case .NEON_LANE_VN_32: @@ -953,7 +964,7 @@ neon_lane_shape :: #force_inline proc "contextless" (e: Operand_Encoding) -> (sh @(private="file", require_results) writeback_matches :: #force_inline proc "contextless" (inst: ^Instruction, f: ^Encoding) -> bool { for e in f.enc { - if e == .A32_REG_LIST { + if e == .A32_REG_LIST || e == .RN_A32_WB || e == .IMPL_SP { return ((f.bits >> 21) & 1 != 0) == inst.writeback } } diff --git a/core/rexcode/isa/arm32/encoding_types.odin b/core/rexcode/isa/arm32/encoding_types.odin index be4e83b7c..e332ac458 100644 --- a/core/rexcode/isa/arm32/encoding_types.odin +++ b/core/rexcode/isa/arm32/encoding_types.odin @@ -326,6 +326,13 @@ Operand_Encoding :: enum u8 { VM_Q_MVE, VFP_IMM8, VM_S_PLUS1, // the second S register of a consecutive pair + DBG_OPTION, // DBG's option, bits 3:0 -- not the wider hint field + MRS_SPEC_REG, // APSR or SPSR, by the R bit + VFP_SPEC_REG, // VMRS/VMSR system register, bits 19:16 + SETEND_ENDIAN, // LE or BE, by the E bit + IMPL_SP, // an SP the syntax names but no field encodes + MODE_IMM5, // processor mode, bits 4:0 (SRS) + RN_A32_WB, // base register whose writeback rides in bit 21 NEON_LANE_VN_32, // Vn:N with the 32-bit lane index in bit 21 // VFP immediate (VMOV.F32/F64 #imm) NEON_IMM8_ABCDEFGH, // bits 18-16 (abc) + bits 3-0 (defgh) NEON_CMODE, // bits 11-8 (cmode for VMOV/VMVN immediate) diff --git a/core/rexcode/isa/arm32/mnemonic_builders.odin b/core/rexcode/isa/arm32/mnemonic_builders.odin index 87763c9aa..44cb6d7a1 100644 --- a/core/rexcode/isa/arm32/mnemonic_builders.odin +++ b/core/rexcode/isa/arm32/mnemonic_builders.odin @@ -620,10 +620,22 @@ inst_swp_r_r_r :: #force_inline proc "contextless" (dst: Register, s emit_swp_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swp_r_r_r(dst, src, src2)) } inst_swpb_r_r_r :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .SWPB, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_swpb_r_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_swpb_r_r_r(dst, src, src2)) } -inst_rfe_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFE, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_rfe_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfe_r(dst)) } -inst_srs_imm :: #force_inline proc "contextless" (imm: i64) -> Instruction { return Instruction{mnemonic = .SRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), {}, {}, {}}} } -emit_srs_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64) { append(instructions, inst_srs_imm(imm)) } +inst_rfeda_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFEDA, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_rfeda_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfeda_r(dst)) } +inst_rfedb_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFEDB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_rfedb_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfedb_r(dst)) } +inst_rfeia_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFEIA, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_rfeia_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfeia_r(dst)) } +inst_rfeib_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .RFEIB, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } +emit_rfeib_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_rfeib_r(dst)) } +inst_srsda_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSDA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_srsda_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_srsda_r_imm(dst, imm)) } +inst_srsdb_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSDB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_srsdb_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_srsdb_r_imm(dst, imm)) } +inst_srsia_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSIA, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_srsia_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_srsia_r_imm(dst, imm)) } +inst_srsib_r_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .SRSIB, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_srsib_r_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_srsib_r_imm(dst, imm)) } inst_cdp_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } emit_cdp_cpn_cpop_crd_crd :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64, src: Register, src2: Register) { append(instructions, inst_cdp_cpn_cpop_crd_crd(dst, imm, src, src2)) } inst_cdp2_cpn_cpop_crd_crd :: #force_inline proc "contextless" (dst: Register, imm: i64, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .CDP2, operand_count = 4, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), op_reg(src), op_reg(src2)}} } @@ -742,10 +754,10 @@ emit_vmov_r_r_s_s :: #force_inline proc(instructions: ^[dynamic]Instruc emit_vmov_r_dlane :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, lane: u8) { append(instructions, inst_vmov_r_dlane(dst, src, lane)) } emit_vmov_qlane_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register) { append(instructions, inst_vmov_qlane_r(dst, lane, src)) } emit_vmov_qlane_qlane_r_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, lane: u8, src: Register, lane2: u8, src2: Register, src3: Register) { append(instructions, inst_vmov_qlane_qlane_r_r(dst, lane, src, lane2, src2, src3)) } -inst_vmrs_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vmrs_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmrs_r(dst)) } -inst_vmsr_r :: #force_inline proc "contextless" (dst: Register) -> Instruction { return Instruction{mnemonic = .VMSR, operand_count = 1, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), {}, {}, {}}} } -emit_vmsr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register) { append(instructions, inst_vmsr_r(dst)) } +inst_vmrs_r_psr :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VMRS, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } +emit_vmrs_r_psr :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vmrs_r_psr(dst, imm)) } +inst_vmsr_psr_r :: #force_inline proc "contextless" (imm: i64, src: Register) -> Instruction { return Instruction{mnemonic = .VMSR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_imm(imm), op_reg(src), {}, {}}} } +emit_vmsr_psr_r :: #force_inline proc(instructions: ^[dynamic]Instruction, imm: i64, src: Register) { append(instructions, inst_vmsr_psr_r(imm, src)) } inst_vldr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VLDR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } emit_vldr_s_mem :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Memory) { append(instructions, inst_vldr_s_mem(dst, src)) } inst_vstr_s_mem :: #force_inline proc "contextless" (dst: Register, src: Memory) -> Instruction { return Instruction{mnemonic = .VSTR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_mem(src), {}, {}}} } @@ -846,9 +858,13 @@ inst_vabdl_q_d_d :: #force_inline proc "contextless" (dst: Register, s emit_vabdl_q_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vabdl_q_d_d(dst, src, src2)) } inst_vand_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VAND, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vand_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vand_d_d_d(dst, src, src2)) } +inst_vbic_d_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VBIC, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } inst_vbic_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VBIC, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vbic_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vbic_d_imm(dst, imm)) } emit_vbic_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vbic_d_d_d(dst, src, src2)) } +inst_vorr_d_imm :: #force_inline proc "contextless" (dst: Register, imm: i64) -> Instruction { return Instruction{mnemonic = .VORR, operand_count = 2, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_imm(imm), {}, {}}} } inst_vorr_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORR, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } +emit_vorr_d_imm :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, imm: i64) { append(instructions, inst_vorr_d_imm(dst, imm)) } emit_vorr_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorr_d_d_d(dst, src, src2)) } inst_vorn_d_d_d :: #force_inline proc "contextless" (dst: Register, src: Register, src2: Register) -> Instruction { return Instruction{mnemonic = .VORN, operand_count = 3, mode = .A32, cond = 14, length = 4, ops = {op_reg(dst), op_reg(src), op_reg(src2), {}}} } emit_vorn_d_d_d :: #force_inline proc(instructions: ^[dynamic]Instruction, dst: Register, src: Register, src2: Register) { append(instructions, inst_vorn_d_d_d(dst, src, src2)) } @@ -1885,10 +1901,22 @@ inst_swp :: inst_swp_r_r_r emit_swp :: emit_swp_r_r_r inst_swpb :: inst_swpb_r_r_r emit_swpb :: emit_swpb_r_r_r -inst_rfe :: inst_rfe_r -emit_rfe :: emit_rfe_r -inst_srs :: inst_srs_imm -emit_srs :: emit_srs_imm +inst_rfeda :: inst_rfeda_r +emit_rfeda :: emit_rfeda_r +inst_rfedb :: inst_rfedb_r +emit_rfedb :: emit_rfedb_r +inst_rfeia :: inst_rfeia_r +emit_rfeia :: emit_rfeia_r +inst_rfeib :: inst_rfeib_r +emit_rfeib :: emit_rfeib_r +inst_srsda :: inst_srsda_r_imm +emit_srsda :: emit_srsda_r_imm +inst_srsdb :: inst_srsdb_r_imm +emit_srsdb :: emit_srsdb_r_imm +inst_srsia :: inst_srsia_r_imm +emit_srsia :: emit_srsia_r_imm +inst_srsib :: inst_srsib_r_imm +emit_srsib :: emit_srsib_r_imm inst_cdp :: inst_cdp_cpn_cpop_crd_crd emit_cdp :: emit_cdp_cpn_cpop_crd_crd inst_cdp2 :: inst_cdp2_cpn_cpop_crd_crd @@ -1983,10 +2011,10 @@ inst_vcvtr :: inst_vcvtr_s_s emit_vcvtr :: emit_vcvtr_s_s inst_vmov :: proc{ inst_vmov_s_s, inst_vmov_s_imm8, inst_vmov_r_r_d, inst_vmov_r_r_s_s, inst_vmov_r_dlane, inst_vmov_qlane_r, inst_vmov_qlane_qlane_r_r } emit_vmov :: proc{ emit_vmov_s_s, emit_vmov_s_imm8, emit_vmov_r_r_d, emit_vmov_r_r_s_s, emit_vmov_r_dlane, emit_vmov_qlane_r, emit_vmov_qlane_qlane_r_r } -inst_vmrs :: inst_vmrs_r -emit_vmrs :: emit_vmrs_r -inst_vmsr :: inst_vmsr_r -emit_vmsr :: emit_vmsr_r +inst_vmrs :: inst_vmrs_r_psr +emit_vmrs :: emit_vmrs_r_psr +inst_vmsr :: inst_vmsr_psr_r +emit_vmsr :: emit_vmsr_psr_r inst_vldr :: inst_vldr_s_mem emit_vldr :: emit_vldr_s_mem inst_vstr :: inst_vstr_s_mem @@ -2067,10 +2095,10 @@ inst_vabdl :: inst_vabdl_q_d_d emit_vabdl :: emit_vabdl_q_d_d inst_vand :: inst_vand_d_d_d emit_vand :: emit_vand_d_d_d -inst_vbic :: inst_vbic_d_d_d -emit_vbic :: emit_vbic_d_d_d -inst_vorr :: inst_vorr_d_d_d -emit_vorr :: emit_vorr_d_d_d +inst_vbic :: proc{ inst_vbic_d_imm, inst_vbic_d_d_d } +emit_vbic :: proc{ emit_vbic_d_imm, emit_vbic_d_d_d } +inst_vorr :: proc{ inst_vorr_d_imm, inst_vorr_d_d_d } +emit_vorr :: proc{ emit_vorr_d_imm, emit_vorr_d_d_d } inst_vorn :: inst_vorn_d_d_d emit_vorn :: emit_vorn_d_d_d inst_veor :: inst_veor_d_d_d diff --git a/core/rexcode/isa/arm32/mnemonics.odin b/core/rexcode/isa/arm32/mnemonics.odin index 5494705f4..617124fa3 100644 --- a/core/rexcode/isa/arm32/mnemonics.odin +++ b/core/rexcode/isa/arm32/mnemonics.odin @@ -207,8 +207,9 @@ Mnemonic :: enum u16 { // ------------------------------------------------------------------------- // ARMv6 / Return-from-Exception // ------------------------------------------------------------------------- - RFE, // return from exception - SRS, // store return state + // The addressing mode is part of the name, as it is for LDM and STM. + RFEDA, RFEDB, RFEIA, RFEIB, // return from exception + SRSDA, SRSDB, SRSIA, SRSIB, // store return state // ------------------------------------------------------------------------- // Coprocessor (legacy CP-space; many subsumed by VFP/NEON) diff --git a/core/rexcode/isa/arm32/operands.odin b/core/rexcode/isa/arm32/operands.odin index 0a68f1bf1..3e9f77471 100644 --- a/core/rexcode/isa/arm32/operands.odin +++ b/core/rexcode/isa/arm32/operands.odin @@ -67,8 +67,9 @@ Index_Mode :: enum u8 { // multiplied by four in every Instruction. Field syntax and composite // literals are unchanged, so this is invisible to callers. // -// A Register's raw value never exceeds REG_QPR|31 = 0x401F, so 15 bits hold -// one losslessly (index uses Register(0), not a high sentinel, for "absent"). +// A memory base or index is always a GPR, whose raw value never exceeds +// REG_GPR|15 = 0x100F, so 15 bits hold one losslessly (index uses +// Register(0), not a high sentinel, for "absent"). // `disp` gets 19 bits (+/-262,143) against a worst case of 4,095 -- the imm12 // of an A32 load -- so there is ~64x headroom. Memory :: bit_field u64 { @@ -115,14 +116,16 @@ Operand :: struct #packed { // op.shift_type, op.shift_amt and op.lane still read and write // exactly as they did when these were separate fields. using _: bit_field u32 { - reg: Register | 15, + // Sixteen bits, not fifteen: the class nibble reaches 0x9000 for + // the endian tokens and 0x8000 for the coprocessor registers, + // and both were silently truncating. + reg: Register | 16, shift_type: Shift_Type | 4, // GPR_SHIFTED; .LSL/0 when plain shift_amt: u8 | 6, // 0..32, or the Rs index for RSR lane: u8 | 5, // SIMD lane for DPR_ELEM / QPR_ELEM // Whether `lane` means anything. Lane 0 is a real index -- `d0[0]` // is not `d0` -- so it cannot be spelled by lane == 0. has_lane: bool | 1, - // 1 bit spare }, mem: Memory, immediate: i64, diff --git a/core/rexcode/isa/arm32/printer.odin b/core/rexcode/isa/arm32/printer.odin index 23d679f89..ff21c8506 100644 --- a/core/rexcode/isa/arm32/printer.odin +++ b/core/rexcode/isa/arm32/printer.odin @@ -501,6 +501,8 @@ write_register :: proc(sb: ^strings.Builder, r: Register, uppercase: bool = fals } case REG_COPROC: fmt.sbprintf(sb, "c%d", hw) + case REG_ENDIAN: + strings.write_string(sb, hw == 0 ? "le" : "be") case: fmt.sbprintf(sb, "?%d", hw) } diff --git a/core/rexcode/isa/arm32/registers.odin b/core/rexcode/isa/arm32/registers.odin index 9bdb102c4..a366e7162 100644 --- a/core/rexcode/isa/arm32/registers.odin +++ b/core/rexcode/isa/arm32/registers.odin @@ -35,6 +35,9 @@ REG_SREG :: u16(0x5000) REG_FPSC :: u16(0x6000) REG_BANKED :: u16(0x7000) REG_COPROC :: u16(0x8000) +// SETEND names its argument `le` or `be`. That is a bare token in the syntax, +// which is what the special-register classes above already model. +REG_ENDIAN :: u16(0x9000) REG_CLASS_MASK :: u16(0xF000) REG_HW_MASK :: u16(0x0FFF) @@ -160,6 +163,9 @@ SPSR :: Register(REG_SREG | 2) // values rather than expanding the Register set. // FPSCR / FPSID and friends +LE :: Register(REG_ENDIAN | 0) +BE :: Register(REG_ENDIAN | 1) + FPSID :: Register(REG_FPSC | 0) FPSCR :: Register(REG_FPSC | 1) MVFR2 :: Register(REG_FPSC | 5) diff --git a/core/rexcode/isa/arm32/tablegen/encoding_table.odin b/core/rexcode/isa/arm32/tablegen/encoding_table.odin index a5447e1e7..19efb4f2a 100644 --- a/core/rexcode/isa/arm32/tablegen/encoding_table.odin +++ b/core/rexcode/isa/arm32/tablegen/encoding_table.odin @@ -832,7 +832,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // MSR / MRS (status reg access) .MRS = { - {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD, .NONE, .NONE, .NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {}}, + {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD, .MRS_SPEC_REG, .NONE, .NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {}}, // T32 MRS: high=11110011 1110 1111 low=10 0 0 Rd 0000 0000 {.MRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RD_T32, .NONE, .NONE, .NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, @@ -849,7 +849,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .CPS = { {.CPS, {.IMM_IFLAGS, .NONE, .NONE, .NONE}, {.CPS_IFLAGS, .NONE, .NONE, .NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {cond_in_28=false}, {}} }, // SETEND (deprecated in ARMv8): 1111 0001 0000 0001 0000 000E 0000 0000 - .SETEND = { {.SETEND, {.IMM_ENDIAN, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {cond_in_28=false, deprecated=true}, {}} }, + .SETEND = { {.SETEND, {.IMM_ENDIAN, .NONE, .NONE, .NONE}, {.SETEND_ENDIAN, .NONE, .NONE, .NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {cond_in_28=false, deprecated=true}, {}} }, // SETPAN (ARMv8.1): A32 = 1111 0001 0001 0000 0000 0000 imm1 0000 0000 → bit 9 = imm // T16: 1011 0110 0001 0 imm1 000 → bit 3 = imm @@ -887,7 +887,7 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.SEV, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF3AF8004, 0xFFFFFFFF, .V6T2, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .SEVL = { {.SEVL, {.NONE, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}, {}} }, - .DBG = { {.DBG, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {}} }, + .DBG = { {.DBG, {.IMM_HINT, .NONE, .NONE, .NONE}, {.DBG_OPTION, .NONE, .NONE, .NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {}} }, .HINT = { {.HINT, {.IMM_HINT, .NONE, .NONE, .NONE}, {.HINT_FIELD, .NONE, .NONE, .NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {}} }, // Memory barriers (ARMv7): 1111 0101 0111 1111 1111 0000 type imm4 @@ -1154,13 +1154,39 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ .SWPB = { {.SWPB, {.GPR, .GPR, .GPR, .NONE}, {.RT_A32, .RM_A32, .RN_A32, .NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {}} }, // RFE / SRS (return-from-exception / store return state) - .RFE = { - // 1111 100 P U 0 W 1 Rn 0000 1010 0000 0000 - {.RFE, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32, .NONE, .NONE, .NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {cond_in_28=false}, {}}, + // 1111 100 P U 0 W 1 Rn 0000 1010 0000 0000 + .RFEDA = { + {.RFEDA, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF8100A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + {.RFEDA, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF8300A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, }, - .SRS = { - // 1111 100 P U 1 W 0 1101 0000 0101 000 mode4 - {.SRS, {.IMM, .NONE, .NONE, .NONE}, {.NONE, .NONE, .NONE, .NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {cond_in_28=false}, {}}, + .RFEDB = { + {.RFEDB, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF9100A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + {.RFEDB, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF9300A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + }, + .RFEIA = { + {.RFEIA, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF8900A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + {.RFEIA, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF8B00A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + }, + .RFEIB = { + {.RFEIB, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF9900A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + {.RFEIB, {.GPR, .NONE, .NONE, .NONE}, {.RN_A32_WB, .NONE, .NONE, .NONE}, 0xF9B00A00, 0xFFF0FFFF, .V6, .A32, {cond_in_28=false}, {}}, + }, + // 1111 100 P U 1 W 0 1101 0000 0101 000 mode4 + .SRSDA = { + {.SRSDA, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF84D0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + {.SRSDA, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF86D0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + }, + .SRSDB = { + {.SRSDB, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF94D0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + {.SRSDB, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF96D0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + }, + .SRSIA = { + {.SRSIA, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF8CD0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + {.SRSIA, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF8ED0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + }, + .SRSIB = { + {.SRSIB, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF9CD0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, + {.SRSIB, {.GPR, .IMM, .NONE, .NONE}, {.IMPL_SP, .MODE_IMM5, .NONE, .NONE}, 0xF9ED0500, 0xFFFFFFE0, .V6, .A32, {cond_in_28=false}, {}}, }, // ========================================================================= @@ -1605,8 +1631,8 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ // VMRS / VMSR (access FPSCR + friends as GPR) // VMRS: cond 1110 1111 0001 Rt 1010 0001 0000 (Rt=PC means transfer to APSR.NZCV) - .VMRS = { {.VMRS, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {}} }, - .VMSR = { {.VMSR, {.GPR, .NONE, .NONE, .NONE}, {.RT_A32, .NONE, .NONE, .NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {}} }, + .VMRS = { {.VMRS, {.GPR, .PSR_FIELD, .NONE, .NONE}, {.RT_A32, .VFP_SPEC_REG, .NONE, .NONE}, 0x0EF10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {}} }, + .VMSR = { {.VMSR, {.PSR_FIELD, .GPR, .NONE, .NONE}, {.VFP_SPEC_REG, .RT_A32, .NONE, .NONE}, 0x0EE10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {}} }, // VLDR / VSTR (single / double): cond 1101 U D 0 1 Rn Vd 101 sz imm8 .VLDR = { @@ -1803,12 +1829,36 @@ ENCODING_TABLE := #partial [Mnemonic][]Encoding{ {.VAND, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VBIC = { + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800130, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800170, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800330, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800370, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800530, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800570, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800730, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800770, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800930, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800970, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VBIC, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800B30, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VBIC, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800B70, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, // VBIC D: 1111 0010 0100 Vn Vd 0001 N 0 M 1 Vm {.VBIC, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, {.VBIC, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, }, .VORR = { + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800110, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800150, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800310, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800350, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800510, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800550, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800710, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800750, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I32, .NONE}}, + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800910, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800950, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VORR, {.DPR, .IMM, .NONE, .NONE}, {.VD_D, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800B10, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, + {.VORR, {.QPR, .IMM, .NONE, .NONE}, {.VD_Q, .NEON_IMM8_ABCDEFGH, .NONE, .NONE}, 0xF2800B50, 0xFEB80FF0, .NEON, .A32, {cond_in_28=false}, {.I16, .NONE}}, {.VORR, {.DPR, .DPR, .DPR, .NONE}, {.VD_D, .VN_D, .VM_D, .NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {cond_in_28=false}, {}}, {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {cond_in_28=false}, {}}, {.VORR, {.QPR, .QPR, .QPR, .NONE}, {.VD_Q, .VN_Q, .VM_Q, .NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true, cond_in_28=false}, {}}, diff --git a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin index c29cc3c20..ad30716ed 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/decode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -DECODE_ENTRIES := [1663]lib.Decode_Entry{ +DECODE_ENTRIES := [1701]lib.Decode_Entry{ { .MUL, {.GPR,.GPR,.GPR,.NONE}, {.RN_A32,.RM_A32,.RS_A32,.NONE}, 0x00000090, 0x0FE000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000010, 0x0FE00090, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -65,8 +65,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .SMLAL, {.GPR,.GPR,.GPR,.GPR}, {.RDLO_A32,.RDHI_A32,.RM_A32,.RS_A32}, 0x00F00090, 0x0FF000F0, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSC, {.GPR,.GPR,.GPR_RSR,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00010, 0x0FF00090, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSC, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00F00000, 0x0FF00010, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} }, - { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.SETEND_ENDIAN,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} }, + { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.MRS_SPEC_REG,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {.NONE,.NONE} }, { .CPS, {.IMM_IFLAGS,.NONE,.NONE,.NONE}, {.CPS_IFLAGS,.NONE,.NONE,.NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {}, {.NONE,.NONE} }, { .HLT, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE1000070, 0xFFF000F0, .V8, .A32, {}, {.NONE,.NONE} }, { .SWP, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} }, @@ -186,8 +186,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000840, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000950, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000D50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000940, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000C50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000040, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VHSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000240, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, @@ -230,8 +230,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCEQ, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000E00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000310, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000300, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000600, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000610, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A00, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2000A10, 0xFFB00F10, .NEON, .A32, {}, {.S8,.NONE} }, @@ -244,8 +244,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100350, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100340, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF2100550, 0xFFB11F51, .NEON, .A32, {}, {.S16,.NONE} }, - { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100D40, 0xFFB00F50, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMUL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100950, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100940, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100040, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -267,8 +267,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100650, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2100510, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .SHA1P, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, - { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100800, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, + { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100D00, 0xFFB00F10, .NEON_HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100910, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100900, 0xFFB00F10, .NEON, .A32, {}, {.I16,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100000, 0xFFB00F10, .NEON, .A32, {}, {.S16,.NONE} }, @@ -314,8 +314,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200310, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200300, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMIN, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200650, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VRSQRTS, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200F50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF2200510, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .SHA1M, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, @@ -337,8 +337,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCGE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200310, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VCGT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200300, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200600, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200F00, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200610, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPMAX, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A00, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPMIN, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200A10, 0xFFB00F10, .NEON, .A32, {}, {.S32,.NONE} }, { .VPADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200B10, 0xFFB00F10, .NEON, .A32, {}, {.I32,.NONE} }, @@ -367,43 +367,67 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .SUB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02500000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02600000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .RSB, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02700000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800850, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E50, 0xFEB80FF0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E70, 0xFEB80FF0, .NEON, .A32, {}, {.I64,.NONE} }, { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F50, 0xFEB80FF0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800050, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800100, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBW, {.QPR,.QPR,.DPR,.NONE}, {.VD_Q,.VN_Q,.VM_D,.NONE}, 0xF2800300, 0xFFB11F50, .NEON, .A32, {}, {.S8,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800570, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800130, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800370, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800730, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800930, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800170, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B70, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800970, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800330, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B30, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800770, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800530, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800950, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800110, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B50, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800350, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800910, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800150, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B10, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800310, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800510, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800550, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800750, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800710, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOVL, {.QPR,.DPR,.NONE,.NONE}, {.VD_Q,.VM_D,.NONE,.NONE}, 0xF2880A10, 0xFFB80FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800210, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800610, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800010, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A10, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E30, 0xFEB80FB0, .NEON, .A32, {}, {.I64,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800410, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800810, 0xFEB80FB0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800F10, 0xFEB80FB0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800E10, 0xFEB80FB0, .NEON, .A32, {}, {.I8,.NONE} }, + { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOV, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C10, 0xFEB80FB0, .NEON, .A32, {}, {.I32,.NONE} }, { .VADDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800000, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VSUBL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800200, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800500, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VABDL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800700, 0xFFB01F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800870, 0xFEB80FD0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800070, 0xFEB80FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800E00, 0xFFB00F50, .NEON, .A32, {}, {.P8,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800C00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800800, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2800A00, 0xFFB00F50, .NEON, .A32, {}, {.S8,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800A30, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800430, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800230, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800830, 0xFEB80F90, .NEON, .A32, {}, {.I16,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800D30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800030, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800C30, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMVN, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800630, 0xFEB80F90, .NEON, .A32, {}, {.I32,.NONE} }, { .VQSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800910, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VQRSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800950, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VSHRN, {.DPR,.QPR,.IMM,.NONE}, {.VD_D,.VM_Q,.NEON_SHIFT_IMM6,.NONE}, 0xF2800810, 0xFE800FD0, .NEON, .A32, {}, {.I16,.NONE} }, @@ -438,8 +462,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900C00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900240, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900800, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900640, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900A00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2900D00, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900B40, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF2900340, 0xFFB00F50, .NEON, .A32, {}, {.S16,.NONE} }, @@ -461,18 +485,18 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMUL, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00040, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00A40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00C00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00800, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00240, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00640, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00A00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00B40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00D00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00340, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00900, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00740, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQDMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF2A00B00, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00C40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQRDMULH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR32,.NONE}, 0xF2A00D40, 0xFFB00F50, .NEON, .A32, {}, {.S32,.NONE} }, { .VQRDMLAH, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF2A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, @@ -502,11 +526,11 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VABD, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000740, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VEOR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000850, 0xFFB00F50, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000350, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000340, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, - { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, + { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000310, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000300, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .VACGE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, @@ -518,8 +542,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3000510, 0xFFB00F50, .NEON, .A32, {}, {.U8,.NONE} }, { .SHA256H, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3000C40, 0xFFB00F50, .CRYPTO, .A32, {}, {.SZ32,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000800, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, - { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000D10, 0xFFB00F10, .NEON, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000910, 0xFFB00F10, .NEON, .A32, {}, {.P8,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000900, 0xFFB00F10, .NEON, .A32, {}, {.I8,.NONE} }, { .VHADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000000, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, { .VHSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF3000200, 0xFFB00F10, .NEON, .A32, {}, {.U8,.NONE} }, @@ -580,11 +604,11 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .ESB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F010, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, { .CSDB, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F014, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, - { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, + { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.DBG_OPTION,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, { .VCLE, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200350, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200340, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E40, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200E50, 0xFFB11F51, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VM_Q,.VN_Q,.NONE}, 0xF3200550, 0xFFB11F51, .NEON, .A32, {}, {.U32,.NONE} }, { .VSUB, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200840, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, @@ -597,8 +621,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCEQ, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200850, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VCGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E40, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLE, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200310, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200300, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VCLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E00, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACGT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF3200E50, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VACLT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200E10, 0xFFB00F50, .NEON, .A32, {}, {.F32,.NONE} }, { .VQRSHL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VM_D,.VN_D,.NONE}, 0xF3200510, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, @@ -652,12 +676,12 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMUL, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900840, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLA, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900040, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900440, 0xFFB00F50, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900C00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900A40, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900800, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900240, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3900A00, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_16,.NONE}, 0xF3900640, 0xFFB00F50, .NEON, .A32, {}, {.U16,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900E40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_16,.NONE}, 0xF3900F40, 0xFFB00F50, .V8, .A32, {}, {.S16,.NONE} }, { .ORR, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x03900000, 0x0FF00000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -675,128 +699,128 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMLS, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00440, 0xFFB00F50, .NEON, .A32, {}, {.I32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00A40, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMULL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00C00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLAL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00240, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, - { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLAL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00800, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VMLSL, {.QPR,.DPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00640, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, + { .VMLSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xF3A00A00, 0xFFB00F50, .NEON, .A32, {}, {.U32,.NONE} }, { .VQRDMLAH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00E40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .VQRDMLSH, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xF3A00F40, 0xFFB00F50, .V8, .A32, {}, {.S32,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03A00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90700, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90740, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B10340, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10300, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B50340, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90300, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50300, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VABS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B90340, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B50380, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B10380, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90380, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B103C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B503C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B903C0, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B90780, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VNEG, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B907C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VCVT, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60600, 0xFFBF0FD0, .BF16, .A32, {}, {.F16,.F32} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0200, 0xFFBF0FD0, .NEON, .A32, {}, {.I64,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U64,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60200, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20200, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B202C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U16,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0280, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, - { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60280, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA02C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U64,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B602C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VQMOVN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20280, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B20240, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3B60240, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, + { .VQMOVUN, {.DPR,.QPR,.NONE,.NONE}, {.VD_D,.VM_Q,.NONE,.NONE}, 0xF3BA0240, 0xFFBF0FD0, .NEON, .A32, {}, {.S64,.NONE} }, { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00280, 0xFFBF0FD0, .NEON, .A32, {}, {.U8,.NONE} }, { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00200, 0xFFBF0FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B40200, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, - { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VPADDL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80200, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0500, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRECPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0400, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0440, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, + { .VRECPE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB0540, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB05C0, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, { .VRSQRTE, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3BB04C0, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0480, 0xFFBF0FD0, .NEON, .A32, {}, {.U32,.NONE} }, - { .VRSQRTE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3BB0580, 0xFFBF0FD0, .NEON, .A32, {}, {.F32,.NONE} }, + { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHLL_8,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHLL_32,.NONE}, 0xF3BA0300, 0xFFBF0FD0, .NEON, .A32, {}, {.I32,.NONE} }, { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHLL_16,.NONE}, 0xF3B60300, 0xFFBF0FD0, .NEON, .A32, {}, {.I16,.NONE} }, - { .VSHLL, {.QPR,.DPR,.IMM,.NONE}, {.VD_Q,.VM_D,.NEON_SHLL_8,.NONE}, 0xF3B20300, 0xFFBF0FD0, .NEON, .A32, {}, {.I8,.NONE} }, - { .VCLS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B80400, 0xFFBF0FD0, .NEON, .A32, {}, {.S32,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B40440, 0xFFBF0FD0, .NEON, .A32, {}, {.S16,.NONE} }, - { .VCLS, {.QPR,.QPR,.NONE,.NONE}, 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0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VMVN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00580, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B002C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, - { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, - { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, + { .VPADDL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00240, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00680, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, + { .VPADAL, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00600, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B006C0, 0xFFB30FD0, .NEON, .A32, {}, {.U8,.NONE} }, - { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VPADAL, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00640, 0xFFB30FD0, .NEON, .A32, {}, {.S8,.NONE} }, { .VCNT, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00540, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VCNT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00500, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV16, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00140, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VREV16, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xF3B00100, 0xFFB30FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VSWP, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B20040, 0xFFB30FD0, .NEON, .A32, {}, {.NONE,.NONE} }, @@ -805,14 +829,14 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .AESD, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00340, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, { .AESMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B00380, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, { .AESIMC, {.QPR,.QPR,.NONE,.NONE}, {.VD_Q,.VM_Q,.NONE,.NONE}, 0xF3B003C0, 0xFFB30FD0, .CRYPTO, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00900, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00800, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBL, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A00, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_1,.VM_D,.NONE}, 0xF3B00840, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_3,.VM_D,.NONE}, 0xF3B00A40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_4,.VM_D,.NONE}, 0xF3B00B40, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VTBX, {.DPR,.DPR_LIST,.DPR,.NONE}, {.VD_D,.NEON_VN_TABLE_2,.VM_D,.NONE}, 0xF3B00940, 0xFFB00F70, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VDUP, {.DPR,.DPR_ELEM,.NONE,.NONE}, {.VD_D,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C00, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.DPR_ELEM,.NONE,.NONE}, {.VD_Q,.NEON_VM_SCALAR_32,.NONE,.NONE}, 0xF3B00C40, 0xFFB00FD0, .NEON, .A32, {}, {.NONE,.NONE} }, { .MOV, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03B00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, @@ -821,29 +845,29 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03E00000, 0x0FEF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .MVN, {.GPR,.IMM_MOD,.NONE,.NONE}, {.RD,.A32_IMM_MOD,.NONE,.NONE}, 0x03F00000, 0x0FFF0000, .BASE, .A32, {sets_flags=true}, {.NONE,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4000A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF400070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF400080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF400090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF400050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VST3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF400040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF400010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VST4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF400000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04000000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDR, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04100000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_1,.RN_A32,.NONE,.NONE}, 0xF420070F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420060F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF4200A0F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD1, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420020F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2,.RN_A32,.NONE,.NONE}, 0xF420080F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420030F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD2, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_2X,.RN_A32,.NONE,.NONE}, 0xF420090F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3,.RN_A32,.NONE,.NONE}, 0xF420040F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD3, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_3X,.RN_A32,.NONE,.NONE}, 0xF420050F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4,.RN_A32,.NONE,.NONE}, 0xF420000F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, + { .VLD4, {.DPR_LIST,.MEM,.NONE,.NONE}, {.NEON_D_LIST_4X,.RN_A32,.NONE,.NONE}, 0xF420010F, 0xFFF00F0F, .NEON, .A32, {}, {.SZ8,.NONE} }, { .STRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04200000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDRT, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04300000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STRB, {.GPR,.MEM,.NONE,.NONE}, {.RT_A32,.MEM_POST_INDEX,.NONE,.NONE}, 0x04400000, 0x0F700000, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -985,19 +1009,33 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .UBFX, {.GPR,.GPR,.IMM5,.IMM5_W}, {.RD,.RM_A32,.BFI_LSB,.BFX_WIDTH}, 0x07E00050, 0x0FE00070, .V6T2, .A32, {}, {.NONE,.NONE} }, { .UDF, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE7F000F0, 0xFFF000F0, .BASE, .A32, {}, {.NONE,.NONE} }, { .STMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEDA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .LDMDA, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, - { .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEDA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8300A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF84D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF86D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08800000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEIA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8900A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08900000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .STM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08A00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEIA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8B00A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .POP, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x08BD0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, { .LDM, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x08B00000, 0x0FF00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .SRSIA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF8CD0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSIA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF8ED0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, { .STMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09000000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEDB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9100A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .LDMDB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09100000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .PUSH, {.GPR_LIST,.NONE,.NONE,.NONE}, {.A32_REG_LIST,.NONE,.NONE,.NONE}, 0x092D0000, 0x0FFF0000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEDB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9300A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF94D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF96D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, { .STMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09800000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEIB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9900A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, { .LDMIB, {.GPR,.GPR_LIST,.NONE,.NONE}, {.RN_A32,.A32_REG_LIST,.NONE,.NONE}, 0x09900000, 0x0FD00000, .BASE, .A32, {}, {.NONE,.NONE} }, + { .RFEIB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9B00A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSIB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF9CD0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSIB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF9ED0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, { .BLX, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0xFA000000, 0xFE000000, .V5T, .A32, {branch=true, writes_pc=true}, {.NONE,.NONE} }, { .B, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0A000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, { .BL, {.REL24,.NONE,.NONE,.NONE}, {.BRANCH_24,.NONE,.NONE,.NONE}, 0x0B000000, 0x0F000000, .BASE, .A32, {branch=true, cond_branch=true, writes_pc=true}, {.NONE,.NONE} }, @@ -1019,8 +1057,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VCMLA, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_4_HI}, 0xFC200840, 0xFC800F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCMLA, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_4_HI}, 0xFC200800, 0xFC800F10, .FCMA, .A32, {}, {.F16,.NONE} }, { .VFMA, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFC300850, 0xFFB00F50, .BF16, .A32, {}, {.BF16,.NONE} }, - { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.VM_S_PLUS1,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR,.GPR,.GPR,.NONE}, {.VM_D,.RT_A32,.RT2_A32,.NONE}, 0x0C400B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMOV, {.SPR,.SPR,.GPR,.GPR}, {.VM_S,.VM_S_PLUS1,.RT_A32,.RT2_A32}, 0x0C400A10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .MCRR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0xFC400000, 0xFFF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .MCRR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C400000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.GPR,.DPR,.NONE}, {.RT_A32,.RT2_A32,.VM_D,.NONE}, 0x0C500B10, 0x0FF00FD0, .VFPV2, .A32, {}, {.NONE,.NONE} }, @@ -1029,8 +1067,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .MRRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.GPR}, {.COPROC_NUM_FIELD,.COPROC_OPC_MCRR,.RT_A32,.RT2_A32}, 0x0C500000, 0x0FF00000, .V6, .A32, {}, {.NONE,.NONE} }, { .VCADD, {.QPR,.QPR,.QPR,.IMM}, {.VD_Q,.VN_Q,.VM_Q,.NEON_ROT_2}, 0xFC800840, 0xFE800F50, .FCMA, .A32, {}, {.F16,.NONE} }, { .VCADD, {.DPR,.DPR,.DPR,.IMM}, {.VD_D,.VN_D,.VM_D,.NEON_ROT_2}, 0xFC800800, 0xFE800F10, .FCMA, .A32, {}, {.F16,.NONE} }, - { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C800A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C800B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.DPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_D_LIST,.NONE,.NONE}, 0x0C900B00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDM, {.GPR,.SPR_LIST,.NONE,.NONE}, {.RN_A32,.VFP_S_LIST,.NONE,.NONE}, 0x0C900A00, 0x0F900F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VFMSL, {.QPR,.DPR,.DPR,.NONE}, {.VD_Q,.VN_D,.VM_D,.NONE}, 0xFCA00850, 0xFFB00F50, .FHM, .A32, {}, {.F16,.NONE} }, @@ -1039,14 +1077,14 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VUSDOT, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xFCA00D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VFMSL, {.DPR,.SPR,.SPR,.NONE}, {.VD_D,.VN_S,.VM_S,.NONE}, 0xFCA00810, 0xFFB00F10, .FHM, .A32, {}, {.F16,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFCA00D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, - { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPOP, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0CBD0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPOP, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0CBD0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VSTR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VSTR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D000A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, - { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VPUSH, {.DPR_LIST,.NONE,.NONE,.NONE}, {.VFP_D_LIST,.NONE,.NONE,.NONE}, 0x0D2D0B00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VPUSH, {.SPR_LIST,.NONE,.NONE,.NONE}, {.VFP_S_LIST,.NONE,.NONE,.NONE}, 0x0D2D0A00, 0x0FFF0F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.SPR,.GPR,.NONE,.NONE}, {.VN_S,.RT_A32,.NONE,.NONE}, 0x0E000A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, @@ -1056,20 +1094,20 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VSEL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE000A00, 0xFF800F50, .V8, .A32, {cond_in_21=true}, {.F32,.NONE} }, { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E000B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E000A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .MCR2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE000010, 0xFF100010, .V5T, .A32, {}, {.NONE,.NONE} }, { .CDP2, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0xFE000000, 0xFF000010, .V5T, .A32, {}, {.NONE,.NONE} }, { .MCR, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E000010, 0x0F100010, .BASE, .A32, {}, {.NONE,.NONE} }, { .CDP, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.SPR,.NONE,.NONE}, {.RT_A32,.VN_S,.NONE,.NONE}, 0x0E100A10, 0x0FF00F7F, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VMOV, {.GPR,.DPR_ELEM,.NONE,.NONE}, {.RT_A32,.NEON_LANE_VN_32,.NONE,.NONE}, 0x0E100B10, 0x0F100F1F, .NEON, .A32, {}, {.SZ32,.NONE} }, - { .VNMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNMLA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VNMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VNMLA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNMLS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E100A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNMLS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E100B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .MRC2, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0xFE100010, 0xFF100010, .V5T, .A32, {}, {.NONE,.NONE} }, { .MRC, {.COPROC_NUM,.IMM_COPROC_OP,.GPR,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.RT_A32,.COPROC_CRM_FIELD}, 0x0E100010, 0x0F100010, .BASE, .A32, {}, {.NONE,.NONE} }, { .VSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D40, 0xFFB00F50, .DOT, .A32, {}, {.S8,.NONE} }, @@ -1077,14 +1115,14 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D00, 0xFFB00F10, .DOT, .A32, {}, {.S8,.NONE} }, { .VUDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE200D10, 0xFFB00F10, .DOT, .A32, {}, {.U8,.NONE} }, { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VNMUL, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E200B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VNMUL, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E200A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VADD, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B00, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VADD, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VSUB, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E300B40, 0x0FB00B50, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSUB, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E300A40, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_8,.RT_A32,.NONE,.NONE}, 0x0E400B10, 0x0FD00F1F, .VFPV2, .A32, {}, {.SZ8,.NONE} }, @@ -1092,8 +1130,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VUSDOT, {.QPR,.QPR,.DPR_ELEM,.NONE}, {.VD_Q,.VN_Q,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D40, 0xFFB00F50, .V8, .A32, {}, {.S8,.NONE} }, { .VMAXNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A00, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, { .VMAXNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B00, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, - { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VMINNM, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0xFE800A40, 0xFFB00B50, .V8, .A32, {}, {.F32,.NONE} }, + { .VMINNM, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xFE800B40, 0xFFB00B50, .V8, .A32, {}, {.F64,.NONE} }, { .VUSDOT, {.DPR,.DPR,.DPR_ELEM,.NONE}, {.VD_D,.VN_D,.NEON_VM_SCALAR_32,.NONE}, 0xFE800D00, 0xFFB00F10, .V8, .A32, {}, {.S8,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VDIV, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0E800A00, 0x0FB00B50, .VFPV2, .A32, {}, {.F32,.NONE} }, @@ -1106,100 +1144,100 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VFNMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0E900B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00900, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00940, 0x0FB00F50, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, { .VFMA, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B00, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, - { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, + { .VFMA, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A00, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, { .VFMS, {.SPR,.SPR,.SPR,.NONE}, {.VD_S,.VN_S,.VM_S,.NONE}, 0x0EA00A40, 0x0FB00B50, .VFPV4, .A32, {}, {.F32,.NONE} }, - { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VFMS, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0x0EA00B40, 0x0FB00B50, .VFPV4, .A32, {}, {.F64,.NONE} }, { .VCMP, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50B40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMPE, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50A40, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50940, 0x0FBF0FFF, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCMPE, {.SPR,.IMM,.NONE,.NONE}, {.VD_S,.IMPL,.NONE,.NONE}, 0x0EB50AC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMPE, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.IMPL,.NONE,.NONE}, 0x0EB50BC0, 0x0FBF0FFF, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCVTA, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBC0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBC0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, - { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTN, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBD0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, + { .VCVTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBD0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBE0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VCVTP, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBE0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTM, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0xFEBF0B40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F64} }, { .VCVTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBF0A40, 0xFFBF0FD0, .V8, .A32, {}, {.U32,.F32} }, { .VRINTA, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB80B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTA, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB80A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTN, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEB90A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, - { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, + { .VRINTN, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEB90B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBA0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBA0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTM, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0xFEBB0B40, 0xFFBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTM, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0xFEBB0A40, 0xFFBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VABS, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VABS, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VNEG, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, - { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, - { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VNEG, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VSQRT, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB10BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB10AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VSQRT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB109C0, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40940, 0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.NONE} }, + { .VCMP, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, + { .VCMP, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VCMPE, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB40AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VCMPE, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB40BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F64} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S32} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBF0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U16,.F64} }, { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBB0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.U32} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBB0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.U16} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBF0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.U32,.F32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F32} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S16} }, - { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F64,.S32} }, { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0BC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBE0B40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S16,.F64} }, + { .VCVT, {.DPR,.DPR,.IMM,.NONE}, {.VD_D,.VM_D,.VFP_FBITS,.NONE}, 0x0EBA0B40, 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0x0FBF0FD0, .HALF_FP, .A32, {}, {.F16,.S32} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBA0A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.S16} }, + { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBE0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.S32,.F32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.U32} }, { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.S32} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, - { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, - { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, - { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB80A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.U32} }, - { .VCVT, {.SPR,.SPR,.IMM,.NONE}, {.VD_S,.VM_S,.VFP_FBITS,.NONE}, 0x0EBB0AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.U32} }, { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.S32} }, + { .VCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB70BC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.F64} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB70AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.F32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, + { .VCVT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0AC0, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, + { .VCVT, {.DPR,.SPR,.NONE,.NONE}, {.VD_D,.VM_S,.NONE,.NONE}, 0x0EB80B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.U32} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, { .VCVTB, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30A40, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, - { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB30AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F16,.F32} }, + { .VCVTT, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB20AC0, 0x0FBF0FD0, .VFPV3, .A32, {}, {.F32,.F16} }, + { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBD0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F32} }, { .VCVTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EBC0A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F32} }, - { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBD0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.S32,.F64} }, { .VCVTR, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EBC0B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.U32,.F64} }, { .VMOV, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB00B40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F64,.NONE} }, { .VMOV, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB00A40, 0x0FBF0FD0, .VFPV2, .A32, {}, {.F32,.NONE} }, { .VRINTR, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTR, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, - { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTZ, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB60AC0, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, + { .VRINTZ, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB60BC0, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VRINTX, {.SPR,.SPR,.NONE,.NONE}, {.VD_S,.VM_S,.NONE,.NONE}, 0x0EB70A40, 0x0FBF0FD0, .V8, .A32, {}, {.F32,.NONE} }, { .VRINTX, {.DPR,.DPR,.NONE,.NONE}, {.VD_D,.VM_D,.NONE,.NONE}, 0x0EB70B40, 0x0FBF0FD0, .V8, .A32, {}, {.F64,.NONE} }, { .VJCVT, {.SPR,.DPR,.NONE,.NONE}, {.VD_S,.VM_D,.NONE,.NONE}, 0x0EB90BC0, 0x0FBF0FD0, .V8, .A32, {}, {.S32,.F64} }, - { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, { .VMOV, {.SPR,.IMM8,.NONE,.NONE}, {.VD_S,.VFP_IMM8,.NONE,.NONE}, 0x0EB00A00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F32,.NONE} }, + { .VMOV, {.DPR,.IMM8,.NONE,.NONE}, {.VD_D,.VFP_IMM8,.NONE,.NONE}, 0x0EB00B00, 0x0FB00FF0, .VFPV3, .A32, {}, {.F64,.NONE} }, { .VDUP, {.DPR,.GPR,.NONE,.NONE}, {.VN_D,.RT_A32,.NONE,.NONE}, 0x0EC00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VMSR, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.VFP_SPEC_REG,.RT_A32,.NONE,.NONE}, 0x0EE10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VDUP, {.QPR,.GPR,.NONE,.NONE}, {.VN_Q,.RT_A32,.NONE,.NONE}, 0x0EE00B10, 0x0FF00FD0, .NEON, .A32, {}, {.SZ8,.NONE} }, - { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RT_A32,.VFP_SPEC_REG,.NONE,.NONE}, 0x0EF10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .SVC, {.IMM,.NONE,.NONE,.NONE}, {.A32_IMM24,.NONE,.NONE,.NONE}, 0x0F000000, 0x0F000000, .BASE, .A32, {}, {.NONE,.NONE} }, { .SG, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xE97FE97F, 0xFFFFFFFF, .V8M_SE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .TBB, {.GPR,.GPR,.NONE,.NONE}, {.RN_T32,.RM_T32,.NONE,.NONE}, 0xE8D0F000, 0xFFF0FFF0, .V6T2, .T32, {branch=true, writes_pc=true, thumb32=true}, {.NONE,.NONE} }, @@ -1256,10 +1294,10 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VMOV, {.QPR_ELEM,.QPR_ELEM,.GPR,.GPR}, {.VD_Q,.VD_Q,.RT_T32,.RT2_T32}, 0xEC000F00, 0xFF900F11, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VLDRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED901E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, { .VSTRB, {.QPR,.MEM,.NONE,.NONE}, {.VD_Q,.MEM_IMM12_OFFSET,.NONE,.NONE}, 0xED801E00, 0xFFB01F00, .MVE_INT, .T32, {thumb32=true}, {.SZ8,.NONE} }, - { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xEC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, - { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xEC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xEC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX2, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xEC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xEC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3, {.IMM_COPROC,.SPR,.SPR,.SPR}, {.CDE_COPROC_FIELD,.VD_S,.VN_S,.VM_S}, 0xEC800000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VADDLV, {.GPR,.GPR,.QPR,.NONE}, {.RD_T32,.RN_T32,.VM_Q,.NONE}, 0xEE890F00, 0xEFFF0FD1, .MVE_INT, .T32, {thumb32=true}, {.S32,.NONE} }, @@ -1539,8 +1577,8 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ { .VLDRW, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900F40, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U32,.NONE} }, { .VLDRD, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900FD0, 0xFEF00FF1, .MVE_INT, .T32, {thumb32=true}, {.U64,.NONE} }, { .VLDRB, {.QPR,.MEM,.QPR,.NONE}, {.VD_Q,.RN_T32,.VM_Q,.NONE}, 0xFC900E00, 0xFEF00FD1, .MVE_INT, .T32, {thumb32=true}, {.U8,.NONE} }, - { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX1A, {.IMM_COPROC,.DPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_D,.CDE_IMM_FIELD,.NONE}, 0xFC300000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, + { .VCX1A, {.IMM_COPROC,.SPR,.IMM,.NONE}, {.CDE_COPROC_FIELD,.VD_S,.CDE_IMM_FIELD,.NONE}, 0xFC200000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2A, {.IMM_COPROC,.SPR,.SPR,.IMM}, {.CDE_COPROC_FIELD,.VD_S,.VM_S,.CDE_IMM_FIELD}, 0xFC600000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX2A, {.IMM_COPROC,.DPR,.DPR,.IMM}, {.CDE_COPROC_FIELD,.VD_D,.VM_D,.CDE_IMM_FIELD}, 0xFC700000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, { .VCX3A, {.IMM_COPROC,.DPR,.DPR,.DPR}, {.CDE_COPROC_FIELD,.VD_D,.VN_D,.VM_D}, 0xFC900000, 0xFF300000, .CDE, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -1675,7 +1713,7 @@ DECODE_ENTRIES := [1663]lib.Decode_Entry{ } @(rodata) -DECODE_FORM_IDX := [1663]u16{ +DECODE_FORM_IDX := [1701]u16{ 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 2, 2, 2, 1, 2, 2, 2, 5, 4, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, 5, 4, 0, 2, 1, 1, @@ -1687,103 +1725,106 @@ DECODE_FORM_IDX := [1663]u16{ 1, 0, 0, 0, 5, 4, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 2, 1, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 0, 0, 0, 2, 1, 0, 0, 0, 5, 4, 1, 1, 1, 9, 14, - 8, 6, 10, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, + 8, 10, 6, 4, 3, 3, 1, 4, 4, 3, 3, 1, 3, 7, 3, 3, 0, 0, 9, 3, 3, 1, 4, 1, 1, 0, 0, 5, 13, 5, 9, 3, - 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 8, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 10, 4, 9, 7, 4, - 4, 5, 5, 2, 4, 4, 1, 4, 9, 4, 4, 2, 2, 11, 4, 4, - 2, 0, 3, 6, 6, 4, 1, 1, 1, 1, 0, 1, 1, 0, 1, 8, + 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 0, 0, 0, 8, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 4, 10, 9, 7, 4, + 4, 5, 5, 2, 4, 4, 13, 4, 9, 4, 4, 2, 2, 11, 4, 4, + 2, 0, 6, 3, 6, 4, 1, 1, 1, 1, 0, 1, 1, 12, 1, 8, 1, 1, 10, 1, 1, 1, 1, 1, 1, 3, 5, 5, 5, 11, 14, 10, - 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 1, 5, 5, 5, 4, 4, - 5, 5, 9, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, - 1, 2, 2, 0, 2, 2, 2, 2, 2, 8, 2, 2, 2, 0, 2, 0, + 8, 10, 4, 5, 5, 6, 6, 3, 5, 5, 13, 5, 5, 5, 4, 4, + 5, 9, 5, 1, 4, 0, 7, 13, 7, 5, 9, 3, 2, 2, 2, 2, + 1, 2, 2, 12, 2, 2, 2, 2, 8, 2, 2, 2, 2, 0, 2, 0, 7, 12, 4, 7, 7, 1, 11, 5, 6, 0, 8, 3, 3, 3, 0, 10, - 3, 3, 0, 3, 0, 3, 25, 22, 23, 24, 21, 0, 0, 0, 10, 20, - 15, 11, 18, 19, 17, 12, 13, 14, 16, 0, 0, 0, 0, 10, 11, 6, - 0, 0, 0, 6, 5, 8, 9, 3, 4, 2, 7, 0, 0, 0, 0, 0, - 1, 1, 1, 1, 1, 1, 5, 0, 0, 0, 0, 0, 0, 4, 0, 1, - 1, 1, 1, 1, 1, 1, 18, 12, 11, 7, 1, 6, 1, 1, 6, 0, - 2, 2, 0, 0, 2, 4, 4, 4, 4, 3, 2, 2, 2, 2, 2, 2, - 2, 19, 13, 12, 2, 8, 2, 7, 2, 7, 1, 3, 1, 3, 1, 3, - 6, 6, 5, 5, 0, 1, 0, 3, 0, 3, 0, 3, 7, 13, 7, 1, - 9, 9, 12, 14, 6, 7, 7, 9, 9, 7, 7, 1, 3, 7, 9, 7, - 6, 12, 6, 1, 0, 7, 7, 7, 3, 3, 8, 0, 5, 11, 13, 3, - 6, 6, 8, 8, 6, 6, 0, 0, 8, 6, 6, 0, 6, 6, 3, 4, - 3, 3, 6, 2, 2, 0, 9, 9, 11, 10, 4, 7, 2, 2, 2, 1, - 4, 11, 8, 8, 10, 0, 6, 3, 4, 0, 0, 0, 0, 1, 10, 4, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 11, 13, 11, - 1, 13, 11, 8, 3, 3, 3, 9, 1, 5, 9, 10, 12, 10, 1, 0, - 12, 0, 7, 5, 1, 1, 1, 8, 0, 2, 8, 0, 4, 0, 15, 12, - 1, 11, 14, 8, 0, 10, 0, 0, 0, 0, 3, 3, 3, 3, 3, 3, - 3, 3, 3, 3, 0, 0, 0, 4, 4, 5, 5, 4, 4, 4, 4, 4, - 20, 14, 13, 9, 4, 8, 4, 8, 4, 6, 6, 3, 5, 5, 7, 7, - 5, 5, 5, 5, 5, 21, 15, 14, 10, 5, 5, 9, 5, 9, 7, 7, - 0, 2, 5, 3, 4, 8, 6, 7, 9, 3, 6, 8, 2, 4, 7, 5, - 9, 10, 0, 1, 2, 5, 3, 1, 0, 4, 2, 2, 1, 0, 4, 0, - 2, 1, 0, 3, 1, 2, 3, 1, 0, 2, 3, 2, 1, 2, 4, 3, - 5, 0, 1, 2, 5, 3, 0, 1, 4, 1, 5, 0, 4, 2, 3, 3, - 1, 5, 4, 2, 0, 2, 3, 4, 3, 2, 4, 0, 0, 0, 11, 13, - 12, 10, 14, 15, 12, 13, 13, 12, 14, 15, 16, 14, 17, 15, 14, 15, - 16, 17, 2, 3, 1, 0, 0, 1, 1, 0, 0, 1, 3, 5, 0, 1, - 2, 3, 0, 1, 1, 0, 1, 0, 0, 0, 0, 0, 2, 3, 0, 1, - 3, 2, 1, 0, 2, 3, 3, 0, 3, 0, 3, 2, 3, 1, 0, 1, - 2, 0, 0, 1, 1, 0, 2, 2, 3, 0, 2, 1, 0, 2, 1, 1, - 0, 1, 0, 0, 0, 2, 0, 2, 0, 0, 6, 5, 4, 4, 5, 4, - 3, 3, 4, 3, 2, 2, 7, 5, 4, 4, 6, 4, 3, 3, 5, 3, - 2, 2, 4, 0, 0, 0, 0, 0, 1, 1, 0, 0, 1, 0, 0, 0, - 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 3, 3, 0, 3, 0, 3, 21, 22, 23, 25, 24, 0, 0, 5, 0, 3, + 6, 8, 1, 11, 9, 2, 10, 7, 4, 9, 0, 11, 3, 8, 1, 10, + 2, 4, 5, 7, 6, 0, 11, 13, 10, 15, 20, 12, 14, 19, 18, 17, + 16, 0, 0, 0, 0, 11, 10, 6, 0, 0, 0, 7, 4, 3, 6, 9, + 2, 8, 5, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 5, 0, + 0, 0, 0, 0, 0, 4, 0, 1, 1, 1, 1, 1, 1, 1, 18, 12, + 11, 7, 1, 6, 1, 6, 1, 0, 2, 2, 0, 0, 2, 4, 4, 4, + 4, 3, 2, 2, 2, 2, 2, 2, 2, 19, 13, 12, 8, 2, 2, 7, + 7, 2, 3, 1, 3, 1, 3, 1, 6, 6, 5, 5, 0, 1, 0, 3, + 0, 3, 0, 3, 7, 13, 7, 1, 9, 9, 12, 14, 6, 7, 7, 9, + 9, 7, 7, 1, 3, 9, 7, 7, 12, 6, 6, 1, 0, 7, 7, 7, + 3, 3, 8, 0, 5, 13, 11, 3, 6, 6, 8, 8, 6, 6, 0, 0, + 8, 6, 6, 0, 6, 6, 3, 4, 3, 3, 6, 2, 2, 0, 9, 9, + 11, 10, 4, 7, 2, 2, 2, 1, 4, 11, 8, 8, 10, 0, 6, 3, + 4, 0, 0, 0, 0, 1, 10, 4, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 11, 11, 13, 1, 13, 11, 8, 3, 3, 3, 9, + 1, 5, 9, 10, 10, 12, 1, 0, 12, 0, 7, 5, 1, 1, 1, 8, + 0, 2, 8, 0, 4, 0, 15, 12, 1, 11, 14, 8, 0, 10, 0, 0, + 0, 0, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 0, 0, 4, + 4, 5, 5, 4, 4, 4, 4, 4, 20, 14, 13, 4, 9, 4, 8, 4, + 8, 6, 6, 3, 5, 5, 7, 7, 5, 5, 5, 5, 5, 21, 15, 14, + 10, 5, 9, 5, 9, 5, 7, 7, 0, 8, 9, 5, 2, 6, 4, 3, + 7, 3, 2, 4, 5, 6, 7, 8, 9, 10, 2, 1, 0, 3, 2, 1, + 5, 4, 0, 0, 1, 2, 4, 0, 1, 2, 2, 0, 1, 3, 2, 3, + 1, 0, 1, 3, 2, 1, 2, 5, 3, 4, 0, 5, 3, 2, 4, 0, + 1, 2, 3, 1, 5, 4, 0, 0, 1, 3, 2, 4, 5, 2, 4, 3, + 2, 4, 3, 0, 0, 0, 12, 10, 11, 13, 14, 13, 12, 15, 14, 15, + 13, 12, 17, 14, 16, 15, 17, 15, 16, 14, 2, 3, 1, 0, 1, 0, + 0, 1, 1, 0, 5, 3, 2, 0, 3, 1, 1, 0, 1, 0, 1, 0, + 0, 0, 0, 0, 1, 0, 3, 2, 0, 2, 3, 1, 2, 3, 3, 0, + 3, 0, 3, 2, 1, 0, 3, 0, 2, 1, 1, 0, 1, 0, 2, 2, + 0, 2, 1, 3, 1, 0, 2, 0, 1, 0, 1, 0, 0, 2, 0, 2, + 0, 0, 6, 5, 4, 4, 5, 4, 3, 3, 4, 3, 2, 2, 7, 5, + 4, 4, 6, 4, 3, 3, 5, 3, 2, 2, 4, 0, 0, 0, 0, 0, + 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 3, 0, 3, 0, 0, 0, 0, 0, - 3, 0, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, - 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, - 0, 7, 9, 7, 0, 0, 6, 8, 0, 0, 1, 0, 1, 0, 1, 0, - 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 0, 1, 0, 1, 4, 32, - 31, 3, 2, 1, 0, 2, 2, 0, 1, 0, 1, 0, 0, 0, 0, 5, - 26, 0, 1, 1, 0, 0, 0, 3, 3, 2, 2, 2, 0, 1, 0, 1, - 2, 2, 0, 1, 1, 0, 30, 1, 3, 0, 1, 1, 0, 2, 2, 0, - 1, 2, 2, 1, 0, 0, 1, 2, 2, 0, 1, 1, 0, 5, 2, 3, - 3, 2, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 1, 0, 1, 0, - 1, 0, 0, 1, 1, 0, 2, 0, 1, 1, 0, 4, 0, 1, 34, 31, - 30, 32, 28, 26, 25, 27, 29, 33, 21, 19, 18, 20, 22, 15, 14, 16, - 12, 9, 11, 13, 17, 23, 5, 4, 6, 2, 0, 1, 3, 7, 24, 8, - 0, 1, 0, 1, 0, 1, 2, 3, 1, 0, 0, 1, 1, 0, 0, 1, - 0, 3, 2, 0, 0, 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, - 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, 3, 1, 1, 4, 4, 4, - 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, 10, 9, 8, 7, 8, 8, - 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 29, 0, 0, 0, - 1, 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, 0, 0, 0, 7, 28, 27, - 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 17, 17, 17, 6, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 16, 16, 11, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, 10, 10, 12, 12, 8, 4, - 6, 0, 0, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, 6, 4, 8, 9, 7, 0, - 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, 3, 1, 2, 2, 2, 2, - 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 2, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 2, 9, 8, - 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, 8, 7, 6, 6, 6, 6, - 5, 5, 2, 1, 2, 2, 1, 2, 5, 5, 5, 4, 1, 1, 2, 2, - 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 3, 0, 3, 0, 0, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 3, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, + 1, 1, 0, 1, 0, 1, 0, 0, 0, 0, 1, 0, 1, 0, 0, 0, + 1, 0, 1, 1, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, + 0, 0, 0, 0, 0, 1, 0, 7, 7, 9, 0, 0, 6, 8, 0, 0, + 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 0, 1, 0, 1, 0, + 0, 1, 1, 0, 4, 32, 31, 3, 2, 1, 0, 2, 2, 1, 0, 1, + 0, 0, 0, 0, 0, 5, 26, 1, 0, 0, 1, 0, 0, 3, 3, 2, + 2, 2, 1, 0, 1, 0, 2, 2, 1, 0, 1, 0, 30, 1, 3, 0, + 1, 0, 1, 2, 2, 0, 1, 2, 2, 1, 0, 0, 1, 2, 2, 1, + 0, 0, 1, 3, 2, 5, 2, 3, 1, 0, 1, 0, 0, 1, 1, 0, + 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 2, 4, + 0, 1, 0, 1, 32, 31, 33, 29, 27, 26, 28, 30, 34, 23, 21, 20, + 22, 24, 17, 16, 18, 14, 12, 11, 13, 15, 19, 25, 7, 5, 4, 6, + 8, 1, 0, 2, 3, 9, 0, 1, 1, 0, 2, 0, 1, 3, 1, 0, + 0, 1, 0, 1, 0, 1, 0, 2, 3, 0, 0, 1, 0, 0, 0, 0, + 0, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 2, 2, 1, 3, + 3, 1, 1, 4, 4, 4, 4, 4, 3, 5, 4, 7, 5, 11, 10, 8, + 10, 9, 8, 7, 8, 8, 8, 8, 1, 1, 1, 1, 0, 0, 0, 0, + 0, 0, 29, 0, 0, 1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 4, 0, + 0, 0, 0, 7, 28, 27, 2, 14, 14, 2, 0, 0, 0, 0, 0, 0, + 0, 17, 17, 17, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 16, 16, 11, 5, 5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15, 8, 8, 2, + 10, 10, 12, 12, 8, 4, 6, 0, 0, 2, 2, 2, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 3, + 6, 4, 8, 9, 7, 0, 0, 7, 8, 7, 6, 7, 7, 7, 7, 4, + 3, 1, 2, 2, 2, 2, 2, 1, 1, 1, 1, 1, 1, 0, 0, 0, + 0, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 0, 0, 0, 2, 9, 8, 7, 7, 7, 7, 6, 6, 1, 1, 1, 10, + 8, 7, 6, 6, 6, 6, 5, 5, 2, 1, 2, 2, 1, 2, 5, 5, + 5, 4, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, 1, 1, 0, 1, 1, 1, - 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, 0, 1, 0, 1, 1, 0, - 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, 0, 0, 11, 11, 0, 0, - 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, 0, 0, 0, 0, 0, 15, - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2, - 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, 6, 6, 6, 6, 3, 4, - 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, 1, 2, 0, 0, 9, 5, - 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, 5, 6, 5, 5, 5, 5, - 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, 0, 1, 1, 1, 1, 1, - 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, 2, 1, 1, 1, 2, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 3, + 1, 1, 0, 1, 1, 1, 1, 1, 1, 2, 1, 2, 2, 2, 2, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 1, 1, 1, 1, + 1, 0, 0, 1, 1, 0, 0, 0, 2, 2, 2, 2, 2, 2, 0, 0, + 0, 0, 11, 11, 0, 0, 0, 10, 10, 12, 2, 16, 6, 0, 0, 0, + 0, 0, 0, 0, 0, 15, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 2, 2, 2, 6, 6, 7, 7, 6, 3, 8, 8, + 6, 6, 6, 6, 3, 4, 3, 6, 6, 6, 3, 3, 3, 2, 0, 2, + 1, 2, 0, 0, 9, 5, 7, 4, 4, 4, 4, 4, 5, 4, 4, 4, + 5, 6, 5, 5, 5, 5, 6, 7, 0, 10, 1, 1, 1, 1, 9, 11, + 0, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 0, 1, 2, + 2, 1, 1, 1, 2, } @(rodata) -DECODE_BUCKET_LIST := [5363]u16{ +DECODE_BUCKET_LIST := [5451]u16{ 0, 1, 2, 3, 0, 4, 1, 5, 2, 6, 7, 8, 9, 6, 10, 7, 11, 8, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 16, 17, 23, 24, 25, 26, 27, 28, 29, 30, 31, 25, 26, 32, 33, 34, 35, 32, 36, @@ -1822,304 +1863,309 @@ DECODE_BUCKET_LIST := [5363]u16{ 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 329, 328, 330, 331, 332, 333, 334, 356, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 357, 356, 358, 361, 360, 362, 359, 363, 364, - 365, 370, 375, 376, 369, 374, 371, 368, 372, 367, 373, 366, 377, 378, 379, 380, - 381, 382, 384, 383, 385, 386, 392, 388, 387, 393, 391, 390, 389, 394, 395, 396, - 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, - 413, 414, 415, 416, 417, 418, 419, 420, 421, 422, 423, 424, 426, 425, 428, 427, - 429, 430, 431, 432, 433, 434, 436, 435, 437, 438, 439, 440, 395, 396, 397, 398, - 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 441, - 414, 442, 443, 444, 445, 446, 447, 448, 449, 450, 451, 453, 452, 454, 455, 456, - 457, 458, 459, 461, 460, 462, 463, 464, 465, 466, 467, 395, 396, 397, 398, 399, - 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 468, 395, - 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, - 412, 413, 469, 470, 471, 468, 362, 360, 361, 359, 358, 363, 364, 365, 376, 375, - 374, 372, 371, 370, 373, 368, 369, 367, 366, 377, 378, 379, 380, 382, 381, 383, - 384, 385, 386, 394, 393, 392, 391, 389, 390, 388, 387, 395, 396, 397, 398, 399, - 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 472, 415, - 416, 417, 418, 419, 420, 421, 422, 423, 424, 425, 426, 427, 428, 429, 430, 431, - 432, 434, 433, 435, 436, 437, 438, 439, 440, 395, 396, 397, 398, 399, 400, 401, - 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 473, 472, 442, 443, - 444, 445, 446, 447, 448, 449, 450, 451, 452, 453, 454, 455, 457, 456, 458, 459, - 460, 461, 462, 463, 464, 465, 466, 467, 395, 396, 397, 398, 399, 400, 401, 402, - 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 474, 395, 396, 397, 398, - 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 469, - 470, 475, 474, 477, 476, 478, 479, 480, 481, 483, 482, 484, 485, 486, 487, 488, - 489, 490, 491, 492, 493, 494, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, - 505, 506, 507, 508, 510, 509, 511, 512, 513, 514, 515, 516, 517, 518, 519, 521, - 520, 522, 523, 524, 525, 526, 527, 528, 529, 530, 531, 532, 533, 534, 535, 536, - 537, 538, 539, 540, 541, 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, - 553, 554, 555, 556, 557, 558, 559, 560, 561, 562, 563, 564, 565, 566, 567, 568, - 569, 570, 571, 572, 573, 575, 574, 576, 577, 578, 579, 580, 581, 582, 583, 584, - 585, 586, 587, 588, 589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, - 601, 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 614, 477, 476, - 478, 479, 480, 481, 483, 482, 484, 485, 486, 487, 488, 489, 490, 491, 492, 494, - 493, 495, 496, 497, 498, 499, 500, 501, 502, 503, 504, 505, 506, 507, 508, 510, - 509, 511, 512, 513, 514, 515, 516, 517, 518, 519, 520, 521, 522, 523, 524, 525, - 527, 526, 528, 529, 530, 531, 532, 615, 534, 535, 536, 537, 538, 539, 540, 541, - 542, 543, 544, 545, 546, 547, 548, 549, 550, 551, 552, 553, 554, 555, 556, 557, - 558, 559, 616, 573, 574, 575, 576, 577, 578, 579, 580, 581, 582, 583, 584, 585, - 586, 587, 589, 588, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600, 601, - 602, 603, 604, 605, 606, 607, 608, 609, 610, 611, 612, 613, 617, 361, 362, 360, - 359, 358, 618, 619, 620, 376, 373, 374, 375, 372, 371, 370, 368, 367, 369, 366, - 621, 622, 623, 624, 382, 381, 625, 626, 627, 394, 393, 390, 391, 392, 389, 388, - 387, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, - 408, 409, 410, 411, 412, 413, 630, 631, 632, 633, 634, 635, 636, 637, 638, 639, - 640, 641, 642, 643, 644, 645, 646, 647, 648, 649, 650, 628, 629, 395, 396, 397, - 398, 399, 400, 401, 402, 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, - 651, 630, 652, 653, 654, 655, 656, 657, 658, 659, 660, 661, 662, 663, 665, 664, - 667, 666, 668, 669, 670, 671, 628, 629, 395, 396, 397, 398, 399, 400, 401, 402, - 403, 404, 405, 406, 407, 408, 409, 410, 411, 412, 413, 672, 675, 674, 673, 680, - 679, 678, 677, 676, 683, 687, 688, 682, 685, 684, 686, 681, 689, 692, 690, 691, - 695, 698, 693, 697, 696, 694, 701, 700, 699, 704, 702, 703, 705, 709, 708, 706, - 707, 711, 713, 710, 712, 714, 716, 715, 718, 717, 720, 722, 721, 719, 724, 728, - 725, 727, 726, 723, 733, 730, 729, 731, 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1424, + 1425, 1418, 1423, 1424, 1425, 1399, 1423, 1424, 1425, 1400, 1423, 1424, 1425, 1405, 1414, 1423, + 1424, 1425, 1414, 1423, 1424, 1425, 1414, 1423, 1424, 1425, 1414, 1424, 1423, 1425, 1404, 1454, + 1423, 1424, 1425, 1423, 1424, 1425, 1399, 1423, 1424, 1425, 1400, 1423, 1424, 1425, 1405, 1414, + 1424, 1423, 1425, 1414, 1424, 1423, 1425, 1414, 1423, 1424, 1425, 1414, 1423, 1424, 1425, 1404, + 1455, 1423, 1424, 1425, 1423, 1424, 1425, 1399, 1423, 1424, 1425, 1400, 1423, 1424, 1425, 1405, + 1452, 1414, 1423, 1424, 1425, 1414, 1424, 1423, 1425, 1446, 1452, 1414, 1423, 1424, 1425, 1414, + 1423, 1424, 1425, 1404, 1450, 1424, 1423, 1425, 1424, 1423, 1425, 1399, 1448, 1449, 1423, 1424, + 1425, 1400, 1424, 1423, 1425, 1445, 1405, 1453, 1414, 1424, 1423, 1425, 1414, 1424, 1423, 1425, + 1426, 1427, 1428, 1429, 1430, 1432, 1433, 1434, 1435, 1437, 1438, 1439, 1440, 1447, 1453, 1414, + 1424, 1423, 1425, 1431, 1436, 1442, 1443, 1444, 1414, 1423, 1424, 1425, 1404, 1451, 1424, 1423, + 1425, 1424, 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1423, 1424, 1425, 1414, 1424, 1423, 1425, 1414, 1423, 1424, 1425, + 1414, 1423, 1424, 1425, 1404, 1454, 1424, 1423, 1425, 1423, 1424, 1425, 1399, 1423, 1424, 1425, + 1400, 1423, 1424, 1425, 1405, 1414, 1424, 1423, 1425, 1414, 1424, 1423, 1425, 1414, 1424, 1423, + 1425, 1414, 1424, 1423, 1425, 1404, 1455, 1423, 1424, 1425, 1423, 1424, 1425, 1399, 1424, 1423, + 1425, 1400, 1423, 1424, 1425, 1405, 1414, 1424, 1423, 1425, 1414, 1424, 1423, 1425, 1414, 1424, + 1423, 1425, 1414, 1424, 1423, 1425, 1404, 1423, 1424, 1425, 1424, 1423, 1425, 1399, 1424, 1423, + 1425, 1400, 1423, 1424, 1425, 1456, 1457, 1458, 1405, 1414, 1424, 1423, 1425, 1414, 1424, 1423, + 1425, 1414, 1424, 1423, 1425, 1414, 1424, 1423, 1425, 1404, 1424, 1423, 1425, 1424, 1423, 1425, + 1399, 1424, 1423, 1425, 1400, 1459, 1423, 1424, 1425, 1463, 1462, 1465, 1464, 1469, 1461, 1460, + 1471, 1475, 1468, 1474, 1477, 1476, 1473, 1471, 1472, 1466, 1467, 1470, 1478, 1479, 1482, 1486, + 1541, 1485, 1544, 1481, 1487, 1540, 1484, 1543, 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1604, 1346, 1606, 1349, 1350, + 1353, 1354, 1355, 1356, 1357, 1358, 1367, 1368, 1369, 1370, 1619, 1313, 1314, 1329, 1330, 1331, + 1596, 1343, 1601, 1602, 1603, 1604, 1346, 1606, 1349, 1350, 1353, 1354, 1355, 1356, 1357, 1358, + 1367, 1368, 1369, 1370, 1619, 1575, 1584, 1585, 1313, 1314, 1315, 1329, 1330, 1331, 1332, 1596, + 1341, 1343, 1601, 1602, 1603, 1604, 1346, 1606, 1349, 1350, 1353, 1354, 1355, 1356, 1357, 1358, + 1367, 1368, 1369, 1370, 1619, 1590, 1313, 1314, 1329, 1330, 1331, 1596, 1342, 1343, 1601, 1602, + 1603, 1604, 1346, 1606, 1349, 1350, 1353, 1354, 1355, 1356, 1357, 1358, 1367, 1368, 1369, 1370, + 1615, 1619, 1313, 1314, 1329, 1330, 1331, 1596, 1343, 1601, 1602, 1603, 1604, 1346, 1606, 1349, + 1350, 1353, 1354, 1355, 1356, 1357, 1358, 1367, 1368, 1369, 1370, 1615, 1619, 1313, 1314, 1329, + 1330, 1331, 1596, 1343, 1601, 1602, 1603, 1604, 1346, 1606, 1349, 1350, 1353, 1354, 1355, 1356, + 1357, 1358, 1367, 1368, 1369, 1370, 1615, 1619, 1574, 1584, 1585, 1313, 1314, 1315, 1329, 1330, + 1331, 1332, 1596, 1341, 1343, 1601, 1602, 1603, 1604, 1346, 1606, 1349, 1350, 1353, 1354, 1355, + 1356, 1357, 1358, 1367, 1368, 1369, 1370, 1615, 1619, 1291, 1292, 1324, 1325, 1326, 1327, 1335, + 1336, 1337, 1338, 1597, 1598, 1599, 1600, 1606, 1351, 1352, 1359, 1360, 1361, 1362, 1363, 1364, + 1365, 1366, 1611, 1612, 1613, 1614, 1388, 1617, 1620, 1597, 1598, 1599, 1600, 1606, 1351, 1352, + 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1617, 1620, 1597, 1598, 1599, 1600, 1606, 1351, + 1352, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1617, 1620, 1582, 1583, 1322, 1323, 1333, + 1334, 1339, 1340, 1597, 1598, 1599, 1600, 1606, 1351, 1352, 1359, 1360, 1361, 1362, 1363, 1364, + 1365, 1366, 1607, 1608, 1609, 1610, 1617, 1620, 1324, 1325, 1326, 1327, 1335, 1336, 1337, 1338, + 1597, 1598, 1599, 1600, 1606, 1351, 1352, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1611, + 1612, 1613, 1614, 1388, 1616, 1618, 1620, 1597, 1598, 1599, 1600, 1606, 1351, 1352, 1359, 1360, + 1361, 1362, 1363, 1364, 1365, 1366, 1616, 1618, 1620, 1293, 1294, 1295, 1296, 1305, 1306, 1307, + 1308, 1597, 1598, 1599, 1600, 1606, 1351, 1352, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, + 1616, 1618, 1620, 1582, 1583, 1303, 1304, 1322, 1323, 1333, 1334, 1339, 1340, 1597, 1598, 1599, + 1600, 1606, 1351, 1352, 1359, 1360, 1361, 1362, 1363, 1364, 1365, 1366, 1607, 1608, 1609, 1610, + 1616, 1618, 1620, 1594, 1595, 1596, 1344, 1605, 1347, 1606, 1371, 1372, 1373, 1374, 1375, 1376, + 1377, 1378, 1379, 1380, 1381, 1382, 1595, 1596, 1344, 1605, 1347, 1606, 1371, 1372, 1373, 1374, + 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1596, 1605, 1345, 1348, 1606, 1371, 1372, 1373, + 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1596, 1345, 1605, 1348, 1606, 1371, 1372, + 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1594, 1595, 1596, 1344, 1605, 1347, + 1606, 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1595, 1596, 1344, + 1605, 1347, 1606, 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, 1596, + 1605, 1345, 1348, 1606, 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, 1382, + 1596, 1605, 1345, 1348, 1606, 1371, 1372, 1373, 1374, 1375, 1376, 1377, 1378, 1379, 1380, 1381, + 1382, 1606, 1385, 1386, 1387, 1606, 1385, 1386, 1387, 1606, 1385, 1386, 1387, 1576, 1577, 1578, + 1579, 1580, 1581, 1586, 1587, 1588, 1589, 1591, 1592, 1593, 1606, 1385, 1386, 1387, 1606, 1385, + 1386, 1387, 1606, 1385, 1386, 1387, 1606, 1385, 1386, 1387, 1576, 1577, 1578, 1579, 1580, 1581, + 1586, 1587, 1588, 1589, 1591, 1592, 1593, 1606, 1385, 1386, 1387, } DECODE_INDEX_A32 := [256]lib.Decode_Index{ @@ -2163,607 +2209,599 @@ DECODE_INDEX_A32 := [256]lib.Decode_Index{ 0x25 = { 477, 51}, 0x26 = { 528, 54}, 0x27 = { 582, 19}, - 0x28 = { 601, 57}, - 0x29 = { 658, 47}, - 0x2A = { 705, 46}, - 0x2B = { 751, 23}, - 0x2C = { 774, 57}, - 0x2D = { 831, 47}, - 0x2E = { 878, 46}, - 0x2F = { 924, 23}, - 0x30 = { 947, 58}, - 0x31 = { 1005, 27}, - 0x32 = { 1032, 45}, - 0x33 = { 1077, 9}, - 0x34 = { 1086, 58}, - 0x35 = { 1144, 27}, - 0x36 = { 1171, 33}, - 0x37 = { 1204, 9}, - 0x38 = { 1213, 58}, - 0x39 = { 1271, 43}, - 0x3A = { 1314, 42}, - 0x3B = { 1356, 156}, - 0x3C = { 1512, 58}, - 0x3D = { 1570, 43}, - 0x3E = { 1613, 42}, - 0x3F = { 1655, 156}, - 0x40 = { 1811, 12}, - 0x41 = { 1823, 1}, - 0x42 = { 1824, 12}, - 0x43 = { 1836, 1}, - 0x44 = { 1837, 1}, - 0x45 = { 1838, 2}, - 0x46 = { 1840, 1}, - 0x47 = { 1841, 1}, - 0x48 = { 1842, 13}, - 0x49 = { 1855, 1}, - 0x4A = { 1856, 17}, - 0x4B = { 1873, 1}, - 0x4C = { 1874, 13}, - 0x4D = { 1887, 2}, - 0x4E = { 1889, 17}, - 0x4F = { 1906, 1}, - 0x50 = { 1907, 1}, - 0x51 = { 1908, 1}, - 0x52 = { 1909, 1}, - 0x53 = { 1910, 1}, - 0x54 = { 1911, 1}, - 0x55 = { 1912, 1}, - 0x56 = { 1913, 1}, - 0x57 = { 1914, 6}, - 0x58 = { 1920, 1}, - 0x59 = { 1921, 1}, - 0x5A = { 1922, 1}, - 0x5B = { 1923, 1}, - 0x5C = { 1924, 1}, - 0x5D = { 1925, 3}, - 0x5E = { 1928, 1}, - 0x5F = { 1929, 1}, - 0x61 = { 1930, 6}, - 0x62 = { 1936, 6}, - 0x63 = { 1942, 6}, - 0x65 = { 1948, 6}, - 0x66 = { 1954, 6}, - 0x67 = { 1960, 6}, - 0x68 = { 1966, 5}, - 0x6A = { 1971, 4}, - 0x6B = { 1975, 5}, - 0x6C = { 1980, 2}, - 0x6E = { 1982, 4}, - 0x6F = { 1986, 5}, - 0x70 = { 1991, 9}, - 0x71 = { 2000, 2}, - 0x73 = { 2002, 1}, - 0x74 = { 2003, 5}, - 0x75 = { 2008, 7}, - 0x78 = { 2015, 3}, - 0x79 = { 2018, 1}, - 0x7A = { 2019, 1}, - 0x7B = { 2020, 1}, - 0x7C = { 2021, 3}, - 0x7D = { 2024, 3}, - 0x7E = { 2027, 1}, - 0x7F = { 2028, 2}, - 0x80 = { 2030, 1}, - 0x81 = { 2031, 2}, - 0x82 = { 2033, 1}, - 0x83 = { 2034, 2}, - 0x84 = { 2036, 1}, - 0x85 = { 2037, 1}, - 0x86 = { 2038, 1}, - 0x87 = { 2039, 1}, - 0x88 = { 2040, 1}, - 0x89 = { 2041, 2}, - 0x8A = { 2043, 1}, - 0x8B = { 2044, 3}, - 0x8C = { 2047, 1}, - 0x8D = { 2048, 1}, - 0x8E = { 2049, 1}, - 0x8F = { 2050, 1}, - 0x90 = { 2051, 1}, - 0x91 = { 2052, 2}, - 0x92 = { 2054, 2}, - 0x93 = { 2056, 2}, - 0x94 = { 2058, 1}, - 0x95 = { 2059, 1}, - 0x96 = { 2060, 1}, - 0x97 = { 2061, 1}, - 0x98 = { 2062, 1}, - 0x99 = { 2063, 2}, - 0x9A = { 2065, 1}, - 0x9B = { 2066, 2}, - 0x9C = { 2068, 1}, - 0x9D = { 2069, 1}, - 0x9E = { 2070, 1}, - 0x9F = { 2071, 1}, - 0xA0 = { 2072, 2}, - 0xA1 = { 2074, 2}, - 0xA2 = { 2076, 2}, - 0xA3 = { 2078, 2}, - 0xA4 = { 2080, 2}, - 0xA5 = { 2082, 2}, - 0xA6 = { 2084, 2}, - 0xA7 = { 2086, 2}, - 0xA8 = { 2088, 2}, - 0xA9 = { 2090, 2}, - 0xAA = { 2092, 2}, - 0xAB = { 2094, 2}, - 0xAC = { 2096, 2}, - 0xAD = { 2098, 2}, - 0xAE = { 2100, 2}, - 0xAF = { 2102, 2}, - 0xB0 = { 2104, 2}, - 0xB1 = { 2106, 2}, - 0xB2 = { 2108, 2}, - 0xB3 = { 2110, 2}, - 0xB4 = { 2112, 2}, - 0xB5 = { 2114, 2}, - 0xB6 = { 2116, 2}, - 0xB7 = { 2118, 2}, - 0xB8 = { 2120, 2}, - 0xB9 = { 2122, 2}, - 0xBA = { 2124, 2}, - 0xBB = { 2126, 2}, - 0xBC = { 2128, 2}, - 0xBD = { 2130, 2}, - 0xBE = { 2132, 2}, - 0xBF = { 2134, 2}, - 0xC0 = { 2136, 7}, - 0xC1 = { 2143, 4}, - 0xC2 = { 2147, 12}, - 0xC3 = { 2159, 5}, - 0xC4 = { 2164, 11}, - 0xC5 = { 2175, 8}, - 0xC6 = { 2183, 12}, - 0xC7 = { 2195, 5}, - 0xC8 = { 2200, 6}, - 0xC9 = { 2206, 6}, - 0xCA = { 2212, 12}, - 0xCB = { 2224, 8}, - 0xCC = { 2232, 6}, - 0xCD = { 2238, 6}, - 0xCE = { 2244, 12}, - 0xCF = { 2256, 6}, - 0xD0 = { 2262, 4}, - 0xD1 = { 2266, 4}, - 0xD2 = { 2270, 4}, - 0xD3 = { 2274, 2}, - 0xD4 = { 2276, 4}, - 0xD5 = { 2280, 4}, - 0xD6 = { 2284, 2}, - 0xD7 = { 2286, 2}, - 0xD8 = { 2288, 4}, - 0xD9 = { 2292, 4}, - 0xDA = { 2296, 2}, - 0xDB = { 2298, 2}, - 0xDC = { 2300, 4}, - 0xDD = { 2304, 4}, - 0xDE = { 2308, 2}, - 0xDF = { 2310, 2}, - 0xE0 = { 2312, 19}, - 0xE1 = { 2331, 14}, - 0xE2 = { 2345, 19}, - 0xE3 = { 2364, 15}, - 0xE4 = { 2379, 17}, - 0xE5 = { 2396, 13}, - 0xE6 = { 2409, 18}, - 0xE7 = { 2427, 15}, - 0xE8 = { 2442, 14}, - 0xE9 = { 2456, 11}, - 0xEA = { 2467, 10}, - 0xEB = { 2477, 91}, - 0xEC = { 2568, 15}, - 0xED = { 2583, 11}, - 0xEE = { 2594, 12}, - 0xEF = { 2606, 92}, - 0xF0 = { 2698, 3}, - 0xF1 = { 2701, 3}, - 0xF2 = { 2704, 3}, - 0xF3 = { 2707, 3}, - 0xF4 = { 2710, 3}, - 0xF5 = { 2713, 3}, - 0xF6 = { 2716, 3}, - 0xF7 = { 2719, 3}, - 0xF8 = { 2722, 1}, - 0xF9 = { 2723, 1}, - 0xFA = { 2724, 1}, - 0xFB = { 2725, 1}, - 0xFC = { 2726, 1}, - 0xFD = { 2727, 1}, - 0xFE = { 2728, 1}, - 0xFF = { 2729, 1}, + 0x28 = { 601, 81}, + 0x29 = { 682, 47}, + 0x2A = { 729, 46}, + 0x2B = { 775, 23}, + 0x2C = { 798, 81}, + 0x2D = { 879, 47}, + 0x2E = { 926, 46}, + 0x2F = { 972, 23}, + 0x30 = { 995, 58}, + 0x31 = { 1053, 27}, + 0x32 = { 1080, 45}, + 0x33 = { 1125, 9}, + 0x34 = { 1134, 58}, + 0x35 = { 1192, 27}, + 0x36 = { 1219, 33}, + 0x37 = { 1252, 9}, + 0x38 = { 1261, 82}, + 0x39 = { 1343, 43}, + 0x3A = { 1386, 42}, + 0x3B = { 1428, 156}, + 0x3C = { 1584, 82}, + 0x3D = { 1666, 43}, + 0x3E = { 1709, 42}, + 0x3F = { 1751, 156}, + 0x40 = { 1907, 12}, + 0x41 = { 1919, 1}, + 0x42 = { 1920, 12}, + 0x43 = { 1932, 1}, + 0x44 = { 1933, 1}, + 0x45 = { 1934, 2}, + 0x46 = { 1936, 1}, + 0x47 = { 1937, 1}, + 0x48 = { 1938, 13}, + 0x49 = { 1951, 1}, + 0x4A = { 1952, 17}, + 0x4B = { 1969, 1}, + 0x4C = { 1970, 13}, + 0x4D = { 1983, 2}, + 0x4E = { 1985, 17}, + 0x4F = { 2002, 1}, + 0x50 = { 2003, 1}, + 0x51 = { 2004, 1}, + 0x52 = { 2005, 1}, + 0x53 = { 2006, 1}, + 0x54 = { 2007, 1}, + 0x55 = { 2008, 1}, + 0x56 = { 2009, 1}, + 0x57 = { 2010, 6}, + 0x58 = { 2016, 1}, + 0x59 = { 2017, 1}, + 0x5A = { 2018, 1}, + 0x5B = { 2019, 1}, + 0x5C = { 2020, 1}, + 0x5D = { 2021, 3}, + 0x5E = { 2024, 1}, + 0x5F = { 2025, 1}, + 0x61 = { 2026, 6}, + 0x62 = { 2032, 6}, + 0x63 = { 2038, 6}, + 0x65 = { 2044, 6}, + 0x66 = { 2050, 6}, + 0x67 = { 2056, 6}, + 0x68 = { 2062, 5}, + 0x6A = { 2067, 4}, + 0x6B = { 2071, 5}, + 0x6C = { 2076, 2}, + 0x6E = { 2078, 4}, + 0x6F = { 2082, 5}, + 0x70 = { 2087, 9}, + 0x71 = { 2096, 2}, + 0x73 = { 2098, 1}, + 0x74 = { 2099, 5}, + 0x75 = { 2104, 7}, + 0x78 = { 2111, 3}, + 0x79 = { 2114, 1}, + 0x7A = { 2115, 1}, + 0x7B = { 2116, 1}, + 0x7C = { 2117, 3}, + 0x7D = { 2120, 3}, + 0x7E = { 2123, 1}, + 0x7F = { 2124, 2}, + 0x80 = { 2126, 1}, + 0x81 = { 2127, 2}, + 0x82 = { 2129, 1}, + 0x83 = { 2130, 2}, + 0x84 = { 2132, 1}, + 0x86 = { 2133, 1}, + 0x88 = { 2134, 1}, + 0x89 = { 2135, 2}, + 0x8A = { 2137, 1}, + 0x8B = { 2138, 3}, + 0x8C = { 2141, 1}, + 0x8E = { 2142, 1}, + 0x90 = { 2143, 1}, + 0x91 = { 2144, 2}, + 0x92 = { 2146, 2}, + 0x93 = { 2148, 2}, + 0x94 = { 2150, 1}, + 0x96 = { 2151, 1}, + 0x98 = { 2152, 1}, + 0x99 = { 2153, 2}, + 0x9A = { 2155, 1}, + 0x9B = { 2156, 2}, + 0x9C = { 2158, 1}, + 0x9E = { 2159, 1}, + 0xA0 = { 2160, 2}, + 0xA1 = { 2162, 2}, + 0xA2 = { 2164, 2}, + 0xA3 = { 2166, 2}, + 0xA4 = { 2168, 2}, + 0xA5 = { 2170, 2}, + 0xA6 = { 2172, 2}, + 0xA7 = { 2174, 2}, + 0xA8 = { 2176, 2}, + 0xA9 = { 2178, 2}, + 0xAA = { 2180, 2}, + 0xAB = { 2182, 2}, + 0xAC = { 2184, 2}, + 0xAD = { 2186, 2}, + 0xAE = { 2188, 2}, + 0xAF = { 2190, 2}, + 0xB0 = { 2192, 2}, + 0xB1 = { 2194, 2}, + 0xB2 = { 2196, 2}, + 0xB3 = { 2198, 2}, + 0xB4 = { 2200, 2}, + 0xB5 = { 2202, 2}, + 0xB6 = { 2204, 2}, + 0xB7 = { 2206, 2}, + 0xB8 = { 2208, 2}, + 0xB9 = { 2210, 2}, + 0xBA = { 2212, 2}, + 0xBB = { 2214, 2}, + 0xBC = { 2216, 2}, + 0xBD = { 2218, 2}, + 0xBE = { 2220, 2}, + 0xBF = { 2222, 2}, + 0xC0 = { 2224, 7}, + 0xC1 = { 2231, 4}, + 0xC2 = { 2235, 12}, + 0xC3 = { 2247, 5}, + 0xC4 = { 2252, 11}, + 0xC5 = { 2263, 8}, + 0xC6 = { 2271, 12}, + 0xC7 = { 2283, 5}, + 0xC8 = { 2288, 6}, + 0xC9 = { 2294, 6}, + 0xCA = { 2300, 12}, + 0xCB = { 2312, 8}, + 0xCC = { 2320, 6}, + 0xCD = { 2326, 6}, + 0xCE = { 2332, 12}, + 0xCF = { 2344, 6}, + 0xD0 = { 2350, 4}, + 0xD1 = { 2354, 4}, + 0xD2 = { 2358, 4}, + 0xD3 = { 2362, 2}, + 0xD4 = { 2364, 4}, + 0xD5 = { 2368, 4}, + 0xD6 = { 2372, 2}, + 0xD7 = { 2374, 2}, + 0xD8 = { 2376, 4}, + 0xD9 = { 2380, 4}, + 0xDA = { 2384, 2}, + 0xDB = { 2386, 2}, + 0xDC = { 2388, 4}, + 0xDD = { 2392, 4}, + 0xDE = { 2396, 2}, + 0xDF = { 2398, 2}, + 0xE0 = { 2400, 19}, + 0xE1 = { 2419, 14}, + 0xE2 = { 2433, 19}, + 0xE3 = { 2452, 15}, + 0xE4 = { 2467, 17}, + 0xE5 = { 2484, 13}, + 0xE6 = { 2497, 18}, + 0xE7 = { 2515, 15}, + 0xE8 = { 2530, 14}, + 0xE9 = { 2544, 11}, + 0xEA = { 2555, 10}, + 0xEB = { 2565, 91}, + 0xEC = { 2656, 15}, + 0xED = { 2671, 11}, + 0xEE = { 2682, 12}, + 0xEF = { 2694, 92}, + 0xF0 = { 2786, 3}, + 0xF1 = { 2789, 3}, + 0xF2 = { 2792, 3}, + 0xF3 = { 2795, 3}, + 0xF4 = { 2798, 3}, + 0xF5 = { 2801, 3}, + 0xF6 = { 2804, 3}, + 0xF7 = { 2807, 3}, + 0xF8 = { 2810, 1}, + 0xF9 = { 2811, 1}, + 0xFA = { 2812, 1}, + 0xFB = { 2813, 1}, + 0xFC = { 2814, 1}, + 0xFD = { 2815, 1}, + 0xFE = { 2816, 1}, + 0xFF = { 2817, 1}, } DECODE_INDEX_T32 := [128]lib.Decode_Index{ - 0x74 = { 2730, 23}, - 0x75 = { 2753, 19}, - 0x76 = { 2772, 19}, - 0x77 = { 2791, 104}, - 0x78 = { 2895, 31}, - 0x79 = { 2926, 38}, - 0x7A = { 2964, 23}, - 0x7B = { 2987, 14}, - 0x7C = { 3001, 20}, - 0x7D = { 3021, 71}, - 0x7E = { 3092, 23}, - 0x7F = { 3115, 126}, + 0x74 = { 2818, 23}, + 0x75 = { 2841, 19}, + 0x76 = { 2860, 19}, + 0x77 = { 2879, 104}, + 0x78 = { 2983, 31}, + 0x79 = { 3014, 38}, + 0x7A = { 3052, 23}, + 0x7B = { 3075, 14}, + 0x7C = { 3089, 20}, + 0x7D = { 3109, 71}, + 0x7E = { 3180, 23}, + 0x7F = { 3203, 126}, } DECODE_INDEX_T16 := [64]lib.Decode_Index{ - 0x00 = { 3241, 1}, - 0x01 = { 3242, 1}, - 0x02 = { 3243, 1}, - 0x03 = { 3244, 1}, - 0x04 = { 3245, 1}, - 0x05 = { 3246, 1}, - 0x06 = { 3247, 2}, - 0x07 = { 3249, 2}, - 0x08 = { 3251, 1}, - 0x09 = { 3252, 1}, - 0x0A = { 3253, 1}, - 0x0B = { 3254, 1}, - 0x0C = { 3255, 1}, - 0x0D = { 3256, 1}, - 0x0E = { 3257, 1}, - 0x0F = { 3258, 1}, - 0x10 = { 3259, 16}, - 0x11 = { 3275, 7}, - 0x12 = { 3282, 1}, - 0x13 = { 3283, 1}, - 0x14 = { 3284, 2}, - 0x15 = { 3286, 2}, - 0x16 = { 3288, 2}, - 0x17 = { 3290, 2}, - 0x18 = { 3292, 1}, - 0x19 = { 3293, 1}, - 0x1A = { 3294, 1}, - 0x1B = { 3295, 1}, - 0x1C = { 3296, 1}, - 0x1D = { 3297, 1}, - 0x1E = { 3298, 1}, - 0x1F = { 3299, 1}, - 0x20 = { 3300, 1}, - 0x21 = { 3301, 1}, - 0x22 = { 3302, 1}, - 0x23 = { 3303, 1}, - 0x24 = { 3304, 1}, - 0x25 = { 3305, 1}, - 0x26 = { 3306, 1}, - 0x27 = { 3307, 1}, - 0x28 = { 3308, 1}, - 0x29 = { 3309, 1}, - 0x2A = { 3310, 1}, - 0x2B = { 3311, 1}, - 0x2C = { 3312, 7}, - 0x2D = { 3319, 2}, - 0x2E = { 3321, 4}, - 0x2F = { 3325, 8}, - 0x30 = { 3333, 1}, - 0x31 = { 3334, 1}, - 0x32 = { 3335, 1}, - 0x33 = { 3336, 1}, - 0x34 = { 3337, 1}, - 0x35 = { 3338, 1}, - 0x36 = { 3339, 1}, - 0x37 = { 3340, 3}, - 0x38 = { 3343, 1}, - 0x39 = { 3344, 1}, + 0x00 = { 3329, 1}, + 0x01 = { 3330, 1}, + 0x02 = { 3331, 1}, + 0x03 = { 3332, 1}, + 0x04 = { 3333, 1}, + 0x05 = { 3334, 1}, + 0x06 = { 3335, 2}, + 0x07 = { 3337, 2}, + 0x08 = { 3339, 1}, + 0x09 = { 3340, 1}, + 0x0A = { 3341, 1}, + 0x0B = { 3342, 1}, + 0x0C = { 3343, 1}, + 0x0D = { 3344, 1}, + 0x0E = { 3345, 1}, + 0x0F = { 3346, 1}, + 0x10 = { 3347, 16}, + 0x11 = { 3363, 7}, + 0x12 = { 3370, 1}, + 0x13 = { 3371, 1}, + 0x14 = { 3372, 2}, + 0x15 = { 3374, 2}, + 0x16 = { 3376, 2}, + 0x17 = { 3378, 2}, + 0x18 = { 3380, 1}, + 0x19 = { 3381, 1}, + 0x1A = { 3382, 1}, + 0x1B = { 3383, 1}, + 0x1C = { 3384, 1}, + 0x1D = { 3385, 1}, + 0x1E = { 3386, 1}, + 0x1F = { 3387, 1}, + 0x20 = { 3388, 1}, + 0x21 = { 3389, 1}, + 0x22 = { 3390, 1}, + 0x23 = { 3391, 1}, + 0x24 = { 3392, 1}, + 0x25 = { 3393, 1}, + 0x26 = { 3394, 1}, + 0x27 = { 3395, 1}, + 0x28 = { 3396, 1}, + 0x29 = { 3397, 1}, + 0x2A = { 3398, 1}, + 0x2B = { 3399, 1}, + 0x2C = { 3400, 7}, + 0x2D = { 3407, 2}, + 0x2E = { 3409, 4}, + 0x2F = { 3413, 8}, + 0x30 = { 3421, 1}, + 0x31 = { 3422, 1}, + 0x32 = { 3423, 1}, + 0x33 = { 3424, 1}, + 0x34 = { 3425, 1}, + 0x35 = { 3426, 1}, + 0x36 = { 3427, 1}, + 0x37 = { 3428, 3}, + 0x38 = { 3431, 1}, + 0x39 = { 3432, 1}, } DECODE_INDEX_T32_SUB := [4096]lib.Decode_Index{ - 0xE84 = { 3345, 6}, - 0xE85 = { 3351, 2}, - 0xE86 = { 3353, 1}, - 0xE87 = { 3354, 1}, - 0xE88 = { 3355, 1}, - 0xE89 = { 3356, 1}, - 0xE8A = { 3357, 1}, - 0xE8B = { 3358, 2}, - 0xE8C = { 3360, 4}, - 0xE8D = { 3364, 6}, - 0xE8E = { 3370, 1}, - 0xE8F = { 3371, 1}, - 0xE90 = { 3372, 1}, - 0xE91 = { 3373, 1}, - 0xE92 = { 3374, 2}, - 0xE93 = { 3376, 1}, - 0xE94 = { 3377, 1}, - 0xE95 = { 3378, 1}, - 0xE96 = { 3379, 1}, - 0xE97 = { 3380, 2}, - 0xE9C = { 3382, 1}, - 0xE9D = { 3383, 1}, - 0xE9E = { 3384, 1}, - 0xE9F = { 3385, 1}, - 0xEA0 = { 3386, 1}, - 0xEA1 = { 3387, 2}, - 0xEA2 = { 3389, 1}, - 0xEA3 = { 3390, 1}, - 0xEA4 = { 3391, 6}, - 0xEA5 = { 3397, 2}, - 0xEA6 = { 3399, 1}, - 0xEA7 = { 3400, 1}, - 0xEA8 = { 3401, 1}, - 0xEA9 = { 3402, 2}, - 0xEB1 = { 3404, 1}, - 0xEB4 = { 3405, 1}, - 0xEB5 = { 3406, 1}, - 0xEB6 = { 3407, 1}, - 0xEB7 = { 3408, 1}, - 0xEBB = { 3409, 1}, - 0xEBC = { 3410, 1}, - 0xEBD = { 3411, 1}, - 0xEC0 = { 3412, 2}, - 0xEC1 = { 3414, 1}, - 0xEC2 = { 3415, 3}, - 0xEC3 = { 3418, 2}, - 0xEC4 = { 3420, 2}, - 0xEC5 = { 3422, 1}, - 0xEC6 = { 3423, 7}, - 0xEC7 = { 3430, 2}, - 0xEC8 = { 3432, 1}, - 0xEC9 = { 3433, 1}, - 0xECA = { 3434, 2}, - 0xECB = { 3436, 2}, - 0xECC = { 3438, 1}, - 0xECD = { 3439, 1}, - 0xECE = { 3440, 2}, - 0xECF = { 3442, 2}, - 0xED6 = { 3444, 4}, - 0xED8 = { 3448, 4}, - 0xED9 = { 3452, 4}, - 0xEDC = { 3456, 4}, - 0xEDD = { 3460, 4}, - 0xEE0 = { 3464, 24}, - 0xEE1 = { 3488, 23}, - 0xEE2 = { 3511, 22}, - 0xEE3 = { 3533, 29}, - 0xEE4 = { 3562, 23}, - 0xEE5 = { 3585, 22}, - 0xEE6 = { 3607, 22}, - 0xEE7 = { 3629, 29}, - 0xEE8 = { 3658, 28}, - 0xEE9 = { 3686, 12}, - 0xEEA = { 3698, 13}, - 0xEEB = { 3711, 18}, - 0xEEC = { 3729, 27}, - 0xEED = { 3756, 13}, - 0xEEE = { 3769, 22}, - 0xEEF = { 3791, 23}, - 0xEF0 = { 3814, 15}, - 0xEF1 = { 3829, 15}, - 0xEF2 = { 3844, 15}, - 0xEF3 = { 3859, 15}, - 0xEF4 = { 3874, 15}, - 0xEF5 = { 3889, 15}, - 0xEF6 = { 3904, 15}, - 0xEF7 = { 3919, 15}, - 0xEF8 = { 3934, 3}, - 0xEF9 = { 3937, 3}, - 0xEFA = { 3940, 3}, - 0xEFB = { 3943, 3}, - 0xEFC = { 3946, 3}, - 0xEFD = { 3949, 3}, - 0xEFE = { 3952, 3}, - 0xEFF = { 3955, 3}, - 0xF00 = { 3958, 11}, - 0xF01 = { 3969, 10}, - 0xF02 = { 3979, 8}, - 0xF03 = { 3987, 8}, - 0xF04 = { 3995, 8}, - 0xF05 = { 4003, 5}, - 0xF06 = { 4008, 5}, - 0xF07 = { 4013, 5}, - 0xF08 = { 4018, 6}, - 0xF09 = { 4024, 6}, - 0xF0A = { 4030, 4}, - 0xF0B = { 4034, 4}, - 0xF0C = { 4038, 4}, - 0xF0D = { 4042, 3}, - 0xF0E = { 4045, 4}, - 0xF0F = { 4049, 4}, - 0xF10 = { 4053, 7}, - 0xF11 = { 4060, 7}, - 0xF12 = { 4067, 6}, - 0xF13 = { 4073, 6}, - 0xF14 = { 4079, 5}, - 0xF15 = { 4084, 4}, - 0xF16 = { 4088, 5}, - 0xF17 = { 4093, 5}, - 0xF18 = { 4098, 5}, - 0xF19 = { 4103, 4}, - 0xF1A = { 4107, 4}, - 0xF1B = { 4111, 5}, - 0xF1C = { 4116, 5}, - 0xF1D = { 4121, 4}, - 0xF1E = { 4125, 4}, - 0xF1F = { 4129, 4}, - 0xF20 = { 4133, 5}, - 0xF21 = { 4138, 4}, - 0xF22 = { 4142, 4}, - 0xF23 = { 4146, 4}, - 0xF24 = { 4150, 5}, - 0xF25 = { 4155, 3}, - 0xF26 = { 4158, 4}, - 0xF27 = { 4162, 4}, - 0xF28 = { 4166, 5}, - 0xF29 = { 4171, 4}, - 0xF2A = { 4175, 4}, - 0xF2B = { 4179, 4}, - 0xF2C = { 4183, 5}, - 0xF2D = { 4188, 3}, - 0xF2E = { 4191, 4}, - 0xF2F = { 4195, 4}, - 0xF30 = { 4199, 6}, - 0xF31 = { 4205, 4}, - 0xF32 = { 4209, 6}, - 0xF33 = { 4215, 4}, - 0xF34 = { 4219, 5}, - 0xF35 = { 4224, 3}, - 0xF36 = { 4227, 6}, - 0xF37 = { 4233, 4}, - 0xF38 = { 4237, 7}, - 0xF39 = { 4244, 4}, - 0xF3A = { 4248, 19}, - 0xF3B = { 4267, 9}, - 0xF3C = { 4276, 5}, - 0xF3D = { 4281, 3}, - 0xF3E = { 4284, 5}, - 0xF3F = { 4289, 4}, - 0xF40 = { 4293, 6}, - 0xF41 = { 4299, 6}, - 0xF42 = { 4305, 5}, - 0xF43 = { 4310, 5}, - 0xF44 = { 4315, 6}, - 0xF45 = { 4321, 5}, - 0xF46 = { 4326, 5}, - 0xF47 = { 4331, 5}, - 0xF48 = { 4336, 6}, - 0xF49 = { 4342, 6}, - 0xF4A = { 4348, 4}, - 0xF4B = { 4352, 4}, - 0xF4C = { 4356, 4}, - 0xF4D = { 4360, 3}, - 0xF4E = { 4363, 4}, - 0xF4F = { 4367, 4}, - 0xF50 = { 4371, 5}, - 0xF51 = { 4376, 5}, - 0xF52 = { 4381, 4}, - 0xF53 = { 4385, 4}, - 0xF54 = { 4389, 5}, - 0xF55 = { 4394, 4}, - 0xF56 = { 4398, 5}, - 0xF57 = { 4403, 5}, - 0xF58 = { 4408, 5}, - 0xF59 = { 4413, 4}, - 0xF5A = { 4417, 4}, - 0xF5B = { 4421, 5}, - 0xF5C = { 4426, 5}, - 0xF5D = { 4431, 4}, - 0xF5E = { 4435, 4}, - 0xF5F = { 4439, 4}, - 0xF60 = { 4443, 5}, - 0xF61 = { 4448, 4}, - 0xF62 = { 4452, 4}, - 0xF63 = { 4456, 4}, - 0xF64 = { 4460, 5}, - 0xF65 = { 4465, 3}, - 0xF66 = { 4468, 4}, - 0xF67 = { 4472, 4}, - 0xF68 = { 4476, 5}, - 0xF69 = { 4481, 4}, - 0xF6A = { 4485, 4}, - 0xF6B = { 4489, 4}, - 0xF6C = { 4493, 5}, - 0xF6D = { 4498, 3}, - 0xF6E = { 4501, 4}, - 0xF6F = { 4505, 4}, - 0xF70 = { 4509, 5}, - 0xF71 = { 4514, 4}, - 0xF72 = { 4518, 4}, - 0xF73 = { 4522, 4}, - 0xF74 = { 4526, 4}, - 0xF75 = { 4530, 3}, - 0xF76 = { 4533, 4}, - 0xF77 = { 4537, 4}, - 0xF78 = { 4541, 8}, - 0xF79 = { 4549, 4}, - 0xF7A = { 4553, 4}, - 0xF7B = { 4557, 4}, - 0xF7C = { 4561, 4}, - 0xF7D = { 4565, 3}, - 0xF7E = { 4568, 4}, - 0xF7F = { 4572, 5}, - 0xF80 = { 4577, 1}, - 0xF81 = { 4578, 1}, - 0xF82 = { 4579, 1}, - 0xF83 = { 4580, 2}, - 0xF84 = { 4582, 1}, - 0xF85 = { 4583, 2}, - 0xF88 = { 4585, 1}, - 0xF89 = { 4586, 2}, - 0xF8A = { 4588, 1}, - 0xF8B = { 4589, 1}, - 0xF8C = { 4590, 1}, - 0xF8D = { 4591, 2}, - 0xF91 = { 4593, 1}, - 0xF93 = { 4594, 1}, - 0xF99 = { 4595, 2}, - 0xF9B = { 4597, 1}, - 0xFA0 = { 4598, 3}, - 0xFA1 = { 4601, 2}, - 0xFA2 = { 4603, 3}, - 0xFA3 = { 4606, 2}, - 0xFA4 = { 4608, 3}, - 0xFA5 = { 4611, 2}, - 0xFA6 = { 4613, 1}, - 0xFA8 = { 4614, 10}, - 0xFA9 = { 4624, 10}, - 0xFAA = { 4634, 6}, - 0xFAB = { 4640, 1}, - 0xFAC = { 4641, 6}, - 0xFAD = { 4647, 6}, - 0xFAE = { 4653, 6}, - 0xFB0 = { 4659, 3}, - 0xFB5 = { 4662, 1}, - 0xFB8 = { 4663, 1}, - 0xFB9 = { 4664, 1}, - 0xFBA = { 4665, 1}, - 0xFBB = { 4666, 1}, - 0xFBC = { 4667, 1}, - 0xFBE = { 4668, 1}, - 0xFC0 = { 4669, 1}, - 0xFC1 = { 4670, 1}, - 0xFC2 = { 4671, 3}, - 0xFC3 = { 4674, 3}, - 0xFC4 = { 4677, 1}, - 0xFC5 = { 4678, 1}, - 0xFC6 = { 4679, 2}, - 0xFC7 = { 4681, 2}, - 0xFC8 = { 4683, 7}, - 0xFC9 = { 4690, 11}, - 0xFCA = { 4701, 3}, - 0xFCB = { 4704, 3}, - 0xFCC = { 4707, 7}, - 0xFCD = { 4714, 7}, - 0xFCE = { 4721, 2}, - 0xFCF = { 4723, 2}, - 0xFD2 = { 4725, 1}, - 0xFD3 = { 4726, 1}, - 0xFD9 = { 4727, 4}, - 0xFDA = { 4731, 1}, - 0xFDB = { 4732, 1}, - 0xFE0 = { 4733, 28}, - 0xFE1 = { 4761, 26}, - 0xFE2 = { 4787, 26}, - 0xFE3 = { 4813, 32}, - 0xFE4 = { 4845, 29}, - 0xFE5 = { 4874, 27}, - 0xFE6 = { 4901, 27}, - 0xFE7 = { 4928, 33}, - 0xFE8 = { 4961, 32}, - 0xFE9 = { 4993, 17}, - 0xFEA = { 5010, 17}, - 0xFEB = { 5027, 29}, - 0xFEC = { 5056, 31}, - 0xFED = { 5087, 18}, - 0xFEE = { 5105, 26}, - 0xFEF = { 5131, 32}, - 0xFF0 = { 5163, 19}, - 0xFF1 = { 5182, 18}, - 0xFF2 = { 5200, 17}, - 0xFF3 = { 5217, 17}, - 0xFF4 = { 5234, 19}, - 0xFF5 = { 5253, 18}, - 0xFF6 = { 5271, 17}, - 0xFF7 = { 5288, 17}, - 0xFF8 = { 5305, 4}, - 0xFF9 = { 5309, 4}, - 0xFFA = { 5313, 4}, - 0xFFB = { 5317, 17}, - 0xFFC = { 5334, 4}, - 0xFFD = { 5338, 4}, - 0xFFE = { 5342, 4}, - 0xFFF = { 5346, 17}, + 0xE84 = { 3433, 6}, + 0xE85 = { 3439, 2}, + 0xE86 = { 3441, 1}, + 0xE87 = { 3442, 1}, + 0xE88 = { 3443, 1}, + 0xE89 = { 3444, 1}, + 0xE8A = { 3445, 1}, + 0xE8B = { 3446, 2}, + 0xE8C = { 3448, 4}, + 0xE8D = { 3452, 6}, + 0xE8E = { 3458, 1}, + 0xE8F = { 3459, 1}, + 0xE90 = { 3460, 1}, + 0xE91 = { 3461, 1}, + 0xE92 = { 3462, 2}, + 0xE93 = { 3464, 1}, + 0xE94 = { 3465, 1}, + 0xE95 = { 3466, 1}, + 0xE96 = { 3467, 1}, + 0xE97 = { 3468, 2}, + 0xE9C = { 3470, 1}, + 0xE9D = { 3471, 1}, + 0xE9E = { 3472, 1}, + 0xE9F = { 3473, 1}, + 0xEA0 = { 3474, 1}, + 0xEA1 = { 3475, 2}, + 0xEA2 = { 3477, 1}, + 0xEA3 = { 3478, 1}, + 0xEA4 = { 3479, 6}, + 0xEA5 = { 3485, 2}, + 0xEA6 = { 3487, 1}, + 0xEA7 = { 3488, 1}, + 0xEA8 = { 3489, 1}, + 0xEA9 = { 3490, 2}, + 0xEB1 = { 3492, 1}, + 0xEB4 = { 3493, 1}, + 0xEB5 = { 3494, 1}, + 0xEB6 = { 3495, 1}, + 0xEB7 = { 3496, 1}, + 0xEBB = { 3497, 1}, + 0xEBC = { 3498, 1}, + 0xEBD = { 3499, 1}, + 0xEC0 = { 3500, 2}, + 0xEC1 = { 3502, 1}, + 0xEC2 = { 3503, 3}, + 0xEC3 = { 3506, 2}, + 0xEC4 = { 3508, 2}, + 0xEC5 = { 3510, 1}, + 0xEC6 = { 3511, 7}, + 0xEC7 = { 3518, 2}, + 0xEC8 = { 3520, 1}, + 0xEC9 = { 3521, 1}, + 0xECA = { 3522, 2}, + 0xECB = { 3524, 2}, + 0xECC = { 3526, 1}, + 0xECD = { 3527, 1}, + 0xECE = { 3528, 2}, + 0xECF = { 3530, 2}, + 0xED6 = { 3532, 4}, + 0xED8 = { 3536, 4}, + 0xED9 = { 3540, 4}, + 0xEDC = { 3544, 4}, + 0xEDD = { 3548, 4}, + 0xEE0 = { 3552, 24}, + 0xEE1 = { 3576, 23}, + 0xEE2 = { 3599, 22}, + 0xEE3 = { 3621, 29}, + 0xEE4 = { 3650, 23}, + 0xEE5 = { 3673, 22}, + 0xEE6 = { 3695, 22}, + 0xEE7 = { 3717, 29}, + 0xEE8 = { 3746, 28}, + 0xEE9 = { 3774, 12}, + 0xEEA = { 3786, 13}, + 0xEEB = { 3799, 18}, + 0xEEC = { 3817, 27}, + 0xEED = { 3844, 13}, + 0xEEE = { 3857, 22}, + 0xEEF = { 3879, 23}, + 0xEF0 = { 3902, 15}, + 0xEF1 = { 3917, 15}, + 0xEF2 = { 3932, 15}, + 0xEF3 = { 3947, 15}, + 0xEF4 = { 3962, 15}, + 0xEF5 = { 3977, 15}, + 0xEF6 = { 3992, 15}, + 0xEF7 = { 4007, 15}, + 0xEF8 = { 4022, 3}, + 0xEF9 = { 4025, 3}, + 0xEFA = { 4028, 3}, + 0xEFB = { 4031, 3}, + 0xEFC = { 4034, 3}, + 0xEFD = { 4037, 3}, + 0xEFE = { 4040, 3}, + 0xEFF = { 4043, 3}, + 0xF00 = { 4046, 11}, + 0xF01 = { 4057, 10}, + 0xF02 = { 4067, 8}, + 0xF03 = { 4075, 8}, + 0xF04 = { 4083, 8}, + 0xF05 = { 4091, 5}, + 0xF06 = { 4096, 5}, + 0xF07 = { 4101, 5}, + 0xF08 = { 4106, 6}, + 0xF09 = { 4112, 6}, + 0xF0A = { 4118, 4}, + 0xF0B = { 4122, 4}, + 0xF0C = { 4126, 4}, + 0xF0D = { 4130, 3}, + 0xF0E = { 4133, 4}, + 0xF0F = { 4137, 4}, + 0xF10 = { 4141, 7}, + 0xF11 = { 4148, 7}, + 0xF12 = { 4155, 6}, + 0xF13 = { 4161, 6}, + 0xF14 = { 4167, 5}, + 0xF15 = { 4172, 4}, + 0xF16 = { 4176, 5}, + 0xF17 = { 4181, 5}, + 0xF18 = { 4186, 5}, + 0xF19 = { 4191, 4}, + 0xF1A = { 4195, 4}, + 0xF1B = { 4199, 5}, + 0xF1C = { 4204, 5}, + 0xF1D = { 4209, 4}, + 0xF1E = { 4213, 4}, + 0xF1F = { 4217, 4}, + 0xF20 = { 4221, 5}, + 0xF21 = { 4226, 4}, + 0xF22 = { 4230, 4}, + 0xF23 = { 4234, 4}, + 0xF24 = { 4238, 5}, + 0xF25 = { 4243, 3}, + 0xF26 = { 4246, 4}, + 0xF27 = { 4250, 4}, + 0xF28 = { 4254, 5}, + 0xF29 = { 4259, 4}, + 0xF2A = { 4263, 4}, + 0xF2B = { 4267, 4}, + 0xF2C = { 4271, 5}, + 0xF2D = { 4276, 3}, + 0xF2E = { 4279, 4}, + 0xF2F = { 4283, 4}, + 0xF30 = { 4287, 6}, + 0xF31 = { 4293, 4}, + 0xF32 = { 4297, 6}, + 0xF33 = { 4303, 4}, + 0xF34 = { 4307, 5}, + 0xF35 = { 4312, 3}, + 0xF36 = { 4315, 6}, + 0xF37 = { 4321, 4}, + 0xF38 = { 4325, 7}, + 0xF39 = { 4332, 4}, + 0xF3A = { 4336, 19}, + 0xF3B = { 4355, 9}, + 0xF3C = { 4364, 5}, + 0xF3D = { 4369, 3}, + 0xF3E = { 4372, 5}, + 0xF3F = { 4377, 4}, + 0xF40 = { 4381, 6}, + 0xF41 = { 4387, 6}, + 0xF42 = { 4393, 5}, + 0xF43 = { 4398, 5}, + 0xF44 = { 4403, 6}, + 0xF45 = { 4409, 5}, + 0xF46 = { 4414, 5}, + 0xF47 = { 4419, 5}, + 0xF48 = { 4424, 6}, + 0xF49 = { 4430, 6}, + 0xF4A = { 4436, 4}, + 0xF4B = { 4440, 4}, + 0xF4C = { 4444, 4}, + 0xF4D = { 4448, 3}, + 0xF4E = { 4451, 4}, + 0xF4F = { 4455, 4}, + 0xF50 = { 4459, 5}, + 0xF51 = { 4464, 5}, + 0xF52 = { 4469, 4}, + 0xF53 = { 4473, 4}, + 0xF54 = { 4477, 5}, + 0xF55 = { 4482, 4}, + 0xF56 = { 4486, 5}, + 0xF57 = { 4491, 5}, + 0xF58 = { 4496, 5}, + 0xF59 = { 4501, 4}, + 0xF5A = { 4505, 4}, + 0xF5B = { 4509, 5}, + 0xF5C = { 4514, 5}, + 0xF5D = { 4519, 4}, + 0xF5E = { 4523, 4}, + 0xF5F = { 4527, 4}, + 0xF60 = { 4531, 5}, + 0xF61 = { 4536, 4}, + 0xF62 = { 4540, 4}, + 0xF63 = { 4544, 4}, + 0xF64 = { 4548, 5}, + 0xF65 = { 4553, 3}, + 0xF66 = { 4556, 4}, + 0xF67 = { 4560, 4}, + 0xF68 = { 4564, 5}, + 0xF69 = { 4569, 4}, + 0xF6A = { 4573, 4}, + 0xF6B = { 4577, 4}, + 0xF6C = { 4581, 5}, + 0xF6D = { 4586, 3}, + 0xF6E = { 4589, 4}, + 0xF6F = { 4593, 4}, + 0xF70 = { 4597, 5}, + 0xF71 = { 4602, 4}, + 0xF72 = { 4606, 4}, + 0xF73 = { 4610, 4}, + 0xF74 = { 4614, 4}, + 0xF75 = { 4618, 3}, + 0xF76 = { 4621, 4}, + 0xF77 = { 4625, 4}, + 0xF78 = { 4629, 8}, + 0xF79 = { 4637, 4}, + 0xF7A = { 4641, 4}, + 0xF7B = { 4645, 4}, + 0xF7C = { 4649, 4}, + 0xF7D = { 4653, 3}, + 0xF7E = { 4656, 4}, + 0xF7F = { 4660, 5}, + 0xF80 = { 4665, 1}, + 0xF81 = { 4666, 1}, + 0xF82 = { 4667, 1}, + 0xF83 = { 4668, 2}, + 0xF84 = { 4670, 1}, + 0xF85 = { 4671, 2}, + 0xF88 = { 4673, 1}, + 0xF89 = { 4674, 2}, + 0xF8A = { 4676, 1}, + 0xF8B = { 4677, 1}, + 0xF8C = { 4678, 1}, + 0xF8D = { 4679, 2}, + 0xF91 = { 4681, 1}, + 0xF93 = { 4682, 1}, + 0xF99 = { 4683, 2}, + 0xF9B = { 4685, 1}, + 0xFA0 = { 4686, 3}, + 0xFA1 = { 4689, 2}, + 0xFA2 = { 4691, 3}, + 0xFA3 = { 4694, 2}, + 0xFA4 = { 4696, 3}, + 0xFA5 = { 4699, 2}, + 0xFA6 = { 4701, 1}, + 0xFA8 = { 4702, 10}, + 0xFA9 = { 4712, 10}, + 0xFAA = { 4722, 6}, + 0xFAB = { 4728, 1}, + 0xFAC = { 4729, 6}, + 0xFAD = { 4735, 6}, + 0xFAE = { 4741, 6}, + 0xFB0 = { 4747, 3}, + 0xFB5 = { 4750, 1}, + 0xFB8 = { 4751, 1}, + 0xFB9 = { 4752, 1}, + 0xFBA = { 4753, 1}, + 0xFBB = { 4754, 1}, + 0xFBC = { 4755, 1}, + 0xFBE = { 4756, 1}, + 0xFC0 = { 4757, 1}, + 0xFC1 = { 4758, 1}, + 0xFC2 = { 4759, 3}, + 0xFC3 = { 4762, 3}, + 0xFC4 = { 4765, 1}, + 0xFC5 = { 4766, 1}, + 0xFC6 = { 4767, 2}, + 0xFC7 = { 4769, 2}, + 0xFC8 = { 4771, 7}, + 0xFC9 = { 4778, 11}, + 0xFCA = { 4789, 3}, + 0xFCB = { 4792, 3}, + 0xFCC = { 4795, 7}, + 0xFCD = { 4802, 7}, + 0xFCE = { 4809, 2}, + 0xFCF = { 4811, 2}, + 0xFD2 = { 4813, 1}, + 0xFD3 = { 4814, 1}, + 0xFD9 = { 4815, 4}, + 0xFDA = { 4819, 1}, + 0xFDB = { 4820, 1}, + 0xFE0 = { 4821, 28}, + 0xFE1 = { 4849, 26}, + 0xFE2 = { 4875, 26}, + 0xFE3 = { 4901, 32}, + 0xFE4 = { 4933, 29}, + 0xFE5 = { 4962, 27}, + 0xFE6 = { 4989, 27}, + 0xFE7 = { 5016, 33}, + 0xFE8 = { 5049, 32}, + 0xFE9 = { 5081, 17}, + 0xFEA = { 5098, 17}, + 0xFEB = { 5115, 29}, + 0xFEC = { 5144, 31}, + 0xFED = { 5175, 18}, + 0xFEE = { 5193, 26}, + 0xFEF = { 5219, 32}, + 0xFF0 = { 5251, 19}, + 0xFF1 = { 5270, 18}, + 0xFF2 = { 5288, 17}, + 0xFF3 = { 5305, 17}, + 0xFF4 = { 5322, 19}, + 0xFF5 = { 5341, 18}, + 0xFF6 = { 5359, 17}, + 0xFF7 = { 5376, 17}, + 0xFF8 = { 5393, 4}, + 0xFF9 = { 5397, 4}, + 0xFFA = { 5401, 4}, + 0xFFB = { 5405, 17}, + 0xFFC = { 5422, 4}, + 0xFFD = { 5426, 4}, + 0xFFE = { 5430, 4}, + 0xFFF = { 5434, 17}, } diff --git a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin index cbaef5e62..b2bc611f0 100644 --- a/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin +++ b/core/rexcode/isa/arm32/tablegen/generated/encode_tables.odin @@ -8,7 +8,7 @@ package rexcode_arm32_generated import lib "../.." @(rodata) -ENCODE_FORMS := [1663]lib.Encoding{ +ENCODE_FORMS := [1701]lib.Encoding{ // .AND { .AND, {.GPR,.GPR,.IMM_MOD,.NONE}, {.RD,.RN_A32,.A32_IMM_MOD,.NONE}, 0x02000000, 0x0FE00000, .BASE, .A32, {}, {.NONE,.NONE} }, { .AND, {.GPR,.GPR,.GPR_SHIFTED,.NONE}, {.RD,.RN_A32,.RM_A32,.NONE}, 0x00000000, 0x0FE00010, .BASE, .A32, {}, {.NONE,.NONE} }, @@ -549,12 +549,12 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RM_A32,.NONE,.NONE}, 0x0120F000, 0x0FB0FFF0, .BASE, .A32, {}, {.NONE,.NONE} }, { .MSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.PSR_FIELD_MASK,.RN_T32,.NONE,.NONE}, 0xF3808000, 0xFFF0F0FF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .MRS - { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.NONE,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {.NONE,.NONE} }, + { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD,.MRS_SPEC_REG,.NONE,.NONE}, 0x010F0000, 0x0FBF0FFF, .BASE, .A32, {}, {.NONE,.NONE} }, { .MRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RD_T32,.NONE,.NONE,.NONE}, 0xF3EF8000, 0xFFFFF0FF, .V6T2, .T32, {thumb32=true}, {.NONE,.NONE} }, // .CPS { .CPS, {.IMM_IFLAGS,.NONE,.NONE,.NONE}, {.CPS_IFLAGS,.NONE,.NONE,.NONE}, 0xF1000000, 0xFFF1FE20, .V6, .A32, {}, {.NONE,.NONE} }, // .SETEND - { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} }, + { .SETEND, {.IMM_ENDIAN,.NONE,.NONE,.NONE}, {.SETEND_ENDIAN,.NONE,.NONE,.NONE}, 0xF1010000, 0xFFFFFDFF, .V6, .A32, {deprecated=true}, {.NONE,.NONE} }, // .NOP { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFFFF, .V6K, .A32, {}, {.NONE,.NONE} }, { .NOP, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0000BF00, 0x0000FFFF, .V6T2, .T32, {}, {.NONE,.NONE} }, @@ -578,7 +578,7 @@ ENCODE_FORMS := [1663]lib.Encoding{ // .SEVL { .SEVL, {.NONE,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0x0320F005, 0x0FFFFFFF, .V8, .A32, {}, {.NONE,.NONE} }, // .DBG - { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, + { .DBG, {.IMM_HINT,.NONE,.NONE,.NONE}, {.DBG_OPTION,.NONE,.NONE,.NONE}, 0x0320F0F0, 0x0FFFFFF0, .V7, .A32, {}, {.NONE,.NONE} }, // .HINT { .HINT, {.IMM_HINT,.NONE,.NONE,.NONE}, {.HINT_FIELD,.NONE,.NONE,.NONE}, 0x0320F000, 0x0FFFFF00, .V6K, .A32, {}, {.NONE,.NONE} }, // .DMB @@ -834,10 +834,30 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .SWP, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01000090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} }, // .SWPB { .SWPB, {.GPR,.GPR,.GPR,.NONE}, {.RT_A32,.RM_A32,.RN_A32,.NONE}, 0x01400090, 0x0FF00FF0, .BASE, .A32, {deprecated=true}, {.NONE,.NONE} }, - // .RFE - { .RFE, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFE10FFFF, .V6, .A32, {}, {.NONE,.NONE} }, - // .SRS - { .SRS, {.IMM,.NONE,.NONE,.NONE}, {.NONE,.NONE,.NONE,.NONE}, 0xF84D0500, 0xFE5FFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + // .RFEDA + { .RFEDA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8100A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEDA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8300A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + // .RFEDB + { .RFEDB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9100A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEDB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9300A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + // .RFEIA + { .RFEIA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8900A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEIA, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF8B00A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + // .RFEIB + { .RFEIB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9900A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + { .RFEIB, {.GPR,.NONE,.NONE,.NONE}, {.RN_A32_WB,.NONE,.NONE,.NONE}, 0xF9B00A00, 0xFFF0FFFF, .V6, .A32, {}, {.NONE,.NONE} }, + // .SRSDA + { .SRSDA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF84D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF86D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + // .SRSDB + { .SRSDB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF94D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSDB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF96D0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + // .SRSIA + { .SRSIA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF8CD0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSIA, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF8ED0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + // .SRSIB + { .SRSIB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF9CD0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, + { .SRSIB, {.GPR,.IMM,.NONE,.NONE}, {.IMPL_SP,.MODE_IMM5,.NONE,.NONE}, 0xF9ED0500, 0xFFFFFFE0, .V6, .A32, {}, {.NONE,.NONE} }, // .CDP { .CDP, {.COPROC_NUM,.IMM_COPROC_OP,.COPROC_REG,.COPROC_REG}, {.COPROC_NUM_FIELD,.COPROC_OPC1_FIELD,.COPROC_CRN_FIELD,.COPROC_CRM_FIELD}, 0x0E000000, 0x0F000010, .BASE, .A32, {}, {.NONE,.NONE} }, // .CDP2 @@ -1147,9 +1167,9 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_16,.RT_A32,.NONE,.NONE}, 0x0E000B30, 0x0FD00F3F, .VFPV2, .A32, {}, {.SZ16,.NONE} }, { .VMOV, {.DPR_ELEM,.GPR,.NONE,.NONE}, {.VMOV_LANE_32,.RT_A32,.NONE,.NONE}, 0x0E000B10, 0x0FD00F7F, .VFPV2, .A32, {}, {.SZ32,.NONE} }, // .VMRS - { .VMRS, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EF10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMRS, {.GPR,.PSR_FIELD,.NONE,.NONE}, {.RT_A32,.VFP_SPEC_REG,.NONE,.NONE}, 0x0EF10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VMSR - { .VMSR, {.GPR,.NONE,.NONE,.NONE}, {.RT_A32,.NONE,.NONE,.NONE}, 0x0EE10A10, 0x0FFF0FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, + { .VMSR, {.PSR_FIELD,.GPR,.NONE,.NONE}, {.VFP_SPEC_REG,.RT_A32,.NONE,.NONE}, 0x0EE10A10, 0x0FF00FFF, .VFPV2, .A32, {}, {.NONE,.NONE} }, // .VLDR { .VLDR, {.SPR,.MEM,.NONE,.NONE}, {.VD_S,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100A00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, { .VLDR, {.DPR,.MEM,.NONE,.NONE}, {.VD_D,.MEM_IMM8_SCALED4,.NONE,.NONE}, 0x0D100B00, 0x0F300F00, .VFPV2, .A32, {}, {.NONE,.NONE} }, @@ -1404,10 +1424,34 @@ ENCODE_FORMS := [1663]lib.Encoding{ { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2000150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, { .VAND, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF000150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VBIC + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800130, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800170, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800330, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800370, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800530, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800570, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800730, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800770, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800930, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800970, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B30, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VBIC, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B70, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, { .VBIC, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2100110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2100150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, { .VBIC, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF100150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, // .VORR + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800110, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800150, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800310, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800350, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800510, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800550, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800710, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800750, 0xFEB80FF0, .NEON, .A32, {}, {.I32,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800910, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800950, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.DPR,.IMM,.NONE,.NONE}, {.VD_D,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B10, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, + { .VORR, {.QPR,.IMM,.NONE,.NONE}, {.VD_Q,.NEON_IMM8_ABCDEFGH,.NONE,.NONE}, 0xF2800B50, 0xFEB80FF0, .NEON, .A32, {}, {.I16,.NONE} }, { .VORR, {.DPR,.DPR,.DPR,.NONE}, {.VD_D,.VN_D,.VM_D,.NONE}, 0xF2200110, 0xFFB00F10, .NEON, .A32, {}, {.NONE,.NONE} }, { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xF2200150, 0xFFB00F50, .NEON, .A32, {}, {.NONE,.NONE} }, { .VORR, {.QPR,.QPR,.QPR,.NONE}, {.VD_Q,.VN_Q,.VM_Q,.NONE}, 0xEF200150, 0xFFB10F51, .MVE_INT, .T32, {thumb32=true}, {.NONE,.NONE} }, @@ -2495,354 +2539,360 @@ ENCODE_RUNS := [lib.Mnemonic]lib.Encode_Run{ .POP = { 585, 3}, .SWP = { 588, 1}, .SWPB = { 589, 1}, - .RFE = { 590, 1}, - .SRS = { 591, 1}, - .CDP = { 592, 1}, - .CDP2 = { 593, 1}, - .MCR = { 594, 1}, - .MCR2 = { 595, 1}, - .MRC = { 596, 1}, - .MRC2 = { 597, 1}, - .MCRR = { 598, 1}, - .MCRR2 = { 599, 1}, - .MRRC = { 600, 1}, - .MRRC2 = { 601, 1}, - .LDC = { 602, 1}, - .LDC2 = { 603, 1}, - .STC = { 604, 1}, - .STC2 = { 605, 1}, - .CRC32B = { 606, 1}, - .CRC32H = { 607, 1}, - .CRC32W = { 608, 1}, - .CRC32CB = { 609, 1}, - .CRC32CH = { 610, 1}, - .CRC32CW = { 611, 1}, - .VADD = { 612, 18}, - .VSUB = { 630, 18}, - .VMUL = { 648, 22}, - .VDIV = { 670, 3}, - .VMLA = { 673, 16}, - .VMLS = { 689, 15}, - .VNMUL = { 704, 2}, - .VNMLA = { 706, 2}, - .VNMLS = { 708, 2}, - .VFMA = { 710, 8}, - .VFMS = { 718, 6}, - .VFNMA = { 724, 3}, - .VFNMS = { 727, 3}, - .VABS = { 730, 12}, - .VNEG = { 742, 12}, - .VSQRT = { 754, 3}, - .VCMP = { 757, 8}, - .VCMPE = { 765, 4}, - .VCVT = { 769, 35}, - .VCVTB = { 804, 2}, - .VCVTT = { 806, 2}, - .VCVTA = { 808, 2}, - .VCVTN = { 810, 2}, - .VCVTP = { 812, 2}, - .VCVTM = { 814, 2}, - .VCVTR = { 816, 4}, - .VMOV = { 820, 33}, - .VMRS = { 853, 1}, - .VMSR = { 854, 1}, - .VLDR = { 855, 2}, - .VSTR = { 857, 2}, - .VLDM = { 859, 2}, - .VSTM = { 861, 2}, - .VPUSH = { 863, 2}, - .VPOP = { 865, 2}, - .VSEL = { 867, 2}, - .VMAXNM = { 869, 2}, - .VMINNM = { 871, 2}, - .VRINTA = { 873, 3}, - .VRINTN = { 876, 3}, - .VRINTP = { 879, 3}, - .VRINTM = { 882, 3}, - .VRINTR = { 885, 2}, - .VRINTZ = { 887, 3}, - .VRINTX = { 890, 3}, - .VADDL = { 893, 6}, - .VADDW = { 899, 6}, - .VSUBL = { 905, 6}, - .VSUBW = { 911, 6}, - .VHADD = { 917, 9}, - .VHSUB = { 926, 9}, - .VRHADD = { 935, 3}, - .VQADD = { 938, 11}, - .VQSUB = { 949, 11}, - .VMULL = { 960, 11}, - .VMLAL = { 971, 10}, - .VMLSL = { 981, 10}, - .VQDMULL = { 991, 4}, - .VQDMLAL = { 995, 4}, - .VQDMLSL = { 999, 4}, - .VQDMULH = { 1003, 8}, - .VQRDMULH = { 1011, 8}, - .VQRDMLAH = { 1019, 8}, - .VQRDMLSH = { 1027, 8}, - .VABA = { 1035, 8}, - .VABAL = { 1043, 6}, - .VABD = { 1049, 10}, - .VABDL = { 1059, 6}, - .VAND = { 1065, 3}, - .VBIC = { 1068, 3}, - .VORR = { 1071, 3}, - .VORN = { 1074, 3}, - .VEOR = { 1077, 3}, - .VBSL = { 1080, 2}, - .VBIT = { 1082, 2}, - .VBIF = { 1084, 2}, - .VMVN = { 1086, 13}, - .VMOVN = { 1099, 3}, - .VQMOVN = { 1102, 6}, - .VQMOVUN = { 1108, 3}, - .VMOVL = { 1111, 6}, - .VTST = { 1117, 6}, - .VCEQ = { 1123, 14}, - .VCGE = { 1137, 16}, - .VCGT = { 1153, 16}, - .VCLE = { 1169, 18}, - .VCLT = { 1187, 18}, - .VACGE = { 1205, 2}, - .VACGT = { 1207, 2}, - .VACLE = { 1209, 2}, - .VACLT = { 1211, 2}, - .VMAX = { 1213, 13}, - .VMIN = { 1226, 13}, - .VPMAX = { 1239, 5}, - .VPMIN = { 1244, 5}, - .VPADD = { 1249, 5}, - .VPADDL = { 1254, 6}, - .VPADAL = { 1260, 4}, - .VRECPE = { 1264, 4}, - .VRECPS = { 1268, 2}, - .VRSQRTE = { 1270, 4}, - .VRSQRTS = { 1274, 2}, - .VSHL = { 1276, 9}, - .VSHR = { 1285, 3}, - .VSRA = { 1288, 3}, - .VRSHL = { 1291, 5}, - .VRSHR = { 1296, 3}, - .VRSRA = { 1299, 2}, - .VSLI = { 1301, 2}, - .VSRI = { 1303, 2}, - .VQSHL = { 1305, 7}, - .VQSHRN = { 1312, 1}, - .VQSHRUN = { 1313, 1}, - .VQRSHL = { 1314, 16}, - .VQRSHRN = { 1330, 1}, - .VQRSHRUN = { 1331, 1}, - .VSHRN = { 1332, 1}, - .VRSHRN = { 1333, 1}, - .VSHLL = { 1334, 4}, - .VCLS = { 1338, 6}, - .VCLZ = { 1344, 6}, - .VCNT = { 1350, 2}, - .VREV16 = { 1352, 2}, - .VREV32 = { 1354, 4}, - .VREV64 = { 1358, 6}, - .VEXT = { 1364, 2}, - .VTBL = { 1366, 4}, - .VTBX = { 1370, 4}, - .VTRN = { 1374, 6}, - .VUZP = { 1380, 5}, - .VZIP = { 1385, 5}, - .VDUP = { 1390, 5}, - .VSWP = { 1395, 2}, - .VLD1 = { 1397, 8}, - .VLD2 = { 1405, 6}, - .VLD3 = { 1411, 5}, - .VLD4 = { 1416, 5}, - .VST1 = { 1421, 7}, - .VST2 = { 1428, 6}, - .VST3 = { 1434, 5}, - .VST4 = { 1439, 5}, - .AESE = { 1444, 1}, - .AESD = { 1445, 1}, - .AESMC = { 1446, 1}, - .AESIMC = { 1447, 1}, - .SHA1H = { 1448, 1}, - .SHA1SU0 = { 1449, 1}, - .SHA1SU1 = { 1450, 1}, - .SHA1C = { 1451, 1}, - .SHA1M = { 1452, 1}, - .SHA1P = { 1453, 1}, - .SHA256H = { 1454, 1}, - .SHA256H2 = { 1455, 1}, - .SHA256SU0 = { 1456, 1}, - .SHA256SU1 = { 1457, 1}, - .VJCVT = { 1458, 1}, - .VSDOT = { 1459, 4}, - .VUDOT = { 1463, 4}, - .VDOT = { 1467, 2}, - .VMMLA = { 1469, 1}, - .VFMAL = { 1470, 2}, - .VFMSL = { 1472, 2}, - .VCMLA = { 1474, 5}, - .VCADD = { 1479, 2}, - .VSMMLA = { 1481, 1}, - .VUMMLA = { 1482, 1}, - .VUSMMLA = { 1483, 1}, - .VSUDOT = { 1484, 2}, - .VUSDOT = { 1486, 4}, - .VQABS = { 1490, 1}, - .VQNEG = { 1491, 1}, - .VMOVX = { 1492, 1}, - .VINS = { 1493, 1}, - .VLD2R = { 1494, 1}, - .VLD3R = { 1495, 1}, - .VLD4R = { 1496, 1}, - .IT = { 1497, 1}, - .TT = { 1498, 1}, - .TTT = { 1499, 1}, - .TTA = { 1500, 1}, - .TTAT = { 1501, 1}, - .SG = { 1502, 1}, - .BXNS = { 1503, 1}, - .BLXNS = { 1504, 1}, - .PAC = { 1505, 1}, - .PACBTI = { 1506, 1}, - .AUT = { 1507, 1}, - .AUTG = { 1508, 1}, - .BTI = { 1509, 1}, - .WLS = { 1510, 1}, - .WLSTP = { 1511, 1}, - .DLS = { 1512, 1}, - .DLSTP = { 1513, 1}, - .LE = { 1514, 1}, - .LETP = { 1515, 1}, - .LCTP = { 1516, 1}, - .BF = { 1517, 1}, - .BFX = { 1518, 1}, - .BFL = { 1519, 1}, - .BFLX = { 1520, 1}, - .BFCSEL = { 1521, 1}, - .CX1 = { 1522, 1}, - .CX1A = { 1523, 1}, - .CX1D = { 1524, 1}, - .CX1DA = { 1525, 1}, - .CX2 = { 1526, 1}, - .CX2A = { 1527, 1}, - .CX2D = { 1528, 1}, - .CX2DA = { 1529, 1}, - .CX3 = { 1530, 1}, - .CX3A = { 1531, 1}, - .CX3D = { 1532, 1}, - .CX3DA = { 1533, 1}, - .VCX1 = { 1534, 2}, - .VCX1A = { 1536, 2}, - .VCX2 = { 1538, 2}, - .VCX2A = { 1540, 2}, - .VCX3 = { 1542, 2}, - .VCX3A = { 1544, 2}, - .VPT = { 1546, 1}, - .VPST = { 1547, 1}, - .VPSEL = { 1548, 1}, - .VPNOT = { 1549, 1}, - .VCTP = { 1550, 1}, - .VADDV = { 1551, 1}, - .VADDVA = { 1552, 1}, - .VADDLV = { 1553, 1}, - .VADDLVA = { 1554, 1}, - .VMAXV = { 1555, 1}, - .VMAXAV = { 1556, 1}, - .VMINV = { 1557, 1}, - .VMINAV = { 1558, 1}, - .VMAXNMV = { 1559, 1}, - .VMAXNMAV = { 1560, 1}, - .VMINNMV = { 1561, 1}, - .VMINNMAV = { 1562, 1}, - .VABAV = { 1563, 1}, - .VMLADAV = { 1564, 1}, - .VMLADAVA = { 1565, 1}, - .VMLADAVX = { 1566, 1}, - .VMLADAVAX = { 1567, 1}, - .VMLALDAV = { 1568, 1}, - .VMLALDAVA = { 1569, 1}, - .VMLALDAVX = { 1570, 1}, - .VMLALDAVAX = { 1571, 1}, - .VMLSDAV = { 1572, 1}, - .VMLSDAVA = { 1573, 1}, - .VMLSDAVX = { 1574, 1}, - .VMLSDAVAX = { 1575, 1}, - .VMLSLDAV = { 1576, 1}, - .VMLSLDAVA = { 1577, 1}, - .VMLSLDAVX = { 1578, 1}, - .VMLSLDAVAX = { 1579, 1}, - .VRMLALDAVH = { 1580, 1}, - .VRMLALDAVHA = { 1581, 1}, - .VRMLALDAVHX = { 1582, 1}, - .VRMLALDAVHAX = { 1583, 1}, - .VRMLSLDAVH = { 1584, 1}, - .VRMLSLDAVHA = { 1585, 1}, - .VRMLSLDAVHX = { 1586, 1}, - .VRMLSLDAVHAX = { 1587, 1}, - .VMLAV = { 1588, 1}, - .VMLAVA = { 1589, 1}, - .VMLSV = { 1590, 1}, - .VMLSVA = { 1591, 1}, - .VCMUL = { 1592, 1}, - .VHCADD = { 1593, 2}, - .VBRSR = { 1595, 1}, - .VSHLC = { 1596, 1}, - .VDDUP = { 1597, 1}, - .VIDUP = { 1598, 1}, - .VDWDUP = { 1599, 1}, - .VIWDUP = { 1600, 1}, - .VMOVNB = { 1601, 1}, - .VMOVNT = { 1602, 1}, - .VQMOVNB = { 1603, 1}, - .VQMOVNT = { 1604, 1}, - .VQMOVUNB = { 1605, 1}, - .VQMOVUNT = { 1606, 1}, - .VSHLLB = { 1607, 1}, - .VSHLLT = { 1608, 1}, - .VMULLB = { 1609, 1}, - .VMULLT = { 1610, 1}, - .VMLALB = { 1611, 1}, - .VMLALT = { 1612, 1}, - .VMLSLB = { 1613, 1}, - .VMLSLT = { 1614, 1}, - .VSHRNB = { 1615, 1}, - .VSHRNT = { 1616, 1}, - .VRSHRNB = { 1617, 1}, - .VRSHRNT = { 1618, 1}, - .VQSHRNB = { 1619, 1}, - .VQSHRNT = { 1620, 1}, - .VQRSHRNB = { 1621, 1}, - .VQRSHRNT = { 1622, 1}, - .VQSHRUNB = { 1623, 1}, - .VQSHRUNT = { 1624, 1}, - .VQRSHRUNB = { 1625, 1}, - .VQRSHRUNT = { 1626, 1}, - .VQDMLADH = { 1627, 1}, - .VQDMLADHX = { 1628, 1}, - .VQDMLSDH = { 1629, 1}, - .VQDMLSDHX = { 1630, 1}, - .VQRDMLADH = { 1631, 1}, - .VQRDMLADHX = { 1632, 1}, - .VQRDMLSDH = { 1633, 1}, - .VQRDMLSDHX = { 1634, 1}, - .VLDRB = { 1635, 2}, - .VLDRH = { 1637, 2}, - .VLDRW = { 1639, 2}, - .VLDRD = { 1641, 2}, - .VSTRB = { 1643, 2}, - .VSTRH = { 1645, 2}, - .VSTRW = { 1647, 2}, - .VSTRD = { 1649, 2}, - .VLD20 = { 1651, 1}, - .VLD21 = { 1652, 1}, - .VLD40 = { 1653, 1}, - .VLD41 = { 1654, 1}, - .VLD42 = { 1655, 1}, - .VLD43 = { 1656, 1}, - .VST20 = { 1657, 1}, - .VST21 = { 1658, 1}, - .VST40 = { 1659, 1}, - .VST41 = { 1660, 1}, - .VST42 = { 1661, 1}, - .VST43 = { 1662, 1}, - ._COUNT = { 1663, 0}, + .RFEDA = { 590, 2}, + .RFEDB = { 592, 2}, + .RFEIA = { 594, 2}, + .RFEIB = { 596, 2}, + .SRSDA = { 598, 2}, + .SRSDB = { 600, 2}, + .SRSIA = { 602, 2}, + .SRSIB = { 604, 2}, + .CDP = { 606, 1}, + .CDP2 = { 607, 1}, + .MCR = { 608, 1}, + .MCR2 = { 609, 1}, + .MRC = { 610, 1}, + .MRC2 = { 611, 1}, + .MCRR = { 612, 1}, + .MCRR2 = { 613, 1}, + .MRRC = { 614, 1}, + .MRRC2 = { 615, 1}, + .LDC = { 616, 1}, + .LDC2 = { 617, 1}, + .STC = { 618, 1}, + .STC2 = { 619, 1}, + .CRC32B = { 620, 1}, + .CRC32H = { 621, 1}, + .CRC32W = { 622, 1}, + .CRC32CB = { 623, 1}, + .CRC32CH = { 624, 1}, + .CRC32CW = { 625, 1}, + .VADD = { 626, 18}, + .VSUB = { 644, 18}, + .VMUL = { 662, 22}, + .VDIV = { 684, 3}, + .VMLA = { 687, 16}, + .VMLS = { 703, 15}, + .VNMUL = { 718, 2}, + .VNMLA = { 720, 2}, + .VNMLS = { 722, 2}, + .VFMA = { 724, 8}, + .VFMS = { 732, 6}, + .VFNMA = { 738, 3}, + .VFNMS = { 741, 3}, + .VABS = { 744, 12}, + .VNEG = { 756, 12}, + .VSQRT = { 768, 3}, + .VCMP = { 771, 8}, + .VCMPE = { 779, 4}, + .VCVT = { 783, 35}, + .VCVTB = { 818, 2}, + .VCVTT = { 820, 2}, + .VCVTA = { 822, 2}, + .VCVTN = { 824, 2}, + .VCVTP = { 826, 2}, + .VCVTM = { 828, 2}, + .VCVTR = { 830, 4}, + .VMOV = { 834, 33}, + .VMRS = { 867, 1}, + .VMSR = { 868, 1}, + .VLDR = { 869, 2}, + .VSTR = { 871, 2}, + .VLDM = { 873, 2}, + .VSTM = { 875, 2}, + .VPUSH = { 877, 2}, + .VPOP = { 879, 2}, + .VSEL = { 881, 2}, + .VMAXNM = { 883, 2}, + .VMINNM = { 885, 2}, + .VRINTA = { 887, 3}, + .VRINTN = { 890, 3}, + .VRINTP = { 893, 3}, + .VRINTM = { 896, 3}, + .VRINTR = { 899, 2}, + .VRINTZ = { 901, 3}, + .VRINTX = { 904, 3}, + .VADDL = { 907, 6}, + .VADDW = { 913, 6}, + .VSUBL = { 919, 6}, + .VSUBW = { 925, 6}, + .VHADD = { 931, 9}, + .VHSUB = { 940, 9}, + .VRHADD = { 949, 3}, + .VQADD = { 952, 11}, + .VQSUB = { 963, 11}, + .VMULL = { 974, 11}, + .VMLAL = { 985, 10}, + .VMLSL = { 995, 10}, + .VQDMULL = { 1005, 4}, + .VQDMLAL = { 1009, 4}, + .VQDMLSL = { 1013, 4}, + .VQDMULH = { 1017, 8}, + .VQRDMULH = { 1025, 8}, + .VQRDMLAH = { 1033, 8}, + .VQRDMLSH = { 1041, 8}, + .VABA = { 1049, 8}, + .VABAL = { 1057, 6}, + .VABD = { 1063, 10}, + .VABDL = { 1073, 6}, + .VAND = { 1079, 3}, + .VBIC = { 1082, 15}, + .VORR = { 1097, 15}, + .VORN = { 1112, 3}, + .VEOR = { 1115, 3}, + .VBSL = { 1118, 2}, + .VBIT = { 1120, 2}, + .VBIF = { 1122, 2}, + .VMVN = { 1124, 13}, + .VMOVN = { 1137, 3}, + .VQMOVN = { 1140, 6}, + .VQMOVUN = { 1146, 3}, + .VMOVL = { 1149, 6}, + .VTST = { 1155, 6}, + .VCEQ = { 1161, 14}, + .VCGE = { 1175, 16}, + .VCGT = { 1191, 16}, + .VCLE = { 1207, 18}, + .VCLT = { 1225, 18}, + .VACGE = { 1243, 2}, + .VACGT = { 1245, 2}, + .VACLE = { 1247, 2}, + .VACLT = { 1249, 2}, + .VMAX = { 1251, 13}, + .VMIN = { 1264, 13}, + .VPMAX = { 1277, 5}, + .VPMIN = { 1282, 5}, + .VPADD = { 1287, 5}, + .VPADDL = { 1292, 6}, + .VPADAL = { 1298, 4}, + .VRECPE = { 1302, 4}, + .VRECPS = { 1306, 2}, + .VRSQRTE = { 1308, 4}, + .VRSQRTS = { 1312, 2}, + .VSHL = { 1314, 9}, + .VSHR = { 1323, 3}, + .VSRA = { 1326, 3}, + .VRSHL = { 1329, 5}, + .VRSHR = { 1334, 3}, + .VRSRA = { 1337, 2}, + .VSLI = { 1339, 2}, + .VSRI = { 1341, 2}, + .VQSHL = { 1343, 7}, + .VQSHRN = { 1350, 1}, + .VQSHRUN = { 1351, 1}, + .VQRSHL = { 1352, 16}, + .VQRSHRN = { 1368, 1}, + .VQRSHRUN = { 1369, 1}, + .VSHRN = { 1370, 1}, + .VRSHRN = { 1371, 1}, + .VSHLL = { 1372, 4}, + .VCLS = { 1376, 6}, + .VCLZ = { 1382, 6}, + .VCNT = { 1388, 2}, + .VREV16 = { 1390, 2}, + .VREV32 = { 1392, 4}, + .VREV64 = { 1396, 6}, + .VEXT = { 1402, 2}, + .VTBL = { 1404, 4}, + .VTBX = { 1408, 4}, + .VTRN = { 1412, 6}, + .VUZP = { 1418, 5}, + .VZIP = { 1423, 5}, + .VDUP = { 1428, 5}, + .VSWP = { 1433, 2}, + .VLD1 = { 1435, 8}, + .VLD2 = { 1443, 6}, + .VLD3 = { 1449, 5}, + .VLD4 = { 1454, 5}, + .VST1 = { 1459, 7}, + .VST2 = { 1466, 6}, + .VST3 = { 1472, 5}, + .VST4 = { 1477, 5}, + .AESE = { 1482, 1}, + .AESD = { 1483, 1}, + .AESMC = { 1484, 1}, + .AESIMC = { 1485, 1}, + .SHA1H = { 1486, 1}, + .SHA1SU0 = { 1487, 1}, + .SHA1SU1 = { 1488, 1}, + .SHA1C = { 1489, 1}, + .SHA1M = { 1490, 1}, + .SHA1P = { 1491, 1}, + .SHA256H = { 1492, 1}, + .SHA256H2 = { 1493, 1}, + .SHA256SU0 = { 1494, 1}, + .SHA256SU1 = { 1495, 1}, + .VJCVT = { 1496, 1}, + .VSDOT = { 1497, 4}, + .VUDOT = { 1501, 4}, + .VDOT = { 1505, 2}, + .VMMLA = { 1507, 1}, + .VFMAL = { 1508, 2}, + .VFMSL = { 1510, 2}, + .VCMLA = { 1512, 5}, + .VCADD = { 1517, 2}, + .VSMMLA = { 1519, 1}, + .VUMMLA = { 1520, 1}, + .VUSMMLA = { 1521, 1}, + .VSUDOT = { 1522, 2}, + .VUSDOT = { 1524, 4}, + .VQABS = { 1528, 1}, + .VQNEG = { 1529, 1}, + .VMOVX = { 1530, 1}, + .VINS = { 1531, 1}, + .VLD2R = { 1532, 1}, + .VLD3R = { 1533, 1}, + .VLD4R = { 1534, 1}, + .IT = { 1535, 1}, + .TT = { 1536, 1}, + .TTT = { 1537, 1}, + .TTA = { 1538, 1}, + .TTAT = { 1539, 1}, + .SG = { 1540, 1}, + .BXNS = { 1541, 1}, + .BLXNS = { 1542, 1}, + .PAC = { 1543, 1}, + .PACBTI = { 1544, 1}, + .AUT = { 1545, 1}, + .AUTG = { 1546, 1}, + .BTI = { 1547, 1}, + .WLS = { 1548, 1}, + .WLSTP = { 1549, 1}, + .DLS = { 1550, 1}, + .DLSTP = { 1551, 1}, + .LE = { 1552, 1}, + .LETP = { 1553, 1}, + .LCTP = { 1554, 1}, + .BF = { 1555, 1}, + .BFX = { 1556, 1}, + .BFL = { 1557, 1}, + .BFLX = { 1558, 1}, + .BFCSEL = { 1559, 1}, + .CX1 = { 1560, 1}, + .CX1A = { 1561, 1}, + .CX1D = { 1562, 1}, + .CX1DA = { 1563, 1}, + .CX2 = { 1564, 1}, + .CX2A = { 1565, 1}, + .CX2D = { 1566, 1}, + .CX2DA = { 1567, 1}, + .CX3 = { 1568, 1}, + .CX3A = { 1569, 1}, + .CX3D = { 1570, 1}, + .CX3DA = { 1571, 1}, + .VCX1 = { 1572, 2}, + .VCX1A = { 1574, 2}, + .VCX2 = { 1576, 2}, + .VCX2A = { 1578, 2}, + .VCX3 = { 1580, 2}, + .VCX3A = { 1582, 2}, + .VPT = { 1584, 1}, + .VPST = { 1585, 1}, + .VPSEL = { 1586, 1}, + .VPNOT = { 1587, 1}, + .VCTP = { 1588, 1}, + .VADDV = { 1589, 1}, + .VADDVA = { 1590, 1}, + .VADDLV = { 1591, 1}, + .VADDLVA = { 1592, 1}, + .VMAXV = { 1593, 1}, + .VMAXAV = { 1594, 1}, + .VMINV = { 1595, 1}, + .VMINAV = { 1596, 1}, + .VMAXNMV = { 1597, 1}, + .VMAXNMAV = { 1598, 1}, + .VMINNMV = { 1599, 1}, + .VMINNMAV = { 1600, 1}, + .VABAV = { 1601, 1}, + .VMLADAV = { 1602, 1}, + .VMLADAVA = { 1603, 1}, + .VMLADAVX = { 1604, 1}, + .VMLADAVAX = { 1605, 1}, + .VMLALDAV = { 1606, 1}, + .VMLALDAVA = { 1607, 1}, + .VMLALDAVX = { 1608, 1}, + .VMLALDAVAX = { 1609, 1}, + .VMLSDAV = { 1610, 1}, + .VMLSDAVA = { 1611, 1}, + .VMLSDAVX = { 1612, 1}, + .VMLSDAVAX = { 1613, 1}, + .VMLSLDAV = { 1614, 1}, + .VMLSLDAVA = { 1615, 1}, + .VMLSLDAVX = { 1616, 1}, + .VMLSLDAVAX = { 1617, 1}, + .VRMLALDAVH = { 1618, 1}, + .VRMLALDAVHA = { 1619, 1}, + .VRMLALDAVHX = { 1620, 1}, + .VRMLALDAVHAX = { 1621, 1}, + .VRMLSLDAVH = { 1622, 1}, + .VRMLSLDAVHA = { 1623, 1}, + .VRMLSLDAVHX = { 1624, 1}, + .VRMLSLDAVHAX = { 1625, 1}, + .VMLAV = { 1626, 1}, + .VMLAVA = { 1627, 1}, + .VMLSV = { 1628, 1}, + .VMLSVA = { 1629, 1}, + .VCMUL = { 1630, 1}, + .VHCADD = { 1631, 2}, + .VBRSR = { 1633, 1}, + .VSHLC = { 1634, 1}, + .VDDUP = { 1635, 1}, + .VIDUP = { 1636, 1}, + .VDWDUP = { 1637, 1}, + .VIWDUP = { 1638, 1}, + .VMOVNB = { 1639, 1}, + .VMOVNT = { 1640, 1}, + .VQMOVNB = { 1641, 1}, + .VQMOVNT = { 1642, 1}, + .VQMOVUNB = { 1643, 1}, + .VQMOVUNT = { 1644, 1}, + .VSHLLB = { 1645, 1}, + .VSHLLT = { 1646, 1}, + .VMULLB = { 1647, 1}, + .VMULLT = { 1648, 1}, + .VMLALB = { 1649, 1}, + .VMLALT = { 1650, 1}, + .VMLSLB = { 1651, 1}, + .VMLSLT = { 1652, 1}, + .VSHRNB = { 1653, 1}, + .VSHRNT = { 1654, 1}, + .VRSHRNB = { 1655, 1}, + .VRSHRNT = { 1656, 1}, + .VQSHRNB = { 1657, 1}, + .VQSHRNT = { 1658, 1}, + .VQRSHRNB = { 1659, 1}, + .VQRSHRNT = { 1660, 1}, + .VQSHRUNB = { 1661, 1}, + .VQSHRUNT = { 1662, 1}, + .VQRSHRUNB = { 1663, 1}, + .VQRSHRUNT = { 1664, 1}, + .VQDMLADH = { 1665, 1}, + .VQDMLADHX = { 1666, 1}, + .VQDMLSDH = { 1667, 1}, + .VQDMLSDHX = { 1668, 1}, + .VQRDMLADH = { 1669, 1}, + .VQRDMLADHX = { 1670, 1}, + .VQRDMLSDH = { 1671, 1}, + .VQRDMLSDHX = { 1672, 1}, + .VLDRB = { 1673, 2}, + .VLDRH = { 1675, 2}, + .VLDRW = { 1677, 2}, + .VLDRD = { 1679, 2}, + .VSTRB = { 1681, 2}, + .VSTRH = { 1683, 2}, + .VSTRW = { 1685, 2}, + .VSTRD = { 1687, 2}, + .VLD20 = { 1689, 1}, + .VLD21 = { 1690, 1}, + .VLD40 = { 1691, 1}, + .VLD41 = { 1692, 1}, + .VLD42 = { 1693, 1}, + .VLD43 = { 1694, 1}, + .VST20 = { 1695, 1}, + .VST21 = { 1696, 1}, + .VST40 = { 1697, 1}, + .VST41 = { 1698, 1}, + .VST42 = { 1699, 1}, + .VST43 = { 1700, 1}, + ._COUNT = { 1701, 0}, } diff --git a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin b/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin index 2b5b56c08..260b508c6 100644 Binary files a/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin and b/core/rexcode/isa/arm32/tables/arm32.bucket_list.bin differ diff --git a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin index 7e581e308..3bf20a293 100644 Binary files a/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin and b/core/rexcode/isa/arm32/tables/arm32.encode_forms.bin differ diff --git a/core/rexcode/isa/arm32/tables/arm32.encode_runs.bin b/core/rexcode/isa/arm32/tables/arm32.encode_runs.bin index 9d9f8e1a3..0f8d5c2d6 100644 Binary files a/core/rexcode/isa/arm32/tables/arm32.encode_runs.bin and b/core/rexcode/isa/arm32/tables/arm32.encode_runs.bin differ diff --git a/core/rexcode/isa/arm32/tables/arm32.entries.bin b/core/rexcode/isa/arm32/tables/arm32.entries.bin index c273a363b..de9e74664 100644 Binary files a/core/rexcode/isa/arm32/tables/arm32.entries.bin and b/core/rexcode/isa/arm32/tables/arm32.entries.bin differ diff --git a/core/rexcode/isa/arm32/tables/arm32.form_idx.bin b/core/rexcode/isa/arm32/tables/arm32.form_idx.bin index 998732394..120b47bb2 100644 Binary files a/core/rexcode/isa/arm32/tables/arm32.form_idx.bin and b/core/rexcode/isa/arm32/tables/arm32.form_idx.bin differ diff --git a/core/rexcode/isa/arm32/tables/arm32.idx_a32.bin b/core/rexcode/isa/arm32/tables/arm32.idx_a32.bin index 73c0caa9f..3a5dfbf65 100644 Binary files a/core/rexcode/isa/arm32/tables/arm32.idx_a32.bin and b/core/rexcode/isa/arm32/tables/arm32.idx_a32.bin differ diff --git a/core/rexcode/isa/arm32/tables/arm32.idx_t16.bin b/core/rexcode/isa/arm32/tables/arm32.idx_t16.bin index f10236a73..2a721b27e 100644 Binary files a/core/rexcode/isa/arm32/tables/arm32.idx_t16.bin and b/core/rexcode/isa/arm32/tables/arm32.idx_t16.bin differ diff --git a/core/rexcode/isa/arm32/tables/arm32.idx_t32.bin b/core/rexcode/isa/arm32/tables/arm32.idx_t32.bin index 28f1b50c5..7537ef06c 100644 Binary files a/core/rexcode/isa/arm32/tables/arm32.idx_t32.bin and b/core/rexcode/isa/arm32/tables/arm32.idx_t32.bin differ diff --git a/core/rexcode/isa/arm32/tables/arm32.idx_t32_sub.bin b/core/rexcode/isa/arm32/tables/arm32.idx_t32_sub.bin index 4f4d6d332..4799a3630 100644 Binary files a/core/rexcode/isa/arm32/tables/arm32.idx_t32_sub.bin and b/core/rexcode/isa/arm32/tables/arm32.idx_t32_sub.bin differ diff --git a/core/rexcode/isa/arm32/tests/smoke.odin b/core/rexcode/isa/arm32/tests/smoke.odin index 6668bef11..6c73e3d7a 100644 --- a/core/rexcode/isa/arm32/tests/smoke.odin +++ b/core/rexcode/isa/arm32/tests/smoke.odin @@ -132,8 +132,9 @@ run_smoke :: proc() { check("VFMA.F32", .VFMA, 0, 0x0EA00A00, 0x0FB00B50) check("VLDR.F32", .VLDR, 0, 0x0D100A00, 0x0F300F00) check("VSTR.F64", .VSTR, 1, 0x0D000B00, 0x0F300F00) - check("VMRS", .VMRS, 0, 0x0EF10A10, 0x0FFF0FFF) - check("VMSR", .VMSR, 0, 0x0EE10A10, 0x0FFF0FFF) + // The system register is an operand now, so its field is not fixed. + check("VMRS", .VMRS, 0, 0x0EF10A10, 0x0FF00FFF) + check("VMSR", .VMSR, 0, 0x0EE10A10, 0x0FF00FFF) check("VPUSH.F32", .VPUSH,0, 0x0D2D0A00, 0x0FFF0F00) check("VPOP.F64", .VPOP, 1, 0x0CBD0B00, 0x0FFF0F00) check("VCMP.F32", .VCMP, 0, 0x0EB40A40, 0x0FBF0FD0) @@ -160,7 +161,9 @@ run_smoke :: proc() { check("VMUL NEON.I8 D", .VMUL, 5, 0xF2000910, 0xFFB00F10) check("VMUL NEON.F32 D", .VMUL, 13, 0xF3000D10, 0xFFB00F10) check("VAND", .VAND, 0, 0xF2000110, 0xFFB00F10) - check("VORR", .VORR, 0, 0xF2200110, 0xFFB00F10) + // The modified-immediate forms come first; the register form follows. + check("VORR imm", .VORR, 0, 0xF2800110, 0xFEB80FF0) + check("VORR reg", .VORR, 12, 0xF2200110, 0xFFB00F10) check("VEOR", .VEOR, 0, 0xF3000110, 0xFFB00F10) check("VBSL", .VBSL, 0, 0xF3100110, 0xFFB00F10) check("VMAX.S16 D", .VMAX, 1, 0xF2100600, 0xFFB00F10)